Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 5
- Errors: 0
- Boot result: PASS
- Kernel Errors: 3
1 06:15:56.692847 lava-dispatcher, installed at version: 2024.01
2 06:15:56.693586 start: 0 validate
3 06:15:56.694056 Start time: 2024-08-31 06:15:56.694026+00:00 (UTC)
4 06:15:56.694586 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:15:56.695120 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:15:56.735406 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:15:56.736098 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:15:56.766212 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:15:56.766826 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:15:56.796879 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:15:56.797460 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:15:56.829195 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:15:56.829763 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc5-219-g1934261d89746%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 06:15:56.868107 validate duration: 0.17
16 06:15:56.869156 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:15:56.869569 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:15:56.869969 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:15:56.870661 Not decompressing ramdisk as can be used compressed.
20 06:15:56.871212 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 06:15:56.871565 saving as /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/ramdisk/initrd.cpio.gz
22 06:15:56.871905 total size: 5628169 (5 MB)
23 06:15:56.907280 progress 0 % (0 MB)
24 06:15:56.911407 progress 5 % (0 MB)
25 06:15:56.915718 progress 10 % (0 MB)
26 06:15:56.919483 progress 15 % (0 MB)
27 06:15:56.923484 progress 20 % (1 MB)
28 06:15:56.927078 progress 25 % (1 MB)
29 06:15:56.931121 progress 30 % (1 MB)
30 06:15:56.935280 progress 35 % (1 MB)
31 06:15:56.938918 progress 40 % (2 MB)
32 06:15:56.942948 progress 45 % (2 MB)
33 06:15:56.946569 progress 50 % (2 MB)
34 06:15:56.950601 progress 55 % (2 MB)
35 06:15:56.954590 progress 60 % (3 MB)
36 06:15:56.958200 progress 65 % (3 MB)
37 06:15:56.962331 progress 70 % (3 MB)
38 06:15:56.965959 progress 75 % (4 MB)
39 06:15:56.969965 progress 80 % (4 MB)
40 06:15:56.973687 progress 85 % (4 MB)
41 06:15:56.977683 progress 90 % (4 MB)
42 06:15:56.981441 progress 95 % (5 MB)
43 06:15:56.984762 progress 100 % (5 MB)
44 06:15:56.985418 5 MB downloaded in 0.11 s (47.29 MB/s)
45 06:15:56.985971 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:15:56.986922 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:15:56.987247 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:15:56.987539 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:15:56.988043 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/kernel/Image
51 06:15:56.988317 saving as /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/kernel/Image
52 06:15:56.988542 total size: 45308416 (43 MB)
53 06:15:56.988761 No compression specified
54 06:15:57.021977 progress 0 % (0 MB)
55 06:15:57.049965 progress 5 % (2 MB)
56 06:15:57.077381 progress 10 % (4 MB)
57 06:15:57.104809 progress 15 % (6 MB)
58 06:15:57.131812 progress 20 % (8 MB)
59 06:15:57.159149 progress 25 % (10 MB)
60 06:15:57.186091 progress 30 % (12 MB)
61 06:15:57.213187 progress 35 % (15 MB)
62 06:15:57.240630 progress 40 % (17 MB)
63 06:15:57.267928 progress 45 % (19 MB)
64 06:15:57.294913 progress 50 % (21 MB)
65 06:15:57.322287 progress 55 % (23 MB)
66 06:15:57.349925 progress 60 % (25 MB)
67 06:15:57.377161 progress 65 % (28 MB)
68 06:15:57.404350 progress 70 % (30 MB)
69 06:15:57.431812 progress 75 % (32 MB)
70 06:15:57.459032 progress 80 % (34 MB)
71 06:15:57.486118 progress 85 % (36 MB)
72 06:15:57.513134 progress 90 % (38 MB)
73 06:15:57.540247 progress 95 % (41 MB)
74 06:15:57.566902 progress 100 % (43 MB)
75 06:15:57.567589 43 MB downloaded in 0.58 s (74.62 MB/s)
76 06:15:57.568120 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:15:57.569017 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:15:57.569318 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:15:57.569598 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:15:57.570077 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 06:15:57.570360 saving as /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/dtb/meson-g12b-a311d-libretech-cc.dtb
83 06:15:57.570585 total size: 54667 (0 MB)
84 06:15:57.570801 No compression specified
85 06:15:57.608124 progress 59 % (0 MB)
86 06:15:57.609018 progress 100 % (0 MB)
87 06:15:57.609595 0 MB downloaded in 0.04 s (1.34 MB/s)
88 06:15:57.610097 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:15:57.610944 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:15:57.611226 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:15:57.611503 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:15:57.611960 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 06:15:57.612242 saving as /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/nfsrootfs/full.rootfs.tar
95 06:15:57.612464 total size: 120894716 (115 MB)
96 06:15:57.612685 Using unxz to decompress xz
97 06:15:57.648359 progress 0 % (0 MB)
98 06:15:58.429435 progress 5 % (5 MB)
99 06:15:59.257079 progress 10 % (11 MB)
100 06:16:00.084557 progress 15 % (17 MB)
101 06:16:00.824942 progress 20 % (23 MB)
102 06:16:01.416373 progress 25 % (28 MB)
103 06:16:02.236893 progress 30 % (34 MB)
104 06:16:03.023593 progress 35 % (40 MB)
105 06:16:03.393389 progress 40 % (46 MB)
106 06:16:03.781132 progress 45 % (51 MB)
107 06:16:04.493316 progress 50 % (57 MB)
108 06:16:05.375503 progress 55 % (63 MB)
109 06:16:06.152385 progress 60 % (69 MB)
110 06:16:06.915251 progress 65 % (74 MB)
111 06:16:07.700946 progress 70 % (80 MB)
112 06:16:08.527153 progress 75 % (86 MB)
113 06:16:09.346564 progress 80 % (92 MB)
114 06:16:10.109088 progress 85 % (98 MB)
115 06:16:10.968983 progress 90 % (103 MB)
116 06:16:11.746781 progress 95 % (109 MB)
117 06:16:12.582917 progress 100 % (115 MB)
118 06:16:12.595590 115 MB downloaded in 14.98 s (7.69 MB/s)
119 06:16:12.596353 end: 1.4.1 http-download (duration 00:00:15) [common]
121 06:16:12.597280 end: 1.4 download-retry (duration 00:00:15) [common]
122 06:16:12.597606 start: 1.5 download-retry (timeout 00:09:44) [common]
123 06:16:12.597893 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 06:16:12.598423 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/modules.tar.xz
125 06:16:12.598718 saving as /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/modules/modules.tar
126 06:16:12.598935 total size: 11496964 (10 MB)
127 06:16:12.599159 Using unxz to decompress xz
128 06:16:12.657862 progress 0 % (0 MB)
129 06:16:12.737951 progress 5 % (0 MB)
130 06:16:12.827784 progress 10 % (1 MB)
131 06:16:12.909039 progress 15 % (1 MB)
132 06:16:12.998825 progress 20 % (2 MB)
133 06:16:13.074867 progress 25 % (2 MB)
134 06:16:13.156557 progress 30 % (3 MB)
135 06:16:13.230511 progress 35 % (3 MB)
136 06:16:13.311208 progress 40 % (4 MB)
137 06:16:13.394048 progress 45 % (4 MB)
138 06:16:13.477864 progress 50 % (5 MB)
139 06:16:13.560867 progress 55 % (6 MB)
140 06:16:13.652435 progress 60 % (6 MB)
141 06:16:13.754859 progress 65 % (7 MB)
142 06:16:13.845611 progress 70 % (7 MB)
143 06:16:13.945702 progress 75 % (8 MB)
144 06:16:14.056269 progress 80 % (8 MB)
145 06:16:14.174696 progress 85 % (9 MB)
146 06:16:14.260043 progress 90 % (9 MB)
147 06:16:14.352098 progress 95 % (10 MB)
148 06:16:14.435939 progress 100 % (10 MB)
149 06:16:14.452202 10 MB downloaded in 1.85 s (5.92 MB/s)
150 06:16:14.452787 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:16:14.453609 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:16:14.453877 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 06:16:14.454143 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 06:16:30.889633 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_
156 06:16:30.890206 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 06:16:30.890489 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 06:16:30.891218 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k
159 06:16:30.891704 makedir: /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin
160 06:16:30.892079 makedir: /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/tests
161 06:16:30.892410 makedir: /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/results
162 06:16:30.892740 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-add-keys
163 06:16:30.893276 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-add-sources
164 06:16:30.893783 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-background-process-start
165 06:16:30.894278 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-background-process-stop
166 06:16:30.894799 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-common-functions
167 06:16:30.895315 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-echo-ipv4
168 06:16:30.895804 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-install-packages
169 06:16:30.896320 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-installed-packages
170 06:16:30.896793 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-os-build
171 06:16:30.897271 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-probe-channel
172 06:16:30.897743 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-probe-ip
173 06:16:30.898204 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-target-ip
174 06:16:30.898677 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-target-mac
175 06:16:30.899168 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-target-storage
176 06:16:30.899665 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-test-case
177 06:16:30.900159 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-test-event
178 06:16:30.900628 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-test-feedback
179 06:16:30.901105 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-test-raise
180 06:16:30.901561 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-test-reference
181 06:16:30.902036 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-test-runner
182 06:16:30.902505 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-test-set
183 06:16:30.902987 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-test-shell
184 06:16:30.903479 Updating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-add-keys (debian)
185 06:16:30.904082 Updating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-add-sources (debian)
186 06:16:30.904627 Updating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-install-packages (debian)
187 06:16:30.905125 Updating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-installed-packages (debian)
188 06:16:30.905619 Updating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/bin/lava-os-build (debian)
189 06:16:30.906044 Creating /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/environment
190 06:16:30.906409 LAVA metadata
191 06:16:30.906662 - LAVA_JOB_ID=681515
192 06:16:30.906872 - LAVA_DISPATCHER_IP=192.168.6.2
193 06:16:30.907224 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 06:16:30.908167 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 06:16:30.908477 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 06:16:30.908680 skipped lava-vland-overlay
197 06:16:30.908919 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 06:16:30.909172 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 06:16:30.909371 skipped lava-multinode-overlay
200 06:16:30.909603 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 06:16:30.909849 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 06:16:30.910092 Loading test definitions
203 06:16:30.910363 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 06:16:30.910577 Using /lava-681515 at stage 0
205 06:16:30.911619 uuid=681515_1.6.2.4.1 testdef=None
206 06:16:30.911918 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 06:16:30.912203 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 06:16:30.913745 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 06:16:30.914518 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 06:16:30.916429 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 06:16:30.917237 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 06:16:30.919000 runner path: /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/0/tests/0_timesync-off test_uuid 681515_1.6.2.4.1
215 06:16:30.919536 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 06:16:30.920352 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 06:16:30.920572 Using /lava-681515 at stage 0
219 06:16:30.920923 Fetching tests from https://github.com/kernelci/test-definitions.git
220 06:16:30.921208 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/0/tests/1_kselftest-alsa'
221 06:16:34.434621 Running '/usr/bin/git checkout kernelci.org
222 06:16:34.782409 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 06:16:34.783826 uuid=681515_1.6.2.4.5 testdef=None
224 06:16:34.784311 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 06:16:34.785881 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 06:16:34.791659 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 06:16:34.793398 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 06:16:34.801146 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 06:16:34.802935 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 06:16:34.810557 runner path: /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/0/tests/1_kselftest-alsa test_uuid 681515_1.6.2.4.5
234 06:16:34.811125 BOARD='meson-g12b-a311d-libretech-cc'
235 06:16:34.811566 BRANCH='mainline'
236 06:16:34.812019 SKIPFILE='/dev/null'
237 06:16:34.812450 SKIP_INSTALL='True'
238 06:16:34.812871 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 06:16:34.813302 TST_CASENAME=''
240 06:16:34.813724 TST_CMDFILES='alsa'
241 06:16:34.814783 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 06:16:34.816469 Creating lava-test-runner.conf files
244 06:16:34.816905 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/681515/lava-overlay-yavugp8k/lava-681515/0 for stage 0
245 06:16:34.817581 - 0_timesync-off
246 06:16:34.818063 - 1_kselftest-alsa
247 06:16:34.818726 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 06:16:34.819304 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 06:16:58.270151 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 06:16:58.270593 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 06:16:58.270851 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 06:16:58.271116 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 06:16:58.271372 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 06:16:58.886504 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 06:16:58.886969 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 06:16:58.887228 extracting modules file /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_
257 06:17:00.232053 extracting modules file /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/681515/extract-overlay-ramdisk-jbjh6ijq/ramdisk
258 06:17:01.603003 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 06:17:01.603473 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 06:17:01.603717 [common] Applying overlay to NFS
261 06:17:01.603922 [common] Applying overlay /var/lib/lava/dispatcher/tmp/681515/compress-overlay-_k0_c34x/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_
262 06:17:04.306064 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 06:17:04.306531 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 06:17:04.306796 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 06:17:04.307021 Converting downloaded kernel to a uImage
266 06:17:04.307335 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/kernel/Image /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/kernel/uImage
267 06:17:04.786458 output: Image Name:
268 06:17:04.786877 output: Created: Sat Aug 31 06:17:04 2024
269 06:17:04.787082 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 06:17:04.787283 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
271 06:17:04.787483 output: Load Address: 01080000
272 06:17:04.787679 output: Entry Point: 01080000
273 06:17:04.787873 output:
274 06:17:04.788233 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 06:17:04.788495 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 06:17:04.788759 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 06:17:04.789007 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 06:17:04.789257 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 06:17:04.789483 Building ramdisk /var/lib/lava/dispatcher/tmp/681515/extract-overlay-ramdisk-jbjh6ijq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/681515/extract-overlay-ramdisk-jbjh6ijq/ramdisk
280 06:17:06.910607 >> 165125 blocks
281 06:17:14.656335 Adding RAMdisk u-boot header.
282 06:17:14.656782 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/681515/extract-overlay-ramdisk-jbjh6ijq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/681515/extract-overlay-ramdisk-jbjh6ijq/ramdisk.cpio.gz.uboot
283 06:17:14.909854 output: Image Name:
284 06:17:14.910265 output: Created: Sat Aug 31 06:17:14 2024
285 06:17:14.910667 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 06:17:14.911085 output: Data Size: 23252788 Bytes = 22707.80 KiB = 22.18 MiB
287 06:17:14.911487 output: Load Address: 00000000
288 06:17:14.911882 output: Entry Point: 00000000
289 06:17:14.912333 output:
290 06:17:14.913298 rename /var/lib/lava/dispatcher/tmp/681515/extract-overlay-ramdisk-jbjh6ijq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/ramdisk/ramdisk.cpio.gz.uboot
291 06:17:14.914002 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 06:17:14.914543 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 06:17:14.915066 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 06:17:14.915482 No LXC device requested
295 06:17:14.915970 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 06:17:14.916510 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 06:17:14.917001 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 06:17:14.917405 Checking files for TFTP limit of 4294967296 bytes.
299 06:17:14.920043 end: 1 tftp-deploy (duration 00:01:18) [common]
300 06:17:14.920609 start: 2 uboot-action (timeout 00:05:00) [common]
301 06:17:14.921128 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 06:17:14.921623 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 06:17:14.922120 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 06:17:14.922645 Using kernel file from prepare-kernel: 681515/tftp-deploy-l5bomynz/kernel/uImage
305 06:17:14.923266 substitutions:
306 06:17:14.923671 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 06:17:14.924109 - {DTB_ADDR}: 0x01070000
308 06:17:14.924510 - {DTB}: 681515/tftp-deploy-l5bomynz/dtb/meson-g12b-a311d-libretech-cc.dtb
309 06:17:14.924909 - {INITRD}: 681515/tftp-deploy-l5bomynz/ramdisk/ramdisk.cpio.gz.uboot
310 06:17:14.925300 - {KERNEL_ADDR}: 0x01080000
311 06:17:14.925687 - {KERNEL}: 681515/tftp-deploy-l5bomynz/kernel/uImage
312 06:17:14.926076 - {LAVA_MAC}: None
313 06:17:14.926500 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_
314 06:17:14.926892 - {NFS_SERVER_IP}: 192.168.6.2
315 06:17:14.927276 - {PRESEED_CONFIG}: None
316 06:17:14.927658 - {PRESEED_LOCAL}: None
317 06:17:14.928066 - {RAMDISK_ADDR}: 0x08000000
318 06:17:14.928454 - {RAMDISK}: 681515/tftp-deploy-l5bomynz/ramdisk/ramdisk.cpio.gz.uboot
319 06:17:14.928840 - {ROOT_PART}: None
320 06:17:14.929225 - {ROOT}: None
321 06:17:14.929604 - {SERVER_IP}: 192.168.6.2
322 06:17:14.929981 - {TEE_ADDR}: 0x83000000
323 06:17:14.930359 - {TEE}: None
324 06:17:14.930738 Parsed boot commands:
325 06:17:14.931108 - setenv autoload no
326 06:17:14.931486 - setenv initrd_high 0xffffffff
327 06:17:14.931862 - setenv fdt_high 0xffffffff
328 06:17:14.932284 - dhcp
329 06:17:14.932696 - setenv serverip 192.168.6.2
330 06:17:14.933088 - tftpboot 0x01080000 681515/tftp-deploy-l5bomynz/kernel/uImage
331 06:17:14.933472 - tftpboot 0x08000000 681515/tftp-deploy-l5bomynz/ramdisk/ramdisk.cpio.gz.uboot
332 06:17:14.933861 - tftpboot 0x01070000 681515/tftp-deploy-l5bomynz/dtb/meson-g12b-a311d-libretech-cc.dtb
333 06:17:14.934251 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 06:17:14.934648 - bootm 0x01080000 0x08000000 0x01070000
335 06:17:14.935145 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 06:17:14.936639 start: 2.3 connect-device (timeout 00:05:00) [common]
338 06:17:14.937057 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 06:17:14.950933 Setting prompt string to ['lava-test: # ']
340 06:17:14.953222 end: 2.3 connect-device (duration 00:00:00) [common]
341 06:17:14.953962 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 06:17:14.954637 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 06:17:14.955231 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 06:17:14.956495 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 06:17:14.992087 >> OK - accepted request
346 06:17:14.993994 Returned 0 in 0 seconds
347 06:17:15.095136 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 06:17:15.096970 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 06:17:15.097548 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 06:17:15.098079 Setting prompt string to ['Hit any key to stop autoboot']
352 06:17:15.098561 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 06:17:15.100542 Trying 192.168.56.21...
354 06:17:15.101050 Connected to conserv1.
355 06:17:15.101480 Escape character is '^]'.
356 06:17:15.101901
357 06:17:15.102327 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 06:17:15.102742
359 06:17:26.011963 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 06:17:26.012396 bl2_stage_init 0x01
361 06:17:26.012881 bl2_stage_init 0x81
362 06:17:26.017516 hw id: 0x0000 - pwm id 0x01
363 06:17:26.017771 bl2_stage_init 0xc1
364 06:17:26.017992 bl2_stage_init 0x02
365 06:17:26.018194
366 06:17:26.022963 L0:00000000
367 06:17:26.023244 L1:20000703
368 06:17:26.023462 L2:00008067
369 06:17:26.023675 L3:14000000
370 06:17:26.028663 B2:00402000
371 06:17:26.028907 B1:e0f83180
372 06:17:26.029118
373 06:17:26.029314 TE: 58124
374 06:17:26.029508
375 06:17:26.034142 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 06:17:26.034382
377 06:17:26.034580 Board ID = 1
378 06:17:26.039790 Set A53 clk to 24M
379 06:17:26.040034 Set A73 clk to 24M
380 06:17:26.040234 Set clk81 to 24M
381 06:17:26.045560 A53 clk: 1200 MHz
382 06:17:26.045782 A73 clk: 1200 MHz
383 06:17:26.045978 CLK81: 166.6M
384 06:17:26.046169 smccc: 00012a92
385 06:17:26.050980 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 06:17:26.056559 board id: 1
387 06:17:26.062508 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 06:17:26.073038 fw parse done
389 06:17:26.078993 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 06:17:26.121709 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 06:17:26.132599 PIEI prepare done
392 06:17:26.133015 fastboot data load
393 06:17:26.133400 fastboot data verify
394 06:17:26.138283 verify result: 266
395 06:17:26.143883 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 06:17:26.144344 LPDDR4 probe
397 06:17:26.144731 ddr clk to 1584MHz
398 06:17:26.151122 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 06:17:26.189122
400 06:17:26.189600 dmc_version 0001
401 06:17:26.195837 Check phy result
402 06:17:26.201635 INFO : End of CA training
403 06:17:26.202078 INFO : End of initialization
404 06:17:26.207262 INFO : Training has run successfully!
405 06:17:26.207692 Check phy result
406 06:17:26.212867 INFO : End of initialization
407 06:17:26.213307 INFO : End of read enable training
408 06:17:26.218507 INFO : End of fine write leveling
409 06:17:26.224062 INFO : End of Write leveling coarse delay
410 06:17:26.224500 INFO : Training has run successfully!
411 06:17:26.224902 Check phy result
412 06:17:26.229646 INFO : End of initialization
413 06:17:26.230072 INFO : End of read dq deskew training
414 06:17:26.235214 INFO : End of MPR read delay center optimization
415 06:17:26.240792 INFO : End of write delay center optimization
416 06:17:26.246551 INFO : End of read delay center optimization
417 06:17:26.247023 INFO : End of max read latency training
418 06:17:26.252032 INFO : Training has run successfully!
419 06:17:26.252471 1D training succeed
420 06:17:26.261190 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 06:17:26.308850 Check phy result
422 06:17:26.309356 INFO : End of initialization
423 06:17:26.330638 INFO : End of 2D read delay Voltage center optimization
424 06:17:26.350818 INFO : End of 2D read delay Voltage center optimization
425 06:17:26.403096 INFO : End of 2D write delay Voltage center optimization
426 06:17:26.452317 INFO : End of 2D write delay Voltage center optimization
427 06:17:26.457873 INFO : Training has run successfully!
428 06:17:26.458317
429 06:17:26.458729 channel==0
430 06:17:26.463416 RxClkDly_Margin_A0==88 ps 9
431 06:17:26.463850 TxDqDly_Margin_A0==98 ps 10
432 06:17:26.469036 RxClkDly_Margin_A1==88 ps 9
433 06:17:26.469468 TxDqDly_Margin_A1==98 ps 10
434 06:17:26.469872 TrainedVREFDQ_A0==74
435 06:17:26.474677 TrainedVREFDQ_A1==75
436 06:17:26.475104 VrefDac_Margin_A0==25
437 06:17:26.475509 DeviceVref_Margin_A0==40
438 06:17:26.480195 VrefDac_Margin_A1==25
439 06:17:26.480621 DeviceVref_Margin_A1==39
440 06:17:26.481024
441 06:17:26.481420
442 06:17:26.485783 channel==1
443 06:17:26.486206 RxClkDly_Margin_A0==88 ps 9
444 06:17:26.486607 TxDqDly_Margin_A0==98 ps 10
445 06:17:26.491357 RxClkDly_Margin_A1==98 ps 10
446 06:17:26.491803 TxDqDly_Margin_A1==98 ps 10
447 06:17:26.497013 TrainedVREFDQ_A0==77
448 06:17:26.497451 TrainedVREFDQ_A1==77
449 06:17:26.497854 VrefDac_Margin_A0==22
450 06:17:26.502606 DeviceVref_Margin_A0==37
451 06:17:26.503041 VrefDac_Margin_A1==24
452 06:17:26.508182 DeviceVref_Margin_A1==37
453 06:17:26.508607
454 06:17:26.509011 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 06:17:26.513811
456 06:17:26.541765 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 06:17:26.542343 2D training succeed
458 06:17:26.547390 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 06:17:26.552954 auto size-- 65535DDR cs0 size: 2048MB
460 06:17:26.553387 DDR cs1 size: 2048MB
461 06:17:26.558559 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 06:17:26.558986 cs0 DataBus test pass
463 06:17:26.564207 cs1 DataBus test pass
464 06:17:26.564633 cs0 AddrBus test pass
465 06:17:26.565038 cs1 AddrBus test pass
466 06:17:26.565432
467 06:17:26.569751 100bdlr_step_size ps== 420
468 06:17:26.570189 result report
469 06:17:26.575423 boot times 0Enable ddr reg access
470 06:17:26.580792 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 06:17:26.594288 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 06:17:27.167884 0.0;M3 CHK:0;cm4_sp_mode 0
473 06:17:27.168506 MVN_1=0x00000000
474 06:17:27.173396 MVN_2=0x00000000
475 06:17:27.179118 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 06:17:27.179555 OPS=0x10
477 06:17:27.179961 ring efuse init
478 06:17:27.180390 chipver efuse init
479 06:17:27.184747 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 06:17:27.190315 [0.018961 Inits done]
481 06:17:27.190741 secure task start!
482 06:17:27.191143 high task start!
483 06:17:27.194897 low task start!
484 06:17:27.195326 run into bl31
485 06:17:27.201611 NOTICE: BL31: v1.3(release):4fc40b1
486 06:17:27.209389 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 06:17:27.209832 NOTICE: BL31: G12A normal boot!
488 06:17:27.235450 NOTICE: BL31: BL33 decompress pass
489 06:17:27.241163 ERROR: Error initializing runtime service opteed_fast
490 06:17:28.473959
491 06:17:28.474387
492 06:17:28.482492 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 06:17:28.483017
494 06:17:28.483605 Model: Libre Computer AML-A311D-CC Alta
495 06:17:28.690903 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 06:17:28.714291 DRAM: 2 GiB (effective 3.8 GiB)
497 06:17:28.857277 Core: 408 devices, 31 uclasses, devicetree: separate
498 06:17:28.862604 WDT: Not starting watchdog@f0d0
499 06:17:28.895477 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 06:17:28.907904 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 06:17:28.912868 ** Bad device specification mmc 0 **
502 06:17:28.923148 Card did not respond to voltage select! : -110
503 06:17:28.930879 ** Bad device specification mmc 0 **
504 06:17:28.931477 Couldn't find partition mmc 0
505 06:17:28.939212 Card did not respond to voltage select! : -110
506 06:17:28.944739 ** Bad device specification mmc 0 **
507 06:17:28.945324 Couldn't find partition mmc 0
508 06:17:28.949708 Error: could not access storage.
509 06:17:30.212472 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 06:17:30.213118 bl2_stage_init 0x01
511 06:17:30.213575 bl2_stage_init 0x81
512 06:17:30.218043 hw id: 0x0000 - pwm id 0x01
513 06:17:30.218579 bl2_stage_init 0xc1
514 06:17:30.219032 bl2_stage_init 0x02
515 06:17:30.219467
516 06:17:30.223597 L0:00000000
517 06:17:30.224159 L1:20000703
518 06:17:30.224611 L2:00008067
519 06:17:30.225047 L3:14000000
520 06:17:30.229218 B2:00402000
521 06:17:30.229731 B1:e0f83180
522 06:17:30.230166
523 06:17:30.230599 TE: 58167
524 06:17:30.231030
525 06:17:30.234876 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 06:17:30.235409
527 06:17:30.235848 Board ID = 1
528 06:17:30.240428 Set A53 clk to 24M
529 06:17:30.240960 Set A73 clk to 24M
530 06:17:30.241402 Set clk81 to 24M
531 06:17:30.246036 A53 clk: 1200 MHz
532 06:17:30.246552 A73 clk: 1200 MHz
533 06:17:30.246987 CLK81: 166.6M
534 06:17:30.247416 smccc: 00012abd
535 06:17:30.251603 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 06:17:30.257184 board id: 1
537 06:17:30.263091 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 06:17:30.273759 fw parse done
539 06:17:30.279726 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 06:17:30.322390 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 06:17:30.333217 PIEI prepare done
542 06:17:30.333763 fastboot data load
543 06:17:30.334234 fastboot data verify
544 06:17:30.339006 verify result: 266
545 06:17:30.344498 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 06:17:30.345033 LPDDR4 probe
547 06:17:30.345476 ddr clk to 1584MHz
548 06:17:30.352494 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 06:17:30.389828
550 06:17:30.390425 dmc_version 0001
551 06:17:30.396529 Check phy result
552 06:17:30.402275 INFO : End of CA training
553 06:17:30.402802 INFO : End of initialization
554 06:17:30.407873 INFO : Training has run successfully!
555 06:17:30.408444 Check phy result
556 06:17:30.413520 INFO : End of initialization
557 06:17:30.414054 INFO : End of read enable training
558 06:17:30.419170 INFO : End of fine write leveling
559 06:17:30.424748 INFO : End of Write leveling coarse delay
560 06:17:30.425290 INFO : Training has run successfully!
561 06:17:30.425738 Check phy result
562 06:17:30.430298 INFO : End of initialization
563 06:17:30.430825 INFO : End of read dq deskew training
564 06:17:30.435926 INFO : End of MPR read delay center optimization
565 06:17:30.441564 INFO : End of write delay center optimization
566 06:17:30.447209 INFO : End of read delay center optimization
567 06:17:30.447749 INFO : End of max read latency training
568 06:17:30.452735 INFO : Training has run successfully!
569 06:17:30.453279 1D training succeed
570 06:17:30.461845 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 06:17:30.509565 Check phy result
572 06:17:30.510199 INFO : End of initialization
573 06:17:30.531289 INFO : End of 2D read delay Voltage center optimization
574 06:17:30.551481 INFO : End of 2D read delay Voltage center optimization
575 06:17:30.603543 INFO : End of 2D write delay Voltage center optimization
576 06:17:30.652965 INFO : End of 2D write delay Voltage center optimization
577 06:17:30.658449 INFO : Training has run successfully!
578 06:17:30.658981
579 06:17:30.659432 channel==0
580 06:17:30.664051 RxClkDly_Margin_A0==88 ps 9
581 06:17:30.664558 TxDqDly_Margin_A0==98 ps 10
582 06:17:30.669560 RxClkDly_Margin_A1==88 ps 9
583 06:17:30.670045 TxDqDly_Margin_A1==98 ps 10
584 06:17:30.670484 TrainedVREFDQ_A0==74
585 06:17:30.675141 TrainedVREFDQ_A1==74
586 06:17:30.675621 VrefDac_Margin_A0==25
587 06:17:30.676087 DeviceVref_Margin_A0==40
588 06:17:30.680750 VrefDac_Margin_A1==25
589 06:17:30.681229 DeviceVref_Margin_A1==40
590 06:17:30.681666
591 06:17:30.682102
592 06:17:30.686385 channel==1
593 06:17:30.686873 RxClkDly_Margin_A0==98 ps 10
594 06:17:30.687307 TxDqDly_Margin_A0==88 ps 9
595 06:17:30.692045 RxClkDly_Margin_A1==88 ps 9
596 06:17:30.692568 TxDqDly_Margin_A1==98 ps 10
597 06:17:30.697553 TrainedVREFDQ_A0==77
598 06:17:30.698046 TrainedVREFDQ_A1==77
599 06:17:30.698482 VrefDac_Margin_A0==22
600 06:17:30.703127 DeviceVref_Margin_A0==37
601 06:17:30.703603 VrefDac_Margin_A1==24
602 06:17:30.708743 DeviceVref_Margin_A1==37
603 06:17:30.709225
604 06:17:30.709657 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 06:17:30.710096
606 06:17:30.742365 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 06:17:30.742953 2D training succeed
608 06:17:30.748039 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 06:17:30.753543 auto size-- 65535DDR cs0 size: 2048MB
610 06:17:30.754032 DDR cs1 size: 2048MB
611 06:17:30.759163 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 06:17:30.759648 cs0 DataBus test pass
613 06:17:30.764746 cs1 DataBus test pass
614 06:17:30.765235 cs0 AddrBus test pass
615 06:17:30.765671 cs1 AddrBus test pass
616 06:17:30.766104
617 06:17:30.770394 100bdlr_step_size ps== 420
618 06:17:30.770892 result report
619 06:17:30.776038 boot times 0Enable ddr reg access
620 06:17:30.780464 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 06:17:30.794854 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 06:17:31.368497 0.0;M3 CHK:0;cm4_sp_mode 0
623 06:17:31.369203 MVN_1=0x00000000
624 06:17:31.373952 MVN_2=0x00000000
625 06:17:31.379918 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 06:17:31.380621 OPS=0x10
627 06:17:31.381081 ring efuse init
628 06:17:31.381518 chipver efuse init
629 06:17:31.385386 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 06:17:31.391047 [0.018960 Inits done]
631 06:17:31.391669 secure task start!
632 06:17:31.392151 high task start!
633 06:17:31.395556 low task start!
634 06:17:31.396178 run into bl31
635 06:17:31.402291 NOTICE: BL31: v1.3(release):4fc40b1
636 06:17:31.410023 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 06:17:31.410690 NOTICE: BL31: G12A normal boot!
638 06:17:31.435431 NOTICE: BL31: BL33 decompress pass
639 06:17:31.440892 ERROR: Error initializing runtime service opteed_fast
640 06:17:32.674361
641 06:17:32.675085
642 06:17:32.682721 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 06:17:32.683310
644 06:17:32.683775 Model: Libre Computer AML-A311D-CC Alta
645 06:17:32.890768 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 06:17:32.914281 DRAM: 2 GiB (effective 3.8 GiB)
647 06:17:33.057261 Core: 408 devices, 31 uclasses, devicetree: separate
648 06:17:33.063063 WDT: Not starting watchdog@f0d0
649 06:17:33.095538 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 06:17:33.107771 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 06:17:33.112945 ** Bad device specification mmc 0 **
652 06:17:33.123117 Card did not respond to voltage select! : -110
653 06:17:33.130454 ** Bad device specification mmc 0 **
654 06:17:33.130770 Couldn't find partition mmc 0
655 06:17:33.139111 Card did not respond to voltage select! : -110
656 06:17:33.144643 ** Bad device specification mmc 0 **
657 06:17:33.144941 Couldn't find partition mmc 0
658 06:17:33.149712 Error: could not access storage.
659 06:17:33.492972 Net: eth0: ethernet@ff3f0000
660 06:17:33.493379 starting USB...
661 06:17:33.745103 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 06:17:33.745503 Starting the controller
663 06:17:33.751935 USB XHCI 1.10
664 06:17:35.461376 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 06:17:35.461823 bl2_stage_init 0x01
666 06:17:35.462124 bl2_stage_init 0x81
667 06:17:35.466823 hw id: 0x0000 - pwm id 0x01
668 06:17:35.467135 bl2_stage_init 0xc1
669 06:17:35.467347 bl2_stage_init 0x02
670 06:17:35.467549
671 06:17:35.472421 L0:00000000
672 06:17:35.472889 L1:20000703
673 06:17:35.473219 L2:00008067
674 06:17:35.473535 L3:14000000
675 06:17:35.478039 B2:00402000
676 06:17:35.478522 B1:e0f83180
677 06:17:35.478766
678 06:17:35.478974 TE: 58159
679 06:17:35.479176
680 06:17:35.483628 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 06:17:35.484132
682 06:17:35.484478 Board ID = 1
683 06:17:35.489204 Set A53 clk to 24M
684 06:17:35.489677 Set A73 clk to 24M
685 06:17:35.489924 Set clk81 to 24M
686 06:17:35.494756 A53 clk: 1200 MHz
687 06:17:35.495064 A73 clk: 1200 MHz
688 06:17:35.495272 CLK81: 166.6M
689 06:17:35.495474 smccc: 00012ab5
690 06:17:35.500426 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 06:17:35.506005 board id: 1
692 06:17:35.511999 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 06:17:35.522595 fw parse done
694 06:17:35.528564 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 06:17:35.571040 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 06:17:35.581989 PIEI prepare done
697 06:17:35.582353 fastboot data load
698 06:17:35.582571 fastboot data verify
699 06:17:35.587700 verify result: 266
700 06:17:35.593219 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 06:17:35.593521 LPDDR4 probe
702 06:17:35.593732 ddr clk to 1584MHz
703 06:17:35.600385 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 06:17:35.638458
705 06:17:35.638837 dmc_version 0001
706 06:17:35.645098 Check phy result
707 06:17:35.651044 INFO : End of CA training
708 06:17:35.651348 INFO : End of initialization
709 06:17:35.656615 INFO : Training has run successfully!
710 06:17:35.656914 Check phy result
711 06:17:35.662129 INFO : End of initialization
712 06:17:35.662422 INFO : End of read enable training
713 06:17:35.667718 INFO : End of fine write leveling
714 06:17:35.673382 INFO : End of Write leveling coarse delay
715 06:17:35.673954 INFO : Training has run successfully!
716 06:17:35.674405 Check phy result
717 06:17:35.679060 INFO : End of initialization
718 06:17:35.679557 INFO : End of read dq deskew training
719 06:17:35.684658 INFO : End of MPR read delay center optimization
720 06:17:35.690205 INFO : End of write delay center optimization
721 06:17:35.695799 INFO : End of read delay center optimization
722 06:17:35.696323 INFO : End of max read latency training
723 06:17:35.701419 INFO : Training has run successfully!
724 06:17:35.701912 1D training succeed
725 06:17:35.710573 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 06:17:35.758275 Check phy result
727 06:17:35.758902 INFO : End of initialization
728 06:17:35.779083 INFO : End of 2D read delay Voltage center optimization
729 06:17:35.800258 INFO : End of 2D read delay Voltage center optimization
730 06:17:35.852229 INFO : End of 2D write delay Voltage center optimization
731 06:17:35.901518 INFO : End of 2D write delay Voltage center optimization
732 06:17:35.907062 INFO : Training has run successfully!
733 06:17:35.907550
734 06:17:35.908028 channel==0
735 06:17:35.912687 RxClkDly_Margin_A0==88 ps 9
736 06:17:35.913189 TxDqDly_Margin_A0==98 ps 10
737 06:17:35.918227 RxClkDly_Margin_A1==78 ps 8
738 06:17:35.918700 TxDqDly_Margin_A1==98 ps 10
739 06:17:35.919139 TrainedVREFDQ_A0==74
740 06:17:35.923928 TrainedVREFDQ_A1==74
741 06:17:35.924438 VrefDac_Margin_A0==25
742 06:17:35.924873 DeviceVref_Margin_A0==40
743 06:17:35.929445 VrefDac_Margin_A1==25
744 06:17:35.929922 DeviceVref_Margin_A1==40
745 06:17:35.930358
746 06:17:35.930790
747 06:17:35.935038 channel==1
748 06:17:35.935512 RxClkDly_Margin_A0==98 ps 10
749 06:17:35.935944 TxDqDly_Margin_A0==88 ps 9
750 06:17:35.940654 RxClkDly_Margin_A1==98 ps 10
751 06:17:35.941134 TxDqDly_Margin_A1==98 ps 10
752 06:17:35.946228 TrainedVREFDQ_A0==77
753 06:17:35.946702 TrainedVREFDQ_A1==77
754 06:17:35.947142 VrefDac_Margin_A0==22
755 06:17:35.951868 DeviceVref_Margin_A0==37
756 06:17:35.952370 VrefDac_Margin_A1==24
757 06:17:35.957433 DeviceVref_Margin_A1==37
758 06:17:35.957907
759 06:17:35.958344 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 06:17:35.963050
761 06:17:35.991110 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 06:17:35.991626 2D training succeed
763 06:17:35.996732 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 06:17:36.002261 auto size-- 65535DDR cs0 size: 2048MB
765 06:17:36.002736 DDR cs1 size: 2048MB
766 06:17:36.007833 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 06:17:36.008349 cs0 DataBus test pass
768 06:17:36.013467 cs1 DataBus test pass
769 06:17:36.013940 cs0 AddrBus test pass
770 06:17:36.014373 cs1 AddrBus test pass
771 06:17:36.014798
772 06:17:36.019173 100bdlr_step_size ps== 420
773 06:17:36.019657 result report
774 06:17:36.024729 boot times 0Enable ddr reg access
775 06:17:36.030053 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 06:17:36.043548 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 06:17:36.617231 0.0;M3 CHK:0;cm4_sp_mode 0
778 06:17:36.617783 MVN_1=0x00000000
779 06:17:36.622817 MVN_2=0x00000000
780 06:17:36.628486 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 06:17:36.628962 OPS=0x10
782 06:17:36.629396 ring efuse init
783 06:17:36.629820 chipver efuse init
784 06:17:36.634082 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 06:17:36.639701 [0.018960 Inits done]
786 06:17:36.640209 secure task start!
787 06:17:36.640642 high task start!
788 06:17:36.644263 low task start!
789 06:17:36.644730 run into bl31
790 06:17:36.650958 NOTICE: BL31: v1.3(release):4fc40b1
791 06:17:36.658782 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 06:17:36.659261 NOTICE: BL31: G12A normal boot!
793 06:17:36.684768 NOTICE: BL31: BL33 decompress pass
794 06:17:36.690348 ERROR: Error initializing runtime service opteed_fast
795 06:17:37.923192
796 06:17:37.923819
797 06:17:37.931594 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 06:17:37.932126
799 06:17:37.932572 Model: Libre Computer AML-A311D-CC Alta
800 06:17:38.140017 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 06:17:38.163384 DRAM: 2 GiB (effective 3.8 GiB)
802 06:17:38.306402 Core: 408 devices, 31 uclasses, devicetree: separate
803 06:17:38.311361 WDT: Not starting watchdog@f0d0
804 06:17:38.344537 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 06:17:38.357081 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 06:17:38.361967 ** Bad device specification mmc 0 **
807 06:17:38.372283 Card did not respond to voltage select! : -110
808 06:17:38.380040 ** Bad device specification mmc 0 **
809 06:17:38.380528 Couldn't find partition mmc 0
810 06:17:38.388318 Card did not respond to voltage select! : -110
811 06:17:38.393798 ** Bad device specification mmc 0 **
812 06:17:38.394280 Couldn't find partition mmc 0
813 06:17:38.398820 Error: could not access storage.
814 06:17:38.741345 Net: eth0: ethernet@ff3f0000
815 06:17:38.741912 starting USB...
816 06:17:38.993198 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 06:17:38.993698 Starting the controller
818 06:17:39.000111 USB XHCI 1.10
819 06:17:41.161363 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 06:17:41.161972 bl2_stage_init 0x01
821 06:17:41.162435 bl2_stage_init 0x81
822 06:17:41.166925 hw id: 0x0000 - pwm id 0x01
823 06:17:41.167409 bl2_stage_init 0xc1
824 06:17:41.167858 bl2_stage_init 0x02
825 06:17:41.168352
826 06:17:41.172577 L0:00000000
827 06:17:41.173053 L1:20000703
828 06:17:41.173496 L2:00008067
829 06:17:41.173931 L3:14000000
830 06:17:41.178117 B2:00402000
831 06:17:41.178591 B1:e0f83180
832 06:17:41.179038
833 06:17:41.179479 TE: 58159
834 06:17:41.179922
835 06:17:41.183697 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 06:17:41.184213
837 06:17:41.184667 Board ID = 1
838 06:17:41.189385 Set A53 clk to 24M
839 06:17:41.189862 Set A73 clk to 24M
840 06:17:41.190305 Set clk81 to 24M
841 06:17:41.194848 A53 clk: 1200 MHz
842 06:17:41.195322 A73 clk: 1200 MHz
843 06:17:41.195768 CLK81: 166.6M
844 06:17:41.196248 smccc: 00012ab5
845 06:17:41.200578 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 06:17:41.206101 board id: 1
847 06:17:41.212043 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 06:17:41.222586 fw parse done
849 06:17:41.228687 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 06:17:41.271217 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 06:17:41.282099 PIEI prepare done
852 06:17:41.282627 fastboot data load
853 06:17:41.283094 fastboot data verify
854 06:17:41.287801 verify result: 266
855 06:17:41.293417 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 06:17:41.293949 LPDDR4 probe
857 06:17:41.294413 ddr clk to 1584MHz
858 06:17:41.301353 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 06:17:41.338683
860 06:17:41.339254 dmc_version 0001
861 06:17:41.345336 Check phy result
862 06:17:41.351176 INFO : End of CA training
863 06:17:41.351717 INFO : End of initialization
864 06:17:41.356796 INFO : Training has run successfully!
865 06:17:41.357333 Check phy result
866 06:17:41.362383 INFO : End of initialization
867 06:17:41.362919 INFO : End of read enable training
868 06:17:41.368012 INFO : End of fine write leveling
869 06:17:41.373688 INFO : End of Write leveling coarse delay
870 06:17:41.374229 INFO : Training has run successfully!
871 06:17:41.374699 Check phy result
872 06:17:41.379256 INFO : End of initialization
873 06:17:41.379791 INFO : End of read dq deskew training
874 06:17:41.384816 INFO : End of MPR read delay center optimization
875 06:17:41.390401 INFO : End of write delay center optimization
876 06:17:41.396037 INFO : End of read delay center optimization
877 06:17:41.396591 INFO : End of max read latency training
878 06:17:41.401750 INFO : Training has run successfully!
879 06:17:41.402304 1D training succeed
880 06:17:41.410741 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 06:17:41.458446 Check phy result
882 06:17:41.459038 INFO : End of initialization
883 06:17:41.480154 INFO : End of 2D read delay Voltage center optimization
884 06:17:41.500379 INFO : End of 2D read delay Voltage center optimization
885 06:17:41.552395 INFO : End of 2D write delay Voltage center optimization
886 06:17:41.601816 INFO : End of 2D write delay Voltage center optimization
887 06:17:41.607342 INFO : Training has run successfully!
888 06:17:41.607884
889 06:17:41.608405 channel==0
890 06:17:41.612955 RxClkDly_Margin_A0==88 ps 9
891 06:17:41.613499 TxDqDly_Margin_A0==98 ps 10
892 06:17:41.616276 RxClkDly_Margin_A1==88 ps 9
893 06:17:41.616818 TxDqDly_Margin_A1==88 ps 9
894 06:17:41.621785 TrainedVREFDQ_A0==74
895 06:17:41.622352 TrainedVREFDQ_A1==74
896 06:17:41.622839 VrefDac_Margin_A0==25
897 06:17:41.627518 DeviceVref_Margin_A0==40
898 06:17:41.628164 VrefDac_Margin_A1==25
899 06:17:41.632933 DeviceVref_Margin_A1==40
900 06:17:41.633504
901 06:17:41.633938
902 06:17:41.634365 channel==1
903 06:17:41.634788 RxClkDly_Margin_A0==98 ps 10
904 06:17:41.638625 TxDqDly_Margin_A0==98 ps 10
905 06:17:41.639186 RxClkDly_Margin_A1==88 ps 9
906 06:17:41.644255 TxDqDly_Margin_A1==88 ps 9
907 06:17:41.644827 TrainedVREFDQ_A0==77
908 06:17:41.645275 TrainedVREFDQ_A1==77
909 06:17:41.649803 VrefDac_Margin_A0==22
910 06:17:41.650334 DeviceVref_Margin_A0==37
911 06:17:41.655307 VrefDac_Margin_A1==24
912 06:17:41.655830 DeviceVref_Margin_A1==37
913 06:17:41.656301
914 06:17:41.660911 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 06:17:41.661435
916 06:17:41.689047 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
917 06:17:41.694611 2D training succeed
918 06:17:41.700242 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 06:17:41.700789 auto size-- 65535DDR cs0 size: 2048MB
920 06:17:41.705626 DDR cs1 size: 2048MB
921 06:17:41.706149 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 06:17:41.711233 cs0 DataBus test pass
923 06:17:41.711756 cs1 DataBus test pass
924 06:17:41.712244 cs0 AddrBus test pass
925 06:17:41.716836 cs1 AddrBus test pass
926 06:17:41.717354
927 06:17:41.717789 100bdlr_step_size ps== 420
928 06:17:41.718227 result report
929 06:17:41.722454 boot times 0Enable ddr reg access
930 06:17:41.730054 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 06:17:41.743575 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 06:17:42.317185 0.0;M3 CHK:0;cm4_sp_mode 0
933 06:17:42.317826 MVN_1=0x00000000
934 06:17:42.322703 MVN_2=0x00000000
935 06:17:42.328414 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 06:17:42.328940 OPS=0x10
937 06:17:42.329402 ring efuse init
938 06:17:42.329867 chipver efuse init
939 06:17:42.334031 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 06:17:42.339626 [0.018960 Inits done]
941 06:17:42.340205 secure task start!
942 06:17:42.340678 high task start!
943 06:17:42.344245 low task start!
944 06:17:42.344795 run into bl31
945 06:17:42.350879 NOTICE: BL31: v1.3(release):4fc40b1
946 06:17:42.358733 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 06:17:42.359276 NOTICE: BL31: G12A normal boot!
948 06:17:42.384085 NOTICE: BL31: BL33 decompress pass
949 06:17:42.389775 ERROR: Error initializing runtime service opteed_fast
950 06:17:43.622734
951 06:17:43.623402
952 06:17:43.632212 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 06:17:43.632735
954 06:17:43.633197 Model: Libre Computer AML-A311D-CC Alta
955 06:17:43.839550 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 06:17:43.862984 DRAM: 2 GiB (effective 3.8 GiB)
957 06:17:44.005983 Core: 408 devices, 31 uclasses, devicetree: separate
958 06:17:44.011865 WDT: Not starting watchdog@f0d0
959 06:17:44.044097 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 06:17:44.056502 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 06:17:44.061498 ** Bad device specification mmc 0 **
962 06:17:44.071927 Card did not respond to voltage select! : -110
963 06:17:44.079507 ** Bad device specification mmc 0 **
964 06:17:44.080045 Couldn't find partition mmc 0
965 06:17:44.087912 Card did not respond to voltage select! : -110
966 06:17:44.093323 ** Bad device specification mmc 0 **
967 06:17:44.093820 Couldn't find partition mmc 0
968 06:17:44.097624 Error: could not access storage.
969 06:17:44.440805 Net: eth0: ethernet@ff3f0000
970 06:17:44.441144 starting USB...
971 06:17:44.692707 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 06:17:44.693282 Starting the controller
973 06:17:44.699470 USB XHCI 1.10
974 06:17:46.253533 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 06:17:46.261800 scanning usb for storage devices... 0 Storage Device(s) found
977 06:17:46.313403 Hit any key to stop autoboot: 1
978 06:17:46.314264 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
979 06:17:46.314981 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
980 06:17:46.315556 Setting prompt string to ['=>']
981 06:17:46.316163 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
982 06:17:46.329315 0
983 06:17:46.330245 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 06:17:46.330819 Sending with 10 millisecond of delay
986 06:17:47.466221 => setenv autoload no
987 06:17:47.477097 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 06:17:47.482679 setenv autoload no
989 06:17:47.483510 Sending with 10 millisecond of delay
991 06:17:49.282872 => setenv initrd_high 0xffffffff
992 06:17:49.293778 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
993 06:17:49.294863 setenv initrd_high 0xffffffff
994 06:17:49.295628 Sending with 10 millisecond of delay
996 06:17:50.912648 => setenv fdt_high 0xffffffff
997 06:17:50.923310 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
998 06:17:50.926942 setenv fdt_high 0xffffffff
999 06:17:50.928454 Sending with 10 millisecond of delay
1001 06:17:51.221427 => dhcp
1002 06:17:51.232202 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
1003 06:17:51.233090 dhcp
1004 06:17:51.233564 Speed: 1000, full duplex
1005 06:17:51.234017 BOOTP broadcast 1
1006 06:17:51.479107 BOOTP broadcast 2
1007 06:17:51.492244 DHCP client bound to address 192.168.6.33 (262 ms)
1008 06:17:51.492811 Sending with 10 millisecond of delay
1010 06:17:53.170006 => setenv serverip 192.168.6.2
1011 06:17:53.180840 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1012 06:17:53.181768 setenv serverip 192.168.6.2
1013 06:17:53.182505 Sending with 10 millisecond of delay
1015 06:17:56.908494 => tftpboot 0x01080000 681515/tftp-deploy-l5bomynz/kernel/uImage
1016 06:17:56.919249 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1017 06:17:56.920117 tftpboot 0x01080000 681515/tftp-deploy-l5bomynz/kernel/uImage
1018 06:17:56.920564 Speed: 1000, full duplex
1019 06:17:56.920975 Using ethernet@ff3f0000 device
1020 06:17:56.922402 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1021 06:17:56.927926 Filename '681515/tftp-deploy-l5bomynz/kernel/uImage'.
1022 06:17:56.931421 Load address: 0x1080000
1023 06:17:59.727138 Loading: *################################################## 43.2 MiB
1024 06:17:59.727743 15.4 MiB/s
1025 06:17:59.728238 done
1026 06:17:59.731045 Bytes transferred = 45308480 (2b35a40 hex)
1027 06:17:59.731826 Sending with 10 millisecond of delay
1029 06:18:04.418667 => tftpboot 0x08000000 681515/tftp-deploy-l5bomynz/ramdisk/ramdisk.cpio.gz.uboot
1030 06:18:04.429458 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1031 06:18:04.430056 tftpboot 0x08000000 681515/tftp-deploy-l5bomynz/ramdisk/ramdisk.cpio.gz.uboot
1032 06:18:04.430348 Speed: 1000, full duplex
1033 06:18:04.430597 Using ethernet@ff3f0000 device
1034 06:18:04.431861 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1035 06:18:04.443494 Filename '681515/tftp-deploy-l5bomynz/ramdisk/ramdisk.cpio.gz.uboot'.
1036 06:18:04.444025 Load address: 0x8000000
1037 06:18:11.012478 Loading: *#######################T ########################### 22.2 MiB
1038 06:18:11.013124 3.4 MiB/s
1039 06:18:11.013552 done
1040 06:18:11.016824 Bytes transferred = 23252852 (162cf74 hex)
1041 06:18:11.017560 Sending with 10 millisecond of delay
1043 06:18:16.187181 => tftpboot 0x01070000 681515/tftp-deploy-l5bomynz/dtb/meson-g12b-a311d-libretech-cc.dtb
1044 06:18:16.197977 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
1045 06:18:16.198794 tftpboot 0x01070000 681515/tftp-deploy-l5bomynz/dtb/meson-g12b-a311d-libretech-cc.dtb
1046 06:18:16.199280 Speed: 1000, full duplex
1047 06:18:16.199714 Using ethernet@ff3f0000 device
1048 06:18:16.203023 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1049 06:18:16.215299 Filename '681515/tftp-deploy-l5bomynz/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1050 06:18:16.215834 Load address: 0x1070000
1051 06:18:16.230920 Loading: *################################################## 53.4 KiB
1052 06:18:16.231396 3.1 MiB/s
1053 06:18:16.231832 done
1054 06:18:16.237260 Bytes transferred = 54667 (d58b hex)
1055 06:18:16.237992 Sending with 10 millisecond of delay
1057 06:18:29.547786 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1058 06:18:29.558786 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1059 06:18:29.559820 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1060 06:18:29.560626 Sending with 10 millisecond of delay
1062 06:18:31.901125 => bootm 0x01080000 0x08000000 0x01070000
1063 06:18:31.912044 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1064 06:18:31.912660 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
1065 06:18:31.913737 bootm 0x01080000 0x08000000 0x01070000
1066 06:18:31.914218 ## Booting kernel from Legacy Image at 01080000 ...
1067 06:18:31.917035 Image Name:
1068 06:18:31.922564 Image Type: AArch64 Linux Kernel Image (uncompressed)
1069 06:18:31.923098 Data Size: 45308416 Bytes = 43.2 MiB
1070 06:18:31.924642 Load Address: 01080000
1071 06:18:31.931359 Entry Point: 01080000
1072 06:18:32.121350 Verifying Checksum ... OK
1073 06:18:32.121744 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1074 06:18:32.126870 Image Name:
1075 06:18:32.132371 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1076 06:18:32.132648 Data Size: 23252788 Bytes = 22.2 MiB
1077 06:18:32.134783 Load Address: 00000000
1078 06:18:32.141955 Entry Point: 00000000
1079 06:18:32.239333 Verifying Checksum ... OK
1080 06:18:32.239728 ## Flattened Device Tree blob at 01070000
1081 06:18:32.244823 Booting using the fdt blob at 0x1070000
1082 06:18:32.245115 Working FDT set to 1070000
1083 06:18:32.249310 Loading Kernel Image
1084 06:18:32.399011 Loading Ramdisk to 7e9d3000, end 7fffff34 ... OK
1085 06:18:32.407290 Loading Device Tree to 000000007e9c2000, end 000000007e9d258a ... OK
1086 06:18:32.407586 Working FDT set to 7e9c2000
1087 06:18:32.407882
1088 06:18:32.408507 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1089 06:18:32.408849 start: 2.4.4 auto-login-action (timeout 00:03:43) [common]
1090 06:18:32.409110 Setting prompt string to ['Linux version [0-9]']
1091 06:18:32.409352 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1092 06:18:32.409594 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1093 06:18:32.410580 Starting kernel ...
1094 06:18:32.410847
1095 06:18:32.447126 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1096 06:18:32.447843 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1097 06:18:32.448170 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1098 06:18:32.448421 Setting prompt string to []
1099 06:18:32.448683 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1100 06:18:32.448924 Using line separator: #'\n'#
1101 06:18:32.449134 No login prompt set.
1102 06:18:32.449365 Parsing kernel messages
1103 06:18:32.449574 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1104 06:18:32.449990 [login-action] Waiting for messages, (timeout 00:03:42)
1105 06:18:32.450224 Waiting using forced prompt support (timeout 00:01:51)
1106 06:18:32.467087 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j302873-arm64-gcc-12-defconfig-mzjxc) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Sat Aug 31 04:48:52 UTC 2024
1107 06:18:32.467431 [ 0.000000] KASLR disabled due to lack of seed
1108 06:18:32.472747 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1109 06:18:32.478184 [ 0.000000] efi: UEFI not found.
1110 06:18:32.483731 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1111 06:18:32.494766 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1112 06:18:32.500282 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1113 06:18:32.511343 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1114 06:18:32.522270 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1115 06:18:32.533406 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1116 06:18:32.538930 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1117 06:18:32.544477 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1118 06:18:32.549972 [ 0.000000] NUMA: No NUMA configuration found
1119 06:18:32.555383 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1120 06:18:32.560884 [ 0.000000] NUMA: NODE_DATA [mem 0xe46669c0-0xe4668fff]
1121 06:18:32.561367 [ 0.000000] Zone ranges:
1122 06:18:32.566441 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1123 06:18:32.571930 [ 0.000000] DMA32 empty
1124 06:18:32.572454 [ 0.000000] Normal empty
1125 06:18:32.577441 [ 0.000000] Movable zone start for each node
1126 06:18:32.582971 [ 0.000000] Early memory node ranges
1127 06:18:32.588589 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1128 06:18:32.594015 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1129 06:18:32.599582 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1130 06:18:32.608264 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1131 06:18:32.632607 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1132 06:18:32.638109 [ 0.000000] psci: probing for conduit method from DT.
1133 06:18:32.638610 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1134 06:18:32.643697 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1135 06:18:32.649115 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1136 06:18:32.654636 [ 0.000000] psci: SMC Calling Convention v1.1
1137 06:18:32.660206 [ 0.000000] percpu: Embedded 24 pages/cpu s60056 r8192 d30056 u98304
1138 06:18:32.665682 [ 0.000000] Detected VIPT I-cache on CPU0
1139 06:18:32.671199 [ 0.000000] CPU features: detected: ARM erratum 845719
1140 06:18:32.676728 [ 0.000000] alternatives: applying boot alternatives
1141 06:18:32.693340 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1142 06:18:32.704330 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1143 06:18:32.709854 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1144 06:18:32.715480 <6>[ 0.000000] Fallback order for Node 0: 0
1145 06:18:32.720929 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1146 06:18:32.726515 <6>[ 0.000000] Policy zone: DMA
1147 06:18:32.731971 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1148 06:18:32.737557 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1149 06:18:32.743037 <6>[ 0.000000] software IO TLB: area num 8.
1150 06:18:32.751971 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1151 06:18:32.798390 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1152 06:18:32.803963 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1153 06:18:32.807686 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1154 06:18:32.813038 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1155 06:18:32.818489 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1156 06:18:32.823997 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1157 06:18:32.835243 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1158 06:18:32.840836 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1159 06:18:32.846239 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
1160 06:18:32.851785 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
1161 06:18:32.862785 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1162 06:18:32.863385 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1163 06:18:32.868331 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1164 06:18:32.873813 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1165 06:18:32.888956 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1166 06:18:32.900112 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1167 06:18:32.905718 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1168 06:18:32.911126 <6>[ 0.008765] Console: colour dummy device 80x25
1169 06:18:32.922078 <6>[ 0.012943] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1170 06:18:32.927843 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1171 06:18:32.933223 <6>[ 0.028187] LSM: initializing lsm=capability
1172 06:18:32.938809 <6>[ 0.032703] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 06:18:32.944312 <6>[ 0.040212] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1174 06:18:32.949824 <6>[ 0.050743] rcu: Hierarchical SRCU implementation.
1175 06:18:32.955289 <6>[ 0.053251] rcu: Max phase no-delay instances is 1000.
1176 06:18:32.966284 <6>[ 0.058854] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1177 06:18:32.971874 <6>[ 0.071454] EFI services will not be available.
1178 06:18:32.972444 <6>[ 0.072084] smp: Bringing up secondary CPUs ...
1179 06:18:32.977361 <6>[ 0.077141] Detected VIPT I-cache on CPU1
1180 06:18:32.982864 <6>[ 0.077261] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1181 06:18:32.988431 <6>[ 0.078571] CPU features: detected: Spectre-v2
1182 06:18:32.993953 <6>[ 0.078585] CPU features: detected: Spectre-v4
1183 06:18:32.999466 <6>[ 0.078590] CPU features: detected: Spectre-BHB
1184 06:18:33.004960 <6>[ 0.078595] CPU features: detected: ARM erratum 858921
1185 06:18:33.010459 <6>[ 0.078602] Detected VIPT I-cache on CPU2
1186 06:18:33.015973 <6>[ 0.078679] arch_timer: Enabling local workaround for ARM erratum 858921
1187 06:18:33.021493 <6>[ 0.078696] arch_timer: CPU2: Trapping CNTVCT access
1188 06:18:33.027086 <6>[ 0.078707] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1189 06:18:33.032551 <6>[ 0.079428] Detected VIPT I-cache on CPU3
1190 06:18:33.038044 <6>[ 0.079474] arch_timer: Enabling local workaround for ARM erratum 858921
1191 06:18:33.043545 <6>[ 0.079484] arch_timer: CPU3: Trapping CNTVCT access
1192 06:18:33.049084 <6>[ 0.079491] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1193 06:18:33.054715 <6>[ 0.080166] Detected VIPT I-cache on CPU4
1194 06:18:33.060200 <6>[ 0.080213] arch_timer: Enabling local workaround for ARM erratum 858921
1195 06:18:33.065668 <6>[ 0.080223] arch_timer: CPU4: Trapping CNTVCT access
1196 06:18:33.071184 <6>[ 0.080229] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1197 06:18:33.076713 <6>[ 0.080977] Detected VIPT I-cache on CPU5
1198 06:18:33.082134 <6>[ 0.081025] arch_timer: Enabling local workaround for ARM erratum 858921
1199 06:18:33.087716 <6>[ 0.081035] arch_timer: CPU5: Trapping CNTVCT access
1200 06:18:33.098754 <6>[ 0.081042] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1201 06:18:33.099312 <6>[ 0.081155] smp: Brought up 1 node, 6 CPUs
1202 06:18:33.104259 <6>[ 0.203224] SMP: Total of 6 processors activated.
1203 06:18:33.109810 <6>[ 0.208130] CPU: All CPU(s) started at EL2
1204 06:18:33.115340 <6>[ 0.212473] CPU features: detected: 32-bit EL0 Support
1205 06:18:33.120846 <6>[ 0.217787] CPU features: detected: 32-bit EL1 Support
1206 06:18:33.126307 <6>[ 0.223148] CPU features: detected: CRC32 instructions
1207 06:18:33.131955 <6>[ 0.228541] alternatives: applying system-wide alternatives
1208 06:18:33.149858 <6>[ 0.235683] Memory: 3558020K/4012396K available (17152K kernel code, 5014K rwdata, 11660K rodata, 10240K init, 733K bss, 187148K reserved, 262144K cma-reserved)
1209 06:18:33.150285 <6>[ 0.250064] devtmpfs: initialized
1210 06:18:33.160789 <6>[ 0.259230] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1211 06:18:33.166343 <6>[ 0.263590] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1212 06:18:33.171915 <6>[ 0.274381] 21504 pages in range for non-PLT usage
1213 06:18:33.177422 <6>[ 0.274391] 513024 pages in range for PLT usage
1214 06:18:33.182925 <6>[ 0.275946] pinctrl core: initialized pinctrl subsystem
1215 06:18:33.188442 <6>[ 0.287954] DMI not present or invalid.
1216 06:18:33.193977 <6>[ 0.292021] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1217 06:18:33.199497 <6>[ 0.297036] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1218 06:18:33.210532 <6>[ 0.303867] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1219 06:18:33.216083 <6>[ 0.311961] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1220 06:18:33.221590 <6>[ 0.319419] audit: initializing netlink subsys (disabled)
1221 06:18:33.232679 <5>[ 0.325142] audit: type=2000 audit(0.244:1): state=initialized audit_enabled=0 res=1
1222 06:18:33.238132 <6>[ 0.326436] thermal_sys: Registered thermal governor 'step_wise'
1223 06:18:33.243641 <6>[ 0.332926] thermal_sys: Registered thermal governor 'power_allocator'
1224 06:18:33.249142 <6>[ 0.339179] cpuidle: using governor menu
1225 06:18:33.254767 <6>[ 0.350153] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1226 06:18:33.260278 <6>[ 0.357087] ASID allocator initialised with 65536 entries
1227 06:18:33.268451 <6>[ 0.364614] Serial: AMBA PL011 UART driver
1228 06:18:33.276109 <6>[ 0.375197] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 06:18:33.290764 <6>[ 0.390047] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1230 06:18:33.299748 <6>[ 0.392715] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1231 06:18:33.305308 <6>[ 0.405634] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1232 06:18:33.316262 <6>[ 0.409089] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1233 06:18:33.321854 <6>[ 0.417485] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1234 06:18:33.332876 <6>[ 0.425138] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1235 06:18:33.338426 <6>[ 0.438453] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1236 06:18:33.343943 <6>[ 0.440959] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1237 06:18:33.354936 <6>[ 0.447438] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1238 06:18:33.360507 <6>[ 0.454417] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1239 06:18:33.366030 <6>[ 0.460886] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1240 06:18:33.371502 <6>[ 0.467871] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1241 06:18:33.377059 <6>[ 0.474341] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1242 06:18:33.388112 <6>[ 0.481326] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1243 06:18:33.388660 <6>[ 0.489220] ACPI: Interpreter disabled.
1244 06:18:33.393615 <6>[ 0.494569] iommu: Default domain type: Translated
1245 06:18:33.399137 <6>[ 0.496863] iommu: DMA domain TLB invalidation policy: strict mode
1246 06:18:33.404729 <5>[ 0.503587] SCSI subsystem initialized
1247 06:18:33.410180 <6>[ 0.507477] usbcore: registered new interface driver usbfs
1248 06:18:33.415681 <6>[ 0.512918] usbcore: registered new interface driver hub
1249 06:18:33.421213 <6>[ 0.518435] usbcore: registered new device driver usb
1250 06:18:33.426786 <6>[ 0.524625] pps_core: LinuxPPS API ver. 1 registered
1251 06:18:33.437821 <6>[ 0.528853] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1252 06:18:33.438362 <6>[ 0.538173] PTP clock support registered
1253 06:18:33.443237 <6>[ 0.542471] EDAC MC: Ver: 3.0.0
1254 06:18:33.448734 <6>[ 0.546056] scmi_core: SCMI protocol bus registered
1255 06:18:33.454241 <6>[ 0.551681] FPGA manager framework
1256 06:18:33.459884 <6>[ 0.554436] Advanced Linux Sound Architecture Driver Initialized.
1257 06:18:33.460439 <6>[ 0.561351] vgaarb: loaded
1258 06:18:33.465295 <6>[ 0.563930] clocksource: Switched to clocksource arch_sys_counter
1259 06:18:33.470791 <5>[ 0.570069] VFS: Disk quotas dquot_6.6.0
1260 06:18:33.476304 <6>[ 0.574064] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1261 06:18:33.481834 <6>[ 0.581276] pnp: PnP ACPI: disabled
1262 06:18:33.487331 <6>[ 0.589531] NET: Registered PF_INET protocol family
1263 06:18:33.492927 <6>[ 0.590101] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1264 06:18:33.503899 <6>[ 0.600256] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1265 06:18:33.509427 <6>[ 0.606270] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1266 06:18:33.520479 <6>[ 0.614164] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1267 06:18:33.526032 <6>[ 0.622404] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1268 06:18:33.537053 <6>[ 0.630206] TCP: Hash tables configured (established 32768 bind 32768)
1269 06:18:33.542597 <6>[ 0.636679] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1270 06:18:33.548075 <6>[ 0.643523] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1271 06:18:33.553601 <6>[ 0.650942] NET: Registered PF_UNIX/PF_LOCAL protocol family
1272 06:18:33.559109 <6>[ 0.657009] RPC: Registered named UNIX socket transport module.
1273 06:18:33.564721 <6>[ 0.662809] RPC: Registered udp transport module.
1274 06:18:33.570134 <6>[ 0.667716] RPC: Registered tcp transport module.
1275 06:18:33.575750 <6>[ 0.672630] RPC: Registered tcp-with-tls transport module.
1276 06:18:33.581225 <6>[ 0.678324] RPC: Registered tcp NFSv4.1 backchannel transport module.
1277 06:18:33.586778 <6>[ 0.684972] PCI: CLS 0 bytes, default 64
1278 06:18:33.592274 <6>[ 0.689293] Unpacking initramfs...
1279 06:18:33.597797 <6>[ 0.695436] kvm [1]: nv: 529 coarse grained trap handlers
1280 06:18:33.603308 <6>[ 0.698618] kvm [1]: IPA Size Limit: 40 bits
1281 06:18:33.603767 <6>[ 0.704253] kvm [1]: vgic interrupt IRQ9
1282 06:18:33.608817 <6>[ 0.706985] kvm [1]: Hyp nVHE mode initialized successfully
1283 06:18:33.614342 <5>[ 0.713979] Initialise system trusted keyrings
1284 06:18:33.619858 <6>[ 0.717636] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1285 06:18:33.625359 <6>[ 0.724267] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1286 06:18:33.631197 <5>[ 0.730350] NFS: Registering the id_resolver key type
1287 06:18:33.636443 <5>[ 0.735361] Key type id_resolver registered
1288 06:18:33.641949 <5>[ 0.739736] Key type id_legacy registered
1289 06:18:33.647451 <6>[ 0.743972] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1290 06:18:33.658510 <6>[ 0.750860] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1291 06:18:33.662385 <6>[ 0.758652] 9p: Installing v9fs 9p2000 file system support
1292 06:18:33.700452 <5>[ 0.805298] Key type asymmetric registered
1293 06:18:33.705909 <5>[ 0.805335] Asymmetric key parser 'x509' registered
1294 06:18:33.716990 <6>[ 0.809200] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1295 06:18:33.717549 <6>[ 0.816723] io scheduler mq-deadline registered
1296 06:18:33.722441 <6>[ 0.821457] io scheduler kyber registered
1297 06:18:33.728006 <6>[ 0.825731] io scheduler bfq registered
1298 06:18:33.734503 <6>[ 0.833657] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1299 06:18:33.779592 <6>[ 0.880516] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1300 06:18:33.799808 <6>[ 0.893470] Serial: 8250/16550 driver, 4 port<6>[ 0.898033] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1301 06:18:33.805360 <6>[ 0.907656] printk: legacy console [ttyAML0] enabled
1302 06:18:33.810884 <6>[ 0.907656] printk: legacy console [ttyAML0] enabled
1303 06:18:33.816435 <6>[ 0.912447] printk: legacy bootconsole [meson0] disabled
1304 06:18:33.821998 <6>[ 0.912447] printk: legacy bootconsole [meson0] disabled
1305 06:18:33.827508 <6>[ 0.928727] msm_serial: driver initialized
1306 06:18:33.833153 <6>[ 0.929207] SuperH (H)SCI(F) driver initialized
1307 06:18:33.833712 <6>[ 0.932883] STM32 USART driver initialized
1308 06:18:33.838685 <5>[ 0.938995] random: crng init done
1309 06:18:33.845468 <6>[ 0.944445] loop: module loaded
1310 06:18:33.845975 <6>[ 0.945685] megasas: 07.727.03.00-rc1
1311 06:18:33.850995 <6>[ 0.954768] tun: Universal TUN/TAP device driver, 1.6
1312 06:18:33.856574 <6>[ 0.955957] thunder_xcv, ver 1.0
1313 06:18:33.857133 <6>[ 0.957933] thunder_bgx, ver 1.0
1314 06:18:33.862085 <6>[ 0.961407] nicpf, ver 1.0
1315 06:18:33.867647 <6>[ 0.965879] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1316 06:18:33.873163 <6>[ 0.971792] hns3: Copyright (c) 2017 Huawei Corporation.
1317 06:18:33.878784 <6>[ 0.977378] hclge is initializing
1318 06:18:33.884249 <6>[ 0.980922] e1000: Intel(R) PRO/1000 Network Driver
1319 06:18:33.889847 <6>[ 0.986000] e1000: Copyright (c) 1999-2006 Intel Corporation.
1320 06:18:33.895332 <6>[ 0.992017] e1000e: Intel(R) PRO/1000 Network Driver
1321 06:18:33.900908 <6>[ 0.997180] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1322 06:18:33.906469 <6>[ 1.003368] igb: Intel(R) Gigabit Ethernet Network Driver
1323 06:18:33.912016 <6>[ 1.008965] igb: Copyright (c) 2007-2014 Intel Corporation.
1324 06:18:33.917546 <6>[ 1.014801] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1325 06:18:33.923120 <6>[ 1.021273] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1326 06:18:33.928691 <6>[ 1.028029] sky2: driver version 1.30
1327 06:18:33.934284 <6>[ 1.032923] VFIO - User Level meta-driver version: 0.3
1328 06:18:33.939843 <6>[ 1.040426] usbcore: registered new interface driver usb-storage
1329 06:18:33.945739 <6>[ 1.046661] i2c_dev: i2c /dev entries driver
1330 06:18:33.958129 <6>[ 1.057469] sdhci: Secure Digital Host Controller Interface driver
1331 06:18:33.958631 <6>[ 1.058273] sdhci: Copyright(c) Pierre Ossman
1332 06:18:33.969207 <6>[ 1.063912] Synopsys Designware Multimedia Card Interface Driver
1333 06:18:33.974843 <6>[ 1.070452] sdhci-pltfm: SDHCI platform and OF driver helper
1334 06:18:33.980290 <6>[ 1.078060] ledtrig-cpu: registered to indicate activity on CPUs
1335 06:18:33.985858 <6>[ 1.082105] meson-sm: secure-monitor enabled
1336 06:18:33.993920 <6>[ 1.086999] usbcore: registered new interface driver usbhid
1337 06:18:33.994429 <6>[ 1.091569] usbhid: USB HID core driver
1338 06:18:34.001155 <6>[ 1.106012] NET: Registered PF_PACKET protocol family
1339 06:18:34.006776 <6>[ 1.106104] 9pnet: Installing 9P2000 support
1340 06:18:34.013627 <5>[ 1.110259] Key type dns_resolver registered
1341 06:18:34.015652 <6>[ 1.121712] registered taskstats version 1
1342 06:18:34.021276 <5>[ 1.121970] Loading compiled-in X.509 certificates
1343 06:18:34.027534 <6>[ 1.130631] Demotion targets for Node 0: null
1344 06:18:34.063643 <6>[ 1.168350] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1345 06:18:34.068992 <6>[ 1.168394] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1346 06:18:34.080076 <4>[ 1.178571] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1347 06:18:34.085685 <4>[ 1.181173] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1348 06:18:34.091166 <6>[ 1.188739] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1349 06:18:34.096843 <6>[ 1.199348] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1350 06:18:34.107825 <6>[ 1.201501] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1351 06:18:34.118917 <6>[ 1.209445] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1352 06:18:34.124471 <6>[ 1.218995] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1353 06:18:34.129980 <6>[ 1.225191] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1354 06:18:34.135591 <6>[ 1.230802] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1355 06:18:34.141091 <6>[ 1.238691] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1356 06:18:34.146685 <6>[ 1.246055] hub 1-0:1.0: USB hub found
1357 06:18:34.152260 <6>[ 1.249461] hub 1-0:1.0: 2 ports detected
1358 06:18:34.157832 <6>[ 1.255531] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1359 06:18:34.163339 <6>[ 1.262473] hub 2-0:1.0: USB hub found
1360 06:18:34.167392 <6>[ 1.266012] hub 2-0:1.0: 1 port detected
1361 06:18:34.187649 <6>[ 1.289957] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1362 06:18:34.203951 <6>[ 1.305982] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1363 06:18:34.242255 <6>[ 1.344046] Trying to probe devices needed for running init ...
1364 06:18:34.407445 <6>[ 1.507962] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1365 06:18:34.547960 <6>[ 1.647240] mmc0: new ultra high speed SDR104 SDXC card at address e624
1366 06:18:34.553548 <6>[ 1.649219] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1367 06:18:34.553880 <6>[ 1.654994] mmcblk0: p1
1368 06:18:34.557329 <6>[ 1.660279] Freeing initrd memory: 22704K
1369 06:18:34.620936 <6>[ 1.725801] hub 1-1:1.0: USB hub found
1370 06:18:34.626655 <6>[ 1.726114] hub 1-1:1.0: 4 ports detected
1371 06:18:34.691479 <6>[ 1.792101] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1372 06:18:34.733641 <6>[ 1.838508] hub 2-1:1.0: USB hub found
1373 06:18:34.739489 <6>[ 1.839353] hub 2-1:1.0: 4 ports detected
1374 06:18:46.543142 <6>[ 13.647995] clk: Disabling unused clocks
1375 06:18:46.548544 <6>[ 13.648164] PM: genpd: Disabling unused power domains
1376 06:18:46.556780 <6>[ 13.651855] ALSA device list:
1377 06:18:46.557058 <6>[ 13.655055] No soundcards found.
1378 06:18:46.562354 <6>[ 13.666957] Freeing unused kernel memory: 10240K
1379 06:18:46.568231 <6>[ 13.667040] Run /init as init process
1380 06:18:46.574708 Loading, please wait...
1381 06:18:46.606868 Starting systemd-udevd version 252.22-1~deb12u1
1382 06:18:47.041500 <4>[ 14.140399] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1383 06:18:47.053662 <6>[ 14.156528] mc: Linux media interface: v0.10
1384 06:18:47.117988 <3>[ 14.217442] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1385 06:18:47.123574 <6>[ 14.223113] panfrost ffe40000.gpu: clock rate = 24000000
1386 06:18:47.134612 <3>[ 14.225446] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1387 06:18:47.140204 <6>[ 14.226903] videodev: Linux video capture interface: v2.00
1388 06:18:47.145744 <6>[ 14.227377] meson-vrtc ff8000a8.rtc: registered as rtc0
1389 06:18:47.151319 <6>[ 14.227414] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1390 06:18:47.156956 <6>[ 14.227797] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1391 06:18:47.162447 <6>[ 14.227809] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1392 06:18:47.173540 <6>[ 14.227814] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1393 06:18:47.178986 <6>[ 14.227895] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1394 06:18:47.184652 <6>[ 14.234746] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1395 06:18:47.190235 <6>[ 14.286907] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1396 06:18:47.195702 <6>[ 14.292363] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1397 06:18:47.201258 <6>[ 14.297771] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1398 06:18:47.212355 <6>[ 14.298303] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1399 06:18:47.217898 <6>[ 14.298319] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1400 06:18:47.234893 <6>[ 14.298326] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1401 06:18:47.240073 <6>[ 14.298335] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1402 06:18:47.245620 <6>[ 14.300071] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1403 06:18:47.251172 <6>[ 14.300077] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1404 06:18:47.256714 <6>[ 14.300081] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1405 06:18:47.267807 <6>[ 14.300087] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1406 06:18:47.273379 <6>[ 14.306981] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1407 06:18:47.278904 <6>[ 14.316249] Registered IR keymap rc-empty
1408 06:18:47.284511 <6>[ 14.322257] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1409 06:18:47.289983 <6>[ 14.322265] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1410 06:18:47.295627 <6>[ 14.335683] usbcore: registered new device driver onboard-usb-dev
1411 06:18:47.306619 <6>[ 14.346890] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1412 06:18:47.317720 <6>[ 14.352302] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1413 06:18:47.323280 <6>[ 14.355114] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1414 06:18:47.328915 <6>[ 14.357361] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 0
1415 06:18:47.339908 <4>[ 14.376923] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1416 06:18:47.345522 <6>[ 14.383731] rc rc0: sw decoder init
1417 06:18:47.356661 <6>[ 14.388209] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1418 06:18:47.362108 <6>[ 14.393277] meson-ir ff808000.ir: receiver initialized
1419 06:18:47.367640 <6>[ 14.399704] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1420 06:18:47.373245 <6>[ 14.416887] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1421 06:18:47.384299 <6>[ 14.419016] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1422 06:18:47.389848 <3>[ 14.486496] meson-drm ff900000.vpu: DSI transceiver device is disabled
1423 06:18:47.397173 <6>[ 14.493602] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 1
1424 06:18:47.591708 <6>[ 14.672723] Console: switching to colour frame buffer device 128x48
1425 06:18:47.597457 <6>[ 14.691854] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1426 06:18:47.836926 <6>[ 14.941779] hub 1-1:1.0: USB hub found
1427 06:18:47.842327 <6>[ 14.942071] hub 1-1:1.0: 4 ports detected
1428 06:18:47.848769 <6>[ 14.946797] onboard-usb-dev 1-1: USB disconnect, device number 2
1429 06:18:47.979551 Begin: Loading essential drivers ... done.
1430 06:18:47.985074 Begin: Running /scripts/init-premount ... done.
1431 06:18:47.990567 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1432 06:18:48.001704 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1433 06:18:48.002210 Device /sys/class/net/end0 found
1434 06:18:48.002620 done.
1435 06:18:48.010553 Begin: Waiting up to 180 secs for any network device to become available ... done.
1436 06:18:48.061303 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.158349] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1437 06:18:48.061823
1438 06:18:48.159324 <6>[ 15.256125] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=32)
1439 06:18:48.172841 <6>[ 15.272166] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1440 06:18:48.178333 <6>[ 15.274358] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1441 06:18:48.187726 <6>[ 15.281707] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1442 06:18:48.209290 <6>[ 15.309745] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1443 06:18:48.355383 <6>[ 15.456005] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1444 06:18:48.541031 <6>[ 15.645886] hub 1-1:1.0: USB hub found
1445 06:18:48.546768 <6>[ 15.646362] hub 1-1:1.0: 4 ports detected
1446 06:18:49.624506 IP-Config: no response after 2 secs - giving up
1447 06:18:49.686421 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1448 06:18:51.146944 <6>[ 18.245760] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1449 06:18:51.691075 <4>[ 18.795967] rc rc0: two consecutive events of type space
1450 06:18:52.889486 IP-Config: no response after 3 secs - giving up
1451 06:18:52.954275 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1452 06:18:56.513073 IP-Config: end0 guessed broadcast address 192.168.6.255
1453 06:18:56.518399 IP-Config: end0 complete (dhcp from 192.168.6.1):
1454 06:18:56.524054 address: 192.168.6.33 broadcast: 192.168.6.255 netmask: 255.255.255.0
1455 06:18:56.534962 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1456 06:18:56.535470 rootserver: 192.168.6.1 rootpath:
1457 06:18:56.538477 filename :
1458 06:18:56.621117 done.
1459 06:18:56.627071 Begin: Running /scripts/nfs-bottom ... done.
1460 06:18:56.644077 Begin: Running /scripts/init-bottom ... done.
1461 06:18:56.976252 <30>[ 24.076610] systemd[1]: System time before build time, advancing clock.
1462 06:18:57.027488 <6>[ 24.132261] NET: Registered PF_INET6 protocol family
1463 06:18:57.033112 <6>[ 24.134008] Segment Routing with IPv6
1464 06:18:57.038195 <6>[ 24.135770] In-situ OAM (IOAM) with IPv6
1465 06:18:57.111090 <30>[ 24.188118] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1466 06:18:57.116542 <30>[ 24.215981] systemd[1]: Detected architecture arm64.
1467 06:18:57.117043
1468 06:18:57.124085 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1469 06:18:57.124553
1470 06:18:57.140363 <30>[ 24.241501] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1471 06:18:57.798972 <30>[ 24.898796] systemd[1]: Queued start job for default target graphical.target.
1472 06:18:57.843119 <30>[ 24.942370] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1473 06:18:57.850734 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1474 06:18:57.865733 <30>[ 24.964928] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1475 06:18:57.874028 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1476 06:18:57.889690 <30>[ 24.988979] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1477 06:18:57.898915 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1478 06:18:57.913334 <30>[ 25.012703] systemd[1]: Created slice user.slice - User and Session Slice.
1479 06:18:57.920029 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1480 06:18:57.938908 <30>[ 25.032211] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1481 06:18:57.942660 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1482 06:18:57.956978 <30>[ 25.056139] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1483 06:18:57.966788 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1484 06:18:57.991793 <30>[ 25.080112] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1485 06:18:57.997379 <30>[ 25.094180] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1486 06:18:58.006517 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1487 06:18:58.020634 <30>[ 25.120028] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1488 06:18:58.028840 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1489 06:18:58.040600 <30>[ 25.140039] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1490 06:18:58.050124 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1491 06:18:58.064636 <30>[ 25.164039] systemd[1]: Reached target paths.target - Path Units.
1492 06:18:58.069708 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1493 06:18:58.084622 <30>[ 25.184025] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1494 06:18:58.091947 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1495 06:18:58.104610 <30>[ 25.204004] systemd[1]: Reached target slices.target - Slice Units.
1496 06:18:58.110089 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1497 06:18:58.124655 <30>[ 25.224030] systemd[1]: Reached target swap.target - Swaps.
1498 06:18:58.128645 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1499 06:18:58.144629 <30>[ 25.244048] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1500 06:18:58.153609 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1501 06:18:58.164837 <30>[ 25.264223] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1502 06:18:58.174103 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1503 06:18:58.190539 <30>[ 25.289939] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1504 06:18:58.199392 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1505 06:18:58.213490 <30>[ 25.312831] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1506 06:18:58.222829 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1507 06:18:58.237017 <30>[ 25.336360] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1508 06:18:58.244240 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1509 06:18:58.257490 <30>[ 25.356936] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1510 06:18:58.266652 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1511 06:18:58.282466 <30>[ 25.381829] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1512 06:18:58.288063 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1513 06:18:58.304852 <30>[ 25.404258] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1514 06:18:58.313743 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1515 06:18:58.348815 <30>[ 25.448149] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1516 06:18:58.355507 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1517 06:18:58.374940 <30>[ 25.474331] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1518 06:18:58.382438 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1519 06:18:58.403193 <30>[ 25.502619] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1520 06:18:58.410601 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1521 06:18:58.434439 <30>[ 25.528341] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1522 06:18:58.445580 <30>[ 25.541453] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1523 06:18:58.452794 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1524 06:18:58.467363 <30>[ 25.566760] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1525 06:18:58.475352 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1526 06:18:58.491466 <30>[ 25.590882] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1527 06:18:58.499160 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1528 06:18:58.519606 <30>[ 25.618879] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1529 06:18:58.530626 <6>[ 25.622801] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1530 06:18:58.535541 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1531 06:18:58.555398 <30>[ 25.654780] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1532 06:18:58.563805 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1533 06:18:58.579354 <30>[ 25.678676] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1534 06:18:58.586614 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1535 06:18:58.600417 <6>[ 25.703456] fuse: init (API version 7.40)
1536 06:18:58.619590 <30>[ 25.718900] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1537 06:18:58.626830 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1538 06:18:58.649979 <30>[ 25.749159] systemd[1]: Starting systemd-journald.service - Journal Service...
1539 06:18:58.656286 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1540 06:18:58.679684 <30>[ 25.778990] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1541 06:18:58.687202 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1542 06:18:58.710453 <30>[ 25.809878] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1543 06:18:58.719789 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1544 06:18:58.789266 <30>[ 25.888557] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1545 06:18:58.797969 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1546 06:18:58.821507 <30>[ 25.920811] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1547 06:18:58.829601 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1548 06:18:58.852790 <30>[ 25.952150] systemd[1]: Started systemd-journald.service - Journal Service.
1549 06:18:58.859543 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1550 06:18:58.876554 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1551 06:18:58.893794 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1552 06:18:58.905841 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1553 06:18:58.918479 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1554 06:18:58.935538 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1555 06:18:58.955593 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1556 06:18:58.971522 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1557 06:18:58.987961 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1558 06:18:59.003385 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1559 06:18:59.019500 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1560 06:18:59.034862 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1561 06:18:59.050574 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1562 06:18:59.066644 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1563 06:18:59.083519 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1564 06:18:59.099245 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1565 06:18:59.156643 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1566 06:18:59.173427 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1567 06:18:59.192998 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1568 06:18:59.213618 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1569 06:18:59.230291 <46>[ 26.329506] systemd-journald[231]: Received client request to flush runtime journal.
1570 06:18:59.237517 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1571 06:18:59.317699 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1572 06:18:59.356437 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1573 06:18:59.374857 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1574 06:18:59.387206 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1575 06:18:59.403482 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1576 06:18:59.447196 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1577 06:18:59.492844 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1578 06:18:59.508835 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1579 06:18:59.584610 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1580 06:18:59.597746 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1581 06:18:59.608640 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1582 06:18:59.648866 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1583 06:18:59.665562 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1584 06:18:59.884937 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1585 06:18:59.941470 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1586 06:18:59.964209 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1587 06:19:00.041688 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1588 06:19:00.112591 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1589 06:19:00.132795 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1590 06:19:00.195262 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1591 06:19:00.216180 <5>[ 27.315716] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1592 06:19:00.228342 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1593 06:19:00.265935 <5>[ 27.365354] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1594 06:19:00.271449 <5>[ 27.366021] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1595 06:19:00.282568 [<4>[ 27.373602] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1596 06:19:00.282932 <6>[ 27.382414] cfg80211: failed to load regulatory.db
1597 06:19:00.293329 [0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1598 06:19:00.309358 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1599 06:19:00.332314 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1600 06:19:00.354432 <46>[ 27.442645] systemd-journald[231]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1601 06:19:00.368221 <46>[ 27.455200] systemd-journald[231]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1602 06:19:00.410082 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1603 06:19:00.428433 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1604 06:19:00.443237 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1605 06:19:00.493997 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1606 06:19:00.511131 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1607 06:19:00.528459 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1608 06:19:00.541881 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1609 06:19:00.555806 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1610 06:19:00.568759 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1611 06:19:00.586356 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1612 06:19:00.625707 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1613 06:19:00.641352 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1614 06:19:00.655611 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1615 06:19:00.675191 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1616 06:19:00.693103 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1617 06:19:00.703587 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1618 06:19:00.718420 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1619 06:19:00.735811 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1620 06:19:00.747451 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1621 06:19:00.784354 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1622 06:19:00.798264 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1623 06:19:00.818766 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1624 06:19:00.885951 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1625 06:19:00.905836 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1626 06:19:00.921623 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1627 06:19:00.952286 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1628 06:19:00.967706 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1629 06:19:00.983518 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1630 06:19:00.997031 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1631 06:19:01.060343 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1632 06:19:01.080376 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1633 06:19:01.091949 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1634 06:19:01.104537 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1635 06:19:01.118158 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1636 06:19:01.132912 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1637 06:19:01.160659 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1638 06:19:01.208290 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1639 06:19:01.267614
1640 06:19:01.268333 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1641 06:19:01.268832
1642 06:19:01.274794 debian-bookworm-arm64 login: root (automatic login)
1643 06:19:01.275351
1644 06:19:01.402176 Linux debian-bookworm-arm64 6.11.0-rc5 #1 SMP PREEMPT Sat Aug 31 04:48:52 UTC 2024 aarch64
1645 06:19:01.402599
1646 06:19:01.407809 The programs included with the Debian GNU/Linux system are free software;
1647 06:19:01.413396 the exact distribution terms for each program are described in the
1648 06:19:01.418880 individual files in /usr/share/doc/*/copyright.
1649 06:19:01.419193
1650 06:19:01.424726 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1651 06:19:01.427516 permitted by applicable law.
1652 06:19:02.121337 Matched prompt #10: / #
1654 06:19:02.122267 Setting prompt string to ['/ #']
1655 06:19:02.122606 end: 2.4.4.1 login-action (duration 00:00:30) [common]
1657 06:19:02.123396 end: 2.4.4 auto-login-action (duration 00:00:30) [common]
1658 06:19:02.123716 start: 2.4.5 expect-shell-connection (timeout 00:03:13) [common]
1659 06:19:02.123965 Setting prompt string to ['/ #']
1660 06:19:02.124241 Forcing a shell prompt, looking for ['/ #']
1662 06:19:02.174826 / #
1663 06:19:02.175349 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1664 06:19:02.175688 Waiting using forced prompt support (timeout 00:02:30)
1665 06:19:02.180168
1666 06:19:02.181175 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1667 06:19:02.181881 start: 2.4.6 export-device-env (timeout 00:03:13) [common]
1668 06:19:02.182425 Sending with 10 millisecond of delay
1670 06:19:07.175535 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_'
1671 06:19:07.186491 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/681515/extract-nfsrootfs-t25q4sk_'
1672 06:19:07.187240 Sending with 10 millisecond of delay
1674 06:19:09.287020 / # export NFS_SERVER_IP='192.168.6.2'
1675 06:19:09.298052 export NFS_SERVER_IP='192.168.6.2'
1676 06:19:09.299024 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1677 06:19:09.299699 end: 2.4 uboot-commands (duration 00:01:54) [common]
1678 06:19:09.300488 end: 2 uboot-action (duration 00:01:54) [common]
1679 06:19:09.301203 start: 3 lava-test-retry (timeout 00:06:48) [common]
1680 06:19:09.301864 start: 3.1 lava-test-shell (timeout 00:06:48) [common]
1681 06:19:09.302428 Using namespace: common
1683 06:19:09.403749 / # #
1684 06:19:09.404580 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1685 06:19:09.412170 #
1686 06:19:09.413240 Using /lava-681515
1688 06:19:09.514725 / # export SHELL=/bin/bash
1689 06:19:09.521639 export SHELL=/bin/bash
1691 06:19:09.623264 / # . /lava-681515/environment
1692 06:19:09.628535 . /lava-681515/environment
1694 06:19:09.734075 / # /lava-681515/bin/lava-test-runner /lava-681515/0
1695 06:19:09.735046 Test shell timeout: 10s (minimum of the action and connection timeout)
1696 06:19:09.739445 /lava-681515/bin/lava-test-runner /lava-681515/0
1697 06:19:09.928535 + export TESTRUN_ID=0_timesync-off
1698 06:19:09.936345 + TESTRUN_ID=0_timesync-off
1699 06:19:09.936956 + cd /lava-681515/0/tests/0_timesync-off
1700 06:19:09.937513 ++ cat uuid
1701 06:19:09.945049 + UUID=681515_1.6.2.4.1
1702 06:19:09.945640 + set +x
1703 06:19:09.952939 <LAVA_SIGNAL_STARTRUN 0_timesync-off 681515_1.6.2.4.1>
1704 06:19:09.953532 + systemctl stop systemd-timesyncd
1705 06:19:09.954383 Received signal: <STARTRUN> 0_timesync-off 681515_1.6.2.4.1
1706 06:19:09.954954 Starting test lava.0_timesync-off (681515_1.6.2.4.1)
1707 06:19:09.955632 Skipping test definition patterns.
1708 06:19:10.000198 + set +x
1709 06:19:10.000799 <LAVA_SIGNAL_ENDRUN 0_timesync-off 681515_1.6.2.4.1>
1710 06:19:10.001506 Received signal: <ENDRUN> 0_timesync-off 681515_1.6.2.4.1
1711 06:19:10.002070 Ending use of test pattern.
1712 06:19:10.002508 Ending test lava.0_timesync-off (681515_1.6.2.4.1), duration 0.05
1714 06:19:10.080164 + export TESTRUN_ID=1_kselftest-alsa
1715 06:19:10.087027 + TESTRUN_ID=1_kselftest-alsa
1716 06:19:10.087533 + cd /lava-681515/0/tests/1_kselftest-alsa
1717 06:19:10.087965 ++ cat uuid
1718 06:19:10.092392 + UUID=681515_1.6.2.4.5
1719 06:19:10.092838 + set +x
1720 06:19:10.098040 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 681515_1.6.2.4.5>
1721 06:19:10.098488 + cd ./automated/linux/kselftest/
1722 06:19:10.099196 Received signal: <STARTRUN> 1_kselftest-alsa 681515_1.6.2.4.5
1723 06:19:10.099640 Starting test lava.1_kselftest-alsa (681515_1.6.2.4.5)
1724 06:19:10.100160 Skipping test definition patterns.
1725 06:19:10.126640 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1726 06:19:10.157207 INFO: install_deps skipped
1727 06:19:10.268039 --2024-08-31 06:19:10-- http://storage.kernelci.org/mainline/master/v6.11-rc5-219-g1934261d89746/arm64/defconfig/gcc-12/kselftest.tar.xz
1728 06:19:10.298982 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1729 06:19:10.439325 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1730 06:19:10.579326 HTTP request sent, awaiting response... 200 OK
1731 06:19:10.579833 Length: 6239528 (6.0M) [application/octet-stream]
1732 06:19:10.584674 Saving to: 'kselftest_armhf.tar.gz'
1733 06:19:10.585060
1734 06:19:11.744595
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 49.92K 180KB/s
kselftest_armhf.tar 3%[ ] 218.67K 394KB/s
kselftest_armhf.tar 14%[=> ] 891.29K 1.05MB/s
kselftest_armhf.tar 58%[==========> ] 3.51M 3.17MB/s
kselftest_armhf.tar 100%[===================>] 5.95M 5.13MB/s in 1.2s
1735 06:19:11.745268
1736 06:19:11.846947 2024-08-31 06:19:11 (5.13 MB/s) - 'kselftest_armhf.tar.gz' saved [6239528/6239528]
1737 06:19:11.847414
1738 06:19:20.187540 skiplist:
1739 06:19:20.188363 ========================================
1740 06:19:20.193139 ========================================
1741 06:19:20.233952 alsa:mixer-test
1742 06:19:20.234567 alsa:pcm-test
1743 06:19:20.235086 alsa:test-pcmtest-driver
1744 06:19:20.247329 ============== Tests to run ===============
1745 06:19:20.247909 alsa:mixer-test
1746 06:19:20.253083 alsa:pcm-test
1747 06:19:20.253641 alsa:test-pcmtest-driver
1748 06:19:20.258948 ===========End Tests to run ===============
1749 06:19:20.259500 shardfile-alsa pass
1750 06:19:20.357093 <12>[ 47.460548] kselftest: Running tests in alsa
1751 06:19:20.362517 TAP version 13
1752 06:19:20.370858 1..3
1753 06:19:20.391662 # timeout set to 45
1754 06:19:20.392089 # selftests: alsa: mixer-test
1755 06:19:20.552667 # TAP version 13
1756 06:19:20.553071 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1757 06:19:20.558241 # 1..427
1758 06:19:20.558679 # ok 1 get_value.LCALTA.60
1759 06:19:20.559016 # # LCALTA.60 TDMOUT_A SRC SEL
1760 06:19:20.563719 # ok 2 name.LCALTA.60
1761 06:19:20.564031 # ok 3 write_default.LCALTA.60
1762 06:19:20.569273 # ok 4 write_valid.LCALTA.60
1763 06:19:20.569564 # ok 5 write_invalid.LCALTA.60
1764 06:19:20.574723 # ok 6 event_missing.LCALTA.60
1765 06:19:20.575015 # ok 7 event_spurious.LCALTA.60
1766 06:19:20.580332 # ok 8 get_value.LCALTA.59
1767 06:19:20.580618 # # LCALTA.59 TDMOUT_B SRC SEL
1768 06:19:20.585962 # ok 9 name.LCALTA.59
1769 06:19:20.586250 # ok 10 write_default.LCALTA.59
1770 06:19:20.591537 # ok 11 write_valid.LCALTA.59
1771 06:19:20.591825 # ok 12 write_invalid.LCALTA.59
1772 06:19:20.597030 # ok 13 event_missing.LCALTA.59
1773 06:19:20.597328 # ok 14 event_spurious.LCALTA.59
1774 06:19:20.602581 # ok 15 get_value.LCALTA.58
1775 06:19:20.602873 # # LCALTA.58 TDMOUT_C SRC SEL
1776 06:19:20.608240 # ok 16 name.LCALTA.58
1777 06:19:20.608542 # ok 17 write_default.LCALTA.58
1778 06:19:20.613614 # ok 18 write_valid.LCALTA.58
1779 06:19:20.613904 # ok 19 write_invalid.LCALTA.58
1780 06:19:20.619246 # ok 20 event_missing.LCALTA.58
1781 06:19:20.619529 # ok 21 event_spurious.LCALTA.58
1782 06:19:20.624701 # ok 22 get_value.LCALTA.57
1783 06:19:20.625000 # # LCALTA.57 TDMIN_A SRC SEL
1784 06:19:20.625220 # ok 23 name.LCALTA.57
1785 06:19:20.630280 # ok 24 write_default.LCALTA.57
1786 06:19:20.630568 # ok 25 write_valid.LCALTA.57
1787 06:19:20.635773 # ok 26 write_invalid.LCALTA.57
1788 06:19:20.636083 # ok 27 event_missing.LCALTA.57
1789 06:19:20.641344 # ok 28 event_spurious.LCALTA.57
1790 06:19:20.641642 # ok 29 get_value.LCALTA.56
1791 06:19:20.646855 # # LCALTA.56 TDMIN_B SRC SEL
1792 06:19:20.647147 # ok 30 name.LCALTA.56
1793 06:19:20.652471 # ok 31 write_default.LCALTA.56
1794 06:19:20.663513 # ok 32 write_val<3>[ 47.755687] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1795 06:19:20.663850 id.LCALTA.56
1796 06:19:20.669118 # ok 33 write_invalid.LCALTA.56
1797 06:19:20.669410 # ok 34 event_missing.LCALTA.56
1798 06:19:20.674581 # ok 35 event_spurious.LCALTA.56
1799 06:19:20.674864 # ok 36 get_value.LCALTA.55
1800 06:19:20.680253 # # LCALTA.55 TDMIN_C SRC SEL
1801 06:19:20.680544 # ok 37 name.LCALTA.55
1802 06:19:20.685681 # ok 38 write_default.LCALTA.55
1803 06:19:20.685969 # ok 39 write_valid.LCALTA.55
1804 06:19:20.691245 # ok 40 write_invalid.LCALTA.55
1805 06:19:20.691532 # ok 41 event_missing.LCALTA.55
1806 06:19:20.696774 # ok 42 event_spurious.LCALTA.55
1807 06:19:20.697062 # ok 43 get_value.LCALTA.54
1808 06:19:20.702310 # # LCALTA.54 ACODEC Left DAC Sel
1809 06:19:20.702592 # ok 44 name.LCALTA.54
1810 06:19:20.707925 # ok 45 write_default.LCALTA.54
1811 06:19:20.708233 # ok 46 write_valid.LCALTA.54
1812 06:19:20.713408 # ok 47 write_invalid.LCALTA.54
1813 06:19:20.713691 # ok 48 event_missing.LCALTA.54
1814 06:19:20.718984 # ok 49 event_spurious.LCALTA.54
1815 06:19:20.719268 # ok 50 get_value.LCALTA.53
1816 06:19:20.724503 # # LCALTA.53 ACODEC Right DAC Sel
1817 06:19:20.724798 # ok 51 name.LCALTA.53
1818 06:19:20.730112 # ok 52 write_default.LCALTA.53
1819 06:19:20.730401 # ok 53 write_valid.LCALTA.53
1820 06:19:20.735653 # ok 54 write_invalid.LCALTA.53
1821 06:19:20.735955 # ok 55 event_missing.LCALTA.53
1822 06:19:20.741267 # ok 56 event_spurious.LCALTA.53
1823 06:19:20.741581 # ok 57 get_value.LCALTA.52
1824 06:19:20.746690 # # LCALTA.52 TOACODEC OUT EN Switch
1825 06:19:20.746999 # ok 58 name.LCALTA.52
1826 06:19:20.752264 # ok 59 write_default.LCALTA.52
1827 06:19:20.752564 # ok 60 write_valid.LCALTA.52
1828 06:19:20.757774 # ok 61 write_invalid.LCALTA.52
1829 06:19:20.758071 # ok 62 event_missing.LCALTA.52
1830 06:19:20.763315 # ok 63 event_spurious.LCALTA.52
1831 06:19:20.763604 # ok 64 get_value.LCALTA.51
1832 06:19:20.768888 # # LCALTA.51 TOACODEC SRC
1833 06:19:20.769185 # ok 65 name.LCALTA.51
1834 06:19:20.774413 # ok 66 write_default.LCALTA.51
1835 06:19:20.774700 # ok 67 write_valid.LCALTA.51
1836 06:19:20.779945 # ok 68 write_invalid.LCALTA.51
1837 06:19:20.780243 # ok 69 event_missing.LCALTA.51
1838 06:19:20.785515 # ok 70 event_spurious.LCALTA.51
1839 06:19:20.785796 # ok 71 get_value.LCALTA.50
1840 06:19:20.791161 # # LCALTA.50 TOHDMITX SPDIF SRC
1841 06:19:20.791455 # ok 72 name.LCALTA.50
1842 06:19:20.791674 # ok 73 write_default.LCALTA.50
1843 06:19:20.796683 # ok 74 write_valid.LCALTA.50
1844 06:19:20.796958 # ok 75 write_invalid.LCALTA.50
1845 06:19:20.802279 # ok 76 event_missing.LCALTA.50
1846 06:19:20.807742 # ok 77 event_spurious.LCALTA.50
1847 06:19:20.808051 # ok 78 get_value.LCALTA.49
1848 06:19:20.808276 # # LCALTA.49 TOHDMITX Switch
1849 06:19:20.813315 # ok 79 name.LCALTA.49
1850 06:19:20.813599 # ok 80 write_default.LCALTA.49
1851 06:19:20.818821 # ok 81 write_valid.LCALTA.49
1852 06:19:20.819110 # ok 82 write_invalid.LCALTA.49
1853 06:19:20.824474 # ok 83 event_missing.LCALTA.49
1854 06:19:20.824763 # ok 84 event_spurious.LCALTA.49
1855 06:19:20.829895 # ok 85 get_value.LCALTA.48
1856 06:19:20.830195 # # LCALTA.48 TOHDMITX I2S SRC
1857 06:19:20.835453 # ok 86 name.LCALTA.48
1858 06:19:20.835758 # ok 87 write_default.LCALTA.48
1859 06:19:20.840989 # ok 88 write_valid.LCALTA.48
1860 06:19:20.841286 # ok 89 write_invalid.LCALTA.48
1861 06:19:20.846561 # ok 90 event_missing.LCALTA.48
1862 06:19:20.846847 # ok 91 event_spurious.LCALTA.48
1863 06:19:20.852139 # ok 92 get_value.LCALTA.47
1864 06:19:20.852434 # # LCALTA.47 TODDR_C SRC SEL
1865 06:19:20.857629 # ok 93 name.LCALTA.47
1866 06:19:20.857919 # ok 94 write_default.LCALTA.47
1867 06:19:20.863265 # ok 95 write_valid.LCALTA.47
1868 06:19:20.863564 # ok 96 write_invalid.LCALTA.47
1869 06:19:20.868767 # ok 97 event_missing.LCALTA.47
1870 06:19:20.869061 # ok 98 event_spurious.LCALTA.47
1871 06:19:20.874260 # ok 99 get_value.LCALTA.46
1872 06:19:20.874562 # # LCALTA.46 TODDR_B SRC SEL
1873 06:19:20.874779 # ok 100 name.LCALTA.46
1874 06:19:20.879812 # ok 101 write_default.LCALTA.46
1875 06:19:20.885393 # ok 102 write_valid.LCALTA.46
1876 06:19:20.885715 # ok 103 write_invalid.LCALTA.46
1877 06:19:20.890930 # ok 104 event_missing.LCALTA.46
1878 06:19:20.891234 # ok 105 event_spurious.LCALTA.46
1879 06:19:20.896478 # ok 106 get_value.LCALTA.45
1880 06:19:20.896790 # # LCALTA.45 TODDR_A SRC SEL
1881 06:19:20.897041 # ok 107 name.LCALTA.45
1882 06:19:20.902046 # ok 108 write_default.LCALTA.45
1883 06:19:20.907568 # ok 109 write_valid.LCALTA.45
1884 06:19:20.907892 # ok 110 write_invalid.LCALTA.45
1885 06:19:20.913159 # ok 111 event_missing.LCALTA.45
1886 06:19:20.913489 # ok 112 event_spurious.LCALTA.45
1887 06:19:20.918656 # ok 113 get_value.LCALTA.44
1888 06:19:20.918987 # # LCALTA.44 FRDDR_C SINK 3 SEL
1889 06:19:20.924367 # ok 114 name.LCALTA.44
1890 06:19:20.924701 # ok 115 write_default.LCALTA.44
1891 06:19:20.929748 # ok 116 write_valid.LCALTA.44
1892 06:19:20.930086 # ok 117 write_invalid.LCALTA.44
1893 06:19:20.935341 # ok 118 event_missing.LCALTA.44
1894 06:19:20.935688 # ok 119 event_spurious.LCALTA.44
1895 06:19:20.940867 # ok 120 get_value.LCALTA.43
1896 06:19:20.941209 # # LCALTA.43 FRDDR_C SINK 2 SEL
1897 06:19:20.946431 # ok 121 name.LCALTA.43
1898 06:19:20.946778 # ok 122 write_default.LCALTA.43
1899 06:19:20.951967 # ok 123 write_valid.LCALTA.43
1900 06:19:20.952336 # ok 124 write_invalid.LCALTA.43
1901 06:19:20.957493 # ok 125 event_missing.LCALTA.43
1902 06:19:20.957842 # ok 126 event_spurious.LCALTA.43
1903 06:19:20.963051 # ok 127 get_value.LCALTA.42
1904 06:19:20.963403 # # LCALTA.42 FRDDR_C SINK 1 SEL
1905 06:19:20.968614 # ok 128 name.LCALTA.42
1906 06:19:20.968971 # ok 129 write_default.LCALTA.42
1907 06:19:20.974183 # ok 130 write_valid.LCALTA.42
1908 06:19:20.974531 # ok 131 write_invalid.LCALTA.42
1909 06:19:20.979692 # ok 132 event_missing.LCALTA.42
1910 06:19:20.980078 # ok 133 event_spurious.LCALTA.42
1911 06:19:20.985308 # ok 134 get_value.LCALTA.41
1912 06:19:20.985659 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1913 06:19:20.990793 # ok 135 name.LCALTA.41
1914 06:19:20.991149 # ok 136 write_default.LCALTA.41
1915 06:19:20.996350 # ok 137 write_valid.LCALTA.41
1916 06:19:20.996700 # ok 138 write_invalid.LCALTA.41
1917 06:19:21.001888 # ok 139 event_missing.LCALTA.41
1918 06:19:21.002239 # ok 140 event_spurious.LCALTA.41
1919 06:19:21.007414 # ok 141 get_value.LCALTA.40
1920 06:19:21.007761 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1921 06:19:21.012968 # ok 142 name.LCALTA.40
1922 06:19:21.013319 # ok 143 write_default.LCALTA.40
1923 06:19:21.018503 # ok 144 write_valid.LCALTA.40
1924 06:19:21.018854 # ok 145 write_invalid.LCALTA.40
1925 06:19:21.024171 # ok 146 event_missing.LCALTA.40
1926 06:19:21.024737 # ok 147 event_spurious.LCALTA.40
1927 06:19:21.029614 # ok 148 get_value.LCALTA.39
1928 06:19:21.035309 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1929 06:19:21.035776 # ok 149 name.LCALTA.39
1930 06:19:21.036231 # ok 150 write_default.LCALTA.39
1931 06:19:21.041298 # ok 151 write_valid.LCALTA.39
1932 06:19:21.041756 # ok 152 write_invalid.LCALTA.39
1933 06:19:21.046313 # ok 153 event_missing.LCALTA.39
1934 06:19:21.051833 # ok 154 event_spurious.LCALTA.39
1935 06:19:21.052335 # ok 155 get_value.LCALTA.38
1936 06:19:21.057481 # # LCALTA.38 FRDDR_B SINK 3 SEL
1937 06:19:21.057940 # ok 156 name.LCALTA.38
1938 06:19:21.058354 # ok 157 write_default.LCALTA.38
1939 06:19:21.062870 # ok 158 write_valid.LCALTA.38
1940 06:19:21.063323 # ok 159 write_invalid.LCALTA.38
1941 06:19:21.068516 # ok 160 event_missing.LCALTA.38
1942 06:19:21.073984 # ok 161 event_spurious.LCALTA.38
1943 06:19:21.074502 # ok 162 get_value.LCALTA.37
1944 06:19:21.079521 # # LCALTA.37 FRDDR_B SINK 2 SEL
1945 06:19:21.080012 # ok 163 name.LCALTA.37
1946 06:19:21.080438 # ok 164 write_default.LCALTA.37
1947 06:19:21.085055 # ok 165 write_valid.LCALTA.37
1948 06:19:21.090621 # ok 166 write_invalid.LCALTA.37
1949 06:19:21.091085 # ok 167 event_missing.LCALTA.37
1950 06:19:21.096233 # ok 168 event_spurious.LCALTA.37
1951 06:19:21.096757 # ok 169 get_value.LCALTA.36
1952 06:19:21.101734 # # LCALTA.36 FRDDR_B SINK 1 SEL
1953 06:19:21.102248 # ok 170 name.LCALTA.36
1954 06:19:21.107304 # ok 171 write_default.LCALTA.36
1955 06:19:21.107772 # ok 172 write_valid.LCALTA.36
1956 06:19:21.112831 # ok 173 write_invalid.LCALTA.36
1957 06:19:21.113361 # ok 174 event_missing.LCALTA.36
1958 06:19:21.118434 # ok 175 event_spurious.LCALTA.36
1959 06:19:21.119026 # ok 176 get_value.LCALTA.35
1960 06:19:21.123921 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1961 06:19:21.124504 # ok 177 name.LCALTA.35
1962 06:19:21.129441 # ok 178 write_default.LCALTA.35
1963 06:19:21.129942 # ok 179 write_valid.LCALTA.35
1964 06:19:21.135011 # ok 180 write_invalid.LCALTA.35
1965 06:19:21.135604 # ok 181 event_missing.LCALTA.35
1966 06:19:21.140502 # ok 182 event_spurious.LCALTA.35
1967 06:19:21.140990 # ok 183 get_value.LCALTA.34
1968 06:19:21.146077 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1969 06:19:21.146589 # ok 184 name.LCALTA.34
1970 06:19:21.151618 # ok 185 write_default.LCALTA.34
1971 06:19:21.152191 # ok 186 write_valid.LCALTA.34
1972 06:19:21.157196 # ok 187 write_invalid.LCALTA.34
1973 06:19:21.157735 # ok 188 event_missing.LCALTA.34
1974 06:19:21.162685 # ok 189 event_spurious.LCALTA.34
1975 06:19:21.163169 # ok 190 get_value.LCALTA.33
1976 06:19:21.168341 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1977 06:19:21.168874 # ok 191 name.LCALTA.33
1978 06:19:21.173798 # ok 192 write_default.LCALTA.33
1979 06:19:21.174325 # ok 193 write_valid.LCALTA.33
1980 06:19:21.179357 # ok 194 write_invalid.LCALTA.33
1981 06:19:21.179842 # ok 195 event_missing.LCALTA.33
1982 06:19:21.184903 # ok 196 event_spurious.LCALTA.33
1983 06:19:21.185511 # ok 197 get_value.LCALTA.32
1984 06:19:21.190460 # # LCALTA.32 FRDDR_A SINK 3 SEL
1985 06:19:21.190932 # ok 198 name.LCALTA.32
1986 06:19:21.196054 # ok 199 write_default.LCALTA.32
1987 06:19:21.196582 # ok 200 write_valid.LCALTA.32
1988 06:19:21.201564 # ok 201 write_invalid.LCALTA.32
1989 06:19:21.202039 # ok 202 event_missing.LCALTA.32
1990 06:19:21.207172 # ok 203 event_spurious.LCALTA.32
1991 06:19:21.207731 # ok 204 get_value.LCALTA.31
1992 06:19:21.212706 # # LCALTA.31 FRDDR_A SINK 2 SEL
1993 06:19:21.213284 # ok 205 name.LCALTA.31
1994 06:19:21.218228 # ok 206 write_default.LCALTA.31
1995 06:19:21.218751 # ok 207 write_valid.LCALTA.31
1996 06:19:21.223746 # ok 208 write_invalid.LCALTA.31
1997 06:19:21.224302 # ok 209 event_missing.LCALTA.31
1998 06:19:21.229334 # ok 210 event_spurious.LCALTA.31
1999 06:19:21.229809 # ok 211 get_value.LCALTA.30
2000 06:19:21.234870 # # LCALTA.30 FRDDR_A SINK 1 SEL
2001 06:19:21.235403 # ok 212 name.LCALTA.30
2002 06:19:21.240378 # ok 213 write_default.LCALTA.30
2003 06:19:21.240858 # ok 214 write_valid.LCALTA.30
2004 06:19:21.245924 # ok 215 write_invalid.LCALTA.30
2005 06:19:21.251472 # ok 216 event_missing.LCALTA.30
2006 06:19:21.252057 # ok 217 event_spurious.LCALTA.30
2007 06:19:21.256995 # ok 218 get_value.LCALTA.29
2008 06:19:21.257521 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2009 06:19:21.262544 # ok 219 name.LCALTA.29
2010 06:19:21.263067 # ok 220 write_default.LCALTA.29
2011 06:19:21.268140 # ok 221 write_valid.LCALTA.29
2012 06:19:21.268611 # ok 222 write_invalid.LCALTA.29
2013 06:19:21.273683 # ok 223 event_missing.LCALTA.29
2014 06:19:21.274207 # ok 224 event_spurious.LCALTA.29
2015 06:19:21.279313 # ok 225 get_value.LCALTA.28
2016 06:19:21.279865 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2017 06:19:21.284762 # ok 226 name.LCALTA.28
2018 06:19:21.285289 # ok 227 write_default.LCALTA.28
2019 06:19:21.290398 # ok 228 write_valid.LCALTA.28
2020 06:19:21.290945 # ok 229 write_invalid.LCALTA.28
2021 06:19:21.295875 # ok 230 event_missing.LCALTA.28
2022 06:19:21.296440 # ok 231 event_spurious.LCALTA.28
2023 06:19:21.301466 # ok 232 get_value.LCALTA.27
2024 06:19:21.302037 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2025 06:19:21.307037 # ok 233 name.LCALTA.27
2026 06:19:21.308222 # ok 234 write_default.LCALTA.27
2027 06:19:21.313076 # ok 235 write_valid.LCALTA.27
2028 06:19:21.313620 # ok 236 write_invalid.LCALTA.27
2029 06:19:21.318015 # ok 237 event_missing.LCALTA.27
2030 06:19:21.318507 # ok 238 event_spurious.LCALTA.27
2031 06:19:21.323725 # ok 239 get_value.LCALTA.26
2032 06:19:21.324316 # # LCALTA.26 ELD
2033 06:19:21.329162 # ok 240 name.LCALTA.26
2034 06:19:21.329707 # # ELD is not writeable
2035 06:19:21.334687 # ok 241 # SKIP write_default.LCALTA.26
2036 06:19:21.335529 # # ELD is not writeable
2037 06:19:21.340315 # ok 242 # SKIP write_valid.LCALTA.26
2038 06:19:21.340862 # # ELD is not writeable
2039 06:19:21.345781 # ok 243 # SKIP write_invalid.LCALTA.26
2040 06:19:21.346325 # ok 244 event_missing.LCALTA.26
2041 06:19:21.351332 # ok 245 event_spurious.LCALTA.26
2042 06:19:21.351806 # ok 246 get_value.LCALTA.25
2043 06:19:21.356868 # # LCALTA.25 IEC958 Playback Default
2044 06:19:21.357426 # ok 247 name.LCALTA.25
2045 06:19:21.362399 # ok 248 write_default.LCALTA.25
2046 06:19:21.363016 # ok 249 # SKIP write_valid.LCALTA.25
2047 06:19:21.367976 # ok 250 # SKIP write_invalid.LCALTA.25
2048 06:19:21.373605 # ok 251 event_missing.LCALTA.25
2049 06:19:21.374160 # ok 252 event_spurious.LCALTA.25
2050 06:19:21.379122 # ok 253 get_value.LCALTA.24
2051 06:19:21.379661 # # LCALTA.24 IEC958 Playback Mask
2052 06:19:21.380131 # ok 254 name.LCALTA.24
2053 06:19:21.384591 # # IEC958 Playback Mask is not writeable
2054 06:19:21.390156 # ok 255 # SKIP write_default.LCALTA.24
2055 06:19:21.390682 # # IEC958 Playback Mask is not writeable
2056 06:19:21.395683 # ok 256 # SKIP write_valid.LCALTA.24
2057 06:19:21.401299 # # IEC958 Playback Mask is not writeable
2058 06:19:21.401935 # ok 257 # SKIP write_invalid.LCALTA.24
2059 06:19:21.406797 # ok 258 event_missing.LCALTA.24
2060 06:19:21.407337 # ok 259 event_spurious.LCALTA.24
2061 06:19:21.412549 # ok 260 get_value.LCALTA.23
2062 06:19:21.413110 # # LCALTA.23 Playback Channel Map
2063 06:19:21.417988 # ok 261 name.LCALTA.23
2064 06:19:21.423423 # # Playback Channel Map is not writeable
2065 06:19:21.423954 # ok 262 # SKIP write_default.LCALTA.23
2066 06:19:21.428990 # # Playback Channel Map is not writeable
2067 06:19:21.429544 # ok 263 # SKIP write_valid.LCALTA.23
2068 06:19:21.434497 # # Playback Channel Map is not writeable
2069 06:19:21.440165 # ok 264 # SKIP write_invalid.LCALTA.23
2070 06:19:21.440789 # ok 265 event_missing.LCALTA.23
2071 06:19:21.445641 # ok 266 event_spurious.LCALTA.23
2072 06:19:21.446208 # ok 267 get_value.LCALTA.22
2073 06:19:21.451215 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2074 06:19:21.451745 # ok 268 name.LCALTA.22
2075 06:19:21.456853 # ok 269 write_default.LCALTA.22
2076 06:19:21.457390 # ok 270 write_valid.LCALTA.22
2077 06:19:21.462239 # ok 271 write_invalid.LCALTA.22
2078 06:19:21.462790 # ok 272 event_missing.LCALTA.22
2079 06:19:21.467926 # ok 273 event_spurious.LCALTA.22
2080 06:19:21.473544 # ok 274 get_value.LCALTA.21
2081 06:19:21.474218 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2082 06:19:21.474707 # ok 275 name.LCALTA.21
2083 06:19:21.478913 # ok 276 write_default.LCALTA.21
2084 06:19:21.484442 # ok 277 write_valid.LCALTA.21
2085 06:19:21.485033 # ok 278 write_invalid.LCALTA.21
2086 06:19:21.489986 # ok 279 event_missing.LCALTA.21
2087 06:19:21.490720 # ok 280 event_spurious.LCALTA.21
2088 06:19:21.495548 # ok 281 get_value.LCALTA.20
2089 06:19:21.496183 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2090 06:19:21.501163 # ok 282 name.LCALTA.20
2091 06:19:21.501743 # ok 283 write_default.LCALTA.20
2092 06:19:21.506638 # ok 284 write_valid.LCALTA.20
2093 06:19:21.507207 # ok 285 write_invalid.LCALTA.20
2094 06:19:21.512234 # ok 286 event_missing.LCALTA.20
2095 06:19:21.512789 # ok 287 event_spurious.LCALTA.20
2096 06:19:21.517747 # ok 288 get_value.LCALTA.19
2097 06:19:21.518329 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2098 06:19:21.523224 # ok 289 name.LCALTA.19
2099 06:19:21.523825 # ok 290 write_default.LCALTA.19
2100 06:19:21.528692 # ok 291 write_valid.LCALTA.19
2101 06:19:21.529205 # ok 292 write_invalid.LCALTA.19
2102 06:19:21.534276 # ok 293 event_missing.LCALTA.19
2103 06:19:21.534783 # ok 294 event_spurious.LCALTA.19
2104 06:19:21.539763 # ok 295 get_value.LCALTA.18
2105 06:19:21.540312 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2106 06:19:21.545373 # ok 296 name.LCALTA.18
2107 06:19:21.545932 # ok 297 write_default.LCALTA.18
2108 06:19:21.550893 # ok 298 write_valid.LCALTA.18
2109 06:19:21.551412 # ok 299 write_invalid.LCALTA.18
2110 06:19:21.556434 # ok 300 event_missing.LCALTA.18
2111 06:19:21.556959 # ok 301 event_spurious.LCALTA.18
2112 06:19:21.562007 # ok 302 get_value.LCALTA.17
2113 06:19:21.567876 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2114 06:19:21.568430 # ok 303 name.LCALTA.17
2115 06:19:21.568854 # ok 304 write_default.LCALTA.17
2116 06:19:21.573242 # ok 305 write_valid.LCALTA.17
2117 06:19:21.578738 # ok 306 write_invalid.LCALTA.17
2118 06:19:21.579284 # ok 307 event_missing.LCALTA.17
2119 06:19:21.584375 # ok 308 event_spurious.LCALTA.17
2120 06:19:21.584917 # ok 309 get_value.LCALTA.16
2121 06:19:21.589804 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2122 06:19:21.590368 # ok 310 name.LCALTA.16
2123 06:19:21.595362 # ok 311 write_default.LCALTA.16
2124 06:19:21.595843 # ok 312 write_valid.LCALTA.16
2125 06:19:21.600907 # ok 313 write_invalid.LCALTA.16
2126 06:19:21.601414 # ok 314 event_missing.LCALTA.16
2127 06:19:21.606452 # ok 315 event_spurious.LCALTA.16
2128 06:19:21.607006 # ok 316 get_value.LCALTA.15
2129 06:19:21.612031 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2130 06:19:21.612552 # ok 317 name.LCALTA.15
2131 06:19:21.617567 # ok 318 write_default.LCALTA.15
2132 06:19:21.618121 # ok 319 write_valid.LCALTA.15
2133 06:19:21.623087 # ok 320 write_invalid.LCALTA.15
2134 06:19:21.623720 # ok 321 event_missing.LCALTA.15
2135 06:19:21.628643 # ok 322 event_spurious.LCALTA.15
2136 06:19:21.629168 # ok 323 get_value.LCALTA.14
2137 06:19:21.634192 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2138 06:19:21.634733 # ok 324 name.LCALTA.14
2139 06:19:21.639735 # ok 325 write_default.LCALTA.14
2140 06:19:21.640320 # ok 326 write_valid.LCALTA.14
2141 06:19:21.645427 # ok 327 write_invalid.LCALTA.14
2142 06:19:21.645955 # ok 328 event_missing.LCALTA.14
2143 06:19:21.650945 # ok 329 event_spurious.LCALTA.14
2144 06:19:21.651480 # ok 330 get_value.LCALTA.13
2145 06:19:21.656455 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2146 06:19:21.656998 # ok 331 name.LCALTA.13
2147 06:19:21.661908 # ok 332 write_default.LCALTA.13
2148 06:19:21.662464 # ok 333 write_valid.LCALTA.13
2149 06:19:21.667487 # ok 334 write_invalid.LCALTA.13
2150 06:19:21.668038 # ok 335 event_missing.LCALTA.13
2151 06:19:21.673032 # ok 336 event_spurious.LCALTA.13
2152 06:19:21.673563 # ok 337 get_value.LCALTA.12
2153 06:19:21.678576 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2154 06:19:21.679099 # ok 338 name.LCALTA.12
2155 06:19:21.684164 # ok 339 write_default.LCALTA.12
2156 06:19:21.689677 # ok 340 write_valid.LCALTA.12
2157 06:19:21.690183 # ok 341 write_invalid.LCALTA.12
2158 06:19:21.695319 # ok 342 event_missing.LCALTA.12
2159 06:19:21.695871 # ok 343 event_spurious.LCALTA.12
2160 06:19:21.700792 # ok 344 get_value.LCALTA.11
2161 06:19:21.701315 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2162 06:19:21.706440 # ok 345 name.LCALTA.11
2163 06:19:21.706931 # ok 346 write_default.LCALTA.11
2164 06:19:21.711875 # ok 347 write_valid.LCALTA.11
2165 06:19:21.712434 # ok 348 write_invalid.LCALTA.11
2166 06:19:21.717412 # ok 349 event_missing.LCALTA.11
2167 06:19:21.717928 # ok 350 event_spurious.LCALTA.11
2168 06:19:21.722930 # ok 351 get_value.LCALTA.10
2169 06:19:21.723426 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2170 06:19:21.728577 # ok 352 name.LCALTA.10
2171 06:19:21.729110 # ok 353 write_default.LCALTA.10
2172 06:19:21.734042 # ok 354 write_valid.LCALTA.10
2173 06:19:21.734521 # ok 355 write_invalid.LCALTA.10
2174 06:19:21.739573 # ok 356 event_missing.LCALTA.10
2175 06:19:21.740145 # ok 357 event_spurious.LCALTA.10
2176 06:19:21.745263 # ok 358 get_value.LCALTA.9
2177 06:19:21.745800 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2178 06:19:21.750670 # ok 359 name.LCALTA.9
2179 06:19:21.751153 # ok 360 write_default.LCALTA.9
2180 06:19:21.756422 # ok 361 write_valid.LCALTA.9
2181 06:19:21.756940 # ok 362 write_invalid.LCALTA.9
2182 06:19:21.761801 # ok 363 event_missing.LCALTA.9
2183 06:19:21.762325 # ok 364 event_spurious.LCALTA.9
2184 06:19:21.767402 # ok 365 get_value.LCALTA.8
2185 06:19:21.767883 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2186 06:19:21.772955 # ok 366 name.LCALTA.8
2187 06:19:21.773473 # ok 367 write_default.LCALTA.8
2188 06:19:21.778417 # ok 368 write_valid.LCALTA.8
2189 06:19:21.778918 # ok 369 write_invalid.LCALTA.8
2190 06:19:21.784019 # ok 370 event_missing.LCALTA.8
2191 06:19:21.784534 # ok 371 event_spurious.LCALTA.8
2192 06:19:21.789530 # ok 372 get_value.LCALTA.7
2193 06:19:21.790052 # # LCALTA.7 ACODEC Unmute Ramp Switch
2194 06:19:21.795050 # ok 373 name.LCALTA.7
2195 06:19:21.795533 # ok 374 write_default.LCALTA.7
2196 06:19:21.800661 # ok 375 write_valid.LCALTA.7
2197 06:19:21.801186 # ok 376 write_invalid.LCALTA.7
2198 06:19:21.806207 # ok 377 event_missing.LCALTA.7
2199 06:19:21.806726 # ok 378 event_spurious.LCALTA.7
2200 06:19:21.811692 # ok 379 get_value.LCALTA.6
2201 06:19:21.812200 # # LCALTA.6 ACODEC Mute Ramp Switch
2202 06:19:21.817349 # ok 380 name.LCALTA.6
2203 06:19:21.817881 # ok 381 write_default.LCALTA.6
2204 06:19:21.822805 # ok 382 write_valid.LCALTA.6
2205 06:19:21.823315 # ok 383 write_invalid.LCALTA.6
2206 06:19:21.828464 # ok 384 event_missing.LCALTA.6
2207 06:19:21.828982 # ok 385 event_spurious.LCALTA.6
2208 06:19:21.833897 # ok 386 get_value.LCALTA.5
2209 06:19:21.834429 # # LCALTA.5 ACODEC Volume Ramp Switch
2210 06:19:21.839496 # ok 387 name.LCALTA.5
2211 06:19:21.840057 # ok 388 write_default.LCALTA.5
2212 06:19:21.844969 # ok 389 write_valid.LCALTA.5
2213 06:19:21.845462 # ok 390 write_invalid.LCALTA.5
2214 06:19:21.850537 # ok 391 event_missing.LCALTA.5
2215 06:19:21.851067 # ok 392 event_spurious.LCALTA.5
2216 06:19:21.856159 # ok 393 get_value.LCALTA.4
2217 06:19:21.856710 # # LCALTA.4 ACODEC Ramp Rate
2218 06:19:21.861782 # ok 394 name.LCALTA.4
2219 06:19:21.862329 # ok 395 write_default.LCALTA.4
2220 06:19:21.867181 # ok 396 write_valid.LCALTA.4
2221 06:19:21.868450 # ok 397 write_invalid.LCALTA.4
2222 06:19:21.872817 # ok 398 event_missing.LCALTA.4
2223 06:19:21.873371 # ok 399 event_spurious.LCALTA.4
2224 06:19:21.878345 # ok 400 get_value.LCALTA.3
2225 06:19:21.878871 # # LCALTA.3 ACODEC Playback Volume
2226 06:19:21.883826 # ok 401 name.LCALTA.3
2227 06:19:21.884392 # ok 402 write_default.LCALTA.3
2228 06:19:21.889441 # ok 403 write_valid.LCALTA.3
2229 06:19:21.889965 # ok 404 write_invalid.LCALTA.3
2230 06:19:21.894912 # ok 405 event_missing.LCALTA.3
2231 06:19:21.895427 # ok 406 event_spurious.LCALTA.3
2232 06:19:21.900457 # ok 407 get_value.LCALTA.2
2233 06:19:21.900963 # # LCALTA.2 ACODEC Playback Switch
2234 06:19:21.905964 # ok 408 name.LCALTA.2
2235 06:19:21.906479 # ok 409 write_default.LCALTA.2
2236 06:19:21.911587 # ok 410 write_valid.LCALTA.2
2237 06:19:21.912142 # ok 411 write_invalid.LCALTA.2
2238 06:19:21.917041 # ok 412 event_missing.LCALTA.2
2239 06:19:21.917553 # ok 413 event_spurious.LCALTA.2
2240 06:19:21.922628 # ok 414 get_value.LCALTA.1
2241 06:19:21.923141 # # LCALTA.1 ACODEC Playback Channel Mode
2242 06:19:21.928189 # ok 415 name.LCALTA.1
2243 06:19:21.928679 # ok 416 write_default.LCALTA.1
2244 06:19:21.933712 # ok 417 write_valid.LCALTA.1
2245 06:19:21.934193 # ok 418 write_invalid.LCALTA.1
2246 06:19:21.939323 # ok 419 event_missing.LCALTA.1
2247 06:19:21.939809 # ok 420 event_spurious.LCALTA.1
2248 06:19:21.944834 # ok 421 get_value.LCALTA.0
2249 06:19:21.945318 # # LCALTA.0 TOACODEC Lane Select
2250 06:19:21.950433 # ok 422 name.LCALTA.0
2251 06:19:21.950919 # ok 423 write_default.LCALTA.0
2252 06:19:21.955871 # ok 424 write_valid.LCALTA.0
2253 06:19:21.956387 # ok 425 write_invalid.LCALTA.0
2254 06:19:21.961421 # ok 426 event_missing.LCALTA.0
2255 06:19:21.961896 # ok 427 event_spurious.LCALTA.0
2256 06:19:21.966976 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2257 06:19:21.972613 ok 1 selftests: alsa: mixer-test
2258 06:19:21.973115 # timeout set to 45
2259 06:19:21.973557 # selftests: alsa: pcm-test
2260 06:19:21.978085 # TAP version 13
2261 06:19:21.978567 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2262 06:19:21.983634 # # LCALTA.0 - fe.dai-link-0 (*)
2263 06:19:21.984147 # # LCALTA.0 - fe.dai-link-1 (*)
2264 06:19:21.989183 # # LCALTA.0 - fe.dai-link-2 (*)
2265 06:19:21.989667 # # LCALTA.0 - fe.dai-link-3 (*)
2266 06:19:21.994737 # # LCALTA.0 - fe.dai-link-4 (*)
2267 06:19:21.995220 # # LCALTA.0 - fe.dai-link-5 (*)
2268 06:19:22.000304 # 1..42
2269 06:19:22.005803 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2270 06:19:22.006287 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2271 06:19:22.011539 # # snd_pcm_hw_params: Invalid argument
2272 06:19:22.016899 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2273 06:19:22.022435 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2274 06:19:22.022914 # # snd_pcm_hw_params: Invalid argument
2275 06:19:22.028035 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2276 06:19:22.033547 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2277 06:19:22.039086 # # snd_pcm_hw_params: Invalid argument
2278 06:19:22.044626 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2279 06:19:22.050183 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2280 06:19:22.050666 # # snd_pcm_hw_params: Invalid argument
2281 06:19:22.055725 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2282 06:19:22.061303 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2283 06:19:22.066818 # # snd_pcm_hw_params: Invalid argument
2284 06:19:22.072492 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2285 06:19:22.077898 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2286 06:19:22.078376 # # snd_pcm_hw_params: Invalid argument
2287 06:19:22.083493 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2288 06:19:22.088994 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2289 06:19:22.094647 # # snd_pcm_hw_params: Invalid argument
2290 06:19:22.100149 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2291 06:19:22.100629 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2292 06:19:22.105624 # # snd_pcm_hw_params: Invalid argument
2293 06:19:22.111198 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2294 06:19:22.116795 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2295 06:19:22.117291 # # snd_pcm_hw_params: Invalid argument
2296 06:19:22.127840 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2297 06:19:22.128381 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2298 06:19:22.133609 # # snd_pcm_hw_params: Invalid argument
2299 06:19:22.138994 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2300 06:19:22.144504 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2301 06:19:22.145009 # # snd_pcm_hw_params: Invalid argument
2302 06:19:22.150031 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2303 06:19:22.155588 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2304 06:19:22.161108 # # snd_pcm_hw_params: Invalid argument
2305 06:19:22.166670 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2306 06:19:22.172372 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2307 06:19:22.172877 # # snd_pcm_hw_params: Invalid argument
2308 06:19:22.177769 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2309 06:19:22.183352 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2310 06:19:22.188841 # # snd_pcm_hw_params: Invalid argument
2311 06:19:22.194457 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2312 06:19:22.199935 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2313 06:19:22.200482 # # snd_pcm_hw_params: Invalid argument
2314 06:19:22.205518 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2315 06:19:22.211044 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2316 06:19:22.216650 # # snd_pcm_hw_params: Invalid argument
2317 06:19:22.222119 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2318 06:19:22.222625 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2319 06:19:22.227668 # # snd_pcm_hw_params: Invalid argument
2320 06:19:22.233307 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2321 06:19:22.238796 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2322 06:19:22.244352 # # snd_pcm_hw_params: Invalid argument
2323 06:19:22.249914 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2324 06:19:22.250413 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2325 06:19:22.255495 # # snd_pcm_hw_params: Invalid argument
2326 06:19:22.260955 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2327 06:19:22.266516 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2328 06:19:22.272213 # # snd_pcm_hw_params: Invalid argument
2329 06:19:22.277659 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2330 06:19:22.278171 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2331 06:19:22.283169 # # snd_pcm_hw_params: Invalid argument
2332 06:19:22.288728 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2333 06:19:22.294261 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2334 06:19:22.294769 # # snd_pcm_hw_params: Invalid argument
2335 06:19:22.299792 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2336 06:19:22.305375 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2337 06:19:22.310885 # # snd_pcm_hw_params: Invalid argument
2338 06:19:22.316509 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2339 06:19:22.322029 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2340 06:19:22.322531 # # snd_pcm_hw_params: Invalid argument
2341 06:19:22.327554 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2342 06:19:22.333052 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2343 06:19:22.338627 # # snd_pcm_hw_params: Invalid argument
2344 06:19:22.344191 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2345 06:19:22.349689 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2346 06:19:22.350198 # # snd_pcm_hw_params: Invalid argument
2347 06:19:22.355245 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2348 06:19:22.360765 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2349 06:19:22.366358 # # snd_pcm_hw_params: Invalid argument
2350 06:19:22.371871 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2351 06:19:22.377574 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2352 06:19:22.378080 # # snd_pcm_hw_params: Invalid argument
2353 06:19:22.382973 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2354 06:19:22.388574 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2355 06:19:22.394089 # # snd_pcm_hw_params: Invalid argument
2356 06:19:22.399636 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2357 06:19:22.405182 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2358 06:19:22.405688 # # snd_pcm_hw_params: Invalid argument
2359 06:19:22.410751 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2360 06:19:22.416274 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2361 06:19:22.421877 # # snd_pcm_hw_params: Invalid argument
2362 06:19:22.427386 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2363 06:19:22.432949 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2364 06:19:22.433487 # # snd_pcm_hw_params: Invalid argument
2365 06:19:22.438556 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2366 06:19:22.444035 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2367 06:19:22.449546 # # snd_pcm_hw_params: Invalid argument
2368 06:19:22.455083 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2369 06:19:22.460616 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2370 06:19:22.461149 # # snd_pcm_hw_params: Invalid argument
2371 06:19:22.466201 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2372 06:19:22.471771 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2373 06:19:22.477436 # # snd_pcm_hw_params: Invalid argument
2374 06:19:22.482887 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2375 06:19:22.488578 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2376 06:19:22.489204 # # snd_pcm_hw_params: Invalid argument
2377 06:19:22.494087 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2378 06:19:22.499637 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2379 06:19:22.505131 # # snd_pcm_hw_params: Invalid argument
2380 06:19:22.510703 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2381 06:19:22.516292 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2382 06:19:22.516882 # # snd_pcm_hw_params: Invalid argument
2383 06:19:22.521791 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2384 06:19:22.527330 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2385 06:19:22.532863 # # snd_pcm_hw_params: Invalid argument
2386 06:19:22.538396 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2387 06:19:22.543949 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2388 06:19:22.544548 # # snd_pcm_hw_params: Invalid argument
2389 06:19:22.549502 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2390 06:19:22.555033 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2391 06:19:22.560620 # # snd_pcm_hw_params: Invalid argument
2392 06:19:22.566121 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2393 06:19:22.571693 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2394 06:19:22.572305 # # snd_pcm_hw_params: Invalid argument
2395 06:19:22.577288 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2396 06:19:22.582794 ok 2 selftests: alsa: pcm-test
2397 06:19:22.583382 # timeout set to 45
2398 06:19:22.588391 # selftests: alsa: test-pcmtest-driver
2399 06:19:22.588987 # TAP version 13
2400 06:19:22.589485 # 1..5
2401 06:19:22.593920 # # Starting 5 tests from 1 test cases.
2402 06:19:22.594500 # # RUN pcmtest.playback ...
2403 06:19:22.599465 # # SKIP Can't read patterns. Probably, module isn't loaded
2404 06:19:22.604964 # # OK pcmtest.playback
2405 06:19:22.610535 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2406 06:19:22.616091 # # RUN pcmtest.capture ...
2407 06:19:22.621626 # # SKIP Can't read patterns. Probably, module isn't loaded
2408 06:19:22.627266 # # OK pcmtest.capture
2409 06:19:22.632748 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2410 06:19:22.638306 # # RUN pcmtest.ni_capture ...
2411 06:19:22.643819 # # SKIP Can't read patterns. Probably, module isn't loaded
2412 06:19:22.644652 # # OK pcmtest.ni_capture
2413 06:19:22.654949 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2414 06:19:22.655627 # # RUN pcmtest.ni_playback ...
2415 06:19:22.660575 # # SKIP Can't read patterns. Probably, module isn't loaded
2416 06:19:22.666032 # # OK pcmtest.ni_playback
2417 06:19:22.671570 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2418 06:19:22.677107 # # RUN pcmtest.reset_ioctl ...
2419 06:19:22.682798 # # SKIP Can't read patterns. Probably, module isn't loaded
2420 06:19:22.688400 # # OK pcmtest.reset_ioctl
2421 06:19:22.693768 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2422 06:19:22.699297 # # PASSED: 5 / 5 tests passed.
2423 06:19:22.706206 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2424 06:19:22.706834 ok 3 selftests: alsa: test-pcmtest-driver
2425 06:19:23.291444 alsa_mixer-test_get_value_LCALTA_60 pass
2426 06:19:23.296867 alsa_mixer-test_name_LCALTA_60 pass
2427 06:19:23.297208 alsa_mixer-test_write_default_LCALTA_60 pass
2428 06:19:23.302433 alsa_mixer-test_write_valid_LCALTA_60 pass
2429 06:19:23.307952 alsa_mixer-test_write_invalid_LCALTA_60 pass
2430 06:19:23.313549 alsa_mixer-test_event_missing_LCALTA_60 pass
2431 06:19:23.313857 alsa_mixer-test_event_spurious_LCALTA_60 pass
2432 06:19:23.319053 alsa_mixer-test_get_value_LCALTA_59 pass
2433 06:19:23.324684 alsa_mixer-test_name_LCALTA_59 pass
2434 06:19:23.325258 alsa_mixer-test_write_default_LCALTA_59 pass
2435 06:19:23.330229 alsa_mixer-test_write_valid_LCALTA_59 pass
2436 06:19:23.335798 alsa_mixer-test_write_invalid_LCALTA_59 pass
2437 06:19:23.336381 alsa_mixer-test_event_missing_LCALTA_59 pass
2438 06:19:23.341341 alsa_mixer-test_event_spurious_LCALTA_59 pass
2439 06:19:23.346892 alsa_mixer-test_get_value_LCALTA_58 pass
2440 06:19:23.347458 alsa_mixer-test_name_LCALTA_58 pass
2441 06:19:23.352465 alsa_mixer-test_write_default_LCALTA_58 pass
2442 06:19:23.358001 alsa_mixer-test_write_valid_LCALTA_58 pass
2443 06:19:23.358567 alsa_mixer-test_write_invalid_LCALTA_58 pass
2444 06:19:23.363540 alsa_mixer-test_event_missing_LCALTA_58 pass
2445 06:19:23.369047 alsa_mixer-test_event_spurious_LCALTA_58 pass
2446 06:19:23.374691 alsa_mixer-test_get_value_LCALTA_57 pass
2447 06:19:23.375252 alsa_mixer-test_name_LCALTA_57 pass
2448 06:19:23.380387 alsa_mixer-test_write_default_LCALTA_57 pass
2449 06:19:23.385859 alsa_mixer-test_write_valid_LCALTA_57 pass
2450 06:19:23.386423 alsa_mixer-test_write_invalid_LCALTA_57 pass
2451 06:19:23.391371 alsa_mixer-test_event_missing_LCALTA_57 pass
2452 06:19:23.396943 alsa_mixer-test_event_spurious_LCALTA_57 pass
2453 06:19:23.397510 alsa_mixer-test_get_value_LCALTA_56 pass
2454 06:19:23.402499 alsa_mixer-test_name_LCALTA_56 pass
2455 06:19:23.408027 alsa_mixer-test_write_default_LCALTA_56 pass
2456 06:19:23.408598 alsa_mixer-test_write_valid_LCALTA_56 pass
2457 06:19:23.413578 alsa_mixer-test_write_invalid_LCALTA_56 pass
2458 06:19:23.419085 alsa_mixer-test_event_missing_LCALTA_56 pass
2459 06:19:23.424656 alsa_mixer-test_event_spurious_LCALTA_56 pass
2460 06:19:23.425220 alsa_mixer-test_get_value_LCALTA_55 pass
2461 06:19:23.430186 alsa_mixer-test_name_LCALTA_55 pass
2462 06:19:23.435792 alsa_mixer-test_write_default_LCALTA_55 pass
2463 06:19:23.436432 alsa_mixer-test_write_valid_LCALTA_55 pass
2464 06:19:23.441322 alsa_mixer-test_write_invalid_LCALTA_55 pass
2465 06:19:23.446872 alsa_mixer-test_event_missing_LCALTA_55 pass
2466 06:19:23.447449 alsa_mixer-test_event_spurious_LCALTA_55 pass
2467 06:19:23.452432 alsa_mixer-test_get_value_LCALTA_54 pass
2468 06:19:23.457950 alsa_mixer-test_name_LCALTA_54 pass
2469 06:19:23.458535 alsa_mixer-test_write_default_LCALTA_54 pass
2470 06:19:23.463455 alsa_mixer-test_write_valid_LCALTA_54 pass
2471 06:19:23.469033 alsa_mixer-test_write_invalid_LCALTA_54 pass
2472 06:19:23.469618 alsa_mixer-test_event_missing_LCALTA_54 pass
2473 06:19:23.474574 alsa_mixer-test_event_spurious_LCALTA_54 pass
2474 06:19:23.480249 alsa_mixer-test_get_value_LCALTA_53 pass
2475 06:19:23.480901 alsa_mixer-test_name_LCALTA_53 pass
2476 06:19:23.485734 alsa_mixer-test_write_default_LCALTA_53 pass
2477 06:19:23.491240 alsa_mixer-test_write_valid_LCALTA_53 pass
2478 06:19:23.496818 alsa_mixer-test_write_invalid_LCALTA_53 pass
2479 06:19:23.497387 alsa_mixer-test_event_missing_LCALTA_53 pass
2480 06:19:23.502326 alsa_mixer-test_event_spurious_LCALTA_53 pass
2481 06:19:23.507868 alsa_mixer-test_get_value_LCALTA_52 pass
2482 06:19:23.508473 alsa_mixer-test_name_LCALTA_52 pass
2483 06:19:23.513423 alsa_mixer-test_write_default_LCALTA_52 pass
2484 06:19:23.518969 alsa_mixer-test_write_valid_LCALTA_52 pass
2485 06:19:23.519503 alsa_mixer-test_write_invalid_LCALTA_52 pass
2486 06:19:23.524462 alsa_mixer-test_event_missing_LCALTA_52 pass
2487 06:19:23.530024 alsa_mixer-test_event_spurious_LCALTA_52 pass
2488 06:19:23.530463 alsa_mixer-test_get_value_LCALTA_51 pass
2489 06:19:23.535551 alsa_mixer-test_name_LCALTA_51 pass
2490 06:19:23.541095 alsa_mixer-test_write_default_LCALTA_51 pass
2491 06:19:23.541605 alsa_mixer-test_write_valid_LCALTA_51 pass
2492 06:19:23.546694 alsa_mixer-test_write_invalid_LCALTA_51 pass
2493 06:19:23.552157 alsa_mixer-test_event_missing_LCALTA_51 pass
2494 06:19:23.557765 alsa_mixer-test_event_spurious_LCALTA_51 pass
2495 06:19:23.558504 alsa_mixer-test_get_value_LCALTA_50 pass
2496 06:19:23.563280 alsa_mixer-test_name_LCALTA_50 pass
2497 06:19:23.568824 alsa_mixer-test_write_default_LCALTA_50 pass
2498 06:19:23.569451 alsa_mixer-test_write_valid_LCALTA_50 pass
2499 06:19:23.574338 alsa_mixer-test_write_invalid_LCALTA_50 pass
2500 06:19:23.579926 alsa_mixer-test_event_missing_LCALTA_50 pass
2501 06:19:23.580442 alsa_mixer-test_event_spurious_LCALTA_50 pass
2502 06:19:23.585279 alsa_mixer-test_get_value_LCALTA_49 pass
2503 06:19:23.590832 alsa_mixer-test_name_LCALTA_49 pass
2504 06:19:23.591244 alsa_mixer-test_write_default_LCALTA_49 pass
2505 06:19:23.596381 alsa_mixer-test_write_valid_LCALTA_49 pass
2506 06:19:23.601909 alsa_mixer-test_write_invalid_LCALTA_49 pass
2507 06:19:23.607480 alsa_mixer-test_event_missing_LCALTA_49 pass
2508 06:19:23.607886 alsa_mixer-test_event_spurious_LCALTA_49 pass
2509 06:19:23.613015 alsa_mixer-test_get_value_LCALTA_48 pass
2510 06:19:23.613422 alsa_mixer-test_name_LCALTA_48 pass
2511 06:19:23.618644 alsa_mixer-test_write_default_LCALTA_48 pass
2512 06:19:23.624462 alsa_mixer-test_write_valid_LCALTA_48 pass
2513 06:19:23.629800 alsa_mixer-test_write_invalid_LCALTA_48 pass
2514 06:19:23.630206 alsa_mixer-test_event_missing_LCALTA_48 pass
2515 06:19:23.635378 alsa_mixer-test_event_spurious_LCALTA_48 pass
2516 06:19:23.640846 alsa_mixer-test_get_value_LCALTA_47 pass
2517 06:19:23.641244 alsa_mixer-test_name_LCALTA_47 pass
2518 06:19:23.646316 alsa_mixer-test_write_default_LCALTA_47 pass
2519 06:19:23.651892 alsa_mixer-test_write_valid_LCALTA_47 pass
2520 06:19:23.652198 alsa_mixer-test_write_invalid_LCALTA_47 pass
2521 06:19:23.657427 alsa_mixer-test_event_missing_LCALTA_47 pass
2522 06:19:23.662941 alsa_mixer-test_event_spurious_LCALTA_47 pass
2523 06:19:23.668501 alsa_mixer-test_get_value_LCALTA_46 pass
2524 06:19:23.668778 alsa_mixer-test_name_LCALTA_46 pass
2525 06:19:23.674096 alsa_mixer-test_write_default_LCALTA_46 pass
2526 06:19:23.679671 alsa_mixer-test_write_valid_LCALTA_46 pass
2527 06:19:23.680190 alsa_mixer-test_write_invalid_LCALTA_46 pass
2528 06:19:23.685183 alsa_mixer-test_event_missing_LCALTA_46 pass
2529 06:19:23.690721 alsa_mixer-test_event_spurious_LCALTA_46 pass
2530 06:19:23.691205 alsa_mixer-test_get_value_LCALTA_45 pass
2531 06:19:23.696273 alsa_mixer-test_name_LCALTA_45 pass
2532 06:19:23.701802 alsa_mixer-test_write_default_LCALTA_45 pass
2533 06:19:23.702280 alsa_mixer-test_write_valid_LCALTA_45 pass
2534 06:19:23.707362 alsa_mixer-test_write_invalid_LCALTA_45 pass
2535 06:19:23.712911 alsa_mixer-test_event_missing_LCALTA_45 pass
2536 06:19:23.713396 alsa_mixer-test_event_spurious_LCALTA_45 pass
2537 06:19:23.718433 alsa_mixer-test_get_value_LCALTA_44 pass
2538 06:19:23.724130 alsa_mixer-test_name_LCALTA_44 pass
2539 06:19:23.724605 alsa_mixer-test_write_default_LCALTA_44 pass
2540 06:19:23.729555 alsa_mixer-test_write_valid_LCALTA_44 pass
2541 06:19:23.735120 alsa_mixer-test_write_invalid_LCALTA_44 pass
2542 06:19:23.740679 alsa_mixer-test_event_missing_LCALTA_44 pass
2543 06:19:23.741156 alsa_mixer-test_event_spurious_LCALTA_44 pass
2544 06:19:23.746172 alsa_mixer-test_get_value_LCALTA_43 pass
2545 06:19:23.751735 alsa_mixer-test_name_LCALTA_43 pass
2546 06:19:23.752248 alsa_mixer-test_write_default_LCALTA_43 pass
2547 06:19:23.757300 alsa_mixer-test_write_valid_LCALTA_43 pass
2548 06:19:23.762827 alsa_mixer-test_write_invalid_LCALTA_43 pass
2549 06:19:23.763303 alsa_mixer-test_event_missing_LCALTA_43 pass
2550 06:19:23.768389 alsa_mixer-test_event_spurious_LCALTA_43 pass
2551 06:19:23.773942 alsa_mixer-test_get_value_LCALTA_42 pass
2552 06:19:23.774413 alsa_mixer-test_name_LCALTA_42 pass
2553 06:19:23.779464 alsa_mixer-test_write_default_LCALTA_42 pass
2554 06:19:23.785029 alsa_mixer-test_write_valid_LCALTA_42 pass
2555 06:19:23.785541 alsa_mixer-test_write_invalid_LCALTA_42 pass
2556 06:19:23.790558 alsa_mixer-test_event_missing_LCALTA_42 pass
2557 06:19:23.796303 alsa_mixer-test_event_spurious_LCALTA_42 pass
2558 06:19:23.801686 alsa_mixer-test_get_value_LCALTA_41 pass
2559 06:19:23.802335 alsa_mixer-test_name_LCALTA_41 pass
2560 06:19:23.807251 alsa_mixer-test_write_default_LCALTA_41 pass
2561 06:19:23.812917 alsa_mixer-test_write_valid_LCALTA_41 pass
2562 06:19:23.813565 alsa_mixer-test_write_invalid_LCALTA_41 pass
2563 06:19:23.818307 alsa_mixer-test_event_missing_LCALTA_41 pass
2564 06:19:23.823862 alsa_mixer-test_event_spurious_LCALTA_41 pass
2565 06:19:23.824504 alsa_mixer-test_get_value_LCALTA_40 pass
2566 06:19:23.829391 alsa_mixer-test_name_LCALTA_40 pass
2567 06:19:23.834967 alsa_mixer-test_write_default_LCALTA_40 pass
2568 06:19:23.835606 alsa_mixer-test_write_valid_LCALTA_40 pass
2569 06:19:23.840497 alsa_mixer-test_write_invalid_LCALTA_40 pass
2570 06:19:23.846024 alsa_mixer-test_event_missing_LCALTA_40 pass
2571 06:19:23.851567 alsa_mixer-test_event_spurious_LCALTA_40 pass
2572 06:19:23.852268 alsa_mixer-test_get_value_LCALTA_39 pass
2573 06:19:23.857152 alsa_mixer-test_name_LCALTA_39 pass
2574 06:19:23.862714 alsa_mixer-test_write_default_LCALTA_39 pass
2575 06:19:23.863341 alsa_mixer-test_write_valid_LCALTA_39 pass
2576 06:19:23.868230 alsa_mixer-test_write_invalid_LCALTA_39 pass
2577 06:19:23.873774 alsa_mixer-test_event_missing_LCALTA_39 pass
2578 06:19:23.874400 alsa_mixer-test_event_spurious_LCALTA_39 pass
2579 06:19:23.879355 alsa_mixer-test_get_value_LCALTA_38 pass
2580 06:19:23.884788 alsa_mixer-test_name_LCALTA_38 pass
2581 06:19:23.885409 alsa_mixer-test_write_default_LCALTA_38 pass
2582 06:19:23.890298 alsa_mixer-test_write_valid_LCALTA_38 pass
2583 06:19:23.895855 alsa_mixer-test_write_invalid_LCALTA_38 pass
2584 06:19:23.896492 alsa_mixer-test_event_missing_LCALTA_38 pass
2585 06:19:23.901581 alsa_mixer-test_event_spurious_LCALTA_38 pass
2586 06:19:23.906969 alsa_mixer-test_get_value_LCALTA_37 pass
2587 06:19:23.907571 alsa_mixer-test_name_LCALTA_37 pass
2588 06:19:23.912610 alsa_mixer-test_write_default_LCALTA_37 pass
2589 06:19:23.918022 alsa_mixer-test_write_valid_LCALTA_37 pass
2590 06:19:23.923617 alsa_mixer-test_write_invalid_LCALTA_37 pass
2591 06:19:23.924274 alsa_mixer-test_event_missing_LCALTA_37 pass
2592 06:19:23.929139 alsa_mixer-test_event_spurious_LCALTA_37 pass
2593 06:19:23.934669 alsa_mixer-test_get_value_LCALTA_36 pass
2594 06:19:23.935285 alsa_mixer-test_name_LCALTA_36 pass
2595 06:19:23.940236 alsa_mixer-test_write_default_LCALTA_36 pass
2596 06:19:23.945835 alsa_mixer-test_write_valid_LCALTA_36 pass
2597 06:19:23.946435 alsa_mixer-test_write_invalid_LCALTA_36 pass
2598 06:19:23.951312 alsa_mixer-test_event_missing_LCALTA_36 pass
2599 06:19:23.956879 alsa_mixer-test_event_spurious_LCALTA_36 pass
2600 06:19:23.957506 alsa_mixer-test_get_value_LCALTA_35 pass
2601 06:19:23.962580 alsa_mixer-test_name_LCALTA_35 pass
2602 06:19:23.968036 alsa_mixer-test_write_default_LCALTA_35 pass
2603 06:19:23.968661 alsa_mixer-test_write_valid_LCALTA_35 pass
2604 06:19:23.973678 alsa_mixer-test_write_invalid_LCALTA_35 pass
2605 06:19:23.979061 alsa_mixer-test_event_missing_LCALTA_35 pass
2606 06:19:23.984620 alsa_mixer-test_event_spurious_LCALTA_35 pass
2607 06:19:23.985240 alsa_mixer-test_get_value_LCALTA_34 pass
2608 06:19:23.990159 alsa_mixer-test_name_LCALTA_34 pass
2609 06:19:23.995724 alsa_mixer-test_write_default_LCALTA_34 pass
2610 06:19:23.996400 alsa_mixer-test_write_valid_LCALTA_34 pass
2611 06:19:24.001276 alsa_mixer-test_write_invalid_LCALTA_34 pass
2612 06:19:24.006797 alsa_mixer-test_event_missing_LCALTA_34 pass
2613 06:19:24.007400 alsa_mixer-test_event_spurious_LCALTA_34 pass
2614 06:19:24.012324 alsa_mixer-test_get_value_LCALTA_33 pass
2615 06:19:24.017870 alsa_mixer-test_name_LCALTA_33 pass
2616 06:19:24.018467 alsa_mixer-test_write_default_LCALTA_33 pass
2617 06:19:24.023501 alsa_mixer-test_write_valid_LCALTA_33 pass
2618 06:19:24.028986 alsa_mixer-test_write_invalid_LCALTA_33 pass
2619 06:19:24.034627 alsa_mixer-test_event_missing_LCALTA_33 pass
2620 06:19:24.035234 alsa_mixer-test_event_spurious_LCALTA_33 pass
2621 06:19:24.040084 alsa_mixer-test_get_value_LCALTA_32 pass
2622 06:19:24.040678 alsa_mixer-test_name_LCALTA_32 pass
2623 06:19:24.045622 alsa_mixer-test_write_default_LCALTA_32 pass
2624 06:19:24.051157 alsa_mixer-test_write_valid_LCALTA_32 pass
2625 06:19:24.056725 alsa_mixer-test_write_invalid_LCALTA_32 pass
2626 06:19:24.057331 alsa_mixer-test_event_missing_LCALTA_32 pass
2627 06:19:24.062255 alsa_mixer-test_event_spurious_LCALTA_32 pass
2628 06:19:24.067804 alsa_mixer-test_get_value_LCALTA_31 pass
2629 06:19:24.068443 alsa_mixer-test_name_LCALTA_31 pass
2630 06:19:24.073348 alsa_mixer-test_write_default_LCALTA_31 pass
2631 06:19:24.078911 alsa_mixer-test_write_valid_LCALTA_31 pass
2632 06:19:24.079524 alsa_mixer-test_write_invalid_LCALTA_31 pass
2633 06:19:24.084509 alsa_mixer-test_event_missing_LCALTA_31 pass
2634 06:19:24.089991 alsa_mixer-test_event_spurious_LCALTA_31 pass
2635 06:19:24.095635 alsa_mixer-test_get_value_LCALTA_30 pass
2636 06:19:24.096299 alsa_mixer-test_name_LCALTA_30 pass
2637 06:19:24.101068 alsa_mixer-test_write_default_LCALTA_30 pass
2638 06:19:24.106641 alsa_mixer-test_write_valid_LCALTA_30 pass
2639 06:19:24.107245 alsa_mixer-test_write_invalid_LCALTA_30 pass
2640 06:19:24.112179 alsa_mixer-test_event_missing_LCALTA_30 pass
2641 06:19:24.117727 alsa_mixer-test_event_spurious_LCALTA_30 pass
2642 06:19:24.118335 alsa_mixer-test_get_value_LCALTA_29 pass
2643 06:19:24.123272 alsa_mixer-test_name_LCALTA_29 pass
2644 06:19:24.128822 alsa_mixer-test_write_default_LCALTA_29 pass
2645 06:19:24.129448 alsa_mixer-test_write_valid_LCALTA_29 pass
2646 06:19:24.134351 alsa_mixer-test_write_invalid_LCALTA_29 pass
2647 06:19:24.140037 alsa_mixer-test_event_missing_LCALTA_29 pass
2648 06:19:24.140672 alsa_mixer-test_event_spurious_LCALTA_29 pass
2649 06:19:24.145552 alsa_mixer-test_get_value_LCALTA_28 pass
2650 06:19:24.151021 alsa_mixer-test_name_LCALTA_28 pass
2651 06:19:24.151649 alsa_mixer-test_write_default_LCALTA_28 pass
2652 06:19:24.156654 alsa_mixer-test_write_valid_LCALTA_28 pass
2653 06:19:24.162104 alsa_mixer-test_write_invalid_LCALTA_28 pass
2654 06:19:24.167666 alsa_mixer-test_event_missing_LCALTA_28 pass
2655 06:19:24.168354 alsa_mixer-test_event_spurious_LCALTA_28 pass
2656 06:19:24.173216 alsa_mixer-test_get_value_LCALTA_27 pass
2657 06:19:24.178742 alsa_mixer-test_name_LCALTA_27 pass
2658 06:19:24.179371 alsa_mixer-test_write_default_LCALTA_27 pass
2659 06:19:24.184296 alsa_mixer-test_write_valid_LCALTA_27 pass
2660 06:19:24.189877 alsa_mixer-test_write_invalid_LCALTA_27 pass
2661 06:19:24.190509 alsa_mixer-test_event_missing_LCALTA_27 pass
2662 06:19:24.195520 alsa_mixer-test_event_spurious_LCALTA_27 pass
2663 06:19:24.201068 alsa_mixer-test_get_value_LCALTA_26 pass
2664 06:19:24.201711 alsa_mixer-test_name_LCALTA_26 pass
2665 06:19:24.206674 alsa_mixer-test_write_default_LCALTA_26 skip
2666 06:19:24.212199 alsa_mixer-test_write_valid_LCALTA_26 skip
2667 06:19:24.212839 alsa_mixer-test_write_invalid_LCALTA_26 skip
2668 06:19:24.217796 alsa_mixer-test_event_missing_LCALTA_26 pass
2669 06:19:24.223232 alsa_mixer-test_event_spurious_LCALTA_26 pass
2670 06:19:24.228800 alsa_mixer-test_get_value_LCALTA_25 pass
2671 06:19:24.229452 alsa_mixer-test_name_LCALTA_25 pass
2672 06:19:24.234351 alsa_mixer-test_write_default_LCALTA_25 pass
2673 06:19:24.239898 alsa_mixer-test_write_valid_LCALTA_25 skip
2674 06:19:24.240560 alsa_mixer-test_write_invalid_LCALTA_25 skip
2675 06:19:24.245431 alsa_mixer-test_event_missing_LCALTA_25 pass
2676 06:19:24.250943 alsa_mixer-test_event_spurious_LCALTA_25 pass
2677 06:19:24.251559 alsa_mixer-test_get_value_LCALTA_24 pass
2678 06:19:24.256510 alsa_mixer-test_name_LCALTA_24 pass
2679 06:19:24.262059 alsa_mixer-test_write_default_LCALTA_24 skip
2680 06:19:24.262674 alsa_mixer-test_write_valid_LCALTA_24 skip
2681 06:19:24.267644 alsa_mixer-test_write_invalid_LCALTA_24 skip
2682 06:19:24.273191 alsa_mixer-test_event_missing_LCALTA_24 pass
2683 06:19:24.278800 alsa_mixer-test_event_spurious_LCALTA_24 pass
2684 06:19:24.279424 alsa_mixer-test_get_value_LCALTA_23 pass
2685 06:19:24.284251 alsa_mixer-test_name_LCALTA_23 pass
2686 06:19:24.289796 alsa_mixer-test_write_default_LCALTA_23 skip
2687 06:19:24.290415 alsa_mixer-test_write_valid_LCALTA_23 skip
2688 06:19:24.295346 alsa_mixer-test_write_invalid_LCALTA_23 skip
2689 06:19:24.300894 alsa_mixer-test_event_missing_LCALTA_23 pass
2690 06:19:24.301496 alsa_mixer-test_event_spurious_LCALTA_23 pass
2691 06:19:24.306495 alsa_mixer-test_get_value_LCALTA_22 pass
2692 06:19:24.312100 alsa_mixer-test_name_LCALTA_22 pass
2693 06:19:24.312714 alsa_mixer-test_write_default_LCALTA_22 pass
2694 06:19:24.317551 alsa_mixer-test_write_valid_LCALTA_22 pass
2695 06:19:24.323057 alsa_mixer-test_write_invalid_LCALTA_22 pass
2696 06:19:24.323674 alsa_mixer-test_event_missing_LCALTA_22 pass
2697 06:19:24.328662 alsa_mixer-test_event_spurious_LCALTA_22 pass
2698 06:19:24.334166 alsa_mixer-test_get_value_LCALTA_21 pass
2699 06:19:24.334762 alsa_mixer-test_name_LCALTA_21 pass
2700 06:19:24.339794 alsa_mixer-test_write_default_LCALTA_21 pass
2701 06:19:24.345272 alsa_mixer-test_write_valid_LCALTA_21 pass
2702 06:19:24.350831 alsa_mixer-test_write_invalid_LCALTA_21 pass
2703 06:19:24.351429 alsa_mixer-test_event_missing_LCALTA_21 pass
2704 06:19:24.356329 alsa_mixer-test_event_spurious_LCALTA_21 pass
2705 06:19:24.361889 alsa_mixer-test_get_value_LCALTA_20 pass
2706 06:19:24.362502 alsa_mixer-test_name_LCALTA_20 pass
2707 06:19:24.367448 alsa_mixer-test_write_default_LCALTA_20 pass
2708 06:19:24.372980 alsa_mixer-test_write_valid_LCALTA_20 pass
2709 06:19:24.373596 alsa_mixer-test_write_invalid_LCALTA_20 pass
2710 06:19:24.378542 alsa_mixer-test_event_missing_LCALTA_20 pass
2711 06:19:24.384109 alsa_mixer-test_event_spurious_LCALTA_20 pass
2712 06:19:24.384736 alsa_mixer-test_get_value_LCALTA_19 pass
2713 06:19:24.389672 alsa_mixer-test_name_LCALTA_19 pass
2714 06:19:24.395186 alsa_mixer-test_write_default_LCALTA_19 pass
2715 06:19:24.395783 alsa_mixer-test_write_valid_LCALTA_19 pass
2716 06:19:24.400800 alsa_mixer-test_write_invalid_LCALTA_19 pass
2717 06:19:24.406268 alsa_mixer-test_event_missing_LCALTA_19 pass
2718 06:19:24.411849 alsa_mixer-test_event_spurious_LCALTA_19 pass
2719 06:19:24.412476 alsa_mixer-test_get_value_LCALTA_18 pass
2720 06:19:24.417369 alsa_mixer-test_name_LCALTA_18 pass
2721 06:19:24.422898 alsa_mixer-test_write_default_LCALTA_18 pass
2722 06:19:24.423482 alsa_mixer-test_write_valid_LCALTA_18 pass
2723 06:19:24.428441 alsa_mixer-test_write_invalid_LCALTA_18 pass
2724 06:19:24.433882 alsa_mixer-test_event_missing_LCALTA_18 pass
2725 06:19:24.434479 alsa_mixer-test_event_spurious_LCALTA_18 pass
2726 06:19:24.439475 alsa_mixer-test_get_value_LCALTA_17 pass
2727 06:19:24.444961 alsa_mixer-test_name_LCALTA_17 pass
2728 06:19:24.445565 alsa_mixer-test_write_default_LCALTA_17 pass
2729 06:19:24.450547 alsa_mixer-test_write_valid_LCALTA_17 pass
2730 06:19:24.456078 alsa_mixer-test_write_invalid_LCALTA_17 pass
2731 06:19:24.461677 alsa_mixer-test_event_missing_LCALTA_17 pass
2732 06:19:24.462265 alsa_mixer-test_event_spurious_LCALTA_17 pass
2733 06:19:24.467224 alsa_mixer-test_get_value_LCALTA_16 pass
2734 06:19:24.467808 alsa_mixer-test_name_LCALTA_16 pass
2735 06:19:24.472759 alsa_mixer-test_write_default_LCALTA_16 pass
2736 06:19:24.478259 alsa_mixer-test_write_valid_LCALTA_16 pass
2737 06:19:24.483815 alsa_mixer-test_write_invalid_LCALTA_16 pass
2738 06:19:24.484480 alsa_mixer-test_event_missing_LCALTA_16 pass
2739 06:19:24.489349 alsa_mixer-test_event_spurious_LCALTA_16 pass
2740 06:19:24.494924 alsa_mixer-test_get_value_LCALTA_15 pass
2741 06:19:24.495600 alsa_mixer-test_name_LCALTA_15 pass
2742 06:19:24.500453 alsa_mixer-test_write_default_LCALTA_15 pass
2743 06:19:24.505992 alsa_mixer-test_write_valid_LCALTA_15 pass
2744 06:19:24.506585 alsa_mixer-test_write_invalid_LCALTA_15 pass
2745 06:19:24.511560 alsa_mixer-test_event_missing_LCALTA_15 pass
2746 06:19:24.517077 alsa_mixer-test_event_spurious_LCALTA_15 pass
2747 06:19:24.522703 alsa_mixer-test_get_value_LCALTA_14 pass
2748 06:19:24.523279 alsa_mixer-test_name_LCALTA_14 pass
2749 06:19:24.528191 alsa_mixer-test_write_default_LCALTA_14 pass
2750 06:19:24.533746 alsa_mixer-test_write_valid_LCALTA_14 pass
2751 06:19:24.534341 alsa_mixer-test_write_invalid_LCALTA_14 pass
2752 06:19:24.539269 alsa_mixer-test_event_missing_LCALTA_14 pass
2753 06:19:24.544847 alsa_mixer-test_event_spurious_LCALTA_14 pass
2754 06:19:24.545502 alsa_mixer-test_get_value_LCALTA_13 pass
2755 06:19:24.550365 alsa_mixer-test_name_LCALTA_13 pass
2756 06:19:24.555916 alsa_mixer-test_write_default_LCALTA_13 pass
2757 06:19:24.556561 alsa_mixer-test_write_valid_LCALTA_13 pass
2758 06:19:24.561454 alsa_mixer-test_write_invalid_LCALTA_13 pass
2759 06:19:24.567011 alsa_mixer-test_event_missing_LCALTA_13 pass
2760 06:19:24.567609 alsa_mixer-test_event_spurious_LCALTA_13 pass
2761 06:19:24.572616 alsa_mixer-test_get_value_LCALTA_12 pass
2762 06:19:24.578170 alsa_mixer-test_name_LCALTA_12 pass
2763 06:19:24.578881 alsa_mixer-test_write_default_LCALTA_12 pass
2764 06:19:24.583710 alsa_mixer-test_write_valid_LCALTA_12 pass
2765 06:19:24.589187 alsa_mixer-test_write_invalid_LCALTA_12 pass
2766 06:19:24.594750 alsa_mixer-test_event_missing_LCALTA_12 pass
2767 06:19:24.595370 alsa_mixer-test_event_spurious_LCALTA_12 pass
2768 06:19:24.600278 alsa_mixer-test_get_value_LCALTA_11 pass
2769 06:19:24.605829 alsa_mixer-test_name_LCALTA_11 pass
2770 06:19:24.606443 alsa_mixer-test_write_default_LCALTA_11 pass
2771 06:19:24.611369 alsa_mixer-test_write_valid_LCALTA_11 pass
2772 06:19:24.616932 alsa_mixer-test_write_invalid_LCALTA_11 pass
2773 06:19:24.617554 alsa_mixer-test_event_missing_LCALTA_11 pass
2774 06:19:24.622468 alsa_mixer-test_event_spurious_LCALTA_11 pass
2775 06:19:24.628048 alsa_mixer-test_get_value_LCALTA_10 pass
2776 06:19:24.628652 alsa_mixer-test_name_LCALTA_10 pass
2777 06:19:24.633580 alsa_mixer-test_write_default_LCALTA_10 pass
2778 06:19:24.639106 alsa_mixer-test_write_valid_LCALTA_10 pass
2779 06:19:24.639728 alsa_mixer-test_write_invalid_LCALTA_10 pass
2780 06:19:24.644758 alsa_mixer-test_event_missing_LCALTA_10 pass
2781 06:19:24.650197 alsa_mixer-test_event_spurious_LCALTA_10 pass
2782 06:19:24.655758 alsa_mixer-test_get_value_LCALTA_9 pass
2783 06:19:24.656398 alsa_mixer-test_name_LCALTA_9 pass
2784 06:19:24.661298 alsa_mixer-test_write_default_LCALTA_9 pass
2785 06:19:24.666851 alsa_mixer-test_write_valid_LCALTA_9 pass
2786 06:19:24.667454 alsa_mixer-test_write_invalid_LCALTA_9 pass
2787 06:19:24.672401 alsa_mixer-test_event_missing_LCALTA_9 pass
2788 06:19:24.677945 alsa_mixer-test_event_spurious_LCALTA_9 pass
2789 06:19:24.678537 alsa_mixer-test_get_value_LCALTA_8 pass
2790 06:19:24.683478 alsa_mixer-test_name_LCALTA_8 pass
2791 06:19:24.689031 alsa_mixer-test_write_default_LCALTA_8 pass
2792 06:19:24.689635 alsa_mixer-test_write_valid_LCALTA_8 pass
2793 06:19:24.694624 alsa_mixer-test_write_invalid_LCALTA_8 pass
2794 06:19:24.700135 alsa_mixer-test_event_missing_LCALTA_8 pass
2795 06:19:24.700743 alsa_mixer-test_event_spurious_LCALTA_8 pass
2796 06:19:24.705715 alsa_mixer-test_get_value_LCALTA_7 pass
2797 06:19:24.711228 alsa_mixer-test_name_LCALTA_7 pass
2798 06:19:24.711827 alsa_mixer-test_write_default_LCALTA_7 pass
2799 06:19:24.716772 alsa_mixer-test_write_valid_LCALTA_7 pass
2800 06:19:24.722315 alsa_mixer-test_write_invalid_LCALTA_7 pass
2801 06:19:24.722918 alsa_mixer-test_event_missing_LCALTA_7 pass
2802 06:19:24.727843 alsa_mixer-test_event_spurious_LCALTA_7 pass
2803 06:19:24.733404 alsa_mixer-test_get_value_LCALTA_6 pass
2804 06:19:24.733991 alsa_mixer-test_name_LCALTA_6 pass
2805 06:19:24.738971 alsa_mixer-test_write_default_LCALTA_6 pass
2806 06:19:24.744516 alsa_mixer-test_write_valid_LCALTA_6 pass
2807 06:19:24.745151 alsa_mixer-test_write_invalid_LCALTA_6 pass
2808 06:19:24.750042 alsa_mixer-test_event_missing_LCALTA_6 pass
2809 06:19:24.755613 alsa_mixer-test_event_spurious_LCALTA_6 pass
2810 06:19:24.756278 alsa_mixer-test_get_value_LCALTA_5 pass
2811 06:19:24.761135 alsa_mixer-test_name_LCALTA_5 pass
2812 06:19:24.766735 alsa_mixer-test_write_default_LCALTA_5 pass
2813 06:19:24.767360 alsa_mixer-test_write_valid_LCALTA_5 pass
2814 06:19:24.772352 alsa_mixer-test_write_invalid_LCALTA_5 pass
2815 06:19:24.778043 alsa_mixer-test_event_missing_LCALTA_5 pass
2816 06:19:24.778843 alsa_mixer-test_event_spurious_LCALTA_5 pass
2817 06:19:24.783435 alsa_mixer-test_get_value_LCALTA_4 pass
2818 06:19:24.788926 alsa_mixer-test_name_LCALTA_4 pass
2819 06:19:24.789584 alsa_mixer-test_write_default_LCALTA_4 pass
2820 06:19:24.794433 alsa_mixer-test_write_valid_LCALTA_4 pass
2821 06:19:24.800053 alsa_mixer-test_write_invalid_LCALTA_4 pass
2822 06:19:24.800691 alsa_mixer-test_event_missing_LCALTA_4 pass
2823 06:19:24.805503 alsa_mixer-test_event_spurious_LCALTA_4 pass
2824 06:19:24.811072 alsa_mixer-test_get_value_LCALTA_3 pass
2825 06:19:24.811640 alsa_mixer-test_name_LCALTA_3 pass
2826 06:19:24.816750 alsa_mixer-test_write_default_LCALTA_3 pass
2827 06:19:24.822242 alsa_mixer-test_write_valid_LCALTA_3 pass
2828 06:19:24.822827 alsa_mixer-test_write_invalid_LCALTA_3 pass
2829 06:19:24.827793 alsa_mixer-test_event_missing_LCALTA_3 pass
2830 06:19:24.833255 alsa_mixer-test_event_spurious_LCALTA_3 pass
2831 06:19:24.833799 alsa_mixer-test_get_value_LCALTA_2 pass
2832 06:19:24.838780 alsa_mixer-test_name_LCALTA_2 pass
2833 06:19:24.844345 alsa_mixer-test_write_default_LCALTA_2 pass
2834 06:19:24.844759 alsa_mixer-test_write_valid_LCALTA_2 pass
2835 06:19:24.849898 alsa_mixer-test_write_invalid_LCALTA_2 pass
2836 06:19:24.855433 alsa_mixer-test_event_missing_LCALTA_2 pass
2837 06:19:24.860986 alsa_mixer-test_event_spurious_LCALTA_2 pass
2838 06:19:24.861394 alsa_mixer-test_get_value_LCALTA_1 pass
2839 06:19:24.866540 alsa_mixer-test_name_LCALTA_1 pass
2840 06:19:24.867100 alsa_mixer-test_write_default_LCALTA_1 pass
2841 06:19:24.872089 alsa_mixer-test_write_valid_LCALTA_1 pass
2842 06:19:24.877626 alsa_mixer-test_write_invalid_LCALTA_1 pass
2843 06:19:24.883149 alsa_mixer-test_event_missing_LCALTA_1 pass
2844 06:19:24.883499 alsa_mixer-test_event_spurious_LCALTA_1 pass
2845 06:19:24.888749 alsa_mixer-test_get_value_LCALTA_0 pass
2846 06:19:24.889257 alsa_mixer-test_name_LCALTA_0 pass
2847 06:19:24.894241 alsa_mixer-test_write_default_LCALTA_0 pass
2848 06:19:24.899786 alsa_mixer-test_write_valid_LCALTA_0 pass
2849 06:19:24.905332 alsa_mixer-test_write_invalid_LCALTA_0 pass
2850 06:19:24.905681 alsa_mixer-test_event_missing_LCALTA_0 pass
2851 06:19:24.910870 alsa_mixer-test_event_spurious_LCALTA_0 pass
2852 06:19:24.911351 alsa_mixer-test pass
2853 06:19:24.916419 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2854 06:19:24.921992 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2855 06:19:24.927541 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2856 06:19:24.933100 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2857 06:19:24.933627 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2858 06:19:24.938616 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2859 06:19:24.944171 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2860 06:19:24.949745 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2861 06:19:24.955257 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2862 06:19:24.960800 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2863 06:19:24.961311 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2864 06:19:24.966372 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2865 06:19:24.971919 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2866 06:19:24.977503 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2867 06:19:24.983017 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2868 06:19:24.988644 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2869 06:19:24.989126 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2870 06:19:24.994089 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2871 06:19:24.999629 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2872 06:19:25.005191 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2873 06:19:25.010749 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2874 06:19:25.016256 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2875 06:19:25.016706 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2876 06:19:25.021817 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2877 06:19:25.027369 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2878 06:19:25.032897 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2879 06:19:25.038442 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2880 06:19:25.044022 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2881 06:19:25.044478 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2882 06:19:25.049540 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2883 06:19:25.055091 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2884 06:19:25.060754 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2885 06:19:25.066222 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2886 06:19:25.071804 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2887 06:19:25.077288 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2888 06:19:25.077763 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2889 06:19:25.082846 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2890 06:19:25.088395 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2891 06:19:25.094002 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2892 06:19:25.099536 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2893 06:19:25.105073 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2894 06:19:25.105673 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2895 06:19:25.110637 alsa_pcm-test pass
2896 06:19:25.116185 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2897 06:19:25.127279 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2898 06:19:25.132832 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2899 06:19:25.143926 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2900 06:19:25.149360 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2901 06:19:25.154963 alsa_test-pcmtest-driver pass
2902 06:19:25.160473 + ../../utils/send-to-lava.sh ./output/result.txt
2903 06:19:25.166030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2904 06:19:25.166929 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2906 06:19:25.171642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2907 06:19:25.172419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2909 06:19:25.179004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2910 06:19:25.179720 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2912 06:19:25.219429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2913 06:19:25.220199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2915 06:19:25.270458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2916 06:19:25.271455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2918 06:19:25.319329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2919 06:19:25.320244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2921 06:19:25.375448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2922 06:19:25.376067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2924 06:19:25.429398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2925 06:19:25.430039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2927 06:19:25.477486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2928 06:19:25.478116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2930 06:19:25.525558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2931 06:19:25.526196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2933 06:19:25.578815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2934 06:19:25.579459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2936 06:19:25.631338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2937 06:19:25.632041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2939 06:19:25.683521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2940 06:19:25.684456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2942 06:19:25.733421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2943 06:19:25.735615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2945 06:19:25.793655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2946 06:19:25.795386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2948 06:19:25.844426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2949 06:19:25.845335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2951 06:19:25.896602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2952 06:19:25.897504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2954 06:19:25.949549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2955 06:19:25.950421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2957 06:19:25.997898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2958 06:19:25.998817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2960 06:19:26.046242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2961 06:19:26.047309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2963 06:19:26.097393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2964 06:19:26.098503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2966 06:19:26.149935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2967 06:19:26.150970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2969 06:19:26.204800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2970 06:19:26.205659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2972 06:19:26.246740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2973 06:19:26.247551 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2975 06:19:26.305139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2976 06:19:26.305939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2978 06:19:26.355677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2979 06:19:26.356538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2981 06:19:26.399733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2982 06:19:26.400536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
2984 06:19:26.444325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
2985 06:19:26.445070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
2987 06:19:26.497400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
2988 06:19:26.498201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
2990 06:19:26.547177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
2991 06:19:26.547970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
2993 06:19:26.590843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
2994 06:19:26.591627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
2996 06:19:26.637576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
2997 06:19:26.638328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
2999 06:19:26.683539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3000 06:19:26.684491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3002 06:19:26.728628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3003 06:19:26.729606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3005 06:19:26.779116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3006 06:19:26.780182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3008 06:19:26.836439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3009 06:19:26.837563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3011 06:19:26.892744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3012 06:19:26.893755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3014 06:19:26.945817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3015 06:19:26.946826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3017 06:19:27.000667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3018 06:19:27.001608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3020 06:19:27.047223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3021 06:19:27.048153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3023 06:19:27.100806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3024 06:19:27.101716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3026 06:19:27.145632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3027 06:19:27.146680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3029 06:19:27.194361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3030 06:19:27.195296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3032 06:19:27.245350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3033 06:19:27.246448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3035 06:19:27.290429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3036 06:19:27.291447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3038 06:19:27.337375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3039 06:19:27.338389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3041 06:19:27.384865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3042 06:19:27.385856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3044 06:19:27.438636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3045 06:19:27.439630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3047 06:19:27.487962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3048 06:19:27.488920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3050 06:19:27.534243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3051 06:19:27.535286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3053 06:19:27.580196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3054 06:19:27.581257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3056 06:19:27.624810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3057 06:19:27.625769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3059 06:19:27.677964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3060 06:19:27.678860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3062 06:19:27.725436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3063 06:19:27.726316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3065 06:19:27.785081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3066 06:19:27.785978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3068 06:19:27.829924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3069 06:19:27.830765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3071 06:19:27.881671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3072 06:19:27.882533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3074 06:19:27.932812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3075 06:19:27.933713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3077 06:19:27.976166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3078 06:19:27.977018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3080 06:19:28.020588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3081 06:19:28.021383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3083 06:19:28.078084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3084 06:19:28.078928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3086 06:19:28.127932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3087 06:19:28.128815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3089 06:19:28.171952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3090 06:19:28.172783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3092 06:19:28.227488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3093 06:19:28.228363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3095 06:19:28.277612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3096 06:19:28.278438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3098 06:19:28.322070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3099 06:19:28.322817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3101 06:19:28.372473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3102 06:19:28.373275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3104 06:19:28.416630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3105 06:19:28.417372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3107 06:19:28.468364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3108 06:19:28.469088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3110 06:19:28.514788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3111 06:19:28.515613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3113 06:19:28.569839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3114 06:19:28.570698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3116 06:19:28.615565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3117 06:19:28.616466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3119 06:19:28.660752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3120 06:19:28.661611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3122 06:19:28.709807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3123 06:19:28.710629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3125 06:19:28.753403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3126 06:19:28.754213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3128 06:19:28.800274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3129 06:19:28.801087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3131 06:19:28.846388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3132 06:19:28.847164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3134 06:19:28.900669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3135 06:19:28.901266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3137 06:19:28.948292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3138 06:19:28.948880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3140 06:19:28.996861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3141 06:19:28.997447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3143 06:19:29.050213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3144 06:19:29.050797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3146 06:19:29.098858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3147 06:19:29.099431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3149 06:19:29.146168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3150 06:19:29.146740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3152 06:19:29.198971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3153 06:19:29.199546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3155 06:19:29.250547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3156 06:19:29.251133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3158 06:19:29.304847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3159 06:19:29.305461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3161 06:19:29.348059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3162 06:19:29.348702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3164 06:19:29.395225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3165 06:19:29.395811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3167 06:19:29.447382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3168 06:19:29.447955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3170 06:19:29.492643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3171 06:19:29.493250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3173 06:19:29.545208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3174 06:19:29.545804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3176 06:19:29.602264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3177 06:19:29.602875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3179 06:19:29.652765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3180 06:19:29.653352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3182 06:19:29.705228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3183 06:19:29.705806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3185 06:19:29.760356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3186 06:19:29.760966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3188 06:19:29.811210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3189 06:19:29.811799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3191 06:19:29.856381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3192 06:19:29.857022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3194 06:19:29.925942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3195 06:19:29.926636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3197 06:19:29.992418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3198 06:19:29.993072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3200 06:19:30.089831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3201 06:19:30.090445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3203 06:19:30.155334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3204 06:19:30.156291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3206 06:19:30.216658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3207 06:19:30.217560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3209 06:19:30.261345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3210 06:19:30.262052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3212 06:19:30.311023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3213 06:19:30.312942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3215 06:19:30.363271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3216 06:19:30.364168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3218 06:19:30.414853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3219 06:19:30.415850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3221 06:19:30.469744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3222 06:19:30.470359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3224 06:19:30.514930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3225 06:19:30.515556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3227 06:19:30.562320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3228 06:19:30.562956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3230 06:19:30.622312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3231 06:19:30.622945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3233 06:19:30.666633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3234 06:19:30.667300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3236 06:19:30.715761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3237 06:19:30.716508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3239 06:19:30.773792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3240 06:19:30.774458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3242 06:19:30.818324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3243 06:19:30.819395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3245 06:19:30.872083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3246 06:19:30.872757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3248 06:19:30.921792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3249 06:19:30.922458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3251 06:19:31.009480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3252 06:19:31.010136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3254 06:19:31.064569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3255 06:19:31.065265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3257 06:19:31.118494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3258 06:19:31.119151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3260 06:19:31.175260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3261 06:19:31.175956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3263 06:19:31.239171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3264 06:19:31.240301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3266 06:19:31.297479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3267 06:19:31.298591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3269 06:19:31.356229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3270 06:19:31.357191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3272 06:19:31.414057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3273 06:19:31.415078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3275 06:19:31.475031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3276 06:19:31.476015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3278 06:19:31.518761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3279 06:19:31.519698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3281 06:19:31.566669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3282 06:19:31.567627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3284 06:19:31.616083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3285 06:19:31.617007 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3287 06:19:31.665117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3288 06:19:31.666076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3290 06:19:31.714870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3291 06:19:31.715794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3293 06:19:31.767228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3294 06:19:31.768104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3296 06:19:31.826533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3297 06:19:31.827464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3299 06:19:31.881120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3300 06:19:31.882020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3302 06:19:31.933394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3303 06:19:31.934330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3305 06:19:31.975131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3306 06:19:31.976012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3308 06:19:32.020072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3309 06:19:32.020954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3311 06:19:32.074650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3312 06:19:32.075542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3314 06:19:32.122215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3315 06:19:32.123108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3317 06:19:32.167798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3318 06:19:32.168691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3320 06:19:32.220279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3321 06:19:32.221160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3323 06:19:32.277039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3324 06:19:32.277907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3326 06:19:32.322755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3327 06:19:32.323627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3329 06:19:32.369659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3330 06:19:32.370578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3332 06:19:32.416275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3333 06:19:32.417180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3335 06:19:32.471431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3336 06:19:32.472337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3338 06:19:32.529257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3339 06:19:32.530157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3341 06:19:32.578590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3342 06:19:32.579376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3344 06:19:32.634328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3345 06:19:32.635183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3347 06:19:32.684710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3348 06:19:32.685612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3350 06:19:32.743584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3351 06:19:32.744522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3353 06:19:32.788701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3354 06:19:32.789506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3356 06:19:32.840349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3357 06:19:32.841214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3359 06:19:32.891477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3360 06:19:32.892349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3362 06:19:32.943437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3363 06:19:32.944366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3365 06:19:32.997221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3366 06:19:32.998241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3368 06:19:33.048521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3369 06:19:33.049215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3371 06:19:33.091942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3372 06:19:33.092879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3374 06:19:33.142209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3375 06:19:33.142842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3377 06:19:33.195605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3378 06:19:33.196515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3380 06:19:33.247414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3381 06:19:33.248200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3383 06:19:33.305201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3384 06:19:33.306037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3386 06:19:33.350325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3387 06:19:33.351160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3389 06:19:33.402389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3390 06:19:33.403228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3392 06:19:33.447191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3393 06:19:33.448039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3395 06:19:33.501728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3396 06:19:33.502550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3398 06:19:33.545356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3399 06:19:33.546042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3401 06:19:33.594278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3402 06:19:33.594877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3404 06:19:33.652581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3405 06:19:33.653194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3407 06:19:33.703602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3408 06:19:33.704101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3410 06:19:33.754023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3411 06:19:33.754509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3413 06:19:33.802929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3414 06:19:33.803686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3416 06:19:33.849371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3417 06:19:33.850123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3419 06:19:33.909067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3420 06:19:33.909815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3422 06:19:33.959955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3423 06:19:33.960735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3425 06:19:34.006260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3426 06:19:34.006998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3428 06:19:34.056651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3429 06:19:34.057564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3431 06:19:34.101463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3432 06:19:34.102350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3434 06:19:34.153200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3435 06:19:34.154019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3437 06:19:34.199673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3438 06:19:34.200518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3440 06:19:34.249328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3441 06:19:34.250075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3443 06:19:34.298601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3444 06:19:34.299349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3446 06:19:34.344021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3447 06:19:34.344770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3449 06:19:34.400792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3450 06:19:34.401556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3452 06:19:34.444721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3453 06:19:34.445477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3455 06:19:34.489229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3456 06:19:34.489990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3458 06:19:34.534938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3459 06:19:34.535725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3461 06:19:34.584632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3462 06:19:34.585404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3464 06:19:34.631682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3465 06:19:34.632512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3467 06:19:34.679620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3468 06:19:34.680421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3470 06:19:34.733404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3471 06:19:34.734168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3473 06:19:34.785450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3474 06:19:34.786221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3476 06:19:34.829313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3477 06:19:34.830086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3479 06:19:34.880687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3480 06:19:34.881461 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3482 06:19:34.929789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3483 06:19:34.930555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3485 06:19:34.980581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3486 06:19:34.981351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3488 06:19:35.032611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3489 06:19:35.033374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3491 06:19:35.075456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3492 06:19:35.076230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3494 06:19:35.126341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3495 06:19:35.127168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3497 06:19:35.178653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3498 06:19:35.179508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3500 06:19:35.221864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3501 06:19:35.222638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3503 06:19:35.266114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3504 06:19:35.266886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3506 06:19:35.315656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3507 06:19:35.317032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3509 06:19:35.361146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3510 06:19:35.361922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3512 06:19:35.405223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3513 06:19:35.406031 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3515 06:19:35.449842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3516 06:19:35.450627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3518 06:19:35.500082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3519 06:19:35.500853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3521 06:19:35.550105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3522 06:19:35.550877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3524 06:19:35.602333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3525 06:19:35.603198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3527 06:19:35.653606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3528 06:19:35.654388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3530 06:19:35.702461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3531 06:19:35.703239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3533 06:19:35.752525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3534 06:19:35.753086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3536 06:19:35.796560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3537 06:19:35.797170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3539 06:19:35.861752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3540 06:19:35.862383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3542 06:19:35.906570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3543 06:19:35.907142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3545 06:19:35.959541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3546 06:19:35.960227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3548 06:19:36.003639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3549 06:19:36.004589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3551 06:19:36.062760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3552 06:19:36.063973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3554 06:19:36.117486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3555 06:19:36.118592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3557 06:19:36.288100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3558 06:19:36.289074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3560 06:19:36.338801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3561 06:19:36.339836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3563 06:19:36.382883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3564 06:19:36.383544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3566 06:19:36.437644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3567 06:19:36.438265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3569 06:19:36.492475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3570 06:19:36.493315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3572 06:19:36.542782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3573 06:19:36.543635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3575 06:19:36.585780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3576 06:19:36.586610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3578 06:19:36.641352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3579 06:19:36.642182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3581 06:19:36.696228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3582 06:19:36.697057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3584 06:19:36.745267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3585 06:19:36.746059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3587 06:19:36.793566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3588 06:19:36.794380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3590 06:19:36.837736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3591 06:19:36.838555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3593 06:19:36.889027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3594 06:19:36.889839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3596 06:19:36.937979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3597 06:19:36.938714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3599 06:19:36.987649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3600 06:19:36.988418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3602 06:19:37.037119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3603 06:19:37.037835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3605 06:19:37.089384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3606 06:19:37.090145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3608 06:19:37.138884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3609 06:19:37.139599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3611 06:19:37.196454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3612 06:19:37.197076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3614 06:19:37.239247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3615 06:19:37.240087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3617 06:19:37.292402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3618 06:19:37.293242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3620 06:19:37.335809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3621 06:19:37.336813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3623 06:19:37.385218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3624 06:19:37.386069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3626 06:19:37.444778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3627 06:19:37.445613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3629 06:19:37.488601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3630 06:19:37.489380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3632 06:19:37.545797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3633 06:19:37.546607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3635 06:19:37.598899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3636 06:19:37.599756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3638 06:19:37.648704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3639 06:19:37.649532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3641 06:19:37.698088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3642 06:19:37.698928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3644 06:19:37.749770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3645 06:19:37.750694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3647 06:19:37.795315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3648 06:19:37.796269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3650 06:19:37.839279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3651 06:19:37.840370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3653 06:19:37.882153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3654 06:19:37.882984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3656 06:19:37.930121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3657 06:19:37.930956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3659 06:19:37.978639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3660 06:19:37.979407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3662 06:19:38.022299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3663 06:19:38.022999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3665 06:19:38.071232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3666 06:19:38.072036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3668 06:19:38.116626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3669 06:19:38.117503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3671 06:19:38.173148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3672 06:19:38.174066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3674 06:19:38.230356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3675 06:19:38.231219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3677 06:19:38.273825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3678 06:19:38.274659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3680 06:19:38.326079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3681 06:19:38.327029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3683 06:19:38.377113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3684 06:19:38.377948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3686 06:19:38.429395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3687 06:19:38.430229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3689 06:19:38.487415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3690 06:19:38.488230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3692 06:19:38.532493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3693 06:19:38.533287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3695 06:19:38.587648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3696 06:19:38.588568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3698 06:19:38.629597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3699 06:19:38.630426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3701 06:19:38.676742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3702 06:19:38.679043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3704 06:19:38.729481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3705 06:19:38.730304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3707 06:19:38.777702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3708 06:19:38.778504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3710 06:19:38.826098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3711 06:19:38.826914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3713 06:19:38.869497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3714 06:19:38.870311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3716 06:19:38.922658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3717 06:19:38.923423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3719 06:19:38.978317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3720 06:19:38.979104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3722 06:19:39.028078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3723 06:19:39.028829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3725 06:19:39.079612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3726 06:19:39.080434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3728 06:19:39.123472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3729 06:19:39.124219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3731 06:19:39.174039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3732 06:19:39.174812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3734 06:19:39.216638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3735 06:19:39.217472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3737 06:19:39.260666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3738 06:19:39.261480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3740 06:19:39.311359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3741 06:19:39.312151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3743 06:19:39.364222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3744 06:19:39.365018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3746 06:19:39.414029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3747 06:19:39.414809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3749 06:19:39.460914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3750 06:19:39.461696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3752 06:19:39.510081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3753 06:19:39.510895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3755 06:19:39.552663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3756 06:19:39.553684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3758 06:19:39.605837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3759 06:19:39.606764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3761 06:19:39.651409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3762 06:19:39.652430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3764 06:19:39.693890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3765 06:19:39.694670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3767 06:19:39.748394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3768 06:19:39.749149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3770 06:19:39.797887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3771 06:19:39.798685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3773 06:19:39.845701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3774 06:19:39.846355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3776 06:19:39.894565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3777 06:19:39.895782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3779 06:19:39.945331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3780 06:19:39.946379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3782 06:19:39.988861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3783 06:19:39.989724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3785 06:19:40.045911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3786 06:19:40.046793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3788 06:19:40.089798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3789 06:19:40.090713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3791 06:19:40.140783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3792 06:19:40.141673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3794 06:19:40.201120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3795 06:19:40.202006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3797 06:19:40.252249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3798 06:19:40.253147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3800 06:19:40.295827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3801 06:19:40.296855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3803 06:19:40.338127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3804 06:19:40.339033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3806 06:19:40.381495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3807 06:19:40.382387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3809 06:19:40.424137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3810 06:19:40.425005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3812 06:19:40.472517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3813 06:19:40.473374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3815 06:19:40.529201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3816 06:19:40.530021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3818 06:19:40.579322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3819 06:19:40.580105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3821 06:19:40.625244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3822 06:19:40.626019 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3824 06:19:40.676079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3825 06:19:40.676886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3827 06:19:40.719885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3828 06:19:40.721028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3830 06:19:40.776250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3831 06:19:40.777131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3833 06:19:40.823729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3834 06:19:40.824683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3836 06:19:40.875583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3837 06:19:40.876464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3839 06:19:40.919452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3840 06:19:40.920322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3842 06:19:40.967456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3843 06:19:40.968293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3845 06:19:41.012784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3846 06:19:41.013620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3848 06:19:41.070624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3849 06:19:41.071520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3851 06:19:41.114865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3852 06:19:41.115713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3854 06:19:41.169639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3855 06:19:41.170457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3857 06:19:41.215954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3858 06:19:41.217011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3860 06:19:41.259396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3861 06:19:41.260351 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3863 06:19:41.316202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3864 06:19:41.317222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3866 06:19:41.360788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3867 06:19:41.361660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3869 06:19:41.407268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3870 06:19:41.408121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3872 06:19:41.452409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3873 06:19:41.453269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3875 06:19:41.505466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3876 06:19:41.506362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3878 06:19:41.562199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3879 06:19:41.563216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3881 06:19:41.614216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3882 06:19:41.615155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3884 06:19:41.660087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3885 06:19:41.661148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3887 06:19:41.711809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3888 06:19:41.712774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3890 06:19:41.762423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3891 06:19:41.763325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3893 06:19:41.807495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3894 06:19:41.808438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3896 06:19:41.853876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3897 06:19:41.854782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3899 06:19:41.909159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3900 06:19:41.910083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3902 06:19:41.955880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3903 06:19:41.957336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3905 06:19:42.010020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3906 06:19:42.010912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3908 06:19:42.061764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3909 06:19:42.062688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3911 06:19:42.113101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3912 06:19:42.113942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3914 06:19:42.163006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3915 06:19:42.164015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3917 06:19:42.208434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3918 06:19:42.209287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3920 06:19:42.262820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3921 06:19:42.264742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3923 06:19:42.318037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3924 06:19:42.318868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3926 06:19:42.369940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3927 06:19:42.370831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3929 06:19:42.420858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3930 06:19:42.421709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3932 06:19:42.471818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3933 06:19:42.472727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3935 06:19:42.514890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3936 06:19:42.515837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3938 06:19:42.561125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3939 06:19:42.561946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3941 06:19:42.627169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3942 06:19:42.628128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3944 06:19:42.681236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3945 06:19:42.682043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3947 06:19:42.727345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3948 06:19:42.728219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3950 06:19:42.774078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3951 06:19:42.774966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3953 06:19:42.820192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3954 06:19:42.821281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3956 06:19:42.874839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3957 06:19:42.875782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3959 06:19:42.927212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3960 06:19:42.928398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3962 06:19:42.984892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3963 06:19:42.985891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3965 06:19:43.037666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3966 06:19:43.038692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3968 06:19:43.090520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3969 06:19:43.091511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3971 06:19:43.140290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3972 06:19:43.141257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3974 06:19:43.189290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3975 06:19:43.190217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3977 06:19:43.236827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3978 06:19:43.237777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3980 06:19:43.283059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3981 06:19:43.284024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
3983 06:19:43.328832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
3984 06:19:43.329742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
3986 06:19:43.382268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
3987 06:19:43.383238 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
3989 06:19:43.428961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
3990 06:19:43.429997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
3992 06:19:43.473868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
3993 06:19:43.474783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
3995 06:19:43.520796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
3996 06:19:43.521714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
3998 06:19:43.568969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
3999 06:19:43.569892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4001 06:19:43.623934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4002 06:19:43.624858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4004 06:19:43.680826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4005 06:19:43.681701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4007 06:19:43.738697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4008 06:19:43.739525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4010 06:19:43.785063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4011 06:19:43.785939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4013 06:19:43.844461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4014 06:19:43.845367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4016 06:19:43.890669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4017 06:19:43.891570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4019 06:19:43.935335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4020 06:19:43.936327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4022 06:19:43.991672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4023 06:19:43.992614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4025 06:19:44.040346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4026 06:19:44.041292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4028 06:19:44.087075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4029 06:19:44.087960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4031 06:19:44.145097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4032 06:19:44.145953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4034 06:19:44.197819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4035 06:19:44.198712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4037 06:19:44.248807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4038 06:19:44.249686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4040 06:19:44.294833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4041 06:19:44.295704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4043 06:19:44.342244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4044 06:19:44.343111 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4046 06:19:44.402847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4047 06:19:44.403721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4049 06:19:44.451245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4050 06:19:44.452237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4052 06:19:44.496294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4053 06:19:44.497160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4055 06:19:44.541460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4056 06:19:44.542370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4058 06:19:44.595130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4059 06:19:44.596041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4061 06:19:44.643690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4062 06:19:44.644581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4064 06:19:44.694725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4065 06:19:44.695611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4067 06:19:44.745593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4068 06:19:44.746478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4070 06:19:44.805224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4071 06:19:44.806122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4073 06:19:44.855138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4074 06:19:44.856115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4076 06:19:44.900133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4077 06:19:44.901047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4079 06:19:44.947437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4080 06:19:44.948371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4082 06:19:45.001247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4083 06:19:45.002142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4085 06:19:45.054826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4086 06:19:45.055843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4088 06:19:45.108411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4089 06:19:45.109282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4091 06:19:45.163523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4092 06:19:45.164438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4094 06:19:45.210994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4095 06:19:45.211907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4097 06:19:45.255835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4098 06:19:45.256715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4100 06:19:45.310317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4101 06:19:45.311177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4103 06:19:45.354183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4104 06:19:45.355139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4106 06:19:45.407496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4107 06:19:45.408382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4109 06:19:45.455404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4110 06:19:45.456342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4112 06:19:45.508212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4113 06:19:45.509112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4115 06:19:45.553550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4116 06:19:45.554449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4118 06:19:45.606008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4119 06:19:45.606822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4121 06:19:45.662041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4122 06:19:45.662854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4124 06:19:45.711748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4125 06:19:45.712584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4127 06:19:45.762072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4128 06:19:45.762893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4130 06:19:45.808400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4131 06:19:45.809261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4133 06:19:45.859097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4134 06:19:45.860034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4136 06:19:45.904192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4137 06:19:45.905090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4139 06:19:45.957957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4140 06:19:45.958900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4142 06:19:46.005355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4143 06:19:46.006314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4145 06:19:46.051062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4146 06:19:46.052034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4148 06:19:46.110606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4149 06:19:46.111608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4151 06:19:46.159251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4152 06:19:46.160298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4154 06:19:46.213098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4155 06:19:46.214243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4157 06:19:46.262589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4158 06:19:46.263603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4160 06:19:46.306343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4161 06:19:46.307248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4163 06:19:46.359676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4164 06:19:46.360574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4166 06:19:46.408704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4167 06:19:46.409589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4169 06:19:46.464446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4170 06:19:46.465448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4172 06:19:46.521221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4173 06:19:46.522178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4175 06:19:46.571153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4176 06:19:46.572075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4178 06:19:46.628485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4179 06:19:46.629508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4181 06:19:46.677300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4182 06:19:46.678294 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4184 06:19:46.723053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4185 06:19:46.723950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4187 06:19:46.770737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4189 06:19:46.773696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4190 06:19:46.823142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4191 06:19:46.824076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4193 06:19:46.870248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4194 06:19:46.871127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4196 06:19:46.917154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4197 06:19:46.918024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4199 06:19:46.961224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4200 06:19:46.962095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4202 06:19:47.020401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4203 06:19:47.021299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4205 06:19:47.068201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4206 06:19:47.069076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4208 06:19:47.131323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4209 06:19:47.132234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4211 06:19:47.179179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4212 06:19:47.180104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4214 06:19:47.224527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4215 06:19:47.225409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4217 06:19:47.273431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4218 06:19:47.274301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4220 06:19:47.323200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4221 06:19:47.324171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4223 06:19:47.375870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4224 06:19:47.376853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4226 06:19:47.427542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4227 06:19:47.428573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4229 06:19:47.477332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4230 06:19:47.478182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4232 06:19:47.520390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4233 06:19:47.521234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4235 06:19:47.577546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4236 06:19:47.578393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4238 06:19:47.632725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4239 06:19:47.633582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4241 06:19:47.677151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4242 06:19:47.678114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4244 06:19:47.725113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4245 06:19:47.726014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4247 06:19:47.775775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4248 06:19:47.776702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4250 06:19:47.821326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4251 06:19:47.822227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4253 06:19:47.878399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4254 06:19:47.879433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4256 06:19:47.930211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4257 06:19:47.931285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4259 06:19:47.984177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4260 06:19:47.985133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4262 06:19:48.036011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4263 06:19:48.036910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4265 06:19:48.091838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4266 06:19:48.092774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4268 06:19:48.138951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4269 06:19:48.139834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4271 06:19:48.186764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4272 06:19:48.187645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4274 06:19:48.239104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4275 06:19:48.240027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4277 06:19:48.290743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4278 06:19:48.291670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4280 06:19:48.338006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4281 06:19:48.338928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4283 06:19:48.386119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4284 06:19:48.386998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4286 06:19:48.431804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4287 06:19:48.432740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4289 06:19:48.488275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4290 06:19:48.489112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4292 06:19:48.547541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4293 06:19:48.548544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4295 06:19:48.595875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4296 06:19:48.597000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4298 06:19:48.649367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4299 06:19:48.650134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4301 06:19:48.692740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4302 06:19:48.693668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4304 06:19:48.737082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4305 06:19:48.737940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4307 06:19:48.791975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4308 06:19:48.792894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4310 06:19:48.845078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4311 06:19:48.845958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4313 06:19:48.896269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4314 06:19:48.897168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4316 06:19:48.938187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4317 06:19:48.939048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4319 06:19:48.991429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4320 06:19:48.992304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4322 06:19:49.037636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4323 06:19:49.038503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4325 06:19:49.092918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4326 06:19:49.093897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4328 06:19:49.142201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4329 06:19:49.143201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4331 06:19:49.196607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4332 06:19:49.197580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4334 06:19:49.239011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4335 06:19:49.239622 + set +x
4336 06:19:49.240365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4338 06:19:49.245758 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 681515_1.6.2.4.5>
4339 06:19:49.246287 <LAVA_TEST_RUNNER EXIT>
4340 06:19:49.246986 Received signal: <ENDRUN> 1_kselftest-alsa 681515_1.6.2.4.5
4341 06:19:49.247468 Ending use of test pattern.
4342 06:19:49.247904 Ending test lava.1_kselftest-alsa (681515_1.6.2.4.5), duration 39.15
4344 06:19:49.249582 ok: lava_test_shell seems to have completed
4345 06:19:49.273978 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
shardfile-alsa: pass
4346 06:19:49.275882 end: 3.1 lava-test-shell (duration 00:00:40) [common]
4347 06:19:49.276516 end: 3 lava-test-retry (duration 00:00:40) [common]
4348 06:19:49.277142 start: 4 finalize (timeout 00:06:08) [common]
4349 06:19:49.277765 start: 4.1 power-off (timeout 00:00:30) [common]
4350 06:19:49.278785 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4351 06:19:49.313743 >> OK - accepted request
4352 06:19:49.315647 Returned 0 in 0 seconds
4353 06:19:49.416990 end: 4.1 power-off (duration 00:00:00) [common]
4355 06:19:49.418847 start: 4.2 read-feedback (timeout 00:06:07) [common]
4356 06:19:49.420084 Listened to connection for namespace 'common' for up to 1s
4357 06:19:50.419968 Finalising connection for namespace 'common'
4358 06:19:50.420805 Disconnecting from shell: Finalise
4359 06:19:50.421347 / #
4360 06:19:50.522380 end: 4.2 read-feedback (duration 00:00:01) [common]
4361 06:19:50.523229 end: 4 finalize (duration 00:00:01) [common]
4362 06:19:50.524046 Cleaning after the job
4363 06:19:50.524729 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/ramdisk
4364 06:19:50.537251 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/kernel
4365 06:19:50.560476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/dtb
4366 06:19:50.561852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/nfsrootfs
4367 06:19:50.598489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/681515/tftp-deploy-l5bomynz/modules
4368 06:19:50.605215 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/681515
4369 06:19:53.980504 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/681515
4370 06:19:53.981089 Job finished correctly