Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 21:31:16.228567 lava-dispatcher, installed at version: 2023.08
2 21:31:16.228869 start: 0 validate
3 21:31:16.229058 Start time: 2024-08-31 21:31:16.229046+00:00 (UTC)
4 21:31:16.229282 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 21:31:16.584345 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/kernel/zImage exists
6 21:31:16.698575 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb exists
7 21:31:16.812469 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 21:31:16.926186 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/modules.tar.xz exists
9 21:31:17.044612 validate duration: 0.82
11 21:31:17.045389 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 21:31:17.045722 start: 1.1 download-retry (timeout 00:10:00) [common]
13 21:31:17.046036 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 21:31:17.046489 Not decompressing ramdisk as can be used compressed.
15 21:31:17.046787 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 21:31:17.047029 saving as /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/ramdisk/initrd.cpio.gz
17 21:31:17.047273 total size: 4775763 (4 MB)
18 21:31:17.273977 progress 0 % (0 MB)
19 21:31:17.610369 progress 5 % (0 MB)
20 21:31:17.831316 progress 10 % (0 MB)
21 21:31:17.854513 progress 15 % (0 MB)
22 21:31:17.942958 progress 20 % (0 MB)
23 21:31:17.957328 progress 25 % (1 MB)
24 21:31:18.059229 progress 30 % (1 MB)
25 21:31:18.166047 progress 35 % (1 MB)
26 21:31:18.193606 progress 40 % (1 MB)
27 21:31:18.288685 progress 45 % (2 MB)
28 21:31:18.391072 progress 50 % (2 MB)
29 21:31:18.421031 progress 55 % (2 MB)
30 21:31:18.520235 progress 60 % (2 MB)
31 21:31:18.617223 progress 65 % (2 MB)
32 21:31:18.646682 progress 70 % (3 MB)
33 21:31:18.747150 progress 75 % (3 MB)
34 21:31:18.841731 progress 80 % (3 MB)
35 21:31:18.867687 progress 85 % (3 MB)
36 21:31:18.970939 progress 90 % (4 MB)
37 21:31:19.063603 progress 95 % (4 MB)
38 21:31:19.091235 progress 100 % (4 MB)
39 21:31:19.092013 4 MB downloaded in 2.04 s (2.23 MB/s)
40 21:31:19.092514 end: 1.1.1 http-download (duration 00:00:02) [common]
42 21:31:19.093368 end: 1.1 download-retry (duration 00:00:02) [common]
43 21:31:19.093663 start: 1.2 download-retry (timeout 00:09:58) [common]
44 21:31:19.093949 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 21:31:19.094357 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/kernel/zImage
46 21:31:19.094588 saving as /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/kernel/zImage
47 21:31:19.094808 total size: 11964928 (11 MB)
48 21:31:19.095028 No compression specified
49 21:31:19.210760 progress 0 % (0 MB)
50 21:31:19.561566 progress 5 % (0 MB)
51 21:31:19.879857 progress 10 % (1 MB)
52 21:31:20.106476 progress 15 % (1 MB)
53 21:31:20.335017 progress 20 % (2 MB)
54 21:31:20.559228 progress 25 % (2 MB)
55 21:31:20.781965 progress 30 % (3 MB)
56 21:31:21.003702 progress 35 % (4 MB)
57 21:31:21.228791 progress 40 % (4 MB)
58 21:31:21.453448 progress 45 % (5 MB)
59 21:31:21.673789 progress 50 % (5 MB)
60 21:31:21.894852 progress 55 % (6 MB)
61 21:31:22.048973 progress 60 % (6 MB)
62 21:31:22.256206 progress 65 % (7 MB)
63 21:31:22.475176 progress 70 % (8 MB)
64 21:31:22.693418 progress 75 % (8 MB)
65 21:31:22.914804 progress 80 % (9 MB)
66 21:31:23.134269 progress 85 % (9 MB)
67 21:31:23.353765 progress 90 % (10 MB)
68 21:31:23.491618 progress 95 % (10 MB)
69 21:31:23.711101 progress 100 % (11 MB)
70 21:31:23.711537 11 MB downloaded in 4.62 s (2.47 MB/s)
71 21:31:23.711990 end: 1.2.1 http-download (duration 00:00:05) [common]
73 21:31:23.712709 end: 1.2 download-retry (duration 00:00:05) [common]
74 21:31:23.712939 start: 1.3 download-retry (timeout 00:09:53) [common]
75 21:31:23.713156 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 21:31:23.713478 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
77 21:31:23.713655 saving as /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/dtb/am335x-boneblack.dtb
78 21:31:23.713822 total size: 70308 (0 MB)
79 21:31:23.713990 No compression specified
80 21:31:23.829835 progress 46 % (0 MB)
81 21:31:23.832646 progress 93 % (0 MB)
82 21:31:23.833630 progress 100 % (0 MB)
83 21:31:23.834019 0 MB downloaded in 0.12 s (0.56 MB/s)
84 21:31:23.834423 end: 1.3.1 http-download (duration 00:00:00) [common]
86 21:31:23.835225 end: 1.3 download-retry (duration 00:00:00) [common]
87 21:31:23.835508 start: 1.4 download-retry (timeout 00:09:53) [common]
88 21:31:23.835793 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 21:31:23.836149 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 21:31:23.836400 saving as /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/nfsrootfs/full.rootfs.tar
91 21:31:23.836615 total size: 117747780 (112 MB)
92 21:31:23.836840 Using unxz to decompress xz
93 21:31:23.953113 progress 0 % (0 MB)
94 21:31:26.411055 progress 5 % (5 MB)
95 21:31:28.453488 progress 10 % (11 MB)
96 21:31:30.533127 progress 15 % (16 MB)
97 21:31:32.537148 progress 20 % (22 MB)
98 21:31:34.357729 progress 25 % (28 MB)
99 21:31:35.981093 progress 30 % (33 MB)
100 21:31:37.252352 progress 35 % (39 MB)
101 21:31:38.344103 progress 40 % (44 MB)
102 21:31:39.239619 progress 45 % (50 MB)
103 21:31:39.977724 progress 50 % (56 MB)
104 21:31:40.645814 progress 55 % (61 MB)
105 21:31:41.245428 progress 60 % (67 MB)
106 21:31:41.772036 progress 65 % (73 MB)
107 21:31:42.392690 progress 70 % (78 MB)
108 21:31:42.900521 progress 75 % (84 MB)
109 21:31:43.491248 progress 80 % (89 MB)
110 21:31:44.056780 progress 85 % (95 MB)
111 21:31:44.599642 progress 90 % (101 MB)
112 21:31:45.117616 progress 95 % (106 MB)
113 21:31:45.629993 progress 100 % (112 MB)
114 21:31:45.633508 112 MB downloaded in 21.80 s (5.15 MB/s)
115 21:31:45.633856 end: 1.4.1 http-download (duration 00:00:22) [common]
117 21:31:45.634487 end: 1.4 download-retry (duration 00:00:22) [common]
118 21:31:45.634712 start: 1.5 download-retry (timeout 00:09:31) [common]
119 21:31:45.634934 start: 1.5.1 http-download (timeout 00:09:31) [common]
120 21:31:45.635261 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/modules.tar.xz
121 21:31:45.635430 saving as /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/modules/modules.tar
122 21:31:45.635600 total size: 6916596 (6 MB)
123 21:31:45.635777 Using unxz to decompress xz
124 21:31:45.751525 progress 0 % (0 MB)
125 21:31:45.982796 progress 5 % (0 MB)
126 21:31:46.204153 progress 10 % (0 MB)
127 21:31:46.233271 progress 15 % (1 MB)
128 21:31:46.309263 progress 20 % (1 MB)
129 21:31:46.336552 progress 25 % (1 MB)
130 21:31:46.364670 progress 30 % (2 MB)
131 21:31:46.538511 progress 35 % (2 MB)
132 21:31:46.567989 progress 40 % (2 MB)
133 21:31:46.592605 progress 45 % (2 MB)
134 21:31:46.773450 progress 50 % (3 MB)
135 21:31:46.801885 progress 55 % (3 MB)
136 21:31:46.826718 progress 60 % (3 MB)
137 21:31:46.901994 progress 65 % (4 MB)
138 21:31:46.994095 progress 70 % (4 MB)
139 21:31:47.087709 progress 75 % (4 MB)
140 21:31:47.132670 progress 80 % (5 MB)
141 21:31:47.231108 progress 85 % (5 MB)
142 21:31:47.318193 progress 90 % (5 MB)
143 21:31:47.364923 progress 95 % (6 MB)
144 21:31:47.461676 progress 100 % (6 MB)
145 21:31:47.464983 6 MB downloaded in 1.83 s (3.61 MB/s)
146 21:31:47.465353 end: 1.5.1 http-download (duration 00:00:02) [common]
148 21:31:47.466018 end: 1.5 download-retry (duration 00:00:02) [common]
149 21:31:47.466254 start: 1.6 prepare-tftp-overlay (timeout 00:09:30) [common]
150 21:31:47.466487 start: 1.6.1 extract-nfsrootfs (timeout 00:09:30) [common]
151 21:31:52.969040 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax
152 21:31:52.969334 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 21:31:52.969477 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
154 21:31:52.969748 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig
155 21:31:52.969916 makedir: /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin
156 21:31:52.970047 makedir: /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/tests
157 21:31:52.970176 makedir: /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/results
158 21:31:52.970317 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-add-keys
159 21:31:52.970520 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-add-sources
160 21:31:52.970693 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-background-process-start
161 21:31:52.970864 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-background-process-stop
162 21:31:52.971051 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-common-functions
163 21:31:52.971219 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-echo-ipv4
164 21:31:52.971385 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-install-packages
165 21:31:52.971550 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-installed-packages
166 21:31:52.971712 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-os-build
167 21:31:52.971876 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-probe-channel
168 21:31:52.972039 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-probe-ip
169 21:31:52.972221 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-target-ip
170 21:31:52.972401 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-target-mac
171 21:31:52.972565 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-target-storage
172 21:31:52.972732 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-test-case
173 21:31:52.972898 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-test-event
174 21:31:52.973059 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-test-feedback
175 21:31:52.973221 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-test-raise
176 21:31:52.973383 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-test-reference
177 21:31:52.973547 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-test-runner
178 21:31:52.973710 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-test-set
179 21:31:52.973872 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-test-shell
180 21:31:52.974036 Updating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-add-keys (debian)
181 21:31:52.974252 Updating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-add-sources (debian)
182 21:31:52.974438 Updating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-install-packages (debian)
183 21:31:52.974641 Updating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-installed-packages (debian)
184 21:31:52.974826 Updating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/bin/lava-os-build (debian)
185 21:31:52.974988 Creating /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/environment
186 21:31:52.975115 LAVA metadata
187 21:31:52.975211 - LAVA_JOB_ID=1186701
188 21:31:52.975304 - LAVA_DISPATCHER_IP=192.168.11.5
189 21:31:52.975442 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
190 21:31:52.975758 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 21:31:52.975911 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
192 21:31:52.976000 skipped lava-vland-overlay
193 21:31:52.976107 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 21:31:52.976371 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
195 21:31:52.976466 skipped lava-multinode-overlay
196 21:31:52.976574 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 21:31:52.976686 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
198 21:31:52.976783 Loading test definitions
199 21:31:52.976901 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
200 21:31:52.976997 Using /lava-1186701 at stage 0
201 21:31:52.977384 uuid=1186701_1.6.2.4.1 testdef=None
202 21:31:52.977502 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 21:31:52.977617 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
204 21:31:52.978207 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 21:31:52.978531 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
207 21:31:52.979348 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 21:31:52.979686 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
210 21:31:52.980458 runner path: /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/0/tests/0_timesync-off test_uuid 1186701_1.6.2.4.1
211 21:31:52.980654 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 21:31:52.980990 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
214 21:31:52.981092 Using /lava-1186701 at stage 0
215 21:31:52.981228 Fetching tests from https://github.com/kernelci/test-definitions.git
216 21:31:52.981330 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/0/tests/1_kselftest-dt'
217 21:31:57.621173 Running '/usr/bin/git checkout kernelci.org
218 21:31:57.842487 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 21:31:57.843301 uuid=1186701_1.6.2.4.5 testdef=None
220 21:31:57.843508 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 21:31:57.843973 start: 1.6.2.4.6 test-overlay (timeout 00:09:19) [common]
223 21:31:57.845517 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 21:31:57.846003 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:19) [common]
226 21:31:57.848123 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 21:31:57.848646 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:19) [common]
229 21:31:57.850701 runner path: /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/0/tests/1_kselftest-dt test_uuid 1186701_1.6.2.4.5
230 21:31:57.850866 BOARD='beaglebone-black'
231 21:31:57.850999 BRANCH='mainline'
232 21:31:57.851128 SKIPFILE='/dev/null'
233 21:31:57.851256 SKIP_INSTALL='True'
234 21:31:57.851382 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
235 21:31:57.851511 TST_CASENAME=''
236 21:31:57.851636 TST_CMDFILES='dt'
237 21:31:57.851912 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 21:31:57.852352 Creating lava-test-runner.conf files
240 21:31:57.852442 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1186701/lava-overlay-yva1jeig/lava-1186701/0 for stage 0
241 21:31:57.852565 - 0_timesync-off
242 21:31:57.852657 - 1_kselftest-dt
243 21:31:57.852789 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 21:31:57.852905 start: 1.6.2.5 compress-overlay (timeout 00:09:19) [common]
245 21:32:06.312770 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 21:32:06.312972 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
247 21:32:06.313117 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 21:32:06.313262 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
249 21:32:06.313406 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
250 21:32:06.439160 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 21:32:06.439453 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
252 21:32:06.439615 extracting modules file /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax
253 21:32:06.739035 extracting modules file /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1186701/extract-overlay-ramdisk-5s2vwgrg/ramdisk
254 21:32:07.041162 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 21:32:07.041382 start: 1.6.5 apply-overlay-tftp (timeout 00:09:10) [common]
256 21:32:07.041516 [common] Applying overlay to NFS
257 21:32:07.041621 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1186701/compress-overlay-9hpjwftq/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax
258 21:32:08.217738 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 21:32:08.217955 start: 1.6.6 prepare-kernel (timeout 00:09:09) [common]
260 21:32:08.218109 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:09) [common]
261 21:32:08.218267 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 21:32:08.218404 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 21:32:08.218542 start: 1.6.7 configure-preseed-file (timeout 00:09:09) [common]
264 21:32:08.218674 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 21:32:08.218809 start: 1.6.8 compress-ramdisk (timeout 00:09:09) [common]
266 21:32:08.218912 Building ramdisk /var/lib/lava/dispatcher/tmp/1186701/extract-overlay-ramdisk-5s2vwgrg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1186701/extract-overlay-ramdisk-5s2vwgrg/ramdisk
267 21:32:08.541935 >> 78982 blocks
268 21:32:10.679321 Adding RAMdisk u-boot header.
269 21:32:10.679598 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1186701/extract-overlay-ramdisk-5s2vwgrg/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1186701/extract-overlay-ramdisk-5s2vwgrg/ramdisk.cpio.gz.uboot
270 21:32:10.834594 output: Image Name:
271 21:32:10.834802 output: Created: Sat Aug 31 21:32:10 2024
272 21:32:10.834900 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 21:32:10.834995 output: Data Size: 15343248 Bytes = 14983.64 KiB = 14.63 MiB
274 21:32:10.835086 output: Load Address: 00000000
275 21:32:10.835175 output: Entry Point: 00000000
276 21:32:10.835264 output:
277 21:32:10.835428 rename /var/lib/lava/dispatcher/tmp/1186701/extract-overlay-ramdisk-5s2vwgrg/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/ramdisk/ramdisk.cpio.gz.uboot
278 21:32:10.835594 end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
279 21:32:10.835720 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
280 21:32:10.835844 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
281 21:32:10.835940 No LXC device requested
282 21:32:10.836054 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 21:32:10.836173 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
284 21:32:10.836352 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 21:32:10.836482 Checking files for TFTP limit of 4294967296 bytes.
286 21:32:10.837304 end: 1 tftp-deploy (duration 00:00:54) [common]
287 21:32:10.837478 start: 2 uboot-action (timeout 00:05:00) [common]
288 21:32:10.837648 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 21:32:10.837809 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 21:32:10.837972 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 21:32:10.838220 substitutions:
292 21:32:10.838354 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 21:32:10.838483 - {DTB_ADDR}: 0x88000000
294 21:32:10.838609 - {DTB}: 1186701/tftp-deploy-h_bpql55/dtb/am335x-boneblack.dtb
295 21:32:10.838735 - {INITRD}: 1186701/tftp-deploy-h_bpql55/ramdisk/ramdisk.cpio.gz.uboot
296 21:32:10.838860 - {KERNEL_ADDR}: 0x82000000
297 21:32:10.838983 - {KERNEL}: 1186701/tftp-deploy-h_bpql55/kernel/zImage
298 21:32:10.839106 - {LAVA_MAC}: None
299 21:32:10.839237 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax
300 21:32:10.839361 - {NFS_SERVER_IP}: 192.168.11.5
301 21:32:10.839482 - {PRESEED_CONFIG}: None
302 21:32:10.839603 - {PRESEED_LOCAL}: None
303 21:32:10.839724 - {RAMDISK_ADDR}: 0x83000000
304 21:32:10.839845 - {RAMDISK}: 1186701/tftp-deploy-h_bpql55/ramdisk/ramdisk.cpio.gz.uboot
305 21:32:10.839966 - {ROOT_PART}: None
306 21:32:10.840084 - {ROOT}: None
307 21:32:10.840211 - {SERVER_IP}: 192.168.11.5
308 21:32:10.840331 - {TEE_ADDR}: 0x83000000
309 21:32:10.840450 - {TEE}: None
310 21:32:10.840569 Parsed boot commands:
311 21:32:10.840684 - setenv autoload no
312 21:32:10.840803 - setenv initrd_high 0xffffffff
313 21:32:10.840921 - setenv fdt_high 0xffffffff
314 21:32:10.841039 - dhcp
315 21:32:10.841156 - setenv serverip 192.168.11.5
316 21:32:10.841275 - tftp 0x82000000 1186701/tftp-deploy-h_bpql55/kernel/zImage
317 21:32:10.841393 - tftp 0x83000000 1186701/tftp-deploy-h_bpql55/ramdisk/ramdisk.cpio.gz.uboot
318 21:32:10.841513 - setenv initrd_size ${filesize}
319 21:32:10.841631 - tftp 0x88000000 1186701/tftp-deploy-h_bpql55/dtb/am335x-boneblack.dtb
320 21:32:10.841750 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 21:32:10.841874 - bootz 0x82000000 0x83000000 0x88000000
322 21:32:10.842028 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 21:32:10.842471 start: 2.3 connect-device (timeout 00:05:00) [common]
325 21:32:10.842600 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 21:32:11.201565 Setting prompt string to ['lava-test: # ']
327 21:32:11.201953 end: 2.3 connect-device (duration 00:00:00) [common]
328 21:32:11.202099 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 21:32:11.202285 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 21:32:11.202505 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 21:32:11.202852 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 21:32:11.566754 Returned 0 in 0 seconds
333 21:32:11.667652 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 21:32:11.668652 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 21:32:11.669016 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 21:32:11.669322 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 21:32:11.669604 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 21:32:11.670406 Trying 127.0.0.1...
340 21:32:11.670648 Connected to 127.0.0.1.
341 21:32:11.670906 Escape character is '^]'.
342 21:32:16.575116
343 21:32:16.578756 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 21:32:16.635300 Trying to boot from MMC2
345 21:32:16.683674 Loading Environment from EXT4... Card did not respond to voltage select!
346 21:32:16.751530
347 21:32:16.751815
348 21:32:16.757018 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 21:32:16.757295
350 21:32:16.761963 CPU : AM335X-GP rev 2.1
351 21:32:16.815917 I2C: ready
352 21:32:16.816192 DRAM: 512 MiB
353 21:32:16.870504 No match for driver 'omap_hsmmc'
354 21:32:16.876115 No match for driver 'omap_hsmmc'
355 21:32:16.876414 Some drivers were not found
356 21:32:16.882493 Reset Source: Power-on reset has occurred.
357 21:32:16.882770 RTC 32KCLK Source: External.
358 21:32:16.889913 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 21:32:16.903217 Loading Environment from EXT4... Card did not respond to voltage select!
360 21:32:16.967749 Board: BeagleBone Black
361 21:32:16.971683 <ethaddr> not set. Validating first E-fuse MAC
362 21:32:17.028416 BeagleBone Black:
363 21:32:17.028692 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 21:32:17.033871 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 21:32:17.039869 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 21:32:17.040139 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 21:32:17.044797 Net: eth0: MII MODE
368 21:32:17.054187 cpsw, usb_ether
369 21:32:17.054456 Press SPACE to abort autoboot in 2 seconds
370 21:32:17.105248 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 21:32:17.105592 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 21:32:17.105858 Setting prompt string to ['=> ']
373 21:32:17.106117 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 21:32:17.109437 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 21:32:17.109736 Sending with 10 millisecond of delay
377 21:32:18.244309 => setenv autoload no
378 21:32:18.254816 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 21:32:18.257176 setenv autoload no
380 21:32:18.257654 Sending with 10 millisecond of delay
382 21:32:20.054565 => setenv initrd_high 0xffffffff
383 21:32:20.065068 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 21:32:20.065541 setenv initrd_high 0xffffffff
385 21:32:20.065992 Sending with 10 millisecond of delay
387 21:32:21.682274 => setenv fdt_high 0xffffffff
388 21:32:21.692776 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 21:32:21.693234 setenv fdt_high 0xffffffff
390 21:32:21.693679 Sending with 10 millisecond of delay
392 21:32:21.985129 => dhcp
393 21:32:21.995546 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 21:32:21.996055 dhcp
395 21:32:21.996312 link up on port 0, speed 100, full duplex
396 21:32:21.996532 BOOTP broadcast 1
397 21:32:22.003910 DHCP client bound to address 192.168.11.7 (3 ms)
398 21:32:22.004444 Sending with 10 millisecond of delay
400 21:32:23.740777 => setenv serverip 192.168.11.5
401 21:32:23.751276 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 21:32:23.751750 setenv serverip 192.168.11.5
403 21:32:23.752215 Sending with 10 millisecond of delay
405 21:32:27.295508 => tftp 0x82000000 1186701/tftp-deploy-h_bpql55/kernel/zImage
406 21:32:27.305984 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 21:32:27.306480 tftp 0x82000000 1186701/tftp-deploy-h_bpql55/kernel/zImage
408 21:32:27.306730 link up on port 0, speed 100, full duplex
409 21:32:27.306969 Using cpsw device
410 21:32:27.310265 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
411 21:32:27.315743 Filename '1186701/tftp-deploy-h_bpql55/kernel/zImage'.
412 21:32:27.339412 Load address: 0x82000000
413 21:32:27.511568 Loading: *#################################################################
414 21:32:27.685796 #################################################################
415 21:32:27.860611 #################################################################
416 21:32:28.035862 #################################################################
417 21:32:28.210868 #################################################################
418 21:32:28.392107 #################################################################
419 21:32:28.642713 #################################################################
420 21:32:28.753113 #################################################################
421 21:32:28.928217 #################################################################
422 21:32:29.102836 #################################################################
423 21:32:29.285523 #################################################################
424 21:32:29.454736 #################################################################
425 21:32:29.556761 ####################################
426 21:32:29.557097 5.1 MiB/s
427 21:32:29.557320 done
428 21:32:29.560153 Bytes transferred = 11964928 (b69200 hex)
429 21:32:29.560693 Sending with 10 millisecond of delay
431 21:32:34.067385 => tftp 0x83000000 1186701/tftp-deploy-h_bpql55/ramdisk/ramdisk.cpio.gz.uboot
432 21:32:34.077884 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 21:32:34.078334 tftp 0x83000000 1186701/tftp-deploy-h_bpql55/ramdisk/ramdisk.cpio.gz.uboot
434 21:32:34.078564 link up on port 0, speed 100, full duplex
435 21:32:34.078777 Using cpsw device
436 21:32:34.082115 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
437 21:32:34.142300 Filename '1186701/tftp-deploy-h_bpql55/ramdisk/ramdisk.cpio.gz.uboot'.
438 21:32:34.142575 Load address: 0x83000000
439 21:32:34.262979 Loading: *#################################################################
440 21:32:34.448289 #################################################################
441 21:32:34.615108 #################################################################
442 21:32:34.779960 #################################################################
443 21:32:34.953163 #################################################################
444 21:32:35.127993 #################################################################
445 21:32:35.308162 #################################################################
446 21:32:35.482924 #################################################################
447 21:32:35.686525 #################################################################
448 21:32:35.840289 #################################################################
449 21:32:36.013958 #################################################################
450 21:32:36.188982 #################################################################
451 21:32:36.372487 #################################################################
452 21:32:36.546458 #################################################################
453 21:32:36.721325 #################################################################
454 21:32:36.916026 #################################################################
455 21:32:36.916315 ######
456 21:32:36.916549 5.2 MiB/s
457 21:32:36.916771 done
458 21:32:36.918171 Bytes transferred = 15343312 (ea1ed0 hex)
459 21:32:36.918662 Sending with 10 millisecond of delay
461 21:32:38.775877 => setenv initrd_size ${filesize}
462 21:32:38.786414 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
463 21:32:38.786885 setenv initrd_size ${filesize}
464 21:32:38.787333 Sending with 10 millisecond of delay
466 21:32:42.992832 => tftp 0x88000000 1186701/tftp-deploy-h_bpql55/dtb/am335x-boneblack.dtb
467 21:32:43.003308 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
468 21:32:43.003827 tftp 0x88000000 1186701/tftp-deploy-h_bpql55/dtb/am335x-boneblack.dtb
469 21:32:43.004093 link up on port 0, speed 100, full duplex
470 21:32:43.004369 Using cpsw device
471 21:32:43.007538 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
472 21:32:43.032014 Filename '1186701/tftp-deploy-h_bpql55/dtb/am335x-boneblack.dtb'.
473 21:32:43.032318 Load address: 0x88000000
474 21:32:43.032540 Loading: *#####
475 21:32:43.032749 4.8 MiB/s
476 21:32:43.038681 done
477 21:32:43.038949 Bytes transferred = 70308 (112a4 hex)
478 21:32:43.039382 Sending with 10 millisecond of delay
480 21:32:56.337959 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 21:32:56.348433 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:14)
482 21:32:56.348883 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
483 21:32:56.349336 Sending with 10 millisecond of delay
485 21:32:58.688340 => bootz 0x82000000 0x83000000 0x88000000
486 21:32:58.698842 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
487 21:32:58.699163 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
488 21:32:58.699699 bootz 0x82000000 0x83000000 0x88000000
489 21:32:58.699940 ## Loading init Ramdisk from Legacy Image at 83000000 ...
490 21:32:58.700450 Image Name:
491 21:32:58.700764 Created: 2024-08-31 21:32:10 UTC
492 21:32:58.706048 Image Type: ARM Linux RAMDisk Image (uncompressed)
493 21:32:58.711540 Data Size: 15343248 Bytes = 14.6 MiB
494 21:32:58.711802 Load Address: 00000000
495 21:32:58.718846 Entry Point: 00000000
496 21:32:58.861210 Verifying Checksum ... OK
497 21:32:58.861528 ## Flattened Device Tree blob at 88000000
498 21:32:58.867803 Booting using the fdt blob at 0x88000000
499 21:32:58.872689 Using Device Tree in place at 88000000, end 880142a3
500 21:32:58.880244
501 21:32:58.880521 Starting kernel ...
502 21:32:58.880745
503 21:32:58.881277 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
504 21:32:58.881578 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
505 21:32:58.881829 Setting prompt string to ['Linux version [0-9]']
506 21:32:58.882069 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
507 21:32:58.882318 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
508 21:32:59.711733 [ 0.000000] Booting Linux on physical CPU 0x0
509 21:32:59.717587 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
510 21:32:59.717898 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 21:32:59.718182 Setting prompt string to []
512 21:32:59.718489 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 21:32:59.718778 Using line separator: #'\n'#
514 21:32:59.719028 No login prompt set.
515 21:32:59.719281 Parsing kernel messages
516 21:32:59.719522 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 21:32:59.720008 [login-action] Waiting for messages, (timeout 00:04:11)
518 21:32:59.728766 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j303244-arm-clang-15-multi-v7-defconfig-n82sx) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Sat Aug 31 20:04:28 UTC 2024
519 21:32:59.734543 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 21:32:59.745893 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 21:32:59.751647 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 21:32:59.757382 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 21:32:59.763125 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 21:32:59.769870 [ 0.000000] Memory policy: Data cache writeback
525 21:32:59.770128 [ 0.000000] efi: UEFI not found.
526 21:32:59.777491 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 21:32:59.783155 [ 0.000000] Zone ranges:
528 21:32:59.788927 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 21:32:59.794658 [ 0.000000] Normal empty
530 21:32:59.794884 [ 0.000000] HighMem empty
531 21:32:59.797504 [ 0.000000] Movable zone start for each node
532 21:32:59.803244 [ 0.000000] Early memory node ranges
533 21:32:59.809034 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 21:32:59.817099 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 21:32:59.835296 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 21:32:59.840940 [ 0.000000] AM335X ES2.1 (sgx neon)
537 21:32:59.852754 [ 0.000000] percpu: Embedded 17 pages/cpu s40268 r8192 d21172 u69632
538 21:32:59.870376 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 21:32:59.881871 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 21:32:59.887639 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 21:32:59.893389 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 21:32:59.903545 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 21:32:59.932876 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 21:32:59.938750 <6>[ 0.000000] trace event string verifier disabled
545 21:32:59.939029 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 21:32:59.944500 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 21:32:59.955867 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 21:32:59.961637 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 21:32:59.968944 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 21:32:59.984242 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 21:33:00.002311 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 21:33:00.009090 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 21:33:00.112381 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 21:33:00.123883 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 21:33:00.130651 <6>[ 0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 21:33:00.143586 <6>[ 0.019229] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 21:33:00.151283 <6>[ 0.034390] Console: colour dummy device 80x30
558 21:33:00.157284 Matched prompt #6: WARNING:
559 21:33:00.157402 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 21:33:00.162793 <3>[ 0.039290] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 21:33:00.168508 <3>[ 0.046360] This ensures that you still see kernel messages. Please
562 21:33:00.171951 <3>[ 0.053084] update your kernel commandline.
563 21:33:00.212224 <6>[ 0.057696] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 21:33:00.217961 <6>[ 0.096243] CPU: Testing write buffer coherency: ok
565 21:33:00.223831 <6>[ 0.101613] CPU0: Spectre v2: using BPIALL workaround
566 21:33:00.224094 <6>[ 0.107079] pid_max: default: 32768 minimum: 301
567 21:33:00.235310 <6>[ 0.112281] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 21:33:00.242377 <6>[ 0.120110] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 21:33:00.249375 <6>[ 0.129458] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 21:33:00.257939 <6>[ 0.136387] Setting up static identity map for 0x80300000 - 0x803000ac
571 21:33:00.263612 <6>[ 0.146123] rcu: Hierarchical SRCU implementation.
572 21:33:00.271247 <6>[ 0.151409] rcu: Max phase no-delay instances is 1000.
573 21:33:00.280098 <6>[ 0.162910] EFI services will not be available.
574 21:33:00.285942 <6>[ 0.168186] smp: Bringing up secondary CPUs ...
575 21:33:00.291687 <6>[ 0.173237] smp: Brought up 1 node, 1 CPU
576 21:33:00.297499 <6>[ 0.177636] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 21:33:00.303499 <6>[ 0.184391] CPU: All CPU(s) started in SVC mode.
578 21:33:00.323797 <6>[ 0.189597] Memory: 405452K/522240K available (17408K kernel code, 2536K rwdata, 6644K rodata, 2048K init, 432K bss, 49584K reserved, 65536K cma-reserved, 0K highmem)
579 21:33:00.324045 <6>[ 0.205867] devtmpfs: initialized
580 21:33:00.347126 <6>[ 0.224068] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 21:33:00.358619 <6>[ 0.232690] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 21:33:00.364547 <6>[ 0.243127] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 21:33:00.375323 <6>[ 0.255418] pinctrl core: initialized pinctrl subsystem
584 21:33:00.385042 <6>[ 0.266435] DMI not present or invalid.
585 21:33:00.393448 <6>[ 0.272325] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 21:33:00.403009 <6>[ 0.281276] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 21:33:00.418100 <6>[ 0.292878] thermal_sys: Registered thermal governor 'step_wise'
588 21:33:00.418378 <6>[ 0.293040] cpuidle: using governor menu
589 21:33:00.445520 <6>[ 0.328496] No ATAGs?
590 21:33:00.451675 <6>[ 0.331230] hw-breakpoint: debug architecture 0x4 unsupported.
591 21:33:00.462198 <6>[ 0.343533] Serial: AMBA PL011 UART driver
592 21:33:00.502394 <6>[ 0.385308] iommu: Default domain type: Translated
593 21:33:00.511455 <6>[ 0.390656] iommu: DMA domain TLB invalidation policy: strict mode
594 21:33:00.529065 <5>[ 0.410695] SCSI subsystem initialized
595 21:33:00.543245 <6>[ 0.420637] usbcore: registered new interface driver usbfs
596 21:33:00.550260 <6>[ 0.426599] usbcore: registered new interface driver hub
597 21:33:00.550537 <6>[ 0.432424] usbcore: registered new device driver usb
598 21:33:00.555964 <6>[ 0.438995] pps_core: LinuxPPS API ver. 1 registered
599 21:33:00.567446 <6>[ 0.444433] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 21:33:00.572717 <6>[ 0.454136] PTP clock support registered
601 21:33:00.610597 <6>[ 0.492864] EDAC MC: Ver: 3.0.0
602 21:33:00.616541 <6>[ 0.497091] scmi_core: SCMI protocol bus registered
603 21:33:00.643724 <6>[ 0.526388] vgaarb: loaded
604 21:33:00.667643 <6>[ 0.550694] clocksource: Switched to clocksource dmtimer
605 21:33:00.698513 <6>[ 0.581221] NET: Registered PF_INET protocol family
606 21:33:00.711233 <6>[ 0.586844] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 21:33:00.716985 <6>[ 0.595899] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 21:33:00.728536 <6>[ 0.604828] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 21:33:00.734361 <6>[ 0.613088] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 21:33:00.745856 <6>[ 0.621377] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 21:33:00.751732 <6>[ 0.629077] TCP: Hash tables configured (established 4096 bind 4096)
612 21:33:00.757482 <6>[ 0.636003] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 21:33:00.763356 <6>[ 0.643042] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 21:33:00.770909 <6>[ 0.650650] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 21:33:00.793759 <6>[ 0.671051] RPC: Registered named UNIX socket transport module.
616 21:33:00.794078 <6>[ 0.677438] RPC: Registered udp transport module.
617 21:33:00.799485 <6>[ 0.682606] RPC: Registered tcp transport module.
618 21:33:00.805234 <6>[ 0.687711] RPC: Registered tcp-with-tls transport module.
619 21:33:00.818264 <6>[ 0.693635] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 21:33:00.818535 <6>[ 0.700564] PCI: CLS 0 bytes, default 64
621 21:33:00.825410 <5>[ 0.706432] Initialise system trusted keyrings
622 21:33:00.846129 <6>[ 0.725974] Trying to unpack rootfs image as initramfs...
623 21:33:00.873864 <6>[ 0.750640] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 21:33:00.878550 <6>[ 0.758109] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 21:33:00.927754 <5>[ 0.810678] NFS: Registering the id_resolver key type
626 21:33:00.933512 <5>[ 0.816270] Key type id_resolver registered
627 21:33:00.939357 <5>[ 0.820958] Key type id_legacy registered
628 21:33:00.945126 <6>[ 0.825402] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 21:33:00.954704 <6>[ 0.832604] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 21:33:01.000592 <5>[ 0.883651] Key type asymmetric registered
631 21:33:01.006428 <5>[ 0.888173] Asymmetric key parser 'x509' registered
632 21:33:01.017910 <6>[ 0.893680] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 21:33:01.018191 <6>[ 0.901599] io scheduler mq-deadline registered
634 21:33:01.023789 <6>[ 0.906531] io scheduler kyber registered
635 21:33:01.029341 <6>[ 0.911000] io scheduler bfq registered
636 21:33:01.409120 <6>[ 1.288267] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 21:33:01.451697 <6>[ 1.334502] msm_serial: driver initialized
638 21:33:01.457790 <6>[ 1.339294] SuperH (H)SCI(F) driver initialized
639 21:33:01.463766 <6>[ 1.344621] STMicroelectronics ASC driver initialized
640 21:33:01.466814 <6>[ 1.350291] STM32 USART driver initialized
641 21:33:01.570909 <6>[ 1.453249] brd: module loaded
642 21:33:01.603698 <6>[ 1.485793] loop: module loaded
643 21:33:01.646184 <6>[ 1.528220] CAN device driver interface
644 21:33:01.652926 <6>[ 1.533541] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 21:33:01.658634 <6>[ 1.540645] e1000e: Intel(R) PRO/1000 Network Driver
646 21:33:01.664416 <6>[ 1.546032] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 21:33:01.670149 <6>[ 1.552488] igb: Intel(R) Gigabit Ethernet Network Driver
648 21:33:01.678446 <6>[ 1.558309] igb: Copyright (c) 2007-2014 Intel Corporation.
649 21:33:01.690311 <6>[ 1.567582] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 21:33:01.696028 <6>[ 1.573740] usbcore: registered new interface driver pegasus
651 21:33:01.701910 <6>[ 1.579869] usbcore: registered new interface driver asix
652 21:33:01.707636 <6>[ 1.585779] usbcore: registered new interface driver ax88179_178a
653 21:33:01.713386 <6>[ 1.592374] usbcore: registered new interface driver cdc_ether
654 21:33:01.719135 <6>[ 1.598675] usbcore: registered new interface driver smsc75xx
655 21:33:01.725012 <6>[ 1.604923] usbcore: registered new interface driver smsc95xx
656 21:33:01.730761 <6>[ 1.611156] usbcore: registered new interface driver net1080
657 21:33:01.736549 <6>[ 1.617275] usbcore: registered new interface driver cdc_subset
658 21:33:01.742258 <6>[ 1.623683] usbcore: registered new interface driver zaurus
659 21:33:01.749935 <6>[ 1.629756] usbcore: registered new interface driver cdc_ncm
660 21:33:01.760065 <6>[ 1.639396] usbcore: registered new interface driver usb-storage
661 21:33:01.861190 <6>[ 1.742341] i2c_dev: i2c /dev entries driver
662 21:33:01.920851 <5>[ 1.795684] cpuidle: enable-method property 'ti,am3352' found operations
663 21:33:01.926530 <6>[ 1.805353] sdhci: Secure Digital Host Controller Interface driver
664 21:33:01.934532 <6>[ 1.812124] sdhci: Copyright(c) Pierre Ossman
665 21:33:01.941901 <6>[ 1.818662] Synopsys Designware Multimedia Card Interface Driver
666 21:33:01.946937 <6>[ 1.826719] sdhci-pltfm: SDHCI platform and OF driver helper
667 21:33:02.021625 <6>[ 1.900957] ledtrig-cpu: registered to indicate activity on CPUs
668 21:33:02.047505 <6>[ 1.923132] usbcore: registered new interface driver usbhid
669 21:33:02.047793 <6>[ 1.929166] usbhid: USB HID core driver
670 21:33:02.089179 <6>[ 1.969517] NET: Registered PF_INET6 protocol family
671 21:33:02.148360 <6>[ 2.031427] Segment Routing with IPv6
672 21:33:02.154209 <6>[ 2.035575] In-situ OAM (IOAM) with IPv6
673 21:33:02.161065 <6>[ 2.039969] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 21:33:02.166793 <6>[ 2.047403] NET: Registered PF_PACKET protocol family
675 21:33:02.172676 <6>[ 2.052975] can: controller area network core
676 21:33:02.178418 <6>[ 2.057809] NET: Registered PF_CAN protocol family
677 21:33:02.178689 <6>[ 2.063038] can: raw protocol
678 21:33:02.184169 <6>[ 2.066365] can: broadcast manager protocol
679 21:33:02.190791 <6>[ 2.070959] can: netlink gateway - max_hops=1
680 21:33:02.196822 <5>[ 2.076484] Key type dns_resolver registered
681 21:33:02.203168 <6>[ 2.081555] ThumbEE CPU extension supported.
682 21:33:02.203439 <5>[ 2.086244] Registering SWP/SWPB emulation handler
683 21:33:02.212856 <3>[ 2.091952] omap_voltage_late_init: Voltage driver support not added
684 21:33:02.301459 <5>[ 2.182043] Loading compiled-in X.509 certificates
685 21:33:02.441802 <6>[ 2.311791] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 21:33:02.448858 <6>[ 2.328458] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 21:33:02.476001 <3>[ 2.352897] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 21:33:02.564125 <3>[ 2.441044] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 21:33:02.659712 <6>[ 2.541024] OMAP GPIO hardware version 0.1
690 21:33:02.680988 <6>[ 2.560334] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 21:33:02.753458 <4>[ 2.632510] at24 2-0054: supply vcc not found, using dummy regulator
692 21:33:02.816687 <4>[ 2.695748] at24 2-0055: supply vcc not found, using dummy regulator
693 21:33:02.860749 <4>[ 2.739754] at24 2-0056: supply vcc not found, using dummy regulator
694 21:33:02.899542 <4>[ 2.778576] at24 2-0057: supply vcc not found, using dummy regulator
695 21:33:02.960994 <6>[ 2.840815] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 21:33:03.037328 <3>[ 2.913136] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 21:33:03.062315 <6>[ 2.934493] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 21:33:03.087450 <4>[ 2.965294] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 21:33:03.133472 <4>[ 3.011232] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 21:33:03.191644 <6>[ 3.070883] omap_rng 48310000.rng: Random Number Generator ver. 20
701 21:33:03.215521 <5>[ 3.097571] random: crng init done
702 21:33:03.312577 <6>[ 3.190358] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 21:33:03.850679 <6>[ 3.732041] Freeing initrd memory: 14984K
704 21:33:03.894638 <6>[ 3.771577] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 21:33:03.900365 <6>[ 3.781796] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 21:33:03.912099 <6>[ 3.789058] cpsw-switch 4a100000.switch: ALE Table size 1024
707 21:33:03.917980 <6>[ 3.795524] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 21:33:03.929474 <6>[ 3.803656] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 21:33:03.936974 <6>[ 3.815291] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
710 21:33:03.949032 <5>[ 3.824461] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 21:33:03.977730 <3>[ 3.855075] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 21:33:03.983414 <6>[ 3.863649] edma 49000000.dma: TI EDMA DMA engine driver
713 21:33:04.056558 <3>[ 3.933240] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 21:33:04.070425 <6>[ 3.947702] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
715 21:33:04.089475 <3>[ 3.969957] l3-aon-clkctrl:0000:0: failed to disable
716 21:33:04.133994 <6>[ 4.011381] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 21:33:04.139741 <6>[ 4.020847] printk: legacy console [ttyS0] enabled
718 21:33:04.145363 <6>[ 4.020847] printk: legacy console [ttyS0] enabled
719 21:33:04.151115 <6>[ 4.031168] printk: legacy bootconsole [omap8250] disabled
720 21:33:04.156914 <6>[ 4.031168] printk: legacy bootconsole [omap8250] disabled
721 21:33:04.204609 <4>[ 4.080892] tps65217-pmic: Failed to locate of_node [id: -1]
722 21:33:04.208211 <4>[ 4.088300] tps65217-bl: Failed to locate of_node [id: -1]
723 21:33:04.225033 <6>[ 4.108390] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 21:33:04.243626 <6>[ 4.115418] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 21:33:04.255224 <6>[ 4.129132] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 21:33:04.260904 <6>[ 4.141019] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 21:33:04.284362 <6>[ 4.162020] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 21:33:04.290227 <6>[ 4.171191] sdhci-omap 48060000.mmc: Got CD GPIO
729 21:33:04.298277 <4>[ 4.176315] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 21:33:04.313869 <4>[ 4.190338] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 21:33:04.320250 <4>[ 4.199486] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 21:33:04.330028 <4>[ 4.208146] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 21:33:04.453400 <6>[ 4.332223] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 21:33:04.485227 <6>[ 4.363199] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 21:33:04.507564 <6>[ 4.385484] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 21:33:04.540637 <6>[ 4.419727] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 21:33:04.585854 <6>[ 4.459486] mmc1: new high speed MMC card at address 0001
738 21:33:04.586134 <6>[ 4.467074] mmcblk1: mmc1:0001 M62704 3.56 GiB
739 21:33:04.594242 <6>[ 4.475669] mmcblk1: p1
740 21:33:04.599517 <6>[ 4.480329] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
741 21:33:04.608088 <6>[ 4.488631] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
742 21:33:04.617147 <6>[ 4.496580] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
743 21:33:04.636327 <6>[ 4.511413] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
744 21:33:07.753744 <6>[ 7.631196] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
745 21:33:07.826976 <5>[ 7.670233] Sending DHCP requests ., OK
746 21:33:07.838313 <6>[ 7.714633] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.7
747 21:33:07.838578 <6>[ 7.722861] IP-Config: Complete:
748 21:33:07.849676 <6>[ 7.726396] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.7, mask=255.255.255.0, gw=192.168.11.1
749 21:33:07.855451 <6>[ 7.736989] host=192.168.11.7, domain=usen.ad.jp, nis-domain=(none)
750 21:33:07.867662 <6>[ 7.744082] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
751 21:33:07.867918 <6>[ 7.744116] nameserver0=192.168.11.1
752 21:33:07.873824 <6>[ 7.756426] clk: Disabling unused clocks
753 21:33:07.880309 <6>[ 7.761177] PM: genpd: Disabling unused power domains
754 21:33:07.898233 <6>[ 7.778140] Freeing unused kernel image (initmem) memory: 2048K
755 21:33:07.905636 <6>[ 7.787832] Run /init as init process
756 21:33:07.931157 Loading, please wait...
757 21:33:08.007976 Starting systemd-udevd version 252.22-1~deb12u1
758 21:33:11.038514 <4>[ 10.914721] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
759 21:33:11.205875 <4>[ 11.082129] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 21:33:11.447092 <6>[ 11.330746] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
761 21:33:11.457720 <6>[ 11.336418] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
762 21:33:11.608515 <6>[ 11.490728] hub 1-0:1.0: USB hub found
763 21:33:11.629661 <6>[ 11.511536] hub 1-0:1.0: 1 port detected
764 21:33:11.780878 <6>[ 11.662654] tda998x 0-0070: found TDA19988
765 21:33:14.648991 Begin: Loading essential drivers ... done.
766 21:33:14.654443 Begin: Running /scripts/init-premount ... done.
767 21:33:14.660061 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
768 21:33:14.673935 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
769 21:33:14.674168 Device /sys/class/net/eth0 found
770 21:33:14.674384 done.
771 21:33:14.749003 Begin: Waiting up to 180 secs for any network device to become available ... done.
772 21:33:14.822065 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
773 21:33:14.822364 IP-Config: eth0 guessed broadcast address 192.168.11.255
774 21:33:14.827679 IP-Config: eth0 complete (dhcp from 192.168.11.1):
775 21:33:14.838925 address: 192.168.11.7 broadcast: 192.168.11.255 netmask: 255.255.255.0
776 21:33:14.844455 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
777 21:33:14.850050 domain : usen.ad.jp
778 21:33:14.854980 rootserver: 192.168.11.1 rootpath:
779 21:33:14.855204 filename :
780 21:33:14.936023 done.
781 21:33:14.955000 Begin: Running /scripts/nfs-bottom ... done.
782 21:33:15.025906 Begin: Running /scripts/init-bottom ... done.
783 21:33:16.360148 <30>[ 16.239597] systemd[1]: System time before build time, advancing clock.
784 21:33:16.607481 <30>[ 16.460745] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 21:33:16.616647 <30>[ 16.497897] systemd[1]: Detected architecture arm.
786 21:33:16.628864
787 21:33:16.629143 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 21:33:16.629369
789 21:33:16.671256 <30>[ 16.551248] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 21:33:18.859815 <30>[ 18.738846] systemd[1]: Queued start job for default target graphical.target.
791 21:33:18.877135 <30>[ 18.753939] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 21:33:18.884656 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 21:33:18.919903 <30>[ 18.796095] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 21:33:18.927297 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 21:33:18.967358 <30>[ 18.843275] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 21:33:18.974771 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 21:33:19.014651 <30>[ 18.893928] systemd[1]: Created slice user.slice - User and Session Slice.
798 21:33:19.027277 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 21:33:19.069985 <30>[ 18.941591] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 21:33:19.076094 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 21:33:19.104244 <30>[ 18.981432] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 21:33:19.115150 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 21:33:19.154867 <30>[ 19.021294] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 21:33:19.161226 <30>[ 19.041798] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 21:33:19.169777 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 21:33:19.206006 <30>[ 19.081582] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 21:33:19.213282 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 21:33:19.244380 <30>[ 19.120944] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 21:33:19.251769 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 21:33:19.286630 <30>[ 19.162387] systemd[1]: Reached target paths.target - Path Units.
811 21:33:19.291779 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 21:33:19.323225 <30>[ 19.200814] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 21:33:19.330519 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 21:33:19.363218 <30>[ 19.240823] systemd[1]: Reached target slices.target - Slice Units.
815 21:33:19.368639 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 21:33:19.405099 <30>[ 19.282048] systemd[1]: Reached target swap.target - Swaps.
817 21:33:19.409017 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 21:33:19.444249 <30>[ 19.320947] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 21:33:19.452012 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 21:33:19.485647 <30>[ 19.363127] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 21:33:19.498446 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 21:33:19.597530 <30>[ 19.470062] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 21:33:19.610384 <30>[ 19.487537] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 21:33:19.618764 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 21:33:19.655350 <30>[ 19.532142] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 21:33:19.662805 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 21:33:19.696907 <30>[ 19.574012] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 21:33:19.705139 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 21:33:19.738313 <30>[ 19.615486] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 21:33:19.744297 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 21:33:19.785761 <30>[ 19.663920] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 21:33:19.798698 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 21:33:19.840827 <30>[ 19.712051] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 21:33:19.857447 <30>[ 19.728838] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 21:33:19.906467 <30>[ 19.784822] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 21:33:19.935197 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 21:33:19.996254 <30>[ 19.874313] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 21:33:20.014722 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 21:33:20.094225 <30>[ 19.971350] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 21:33:20.112220 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 21:33:20.186951 <30>[ 20.064828] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 21:33:20.202186 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 21:33:20.226388 <30>[ 20.104553] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 21:33:20.255509 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 21:33:20.333052 <30>[ 20.211793] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 21:33:20.353352 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 21:33:20.416331 <30>[ 20.293790] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 21:33:20.437550 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 21:33:20.461049 <30>[ 20.339624] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 21:33:20.487700 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 21:33:20.554582 <30>[ 20.433078] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 21:33:20.582256 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 21:33:20.620817 <28>[ 20.492530] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 21:33:20.629146 <28>[ 20.506969] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 21:33:20.678606 <30>[ 20.557585] systemd[1]: Starting systemd-journald.service - Journal Service...
856 21:33:20.702869 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 21:33:20.785006 <30>[ 20.663253] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 21:33:20.796466 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 21:33:20.863306 <30>[ 20.741803] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 21:33:20.915198 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 21:33:20.996066 <30>[ 20.873062] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 21:33:21.045881 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 21:33:21.135345 <30>[ 21.013060] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 21:33:21.183098 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 21:33:21.237725 <30>[ 21.116343] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 21:33:21.276628 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 21:33:21.313950 <30>[ 21.192439] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 21:33:21.341917 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 21:33:21.377231 <30>[ 21.254481] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 21:33:21.405358 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 21:33:21.569950 <30>[ 21.449267] systemd[1]: Started systemd-journald.service - Journal Service.
872 21:33:21.592299 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
873 21:33:21.644306 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 21:33:21.684581 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
875 21:33:21.734196 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
876 21:33:21.784508 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
877 21:33:21.834309 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
878 21:33:21.868932 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
879 21:33:21.905625 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
880 21:33:21.925432 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
881 21:33:21.955406 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
882 21:33:21.992871 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
883 21:33:22.076431 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
884 21:33:22.148278 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
885 21:33:22.244009 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
886 21:33:22.357177 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
887 21:33:22.425713 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
888 21:33:22.462567 <46>[ 22.341105] systemd-journald[163]: Received client request to flush runtime journal.
889 21:33:22.569199 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
890 21:33:22.656510 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
891 21:33:23.458221 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
892 21:33:23.803317 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
893 21:33:23.863236 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
894 21:33:24.303164 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
895 21:33:24.473265 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
896 21:33:24.505333 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
897 21:33:24.532856 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
898 21:33:24.604147 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
899 21:33:24.652175 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
900 21:33:25.595337 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
901 21:33:25.666702 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
902 21:33:26.127618 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
903 21:33:26.292178 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
904 21:33:26.375036 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
905 21:33:28.291996 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
906 21:33:28.805230 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
907 21:33:29.203990 <5>[ 29.082894] cfg80211: Loading compiled-in X.509 certificates for regulatory database
908 21:33:29.587000 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
909 21:33:30.898526 <5>[ 30.779400] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
910 21:33:30.946309 <5>[ 30.825717] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
911 21:33:30.961835 <4>[ 30.840644] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
912 21:33:30.967665 <6>[ 30.849626] cfg80211: failed to load regulatory.db
913 21:33:31.323982 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
914 21:33:31.494218 <46>[ 31.363129] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
915 21:33:31.725025 <46>[ 31.597010] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
916 21:33:31.899304 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
917 21:33:40.221640 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
918 21:33:40.259546 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
919 21:33:40.294488 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
920 21:33:40.328544 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
921 21:33:40.418388 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
922 21:33:40.492155 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
923 21:33:40.534060 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
924 21:33:40.614680 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
925 21:33:40.676193 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
926 21:33:40.740421 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
927 21:33:40.759638 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
928 21:33:40.820553 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
929 21:33:40.859535 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
930 21:33:40.911490 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
931 21:33:40.957915 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
932 21:33:40.994969 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
933 21:33:41.038755 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
934 21:33:41.083644 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
935 21:33:41.113089 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
936 21:33:41.141636 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
937 21:33:41.185709 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
938 21:33:41.224100 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
939 21:33:41.255205 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
940 21:33:41.338540 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
941 21:33:41.391631 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
942 21:33:41.531287 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
943 21:33:41.655230 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
944 21:33:41.752570 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
945 21:33:41.795698 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
946 21:33:41.833198 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
947 21:33:41.977823 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
948 21:33:42.021654 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
949 21:33:42.154214 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
950 21:33:42.225937 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
951 21:33:42.261795 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
952 21:33:42.363476 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
953 21:33:42.664259 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
954 21:33:42.724474 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
955 21:33:42.770347 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
956 21:33:42.865744 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
957 21:33:43.042218 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
958 21:33:43.185381
959 21:33:43.190145 Debian GNU/Linux 12 debiadebian-bookworm-armhf login: root (automatic login)
960 21:33:43.190391
961 21:33:43.511339 Linux debian-bookworm-armhf 6.11.0-rc5 #1 SMP Sat Aug 31 20:04:28 UTC 2024 armv7l
962 21:33:43.511661
963 21:33:43.516978 The programs included with the Debian GNU/Linux system are free software;
964 21:33:43.522579 the exact distribution terms for each program are described in the
965 21:33:43.528084 individual files in /usr/share/doc/*/copyright.
966 21:33:43.528371
967 21:33:43.536008 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
968 21:33:43.536256 permitted by applicable law.
969 21:33:48.168796 Unable to match end of the kernel message
971 21:33:48.169602 Setting prompt string to ['/ #']
972 21:33:48.169901 end: 2.4.4.1 login-action (duration 00:00:48) [common]
974 21:33:48.170589 end: 2.4.4 auto-login-action (duration 00:00:49) [common]
975 21:33:48.170880 start: 2.4.5 expect-shell-connection (timeout 00:03:23) [common]
976 21:33:48.171122 Setting prompt string to ['/ #']
977 21:33:48.171331 Forcing a shell prompt, looking for ['/ #']
979 21:33:48.221870 / #
980 21:33:48.222243 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
981 21:33:48.222536 Waiting using forced prompt support (timeout 00:02:30)
982 21:33:48.226735
983 21:33:48.233142 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
984 21:33:48.233476 start: 2.4.6 export-device-env (timeout 00:03:23) [common]
985 21:33:48.233736 Sending with 10 millisecond of delay
987 21:33:53.282409 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax'
988 21:33:53.292977 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1186701/extract-nfsrootfs-f7eabqax'
989 21:33:53.295058 Sending with 10 millisecond of delay
991 21:33:55.453351 / # export NFS_SERVER_IP='192.168.11.5'
992 21:33:55.463917 export NFS_SERVER_IP='192.168.11.5'
993 21:33:55.465173 end: 2.4.6 export-device-env (duration 00:00:07) [common]
994 21:33:55.465519 end: 2.4 uboot-commands (duration 00:01:44) [common]
995 21:33:55.465839 end: 2 uboot-action (duration 00:01:45) [common]
996 21:33:55.466154 start: 3 lava-test-retry (timeout 00:07:22) [common]
997 21:33:55.466469 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
998 21:33:55.466727 Using namespace: common
1000 21:33:55.567474 / # #
1001 21:33:55.567859 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1002 21:33:55.572233 #
1003 21:33:55.578492 Using /lava-1186701
1005 21:33:55.679243 / # export SHELL=/bin/bash
1006 21:33:55.684051 export SHELL=/bin/bash
1008 21:33:55.790664 / # . /lava-1186701/environment
1009 21:33:55.795691 . /lava-1186701/environment
1011 21:33:55.908571 / # /lava-1186701/bin/lava-test-runner /lava-1186701/0
1012 21:33:55.908962 Test shell timeout: 10s (minimum of the action and connection timeout)
1013 21:33:55.913370 /lava-1186701/bin/lava-test-runner /lava-1186701/0
1014 21:33:56.343937 + export TESTRUN_ID=0_timesync-off
1015 21:33:56.351977 + TESTRUN_ID=0_timesync-off
1016 21:33:56.352248 + cd /lava-1186701/0/tests/0_timesync-off
1017 21:33:56.352493 ++ cat uuid
1018 21:33:56.367298 + UUID=1186701_1.6.2.4.1
1019 21:33:56.367553 + set +x
1020 21:33:56.372892 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1186701_1.6.2.4.1>
1021 21:33:56.373352 Received signal: <STARTRUN> 0_timesync-off 1186701_1.6.2.4.1
1022 21:33:56.373591 Starting test lava.0_timesync-off (1186701_1.6.2.4.1)
1023 21:33:56.373864 Skipping test definition patterns.
1024 21:33:56.376086 + systemctl stop systemd-timesyncd
1025 21:33:56.650182 + set +x
1026 21:33:56.650688 Received signal: <ENDRUN> 0_timesync-off 1186701_1.6.2.4.1
1027 21:33:56.650962 Ending use of test pattern.
1028 21:33:56.651185 Ending test lava.0_timesync-off (1186701_1.6.2.4.1), duration 0.28
1030 21:33:56.653398 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1186701_1.6.2.4.1>
1031 21:33:56.872640 + export TESTRUN_ID=1_kselftest-dt
1032 21:33:56.880577 + TESTRUN_ID=1_kselftest-dt
1033 21:33:56.880821 + cd /lava-1186701/0/tests/1_kselftest-dt
1034 21:33:56.881059 ++ cat uuid
1035 21:33:56.896430 + UUID=1186701_1.6.2.4.5
1036 21:33:56.896726 + set +x
1037 21:33:56.902019 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1186701_1.6.2.4.5>
1038 21:33:56.902286 + cd ./automated/linux/kselftest/
1039 21:33:56.902751 Received signal: <STARTRUN> 1_kselftest-dt 1186701_1.6.2.4.5
1040 21:33:56.903003 Starting test lava.1_kselftest-dt (1186701_1.6.2.4.5)
1041 21:33:56.903305 Skipping test definition patterns.
1042 21:33:56.930602 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1043 21:33:57.040261 INFO: install_deps skipped
1044 21:33:57.684502 --2024-08-31 21:33:57-- http://storage.kernelci.org/mainline/master/v6.11-rc5-310-ge8784b0aef62c/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1045 21:33:57.701279 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1046 21:33:57.815956 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1047 21:33:57.927886 HTTP request sent, awaiting response... 200 OK
1048 21:33:57.928180 Length: 2104156 (2.0M) [application/octet-stream]
1049 21:33:57.933460 Saving to: 'kselftest_armhf.tar.gz'
1050 21:33:57.933717
1051 21:33:58.938114 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 2%[ ] 49.92K 224KB/s kselftest_armhf.tar 10%[=> ] 218.67K 492KB/s kselftest_armhf.tar 31%[=====> ] 643.79K 883KB/s kselftest_armhf.tar 62%[===========> ] 1.25M 1.31MB/s kselftest_armhf.tar 100%[===================>] 2.01M 2.00MB/s in 1.0s
1052 21:33:58.938480
1053 21:33:59.206558 2024-08-31 21:33:58 (2.00 MB/s) - 'kselftest_armhf.tar.gz' saved [2104156/2104156]
1054 21:33:59.206892
1055 21:34:17.270763 skiplist:
1056 21:34:17.271137 ========================================
1057 21:34:17.276556 ========================================
1058 21:34:17.406432 dt:test_unprobed_devices.sh
1059 21:34:17.440564 ============== Tests to run ===============
1060 21:34:17.447800 dt:test_unprobed_devices.sh
1061 21:34:17.451888 ===========End Tests to run ===============
1062 21:34:17.461420 shardfile-dt pass
1063 21:34:17.702809 <12>[ 77.587270] kselftest: Running tests in dt
1064 21:34:17.732400 TAP version 13
1065 21:34:17.756877 1..1
1066 21:34:17.812596 # timeout set to 45
1067 21:34:17.812862 # selftests: dt: test_unprobed_devices.sh
1068 21:34:18.702334 # TAP version 13
1069 21:34:31.429202 # 1..255
1070 21:34:31.613417 # ok 1 / # SKIP
1071 21:34:31.635686 # ok 2 /clk_mcasp0
1072 21:34:31.708842 # ok 3 /clk_mcasp0_fixed # SKIP
1073 21:34:31.784226 # ok 4 /cpus/cpu@0 # SKIP
1074 21:34:31.858799 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1075 21:34:31.880449 # ok 6 /fixedregulator0
1076 21:34:31.902377 # ok 7 /leds
1077 21:34:31.923153 # ok 8 /ocp
1078 21:34:31.948330 # ok 9 /ocp/interconnect@44c00000
1079 21:34:31.975044 # ok 10 /ocp/interconnect@44c00000/segment@0
1080 21:34:32.001006 # ok 11 /ocp/interconnect@44c00000/segment@100000
1081 21:34:32.021160 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1082 21:34:32.095446 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1083 21:34:32.121845 # ok 14 /ocp/interconnect@44c00000/segment@200000
1084 21:34:32.149237 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1085 21:34:32.257834 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1086 21:34:32.326953 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1087 21:34:32.409328 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1088 21:34:32.483444 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1089 21:34:32.556091 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1090 21:34:32.629438 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1091 21:34:32.703312 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1092 21:34:32.775836 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1093 21:34:32.849432 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1094 21:34:32.917187 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1095 21:34:32.997601 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1096 21:34:33.073430 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1097 21:34:33.151049 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1098 21:34:33.217804 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1099 21:34:33.297047 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1100 21:34:33.373417 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1101 21:34:33.445571 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1102 21:34:33.522539 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1103 21:34:33.588162 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1104 21:34:33.669428 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1105 21:34:33.736658 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1106 21:34:33.819813 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1107 21:34:33.891229 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1108 21:34:33.968357 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1109 21:34:34.043929 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1110 21:34:34.119930 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1111 21:34:34.192014 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1112 21:34:34.263605 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1113 21:34:34.338030 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1114 21:34:34.420380 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1115 21:34:34.491718 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1116 21:34:34.568526 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1117 21:34:34.641887 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1118 21:34:34.714383 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1119 21:34:34.790435 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1120 21:34:34.857112 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1121 21:34:34.939507 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1122 21:34:35.014743 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1123 21:34:35.089738 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1124 21:34:35.163855 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1125 21:34:35.238731 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1126 21:34:35.304998 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1127 21:34:35.383726 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1128 21:34:35.458223 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1129 21:34:35.534060 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1130 21:34:35.607308 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1131 21:34:35.681129 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1132 21:34:35.755229 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1133 21:34:35.834353 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1134 21:34:35.908330 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1135 21:34:35.976628 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1136 21:34:36.059101 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1137 21:34:36.133647 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1138 21:34:36.205598 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1139 21:34:36.282780 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1140 21:34:36.349489 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1141 21:34:36.430947 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1142 21:34:36.503195 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1143 21:34:36.580315 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1144 21:34:36.672311 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1145 21:34:36.731971 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1146 21:34:36.810305 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1147 21:34:36.884091 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1148 21:34:36.960178 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1149 21:34:37.033993 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1150 21:34:37.110245 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1151 21:34:37.176915 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1152 21:34:37.255412 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1153 21:34:37.330786 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1154 21:34:37.402901 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1155 21:34:37.476682 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1156 21:34:37.553270 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1157 21:34:37.626018 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1158 21:34:37.705142 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1159 21:34:37.773772 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1160 21:34:37.853725 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1161 21:34:37.922601 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1162 21:34:38.001985 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1163 21:34:38.079204 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1164 21:34:38.091705 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1165 21:34:38.119113 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1166 21:34:38.146603 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1167 21:34:38.171213 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1168 21:34:38.190328 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1169 21:34:38.221763 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1170 21:34:38.243105 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1171 21:34:38.266473 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1172 21:34:38.374781 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1173 21:34:38.400946 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1174 21:34:38.417434 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1175 21:34:38.447981 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1176 21:34:38.551731 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1177 21:34:38.632705 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1178 21:34:38.710562 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1179 21:34:38.779188 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1180 21:34:38.855116 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1181 21:34:38.935309 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1182 21:34:39.009196 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1183 21:34:39.084799 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1184 21:34:39.162062 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1185 21:34:39.235684 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1186 21:34:39.311578 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1187 21:34:39.383284 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1188 21:34:39.453041 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1189 21:34:39.536721 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1190 21:34:39.613458 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1191 21:34:39.683977 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1192 21:34:39.711205 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1193 21:34:39.775176 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1194 21:34:39.852644 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1195 21:34:39.930116 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1196 21:34:39.950635 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1197 21:34:40.020138 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1198 21:34:40.043315 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1199 21:34:40.118694 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1200 21:34:40.146698 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1201 21:34:40.169606 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1202 21:34:40.188571 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1203 21:34:40.221598 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1204 21:34:40.236274 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1205 21:34:40.266862 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1206 21:34:40.292939 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1207 21:34:40.318475 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1208 21:34:40.341490 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1209 21:34:40.410174 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1210 21:34:40.492345 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1211 21:34:40.514030 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1212 21:34:40.588557 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1213 21:34:40.659486 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1214 21:34:40.759929 # not ok 145 /ocp/interconnect@47c00000
1215 21:34:40.834102 # not ok 146 /ocp/interconnect@47c00000/segment@0
1216 21:34:40.856172 # ok 147 /ocp/interconnect@48000000
1217 21:34:40.883877 # ok 148 /ocp/interconnect@48000000/segment@0
1218 21:34:40.906684 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1219 21:34:40.934510 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1220 21:34:40.960055 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1221 21:34:40.977008 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1222 21:34:41.006421 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1223 21:34:41.028138 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1224 21:34:41.056764 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1225 21:34:41.124835 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1226 21:34:41.199976 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1227 21:34:41.229513 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1228 21:34:41.250552 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1229 21:34:41.275014 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1230 21:34:41.300720 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1231 21:34:41.317151 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1232 21:34:41.350464 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1233 21:34:41.365729 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1234 21:34:41.390468 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1235 21:34:41.417259 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1236 21:34:41.439097 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1237 21:34:41.468404 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1238 21:34:41.484933 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1239 21:34:41.509557 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1240 21:34:41.534659 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1241 21:34:41.562427 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1242 21:34:41.585059 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1243 21:34:41.611054 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1244 21:34:41.632911 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1245 21:34:41.661015 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1246 21:34:41.679676 # ok 177 /ocp/interconnect@48000000/segment@100000
1247 21:34:41.706533 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1248 21:34:41.727670 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1249 21:34:41.807023 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1250 21:34:41.881505 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1251 21:34:41.948147 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1252 21:34:42.025758 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1253 21:34:42.048805 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1254 21:34:42.070479 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1255 21:34:42.096978 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1256 21:34:42.120500 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1257 21:34:42.136910 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1258 21:34:42.168267 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1259 21:34:42.186746 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1260 21:34:42.217622 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1261 21:34:42.240161 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1262 21:34:42.257629 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1263 21:34:42.286647 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1264 21:34:42.308377 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1265 21:34:42.335245 # ok 196 /ocp/interconnect@48000000/segment@200000
1266 21:34:42.352543 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1267 21:34:42.434003 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1268 21:34:42.455207 # ok 199 /ocp/interconnect@48000000/segment@300000
1269 21:34:42.478123 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1270 21:34:42.498627 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1271 21:34:42.523108 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1272 21:34:42.553985 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1273 21:34:42.576516 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1274 21:34:42.600009 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1275 21:34:42.668997 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1276 21:34:42.692830 # ok 207 /ocp/interconnect@4a000000
1277 21:34:42.714448 # ok 208 /ocp/interconnect@4a000000/segment@0
1278 21:34:42.743878 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1279 21:34:42.768111 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1280 21:34:42.794473 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1281 21:34:42.817510 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1282 21:34:42.885957 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1283 21:34:43.002414 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1284 21:34:43.071038 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1285 21:34:43.187174 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1286 21:34:43.253458 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1287 21:34:43.331669 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1288 21:34:43.436709 # not ok 219 /ocp/interconnect@4b140000
1289 21:34:43.502958 # not ok 220 /ocp/interconnect@4b140000/segment@0
1290 21:34:43.581583 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1291 21:34:43.602831 # ok 222 /ocp/target-module@40300000
1292 21:34:43.624436 # ok 223 /ocp/target-module@40300000/sram@0
1293 21:34:43.698282 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1294 21:34:43.777602 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1295 21:34:43.796698 # ok 226 /ocp/target-module@47400000
1296 21:34:43.822197 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1297 21:34:43.844122 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1298 21:34:43.864945 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1299 21:34:43.886692 # ok 230 /ocp/target-module@47400000/usb@1400
1300 21:34:43.909067 # ok 231 /ocp/target-module@47400000/usb@1800
1301 21:34:43.930764 # ok 232 /ocp/target-module@47810000
1302 21:34:43.953944 # ok 233 /ocp/target-module@49000000
1303 21:34:43.981617 # ok 234 /ocp/target-module@49000000/dma@0
1304 21:34:44.003452 # ok 235 /ocp/target-module@49800000
1305 21:34:44.025441 # ok 236 /ocp/target-module@49800000/dma@0
1306 21:34:44.049586 # ok 237 /ocp/target-module@49900000
1307 21:34:44.073709 # ok 238 /ocp/target-module@49900000/dma@0
1308 21:34:44.093690 # ok 239 /ocp/target-module@49a00000
1309 21:34:44.114562 # ok 240 /ocp/target-module@49a00000/dma@0
1310 21:34:44.142218 # ok 241 /ocp/target-module@4c000000
1311 21:34:44.214434 # not ok 242 /ocp/target-module@4c000000/emif@0
1312 21:34:44.233853 # ok 243 /ocp/target-module@50000000
1313 21:34:44.254530 # ok 244 /ocp/target-module@53100000
1314 21:34:44.328476 # not ok 245 /ocp/target-module@53100000/sham@0
1315 21:34:44.349983 # ok 246 /ocp/target-module@53500000
1316 21:34:44.424040 # not ok 247 /ocp/target-module@53500000/aes@0
1317 21:34:44.450483 # ok 248 /ocp/target-module@56000000
1318 21:34:44.555957 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1319 21:34:44.630330 # ok 250 /opp-table # SKIP
1320 21:34:44.697669 # ok 251 /soc # SKIP
1321 21:34:44.722161 # ok 252 /sound
1322 21:34:44.744931 # ok 253 /target-module@4b000000
1323 21:34:44.769134 # ok 254 /target-module@4b000000/target-module@140000
1324 21:34:44.791040 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1325 21:34:44.799305 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1326 21:34:44.807761 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1327 21:34:47.066754 dt_test_unprobed_devices_sh_ skip
1328 21:34:47.072316 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1329 21:34:47.077909 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1330 21:34:47.078162 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1331 21:34:47.083526 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1332 21:34:47.089152 dt_test_unprobed_devices_sh_fixedregulator0 pass
1333 21:34:47.094806 dt_test_unprobed_devices_sh_leds pass
1334 21:34:47.095094 dt_test_unprobed_devices_sh_ocp pass
1335 21:34:47.100321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1336 21:34:47.105900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1337 21:34:47.111522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1338 21:34:47.122771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1339 21:34:47.128397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1340 21:34:47.134029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1341 21:34:47.145143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1342 21:34:47.150767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1343 21:34:47.162038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1344 21:34:47.173284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1345 21:34:47.184403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1346 21:34:47.190159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1347 21:34:47.201281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1348 21:34:47.212530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1349 21:34:47.223773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1350 21:34:47.235024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1351 21:34:47.240665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1352 21:34:47.251770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1353 21:34:47.263023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1354 21:34:47.274144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1355 21:34:47.285408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1356 21:34:47.291025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1357 21:34:47.302148 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1358 21:34:47.313408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1359 21:34:47.324522 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1360 21:34:47.330157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1361 21:34:47.341276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1362 21:34:47.352526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1363 21:34:47.363767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1364 21:34:47.374894 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1365 21:34:47.380533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1366 21:34:47.391640 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1367 21:34:47.402897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1368 21:34:47.414140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1369 21:34:47.425265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1370 21:34:47.436514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1371 21:34:47.447649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1372 21:34:47.458892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1373 21:34:47.470149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1374 21:34:47.481268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1375 21:34:47.492396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1376 21:34:47.503638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1377 21:34:47.514766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1378 21:34:47.526014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1379 21:34:47.537140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1380 21:34:47.548391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1381 21:34:47.559518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1382 21:34:47.570785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1383 21:34:47.581885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1384 21:34:47.593152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1385 21:34:47.604278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1386 21:34:47.615513 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1387 21:34:47.626654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1388 21:34:47.637916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1389 21:34:47.649138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1390 21:34:47.660283 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1391 21:34:47.665911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1392 21:34:47.677134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1393 21:34:47.688288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1394 21:34:47.699384 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1395 21:34:47.710634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1396 21:34:47.721776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1397 21:34:47.733013 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1398 21:34:47.744128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1399 21:34:47.755383 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1400 21:34:47.766633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1401 21:34:47.777764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1402 21:34:47.789026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1403 21:34:47.800128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1404 21:34:47.811375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1405 21:34:47.822504 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1406 21:34:47.833778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1407 21:34:47.844906 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1408 21:34:47.856129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1409 21:34:47.861758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1410 21:34:47.872886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1411 21:34:47.884125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1412 21:34:47.895250 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1413 21:34:47.906503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1414 21:34:47.912129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1415 21:34:47.928963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1416 21:34:47.940134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1417 21:34:47.945633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1418 21:34:47.962582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1419 21:34:47.974002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1420 21:34:47.984992 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1421 21:34:47.990580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1422 21:34:48.001714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1423 21:34:48.012959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1424 21:34:48.018578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1425 21:34:48.029703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1426 21:34:48.040993 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1427 21:34:48.046459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1428 21:34:48.057700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1429 21:34:48.063326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1430 21:34:48.074466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1431 21:34:48.085702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1432 21:34:48.096850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1433 21:34:48.108076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1434 21:34:48.119325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1435 21:34:48.130473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1436 21:34:48.141703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1437 21:34:48.152966 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1438 21:34:48.164214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1439 21:34:48.175345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1440 21:34:48.186572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1441 21:34:48.197729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1442 21:34:48.214577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1443 21:34:48.225860 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1444 21:34:48.237075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1445 21:34:48.248211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1446 21:34:48.259447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1447 21:34:48.276211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1448 21:34:48.287448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1449 21:34:48.298568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1450 21:34:48.309838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1451 21:34:48.315458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1452 21:34:48.326568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1453 21:34:48.337842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1454 21:34:48.343337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1455 21:34:48.354583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1456 21:34:48.360194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1457 21:34:48.371322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1458 21:34:48.376963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1459 21:34:48.388194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1460 21:34:48.393695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1461 21:34:48.404945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1462 21:34:48.410446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1463 21:34:48.421693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1464 21:34:48.432947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1465 21:34:48.444194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1466 21:34:48.449695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1467 21:34:48.460828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1468 21:34:48.472078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1469 21:34:48.477692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1470 21:34:48.488828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1471 21:34:48.494439 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1472 21:34:48.500064 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1473 21:34:48.505692 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1474 21:34:48.511202 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1475 21:34:48.522434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1476 21:34:48.528064 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1477 21:34:48.533558 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1478 21:34:48.544815 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1479 21:34:48.550435 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1480 21:34:48.561560 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1481 21:34:48.567185 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1482 21:34:48.578314 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1483 21:34:48.583934 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1484 21:34:48.589562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1485 21:34:48.600694 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1486 21:34:48.606310 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1487 21:34:48.617512 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1488 21:34:48.623182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1489 21:34:48.634268 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1490 21:34:48.639891 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1491 21:34:48.651186 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1492 21:34:48.656687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1493 21:34:48.667806 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1494 21:34:48.673436 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1495 21:34:48.684687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1496 21:34:48.690307 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1497 21:34:48.701434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1498 21:34:48.707057 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1499 21:34:48.712681 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1500 21:34:48.723807 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1501 21:34:48.729431 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1502 21:34:48.740561 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1503 21:34:48.746184 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1504 21:34:48.757432 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1505 21:34:48.762932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1506 21:34:48.774181 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1507 21:34:48.785436 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1508 21:34:48.796558 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1509 21:34:48.802179 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1510 21:34:48.813302 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1511 21:34:48.818931 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1512 21:34:48.830179 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1513 21:34:48.835677 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1514 21:34:48.846862 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1515 21:34:48.852517 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1516 21:34:48.863622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1517 21:34:48.874869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1518 21:34:48.880405 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1519 21:34:48.891616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1520 21:34:48.897246 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1521 21:34:48.908368 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1522 21:34:48.914120 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1523 21:34:48.919620 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1524 21:34:48.930740 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1525 21:34:48.936491 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1526 21:34:48.941983 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1527 21:34:48.953269 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1528 21:34:48.958768 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1529 21:34:48.970022 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1530 21:34:48.975519 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1531 21:34:48.986811 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1532 21:34:48.992412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1533 21:34:48.997918 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1534 21:34:49.003518 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1535 21:34:49.014771 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1536 21:34:49.020294 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1537 21:34:49.031520 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1538 21:34:49.037206 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1539 21:34:49.048370 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1540 21:34:49.059580 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1541 21:34:49.070699 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1542 21:34:49.076361 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1543 21:34:49.087580 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1544 21:34:49.098701 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1545 21:34:49.104362 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1546 21:34:49.109884 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1547 21:34:49.115404 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1548 21:34:49.121153 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1549 21:34:49.126657 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1550 21:34:49.132336 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1551 21:34:49.143559 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1552 21:34:49.149169 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1553 21:34:49.154650 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1554 21:34:49.160318 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1555 21:34:49.165972 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1556 21:34:49.171546 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1557 21:34:49.177163 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1558 21:34:49.182641 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1559 21:34:49.188272 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1560 21:34:49.193908 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1561 21:34:49.199532 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1562 21:34:49.205161 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1563 21:34:49.210782 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1564 21:34:49.216275 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1565 21:34:49.221906 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1566 21:34:49.227530 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1567 21:34:49.233158 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1568 21:34:49.238775 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1569 21:34:49.244283 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1570 21:34:49.249899 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1571 21:34:49.255509 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1572 21:34:49.261177 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1573 21:34:49.266787 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1574 21:34:49.272248 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1575 21:34:49.277912 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1576 21:34:49.283534 dt_test_unprobed_devices_sh_opp-table skip
1577 21:34:49.289162 dt_test_unprobed_devices_sh_soc skip
1578 21:34:49.289436 dt_test_unprobed_devices_sh_sound pass
1579 21:34:49.294784 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1580 21:34:49.300419 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1581 21:34:49.311536 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1582 21:34:49.311811 dt_test_unprobed_devices_sh fail
1583 21:34:49.317160 + ../../utils/send-to-lava.sh ./output/result.txt
1584 21:34:49.322463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1585 21:34:49.323032 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1587 21:34:49.359570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1588 21:34:49.360060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1590 21:34:49.458756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1591 21:34:49.459240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1593 21:34:49.556578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1594 21:34:49.557061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1596 21:34:49.653482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1597 21:34:49.653967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1599 21:34:49.749951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1600 21:34:49.750435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1602 21:34:49.845582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1603 21:34:49.846066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1605 21:34:49.943600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1606 21:34:49.944166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1608 21:34:50.040975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1609 21:34:50.041538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1611 21:34:50.137460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1612 21:34:50.137943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1614 21:34:50.235569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1615 21:34:50.236055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1617 21:34:50.329189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1618 21:34:50.329676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1620 21:34:50.426209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1621 21:34:50.426834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1623 21:34:50.524333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1624 21:34:50.524820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1626 21:34:50.618219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1627 21:34:50.618709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1629 21:34:50.713853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1630 21:34:50.714339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1632 21:34:50.812261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1633 21:34:50.812746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1635 21:34:50.907723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1636 21:34:50.908230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1638 21:34:51.006698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1639 21:34:51.007304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1641 21:34:51.106824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1642 21:34:51.107320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1644 21:34:51.206784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1645 21:34:51.207272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1647 21:34:51.307130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1648 21:34:51.307619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1650 21:34:51.406239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1651 21:34:51.406762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1653 21:34:51.507808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1654 21:34:51.508339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1656 21:34:51.605576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1657 21:34:51.606065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1659 21:34:51.704213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1660 21:34:51.704684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1662 21:34:51.800602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1663 21:34:51.801080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1665 21:34:51.898046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1666 21:34:51.898527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1668 21:34:51.996799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1669 21:34:51.997351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1671 21:34:52.093288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1672 21:34:52.093765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1674 21:34:52.189583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1675 21:34:52.190077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1677 21:34:52.284156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1678 21:34:52.284653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1680 21:34:52.379046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1681 21:34:52.379521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1683 21:34:52.474345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1684 21:34:52.474826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1686 21:34:52.572069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1687 21:34:52.572571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1689 21:34:52.669023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1690 21:34:52.669494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1692 21:34:52.768293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1693 21:34:52.768763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1695 21:34:52.863423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1696 21:34:52.863896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1698 21:34:52.966563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1699 21:34:52.967127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1701 21:34:53.063203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1702 21:34:53.063787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1704 21:34:53.157800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1705 21:34:53.158311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1707 21:34:53.253437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1708 21:34:53.253923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1710 21:34:53.349596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1711 21:34:53.350094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1713 21:34:53.442567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1714 21:34:53.443054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1716 21:34:53.539064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1717 21:34:53.539568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1719 21:34:53.638628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1720 21:34:53.639115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1722 21:34:53.737844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1723 21:34:53.738328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1725 21:34:53.836722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1726 21:34:53.837208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1728 21:34:53.939217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1729 21:34:53.939704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1731 21:34:54.037608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1732 21:34:54.038178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1734 21:34:54.133820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1735 21:34:54.134319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1737 21:34:54.228548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1738 21:34:54.229031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1740 21:34:54.326502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1741 21:34:54.326984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1743 21:34:54.422266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1744 21:34:54.422758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1746 21:34:54.518662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1747 21:34:54.519150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1749 21:34:54.615778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1750 21:34:54.616267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1752 21:34:54.713773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1753 21:34:54.714261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1755 21:34:54.809756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1756 21:34:54.810251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1758 21:34:54.904775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1759 21:34:54.905284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1761 21:34:55.005292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1762 21:34:55.005879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1764 21:34:55.103058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1765 21:34:55.103554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1767 21:34:55.202639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1768 21:34:55.203123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1770 21:34:55.300796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1771 21:34:55.301281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1773 21:34:55.397294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1774 21:34:55.397778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1776 21:34:55.497661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1777 21:34:55.498147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1779 21:34:55.596277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1780 21:34:55.596770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1782 21:34:55.693157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1783 21:34:55.693642 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1785 21:34:55.787291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1786 21:34:55.787784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1788 21:34:55.886374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1789 21:34:55.886859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1791 21:34:55.984871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1792 21:34:55.985447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1794 21:34:56.082328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1795 21:34:56.082897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1797 21:34:56.182636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1798 21:34:56.183121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1800 21:34:56.285633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1801 21:34:56.286118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1803 21:34:56.386388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1804 21:34:56.386881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1806 21:34:56.486602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1807 21:34:56.487089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1809 21:34:56.586098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1810 21:34:56.586594 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1812 21:34:56.687672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1813 21:34:56.688170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1815 21:34:56.787470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1816 21:34:56.787957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1818 21:34:56.887468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1819 21:34:56.887951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1821 21:34:56.988227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1822 21:34:56.988792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1824 21:34:57.087086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1825 21:34:57.087647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1827 21:34:57.187727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1828 21:34:57.188232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1830 21:34:57.287348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1831 21:34:57.287832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1833 21:34:57.385468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1834 21:34:57.385950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1836 21:34:57.485069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1837 21:34:57.485545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1839 21:34:57.581227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1840 21:34:57.581710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1842 21:34:57.681309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1843 21:34:57.681789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1845 21:34:57.784957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1846 21:34:57.785436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1848 21:34:57.886940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1849 21:34:57.887419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1851 21:34:57.988352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1852 21:34:57.988913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1854 21:34:58.087676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1855 21:34:58.088243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1857 21:34:58.185291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1858 21:34:58.185775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1860 21:34:58.286052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1861 21:34:58.286535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1863 21:34:58.385669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1864 21:34:58.386167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1866 21:34:58.484781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1867 21:34:58.485261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1869 21:34:58.579921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1870 21:34:58.580425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1872 21:34:58.679674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1873 21:34:58.680154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1875 21:34:58.780477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1876 21:34:58.780958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1878 21:34:58.881519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1879 21:34:58.882005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1881 21:34:58.982554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1882 21:34:58.983122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1884 21:34:59.080298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1885 21:34:59.080862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1887 21:34:59.175133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1888 21:34:59.175618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1890 21:34:59.273129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1891 21:34:59.273612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1893 21:34:59.368046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1894 21:34:59.368560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1896 21:34:59.461621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1897 21:34:59.462108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1899 21:34:59.561255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1900 21:34:59.561739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1902 21:34:59.656991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1903 21:34:59.657482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1905 21:34:59.755494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1906 21:34:59.755969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1908 21:34:59.855854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1909 21:34:59.856312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1911 21:34:59.958094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1912 21:34:59.958569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1914 21:35:00.058248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1915 21:35:00.058807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1917 21:35:00.155838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1918 21:35:00.156318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1920 21:35:00.255322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1921 21:35:00.255800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1923 21:35:00.356335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1924 21:35:00.356813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1926 21:35:00.456999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1927 21:35:00.457489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1929 21:35:00.557752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1930 21:35:00.558230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1932 21:35:00.657247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1933 21:35:00.657729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1935 21:35:00.755379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1936 21:35:00.755857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1938 21:35:00.855866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1939 21:35:00.856347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1941 21:35:00.956253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1942 21:35:00.956732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1944 21:35:01.056014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1946 21:35:01.059142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1947 21:35:01.155505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1949 21:35:01.158508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1950 21:35:01.252260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1952 21:35:01.255374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1953 21:35:01.353979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1954 21:35:01.354468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1956 21:35:01.454740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1957 21:35:01.455226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1959 21:35:01.554150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1960 21:35:01.554629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1962 21:35:01.654747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1963 21:35:01.655227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1965 21:35:01.750519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1966 21:35:01.750996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1968 21:35:01.850905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1969 21:35:01.851382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1971 21:35:01.954465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1972 21:35:01.954940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1974 21:35:02.054239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1975 21:35:02.054797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1977 21:35:02.151959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1978 21:35:02.152452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1980 21:35:02.250705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1981 21:35:02.251181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1983 21:35:02.349967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1984 21:35:02.350442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1986 21:35:02.454826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1987 21:35:02.455301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1989 21:35:02.554468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1990 21:35:02.554942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1992 21:35:02.652806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1993 21:35:02.653280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1995 21:35:02.752817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1996 21:35:02.753293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1998 21:35:02.850715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1999 21:35:02.851197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2001 21:35:02.951511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2002 21:35:02.952004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2004 21:35:03.082331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2005 21:35:03.082841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2007 21:35:03.188175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2008 21:35:03.188673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2010 21:35:03.286729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2011 21:35:03.287206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2013 21:35:03.385677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2014 21:35:03.386175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2016 21:35:03.485669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2017 21:35:03.486166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2019 21:35:03.581085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2020 21:35:03.581576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2022 21:35:03.680980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2023 21:35:03.681455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2025 21:35:03.777795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2026 21:35:03.778269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2028 21:35:03.879534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2029 21:35:03.880006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2031 21:35:03.982841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2032 21:35:03.983628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2034 21:35:04.083641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2035 21:35:04.084211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2037 21:35:04.183336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2038 21:35:04.183811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2040 21:35:04.284905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2041 21:35:04.285386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2043 21:35:04.383227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2044 21:35:04.383748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2046 21:35:04.484460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2047 21:35:04.484991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2049 21:35:04.583923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2050 21:35:04.584438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2052 21:35:04.683843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2053 21:35:04.684327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2055 21:35:04.783746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2056 21:35:04.784260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2058 21:35:04.883682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2059 21:35:04.884170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2061 21:35:04.984071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2062 21:35:04.984613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2064 21:35:05.083095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2065 21:35:05.083649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2067 21:35:05.182424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2068 21:35:05.182909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2070 21:35:05.282149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2071 21:35:05.282625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2073 21:35:05.382465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2074 21:35:05.382941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2076 21:35:05.483792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2077 21:35:05.484257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2079 21:35:05.584371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2080 21:35:05.584848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2082 21:35:05.682019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2083 21:35:05.682501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2085 21:35:05.781205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2086 21:35:05.781679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2088 21:35:05.879318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2089 21:35:05.879825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2091 21:35:05.977715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2092 21:35:05.978199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2094 21:35:06.075756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2095 21:35:06.076324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2097 21:35:06.174421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2098 21:35:06.174916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2100 21:35:06.273312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2101 21:35:06.273801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2103 21:35:06.373325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2104 21:35:06.373813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2106 21:35:06.474733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2107 21:35:06.475220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2109 21:35:06.573627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2110 21:35:06.574115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2112 21:35:06.672896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2113 21:35:06.673384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2115 21:35:06.769099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2116 21:35:06.769587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2118 21:35:06.873726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2119 21:35:06.874223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2121 21:35:06.973242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2122 21:35:06.973730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2124 21:35:07.076008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2125 21:35:07.076626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2127 21:35:07.175043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2128 21:35:07.175520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2130 21:35:07.276026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2131 21:35:07.276551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2133 21:35:07.376259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2134 21:35:07.376766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2136 21:35:07.473843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2137 21:35:07.474327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2139 21:35:07.573734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2140 21:35:07.574228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2142 21:35:07.674090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2143 21:35:07.674571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2145 21:35:07.774185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2146 21:35:07.774669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2148 21:35:07.873969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2149 21:35:07.874457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2151 21:35:07.974802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2152 21:35:07.975284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2154 21:35:08.073702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2155 21:35:08.074260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2157 21:35:08.174299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2158 21:35:08.174780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2160 21:35:08.273818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2161 21:35:08.274297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2163 21:35:08.374413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2164 21:35:08.374902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2166 21:35:08.474062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2167 21:35:08.474546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2169 21:35:08.574783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2170 21:35:08.575277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2172 21:35:08.672538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2173 21:35:08.673017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2175 21:35:08.775578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2176 21:35:08.776065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2178 21:35:08.874778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2179 21:35:08.875274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2181 21:35:08.972049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2182 21:35:08.972567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2184 21:35:09.074907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2185 21:35:09.075482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2187 21:35:09.174268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2188 21:35:09.174766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2190 21:35:09.274528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2191 21:35:09.275012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2193 21:35:09.375396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2194 21:35:09.375892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2196 21:35:09.473692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2197 21:35:09.474195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2199 21:35:09.566526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2200 21:35:09.567007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2202 21:35:09.664025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2203 21:35:09.664541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2205 21:35:09.755529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2206 21:35:09.756013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2208 21:35:09.852283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2209 21:35:09.852762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2211 21:35:09.952442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2212 21:35:09.952921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2214 21:35:10.066138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2215 21:35:10.066706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2217 21:35:10.169366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2218 21:35:10.169853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2220 21:35:10.266357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2221 21:35:10.266842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2223 21:35:10.361532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2224 21:35:10.362040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2226 21:35:10.462148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2227 21:35:10.462636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2229 21:35:10.565741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2230 21:35:10.566233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2232 21:35:10.665577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2233 21:35:10.666122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2235 21:35:10.763487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2236 21:35:10.763974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2238 21:35:10.862785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2239 21:35:10.863261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2241 21:35:10.958684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2242 21:35:10.959160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2244 21:35:11.060545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2245 21:35:11.061147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2247 21:35:11.160710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2248 21:35:11.161182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2250 21:35:11.258121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2251 21:35:11.258598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2253 21:35:11.358745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2254 21:35:11.359229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2256 21:35:11.459725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2257 21:35:11.460229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2259 21:35:11.553743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2261 21:35:11.556705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2262 21:35:11.650199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2263 21:35:11.650698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2265 21:35:11.749571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2266 21:35:11.750057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2268 21:35:11.850478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2269 21:35:11.850974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2271 21:35:11.946192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2272 21:35:11.946680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2274 21:35:12.043574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2275 21:35:12.044132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2277 21:35:12.137478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2278 21:35:12.138055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2280 21:35:12.233584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2281 21:35:12.234083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2283 21:35:12.327339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2284 21:35:12.327854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2286 21:35:12.429468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2287 21:35:12.429957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2289 21:35:12.529829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2290 21:35:12.530311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2292 21:35:12.627206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2293 21:35:12.627692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2295 21:35:12.729022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2296 21:35:12.729528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2298 21:35:12.834273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2299 21:35:12.834771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2301 21:35:12.930536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2302 21:35:12.931031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2304 21:35:13.025648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2305 21:35:13.026230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2307 21:35:13.127576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2308 21:35:13.128155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2310 21:35:13.230354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2311 21:35:13.230840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2313 21:35:13.331123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2314 21:35:13.331619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2316 21:35:13.430494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2317 21:35:13.430994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2319 21:35:13.531081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2320 21:35:13.531572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2322 21:35:13.630507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2323 21:35:13.631013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2325 21:35:13.731831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2326 21:35:13.732326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2328 21:35:13.830989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2329 21:35:13.831485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2331 21:35:13.930745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2332 21:35:13.931233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2334 21:35:14.027659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2335 21:35:14.028257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2337 21:35:14.128744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2338 21:35:14.129310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2340 21:35:14.228494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2341 21:35:14.228977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2343 21:35:14.330359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2344 21:35:14.330846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2346 21:35:14.431747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2347 21:35:14.432249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2349 21:35:14.532455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2350 21:35:14.532944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2352 21:35:14.628996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2353 21:35:14.629280 + set +x
2354 21:35:14.629714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2356 21:35:14.633366 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1186701_1.6.2.4.5>
2357 21:35:14.633851 Received signal: <ENDRUN> 1_kselftest-dt 1186701_1.6.2.4.5
2358 21:35:14.634101 Ending use of test pattern.
2359 21:35:14.634321 Ending test lava.1_kselftest-dt (1186701_1.6.2.4.5), duration 77.73
2361 21:35:14.638807 <LAVA_TEST_RUNNER EXIT>
2362 21:35:14.639288 ok: lava_test_shell seems to have completed
2363 21:35:14.645154 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2364 21:35:14.646216 end: 3.1 lava-test-shell (duration 00:01:19) [common]
2365 21:35:14.646521 end: 3 lava-test-retry (duration 00:01:19) [common]
2366 21:35:14.646823 start: 4 finalize (timeout 00:06:02) [common]
2367 21:35:14.647119 start: 4.1 power-off (timeout 00:00:30) [common]
2368 21:35:14.647501 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2369 21:35:15.012705 Returned 0 in 0 seconds
2370 21:35:15.113643 end: 4.1 power-off (duration 00:00:00) [common]
2372 21:35:15.114655 start: 4.2 read-feedback (timeout 00:06:02) [common]
2373 21:35:15.115311 Listened to connection for namespace 'common' for up to 1s
2374 21:35:15.115902 Listened to connection for namespace 'common' for up to 1s
2375 21:35:16.116285 Finalising connection for namespace 'common'
2376 21:35:16.116769 Disconnecting from shell: Finalise
2377 21:35:16.117089 / #
2378 21:35:16.217710 end: 4.2 read-feedback (duration 00:00:01) [common]
2379 21:35:16.218114 end: 4 finalize (duration 00:00:02) [common]
2380 21:35:16.218522 Cleaning after the job
2381 21:35:16.218879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/ramdisk
2382 21:35:16.222677 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/kernel
2383 21:35:16.225684 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/dtb
2384 21:35:16.226196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/nfsrootfs
2385 21:35:16.275048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186701/tftp-deploy-h_bpql55/modules
2386 21:35:16.278632 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1186701
2387 21:35:16.913217 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1186701
2388 21:35:16.913503 Job finished correctly