Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 23:49:03.146945 lava-dispatcher, installed at version: 2024.01
2 23:49:03.147547 start: 0 validate
3 23:49:03.147793 Start time: 2024-08-31 23:49:03.147777+00:00 (UTC)
4 23:49:03.148030 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 23:49:03.423893 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/kernel/zImage exists
6 23:49:03.562318 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb exists
7 23:49:03.701635 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 23:49:03.840126 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/modules.tar.xz exists
9 23:49:03.982077 validate duration: 0.83
11 23:49:03.982960 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 23:49:03.983306 start: 1.1 download-retry (timeout 00:10:00) [common]
13 23:49:03.983608 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 23:49:03.984183 Not decompressing ramdisk as can be used compressed.
15 23:49:03.984552 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 23:49:03.984759 saving as /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/ramdisk/initrd.cpio.gz
17 23:49:03.985001 total size: 4775763 (4 MB)
18 23:49:04.262674 progress 0 % (0 MB)
19 23:49:04.664233 progress 5 % (0 MB)
20 23:49:04.798143 progress 10 % (0 MB)
21 23:49:04.804485 progress 15 % (0 MB)
22 23:49:04.932950 progress 20 % (0 MB)
23 23:49:04.937088 progress 25 % (1 MB)
24 23:49:04.940972 progress 30 % (1 MB)
25 23:49:04.945413 progress 35 % (1 MB)
26 23:49:05.067865 progress 40 % (1 MB)
27 23:49:05.071863 progress 45 % (2 MB)
28 23:49:05.076186 progress 50 % (2 MB)
29 23:49:05.080959 progress 55 % (2 MB)
30 23:49:05.085239 progress 60 % (2 MB)
31 23:49:05.089482 progress 65 % (2 MB)
32 23:49:05.093114 progress 70 % (3 MB)
33 23:49:05.096249 progress 75 % (3 MB)
34 23:49:05.203195 progress 80 % (3 MB)
35 23:49:05.205995 progress 85 % (3 MB)
36 23:49:05.209060 progress 90 % (4 MB)
37 23:49:05.211867 progress 95 % (4 MB)
38 23:49:05.215035 progress 100 % (4 MB)
39 23:49:05.215495 4 MB downloaded in 1.23 s (3.70 MB/s)
40 23:49:05.215866 end: 1.1.1 http-download (duration 00:00:01) [common]
42 23:49:05.216415 end: 1.1 download-retry (duration 00:00:01) [common]
43 23:49:05.216618 start: 1.2 download-retry (timeout 00:09:59) [common]
44 23:49:05.216811 start: 1.2.1 http-download (timeout 00:09:59) [common]
45 23:49:05.217115 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/kernel/zImage
46 23:49:05.217286 saving as /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/kernel/zImage
47 23:49:05.217412 total size: 11964928 (11 MB)
48 23:49:05.217560 No compression specified
49 23:49:05.353226 progress 0 % (0 MB)
50 23:49:05.360344 progress 5 % (0 MB)
51 23:49:05.367464 progress 10 % (1 MB)
52 23:49:05.374831 progress 15 % (1 MB)
53 23:49:05.382482 progress 20 % (2 MB)
54 23:49:05.389713 progress 25 % (2 MB)
55 23:49:05.494727 progress 30 % (3 MB)
56 23:49:05.502804 progress 35 % (4 MB)
57 23:49:05.511092 progress 40 % (4 MB)
58 23:49:05.519121 progress 45 % (5 MB)
59 23:49:05.526493 progress 50 % (5 MB)
60 23:49:05.627823 progress 55 % (6 MB)
61 23:49:05.638180 progress 60 % (6 MB)
62 23:49:05.646287 progress 65 % (7 MB)
63 23:49:05.654241 progress 70 % (8 MB)
64 23:49:05.662252 progress 75 % (8 MB)
65 23:49:05.761340 progress 80 % (9 MB)
66 23:49:05.771979 progress 85 % (9 MB)
67 23:49:05.780012 progress 90 % (10 MB)
68 23:49:05.788039 progress 95 % (10 MB)
69 23:49:05.894085 progress 100 % (11 MB)
70 23:49:05.894448 11 MB downloaded in 0.68 s (16.85 MB/s)
71 23:49:05.894773 end: 1.2.1 http-download (duration 00:00:01) [common]
73 23:49:05.895287 end: 1.2 download-retry (duration 00:00:01) [common]
74 23:49:05.895457 start: 1.3 download-retry (timeout 00:09:58) [common]
75 23:49:05.895612 start: 1.3.1 http-download (timeout 00:09:58) [common]
76 23:49:06.855938 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
77 23:49:06.856197 saving as /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/dtb/am335x-boneblack.dtb
78 23:49:06.856331 total size: 70308 (0 MB)
79 23:49:06.856455 No compression specified
80 23:49:06.991879 progress 46 % (0 MB)
81 23:49:06.992487 progress 93 % (0 MB)
82 23:49:06.992993 progress 100 % (0 MB)
83 23:49:06.993222 0 MB downloaded in 0.14 s (0.49 MB/s)
84 23:49:06.993496 end: 1.3.1 http-download (duration 00:00:01) [common]
86 23:49:06.994003 end: 1.3 download-retry (duration 00:00:01) [common]
87 23:49:06.994166 start: 1.4 download-retry (timeout 00:09:57) [common]
88 23:49:06.994323 start: 1.4.1 http-download (timeout 00:09:57) [common]
89 23:49:06.994608 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 23:49:06.994742 saving as /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/nfsrootfs/full.rootfs.tar
91 23:49:06.994856 total size: 117747780 (112 MB)
92 23:49:06.994976 Using unxz to decompress xz
93 23:49:07.131601 progress 0 % (0 MB)
94 23:49:07.497988 progress 5 % (5 MB)
95 23:49:07.856732 progress 10 % (11 MB)
96 23:49:08.212245 progress 15 % (16 MB)
97 23:49:08.557825 progress 20 % (22 MB)
98 23:49:08.897338 progress 25 % (28 MB)
99 23:49:09.269838 progress 30 % (33 MB)
100 23:49:09.631463 progress 35 % (39 MB)
101 23:49:09.884458 progress 40 % (44 MB)
102 23:49:10.192331 progress 45 % (50 MB)
103 23:49:10.498070 progress 50 % (56 MB)
104 23:49:10.868255 progress 55 % (61 MB)
105 23:49:11.223185 progress 60 % (67 MB)
106 23:49:11.577673 progress 65 % (73 MB)
107 23:49:11.939123 progress 70 % (78 MB)
108 23:49:12.302541 progress 75 % (84 MB)
109 23:49:12.651575 progress 80 % (89 MB)
110 23:49:13.009922 progress 85 % (95 MB)
111 23:49:13.358896 progress 90 % (101 MB)
112 23:49:13.695655 progress 95 % (106 MB)
113 23:49:14.054653 progress 100 % (112 MB)
114 23:49:14.060528 112 MB downloaded in 7.07 s (15.89 MB/s)
115 23:49:14.060909 end: 1.4.1 http-download (duration 00:00:07) [common]
117 23:49:14.061379 end: 1.4 download-retry (duration 00:00:07) [common]
118 23:49:14.061539 start: 1.5 download-retry (timeout 00:09:50) [common]
119 23:49:14.061696 start: 1.5.1 http-download (timeout 00:09:50) [common]
120 23:49:15.975129 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/modules.tar.xz
121 23:49:15.975478 saving as /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/modules/modules.tar
122 23:49:15.975653 total size: 6919604 (6 MB)
123 23:49:15.975809 Using unxz to decompress xz
124 23:49:16.113820 progress 0 % (0 MB)
125 23:49:16.131670 progress 5 % (0 MB)
126 23:49:16.153595 progress 10 % (0 MB)
127 23:49:16.173777 progress 15 % (1 MB)
128 23:49:16.199133 progress 20 % (1 MB)
129 23:49:16.220783 progress 25 % (1 MB)
130 23:49:16.244097 progress 30 % (2 MB)
131 23:49:16.264776 progress 35 % (2 MB)
132 23:49:16.287848 progress 40 % (2 MB)
133 23:49:16.310596 progress 45 % (3 MB)
134 23:49:16.331485 progress 50 % (3 MB)
135 23:49:16.353890 progress 55 % (3 MB)
136 23:49:16.375149 progress 60 % (3 MB)
137 23:49:16.397966 progress 65 % (4 MB)
138 23:49:16.418830 progress 70 % (4 MB)
139 23:49:16.441813 progress 75 % (4 MB)
140 23:49:16.463159 progress 80 % (5 MB)
141 23:49:16.486611 progress 85 % (5 MB)
142 23:49:16.509384 progress 90 % (5 MB)
143 23:49:16.530138 progress 95 % (6 MB)
144 23:49:16.552960 progress 100 % (6 MB)
145 23:49:16.558115 6 MB downloaded in 0.58 s (11.33 MB/s)
146 23:49:16.558484 end: 1.5.1 http-download (duration 00:00:02) [common]
148 23:49:16.558946 end: 1.5 download-retry (duration 00:00:02) [common]
149 23:49:16.559107 start: 1.6 prepare-tftp-overlay (timeout 00:09:47) [common]
150 23:49:16.559265 start: 1.6.1 extract-nfsrootfs (timeout 00:09:47) [common]
151 23:49:27.147992 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9
152 23:49:27.148325 end: 1.6.1 extract-nfsrootfs (duration 00:00:11) [common]
153 23:49:27.148432 start: 1.6.2 lava-overlay (timeout 00:09:37) [common]
154 23:49:27.148688 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf
155 23:49:27.148815 makedir: /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin
156 23:49:27.148909 makedir: /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/tests
157 23:49:27.148999 makedir: /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/results
158 23:49:27.149096 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-add-keys
159 23:49:27.149255 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-add-sources
160 23:49:27.149387 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-background-process-start
161 23:49:27.149518 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-background-process-stop
162 23:49:27.149688 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-common-functions
163 23:49:27.150326 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-echo-ipv4
164 23:49:27.150566 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-install-packages
165 23:49:27.150762 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-installed-packages
166 23:49:27.150925 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-os-build
167 23:49:27.151090 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-probe-channel
168 23:49:27.151226 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-probe-ip
169 23:49:27.151354 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-target-ip
170 23:49:27.151480 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-target-mac
171 23:49:27.151607 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-target-storage
172 23:49:27.151738 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-test-case
173 23:49:27.151866 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-test-event
174 23:49:27.151992 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-test-feedback
175 23:49:27.152118 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-test-raise
176 23:49:27.152245 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-test-reference
177 23:49:27.152370 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-test-runner
178 23:49:27.152498 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-test-set
179 23:49:27.152624 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-test-shell
180 23:49:27.152756 Updating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-add-keys (debian)
181 23:49:27.194285 Updating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-add-sources (debian)
182 23:49:27.506360 Updating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-install-packages (debian)
183 23:49:27.507031 Updating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-installed-packages (debian)
184 23:49:27.507426 Updating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/bin/lava-os-build (debian)
185 23:49:27.507765 Creating /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/environment
186 23:49:27.507944 LAVA metadata
187 23:49:27.508020 - LAVA_JOB_ID=683458
188 23:49:27.508078 - LAVA_DISPATCHER_IP=192.168.56.76
189 23:49:27.508206 start: 1.6.2.1 ssh-authorize (timeout 00:09:36) [common]
190 23:49:27.508488 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 23:49:27.508582 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:36) [common]
192 23:49:27.508647 skipped lava-vland-overlay
193 23:49:27.508719 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 23:49:27.508794 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:36) [common]
195 23:49:27.508851 skipped lava-multinode-overlay
196 23:49:27.508920 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 23:49:27.508993 start: 1.6.2.4 test-definition (timeout 00:09:36) [common]
198 23:49:27.509060 Loading test definitions
199 23:49:27.509139 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:36) [common]
200 23:49:27.509201 Using /lava-683458 at stage 0
201 23:49:27.509530 uuid=683458_1.6.2.4.1 testdef=None
202 23:49:27.509618 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 23:49:27.509702 start: 1.6.2.4.2 test-overlay (timeout 00:09:36) [common]
204 23:49:27.510194 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 23:49:27.510414 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:36) [common]
207 23:49:27.510982 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 23:49:27.511202 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:36) [common]
210 23:49:30.321152 runner path: /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/0/tests/0_timesync-off test_uuid 683458_1.6.2.4.1
211 23:49:30.405515 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:03) [common]
213 23:49:30.406257 start: 1.6.2.4.5 git-repo-action (timeout 00:09:34) [common]
214 23:49:30.406439 Using /lava-683458 at stage 0
215 23:49:30.406705 Fetching tests from https://github.com/kernelci/test-definitions.git
216 23:49:30.406927 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/0/tests/1_kselftest-dt'
217 23:49:37.355272 Running '/usr/bin/git checkout kernelci.org
218 23:49:37.514537 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 23:49:37.515396 uuid=683458_1.6.2.4.5 testdef=None
220 23:49:37.515623 end: 1.6.2.4.5 git-repo-action (duration 00:00:07) [common]
222 23:49:37.516174 start: 1.6.2.4.6 test-overlay (timeout 00:09:26) [common]
223 23:49:37.518274 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 23:49:37.518764 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:26) [common]
226 23:49:37.521228 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 23:49:37.521826 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:26) [common]
229 23:49:37.524619 runner path: /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/0/tests/1_kselftest-dt test_uuid 683458_1.6.2.4.5
230 23:49:37.524804 BOARD='beaglebone-black'
231 23:49:37.524996 BRANCH='mainline'
232 23:49:37.525151 SKIPFILE='/dev/null'
233 23:49:37.525333 SKIP_INSTALL='True'
234 23:49:37.525489 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
235 23:49:37.525660 TST_CASENAME=''
236 23:49:37.525856 TST_CMDFILES='dt'
237 23:49:37.526366 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 23:49:37.526990 Creating lava-test-runner.conf files
240 23:49:37.527118 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/683458/lava-overlay-h2wki3nf/lava-683458/0 for stage 0
241 23:49:37.527356 - 0_timesync-off
242 23:49:37.527505 - 1_kselftest-dt
243 23:49:37.527739 end: 1.6.2.4 test-definition (duration 00:00:10) [common]
244 23:49:37.527937 start: 1.6.2.5 compress-overlay (timeout 00:09:26) [common]
245 23:49:46.519387 end: 1.6.2.5 compress-overlay (duration 00:00:09) [common]
246 23:49:46.519567 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:17) [common]
247 23:49:46.519648 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 23:49:46.519740 end: 1.6.2 lava-overlay (duration 00:00:19) [common]
249 23:49:46.519820 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:17) [common]
250 23:49:46.617720 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 23:49:46.618049 start: 1.6.4 extract-modules (timeout 00:09:17) [common]
252 23:49:46.618202 extracting modules file /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/modules/modules.tar to /var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9
253 23:49:46.840762 extracting modules file /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/modules/modules.tar to /var/lib/lava/dispatcher/tmp/683458/extract-overlay-ramdisk-rfgylyfj/ramdisk
254 23:49:47.073461 end: 1.6.4 extract-modules (duration 00:00:00) [common]
255 23:49:47.073649 start: 1.6.5 apply-overlay-tftp (timeout 00:09:17) [common]
256 23:49:47.073740 [common] Applying overlay to NFS
257 23:49:47.073811 [common] Applying overlay /var/lib/lava/dispatcher/tmp/683458/compress-overlay-f_xsxvig/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9
258 23:49:48.051673 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 23:49:48.051860 start: 1.6.6 prepare-kernel (timeout 00:09:16) [common]
260 23:49:48.051943 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:16) [common]
261 23:49:48.052030 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 23:49:48.052103 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 23:49:48.052178 start: 1.6.7 configure-preseed-file (timeout 00:09:16) [common]
264 23:49:48.052251 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 23:49:48.052324 start: 1.6.8 compress-ramdisk (timeout 00:09:16) [common]
266 23:49:48.052387 Building ramdisk /var/lib/lava/dispatcher/tmp/683458/extract-overlay-ramdisk-rfgylyfj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/683458/extract-overlay-ramdisk-rfgylyfj/ramdisk
267 23:49:49.046935 >> 78982 blocks
268 23:49:50.930816 Adding RAMdisk u-boot header.
269 23:49:50.931113 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/683458/extract-overlay-ramdisk-rfgylyfj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/683458/extract-overlay-ramdisk-rfgylyfj/ramdisk.cpio.gz.uboot
270 23:49:53.283383 output: Image Name:
271 23:49:53.283633 output: Created: Sat Aug 31 23:49:50 2024
272 23:49:53.283763 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 23:49:53.283876 output: Data Size: 15343185 Bytes = 14983.58 KiB = 14.63 MiB
274 23:49:53.283987 output: Load Address: 00000000
275 23:49:53.284096 output: Entry Point: 00000000
276 23:49:53.284204 output:
277 23:49:53.284446 rename /var/lib/lava/dispatcher/tmp/683458/extract-overlay-ramdisk-rfgylyfj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/ramdisk/ramdisk.cpio.gz.uboot
278 23:49:53.284663 end: 1.6.8 compress-ramdisk (duration 00:00:05) [common]
279 23:49:53.284832 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
280 23:49:53.285031 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:11) [common]
281 23:49:53.285209 No LXC device requested
282 23:49:53.285396 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 23:49:53.285586 start: 1.8 deploy-device-env (timeout 00:09:11) [common]
284 23:49:53.285772 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 23:49:53.285961 Checking files for TFTP limit of 4294967296 bytes.
286 23:49:53.286836 end: 1 tftp-deploy (duration 00:00:49) [common]
287 23:49:53.287085 start: 2 uboot-action (timeout 00:05:00) [common]
288 23:49:53.287282 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 23:49:53.287471 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 23:49:53.287657 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 23:49:53.287955 substitutions:
292 23:49:53.288076 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 23:49:53.288190 - {DTB_ADDR}: 0x88000000
294 23:49:53.288300 - {DTB}: 683458/tftp-deploy-9yflne41/dtb/am335x-boneblack.dtb
295 23:49:53.288410 - {INITRD}: 683458/tftp-deploy-9yflne41/ramdisk/ramdisk.cpio.gz.uboot
296 23:49:53.288520 - {KERNEL_ADDR}: 0x82000000
297 23:49:53.288628 - {KERNEL}: 683458/tftp-deploy-9yflne41/kernel/zImage
298 23:49:53.288737 - {LAVA_MAC}: None
299 23:49:53.288862 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9
300 23:49:53.288977 - {NFS_SERVER_IP}: 192.168.56.76
301 23:49:53.289087 - {PRESEED_CONFIG}: None
302 23:49:53.289195 - {PRESEED_LOCAL}: None
303 23:49:53.289304 - {RAMDISK_ADDR}: 0x83000000
304 23:49:53.289413 - {RAMDISK}: 683458/tftp-deploy-9yflne41/ramdisk/ramdisk.cpio.gz.uboot
305 23:49:53.289522 - {ROOT_PART}: None
306 23:49:53.289629 - {ROOT}: None
307 23:49:53.289740 - {SERVER_IP}: 192.168.56.76
308 23:49:53.289877 - {TEE_ADDR}: 0x83000000
309 23:49:53.290019 - {TEE}: None
310 23:49:53.290158 Parsed boot commands:
311 23:49:53.290296 - setenv autoload no
312 23:49:53.290432 - setenv initrd_high 0xffffffff
313 23:49:53.290568 - setenv fdt_high 0xffffffff
314 23:49:53.290704 - dhcp
315 23:49:53.290847 - setenv serverip 192.168.56.76
316 23:49:53.290980 - tftp 0x82000000 683458/tftp-deploy-9yflne41/kernel/zImage
317 23:49:53.291116 - tftp 0x83000000 683458/tftp-deploy-9yflne41/ramdisk/ramdisk.cpio.gz.uboot
318 23:49:53.291252 - setenv initrd_size ${filesize}
319 23:49:53.291386 - tftp 0x88000000 683458/tftp-deploy-9yflne41/dtb/am335x-boneblack.dtb
320 23:49:53.291521 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 23:49:53.291665 - bootz 0x82000000 0x83000000 0x88000000
322 23:49:53.291852 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 23:49:53.292372 start: 2.3 connect-device (timeout 00:05:00) [common]
325 23:49:53.292531 [common] connect-device Connecting to device using 'telnet conserv3 3000'
326 23:49:53.298313 Setting prompt string to ['lava-test: # ']
327 23:49:53.298865 end: 2.3 connect-device (duration 00:00:00) [common]
328 23:49:53.299059 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 23:49:53.299285 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 23:49:53.299510 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 23:49:53.299878 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-03'
332 23:49:53.313296 >> OK - accepted request
333 23:49:53.314753 Returned 0 in 0 seconds
334 23:49:53.415477 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 23:49:53.416434 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 23:49:53.416783 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 23:49:53.417090 Setting prompt string to ['Hit any key to stop autoboot']
339 23:49:53.417370 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 23:49:53.418185 Trying 192.168.56.22...
341 23:49:53.418389 Connected to conserv3.
342 23:49:53.418593 Escape character is '^]'.
343 23:49:53.418802
344 23:49:53.418999 ser2net port telnet,3000 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
345 23:49:53.419198
346 23:50:02.031917
347 23:50:02.037992 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
348 23:50:02.038387 Trying to boot from MMC1
349 23:50:02.615658
350 23:50:02.615958
351 23:50:02.621198 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
352 23:50:02.621423
353 23:50:02.621585 CPU : AM335X-GP rev 2.0
354 23:50:02.625576 Model: TI AM335x BeagleBone Black
355 23:50:02.625968 DRAM: 512 MiB
356 23:50:06.087033
357 23:50:06.094120 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
358 23:50:06.094376 Trying to boot from MMC1
359 23:50:06.670164
360 23:50:06.670417
361 23:50:06.675758 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
362 23:50:06.675994
363 23:50:06.676124 CPU : AM335X-GP rev 2.0
364 23:50:06.680922 Model: TI AM335x BeagleBone Black
365 23:50:06.681149 DRAM: 512 MiB
366 23:50:08.781116
367 23:50:08.788004 U-Boot SPL 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
368 23:50:08.788219 Trying to boot from MMC1
369 23:50:09.364548
370 23:50:09.364803
371 23:50:09.370052 U-Boot 2023.01-rc4-00025-gb92e12ac87 (Dec 26 2022 - 18:25:48 +0000)
372 23:50:09.370278
373 23:50:09.370408 CPU : AM335X-GP rev 2.0
374 23:50:09.375224 Model: TI AM335x BeagleBone Black
375 23:50:09.375438 DRAM: 512 MiB
376 23:50:09.459664 Core: 160 devices, 18 uclasses, devicetree: separate
377 23:50:09.472951 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
378 23:50:09.874301 NAND: 0 MiB
379 23:50:09.884808 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
380 23:50:09.959136 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
381 23:50:09.979698 <ethaddr> not set. Validating first E-fuse MAC
382 23:50:10.009396 Net: eth2: ethernet@4a100000, eth3: usb_ether
384 23:50:10.068332 Hit any key to stop autoboot: 2
385 23:50:10.068745 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
386 23:50:10.068905 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
387 23:50:10.069023 Setting prompt string to ['=>']
388 23:50:10.069133 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
389 23:50:10.077714 0
390 23:50:10.078214 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
391 23:50:10.078346 Sending with 10 millisecond of delay
393 23:50:11.214867 => setenv autoload no
394 23:50:11.225419 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
395 23:50:11.227071 setenv autoload no
396 23:50:11.227448 Sending with 10 millisecond of delay
398 23:50:13.025856 => setenv initrd_high 0xffffffff
399 23:50:13.036282 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
400 23:50:13.036672 setenv initrd_high 0xffffffff
401 23:50:13.037076 Sending with 10 millisecond of delay
403 23:50:14.653026 => setenv fdt_high 0xffffffff
404 23:50:14.663400 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
405 23:50:14.663767 setenv fdt_high 0xffffffff
406 23:50:14.664158 Sending with 10 millisecond of delay
408 23:50:14.955436 => dhcp
409 23:50:14.965821 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
410 23:50:14.966136 dhcp
411 23:50:14.968457 link up on port 0, speed 100, full duplex
412 23:50:14.968591 BOOTP broadcast 1
413 23:50:15.220560 BOOTP broadcast 2
414 23:50:15.723395 BOOTP broadcast 3
415 23:50:16.725749 BOOTP broadcast 4
416 23:50:18.726447 BOOTP broadcast 5
417 23:50:18.747106 *** Unhandled DHCP Option in OFFER/ACK: 42
418 23:50:18.775704 *** Unhandled DHCP Option in OFFER/ACK: 42
419 23:50:18.781877 DHCP client bound to address 192.168.56.2 (3811 ms)
420 23:50:18.782224 Sending with 10 millisecond of delay
422 23:50:20.583301 => setenv serverip 192.168.56.76
423 23:50:20.593741 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
424 23:50:20.594208 setenv serverip 192.168.56.76
425 23:50:20.594564 Sending with 10 millisecond of delay
427 23:50:24.077745 => tftp 0x82000000 683458/tftp-deploy-9yflne41/kernel/zImage
428 23:50:24.088257 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
429 23:50:24.088760 tftp 0x82000000 683458/tftp-deploy-9yflne41/kernel/zImage
430 23:50:24.088943 link up on port 0, speed 100, full duplex
431 23:50:24.093423 Using ethernet@4a100000 device
432 23:50:24.098915 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
433 23:50:24.106125 Filename '683458/tftp-deploy-9yflne41/kernel/zImage'.
434 23:50:24.106422 Load address: 0x82000000
435 23:50:26.075991 Loading: *################################################## 11.4 MiB
436 23:50:26.076311 5.8 MiB/s
437 23:50:26.076479 done
438 23:50:26.080245 Bytes transferred = 11964928 (b69200 hex)
439 23:50:26.080664 Sending with 10 millisecond of delay
441 23:50:30.529765 => tftp 0x83000000 683458/tftp-deploy-9yflne41/ramdisk/ramdisk.cpio.gz.uboot
442 23:50:30.540241 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
443 23:50:30.540629 tftp 0x83000000 683458/tftp-deploy-9yflne41/ramdisk/ramdisk.cpio.gz.uboot
444 23:50:30.540771 link up on port 0, speed 100, full duplex
445 23:50:30.544883 Using ethernet@4a100000 device
446 23:50:30.550461 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
447 23:50:30.559315 Filename '683458/tftp-deploy-9yflne41/ramdisk/ramdisk.cpio.gz.uboot'.
448 23:50:30.559567 Load address: 0x83000000
449 23:50:32.958580 Loading: *################################################## 14.6 MiB
450 23:50:32.958825 6.1 MiB/s
451 23:50:32.958952 done
452 23:50:32.962743 Bytes transferred = 15343249 (ea1e91 hex)
453 23:50:32.963130 Sending with 10 millisecond of delay
455 23:50:34.823315 => setenv initrd_size ${filesize}
456 23:50:34.833732 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
457 23:50:34.834173 setenv initrd_size ${filesize}
458 23:50:34.834531 Sending with 10 millisecond of delay
460 23:50:38.993166 => tftp 0x88000000 683458/tftp-deploy-9yflne41/dtb/am335x-boneblack.dtb
461 23:50:39.003685 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
462 23:50:39.004108 tftp 0x88000000 683458/tftp-deploy-9yflne41/dtb/am335x-boneblack.dtb
463 23:50:39.004282 link up on port 0, speed 100, full duplex
464 23:50:39.008665 Using ethernet@4a100000 device
465 23:50:39.014360 TFTP from server 192.168.56.76; our IP address is 192.168.56.2
466 23:50:39.024463 Filename '683458/tftp-deploy-9yflne41/dtb/am335x-boneblack.dtb'.
467 23:50:39.024690 Load address: 0x88000000
468 23:50:39.034479 Loading: *################################################## 68.7 KiB
469 23:50:39.034717 5.2 MiB/s
470 23:50:39.042889 done
471 23:50:39.043190 Bytes transferred = 70308 (112a4 hex)
472 23:50:39.043591 Sending with 10 millisecond of delay
474 23:50:52.417331 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
475 23:50:52.428097 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
476 23:50:52.428577 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
477 23:50:52.428976 Sending with 10 millisecond of delay
479 23:50:54.786233 => bootz 0x82000000 0x83000000 0x88000000
480 23:50:54.797035 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
481 23:50:54.797459 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
482 23:50:54.798008 bootz 0x82000000 0x83000000 0x88000000
483 23:50:54.798183 Kernel image @ 0x82000000 [ 0x000000 - 0xb69200 ]
484 23:50:54.798715 ## Loading init Ramdisk from Legacy Image at 83000000 ...
485 23:50:54.804715 Image Name:
486 23:50:54.805018 Created: 2024-08-31 23:49:50 UTC
487 23:50:54.813483 Image Type: ARM Linux RAMDisk Image (uncompressed)
488 23:50:54.813897 Data Size: 15343185 Bytes = 14.6 MiB
489 23:50:54.821028 Load Address: 00000000
490 23:50:54.821383 Entry Point: 00000000
491 23:50:54.996372 Verifying Checksum ... OK
492 23:50:54.996757 ## Flattened Device Tree blob at 88000000
493 23:50:55.002914 Booting using the fdt blob at 0x88000000
494 23:50:55.003302 Working FDT set to 88000000
495 23:50:55.008398 Using Device Tree in place at 88000000, end 880142a3
496 23:50:55.011909 Working FDT set to 88000000
497 23:50:55.025149
498 23:50:55.025537 Starting kernel ...
499 23:50:55.025699
500 23:50:55.026214 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
501 23:50:55.026442 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
502 23:50:55.026623 Setting prompt string to ['Linux version [0-9]']
503 23:50:55.026798 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
504 23:50:55.026974 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
505 23:50:55.853866 [ 0.000000] Booting Linux on physical CPU 0x0
506 23:50:55.859805 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
507 23:50:55.860203 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
508 23:50:55.860406 Setting prompt string to []
509 23:50:55.860594 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
510 23:50:55.860777 Using line separator: #'\n'#
511 23:50:55.860931 No login prompt set.
512 23:50:55.861085 Parsing kernel messages
513 23:50:55.861224 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
514 23:50:55.861503 [login-action] Waiting for messages, (timeout 00:03:57)
515 23:50:55.861669 Waiting using forced prompt support (timeout 00:01:59)
516 23:50:55.873707 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j303495-arm-clang-15-multi-v7-defconfig-5pb5s) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Sat Aug 31 23:07:00 UTC 2024
517 23:50:55.879545 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 23:50:55.884955 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 23:50:55.893895 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 23:50:55.899707 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 23:50:55.905341 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 23:50:55.908102 [ 0.000000] Memory policy: Data cache writeback
523 23:50:55.915069 [ 0.000000] efi: UEFI not found.
524 23:50:55.918579 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 23:50:55.925256 [ 0.000000] Zone ranges:
526 23:50:55.930887 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 23:50:55.936772 [ 0.000000] Normal empty
528 23:50:55.937075 [ 0.000000] HighMem empty
529 23:50:55.939542 [ 0.000000] Movable zone start for each node
530 23:50:55.944994 [ 0.000000] Early memory node ranges
531 23:50:55.951039 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 23:50:55.958292 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 23:50:55.977273 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 23:50:55.981662 [ 0.000000] AM335X ES2.0 (sgx neon)
535 23:50:55.994906 [ 0.000000] percpu: Embedded 17 pages/cpu s40268 r8192 d21172 u69632
536 23:50:56.015150 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.76:/var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 23:50:56.021079 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 23:50:56.032083 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 23:50:56.038096 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 23:50:56.044399 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 23:50:56.074890 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 23:50:56.080907 <6>[ 0.000000] trace event string verifier disabled
543 23:50:56.081297 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 23:50:56.088877 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 23:50:56.094519 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 23:50:56.106200 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 23:50:56.109661 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 23:50:56.125013 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 23:50:56.144167 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 23:50:56.150182 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 23:50:56.254523 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 23:50:56.262883 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 23:50:56.275004 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 23:50:56.283101 <6>[ 0.019222] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 23:50:56.293298 <6>[ 0.034389] Console: colour dummy device 80x30
556 23:50:56.299396 Matched prompt #6: WARNING:
557 23:50:56.299794 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 23:50:56.304908 <3>[ 0.039289] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 23:50:56.307641 <3>[ 0.046367] This ensures that you still see kernel messages. Please
560 23:50:56.313199 <3>[ 0.053093] update your kernel commandline.
561 23:50:56.353764 <6>[ 0.057708] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 23:50:56.359919 <6>[ 0.096231] CPU: Testing write buffer coherency: ok
563 23:50:56.362608 <6>[ 0.101598] CPU0: Spectre v2: using BPIALL workaround
564 23:50:56.368919 <6>[ 0.107066] pid_max: default: 32768 minimum: 301
565 23:50:56.374612 <6>[ 0.112254] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 23:50:56.387194 <6>[ 0.120084] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 23:50:56.393928 <6>[ 0.129429] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 23:50:56.398226 <6>[ 0.136334] Setting up static identity map for 0x80300000 - 0x803000ac
569 23:50:56.405088 <6>[ 0.146056] rcu: Hierarchical SRCU implementation.
570 23:50:56.412236 <6>[ 0.151343] rcu: Max phase no-delay instances is 1000.
571 23:50:56.422092 <6>[ 0.162829] EFI services will not be available.
572 23:50:56.427913 <6>[ 0.168109] smp: Bringing up secondary CPUs ...
573 23:50:56.433628 <6>[ 0.173162] smp: Brought up 1 node, 1 CPU
574 23:50:56.441643 <6>[ 0.177562] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 23:50:56.447516 <6>[ 0.184316] CPU: All CPU(s) started in SVC mode.
576 23:50:56.459849 <6>[ 0.189527] Memory: 405452K/522240K available (17408K kernel code, 2536K rwdata, 6644K rodata, 2048K init, 432K bss, 49584K reserved, 65536K cma-reserved, 0K highmem)
577 23:50:56.464876 <6>[ 0.205776] devtmpfs: initialized
578 23:50:56.489063 <6>[ 0.223949] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 23:50:56.497364 <6>[ 0.232566] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 23:50:56.505500 <6>[ 0.243011] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 23:50:56.516246 <6>[ 0.255301] pinctrl core: initialized pinctrl subsystem
582 23:50:56.527002 <6>[ 0.266293] DMI not present or invalid.
583 23:50:56.533779 <6>[ 0.272178] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 23:50:56.543704 <6>[ 0.281114] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 23:50:56.558567 <6>[ 0.292691] thermal_sys: Registered thermal governor 'step_wise'
586 23:50:56.558879 <6>[ 0.292851] cpuidle: using governor menu
587 23:50:56.587316 <6>[ 0.328308] No ATAGs?
588 23:50:56.592588 <6>[ 0.331040] hw-breakpoint: debug architecture 0x4 unsupported.
589 23:50:56.603060 <6>[ 0.343310] Serial: AMBA PL011 UART driver
590 23:50:56.644127 <6>[ 0.385049] iommu: Default domain type: Translated
591 23:50:56.652347 <6>[ 0.390396] iommu: DMA domain TLB invalidation policy: strict mode
592 23:50:56.670368 <5>[ 0.410833] SCSI subsystem initialized
593 23:50:56.684986 <6>[ 0.420306] usbcore: registered new interface driver usbfs
594 23:50:56.691761 <6>[ 0.426273] usbcore: registered new interface driver hub
595 23:50:56.692118 <6>[ 0.432096] usbcore: registered new device driver usb
596 23:50:56.697320 <6>[ 0.438653] pps_core: LinuxPPS API ver. 1 registered
597 23:50:56.709245 <6>[ 0.444087] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 23:50:56.713376 <6>[ 0.453790] PTP clock support registered
599 23:50:56.752141 <6>[ 0.492496] EDAC MC: Ver: 3.0.0
600 23:50:56.757532 <6>[ 0.496726] scmi_core: SCMI protocol bus registered
601 23:50:56.785719 <6>[ 0.525978] vgaarb: loaded
602 23:50:56.790984 <6>[ 0.529837] clocksource: Switched to clocksource dmtimer
603 23:50:56.839994 <6>[ 0.580738] NET: Registered PF_INET protocol family
604 23:50:56.852764 <6>[ 0.586353] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 23:50:56.859715 <6>[ 0.595398] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 23:50:56.871193 <6>[ 0.604331] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 23:50:56.873679 <6>[ 0.612596] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 23:50:56.885303 <6>[ 0.620883] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 23:50:56.891258 <6>[ 0.628583] TCP: Hash tables configured (established 4096 bind 4096)
610 23:50:56.899884 <6>[ 0.635505] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 23:50:56.905564 <6>[ 0.642546] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 23:50:56.911675 <6>[ 0.650165] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 23:50:56.948915 <6>[ 0.684318] RPC: Registered named UNIX socket transport module.
614 23:50:56.949223 <6>[ 0.690749] RPC: Registered udp transport module.
615 23:50:56.954775 <6>[ 0.695857] RPC: Registered tcp transport module.
616 23:50:56.963199 <6>[ 0.700995] RPC: Registered tcp-with-tls transport module.
617 23:50:56.969092 <6>[ 0.706904] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 23:50:56.975922 <6>[ 0.713825] PCI: CLS 0 bytes, default 64
619 23:50:56.979803 <5>[ 0.719693] Initialise system trusted keyrings
620 23:50:56.998567 <6>[ 0.737829] Trying to unpack rootfs image as initramfs...
621 23:50:57.037124 <6>[ 0.771920] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 23:50:57.041064 <6>[ 0.779395] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 23:50:57.099577 <5>[ 0.840570] NFS: Registering the id_resolver key type
624 23:50:57.105423 <5>[ 0.846160] Key type id_resolver registered
625 23:50:57.111185 <5>[ 0.850837] Key type id_legacy registered
626 23:50:57.119671 <6>[ 0.855279] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 23:50:57.125632 <6>[ 0.862473] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 23:50:57.159797 <5>[ 0.900797] Key type asymmetric registered
629 23:50:57.165678 <5>[ 0.905319] Asymmetric key parser 'x509' registered
630 23:50:57.177268 <6>[ 0.910856] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 23:50:57.177652 <6>[ 0.918746] io scheduler mq-deadline registered
632 23:50:57.182603 <6>[ 0.923723] io scheduler kyber registered
633 23:50:57.187505 <6>[ 0.928173] io scheduler bfq registered
634 23:50:57.556867 <6>[ 1.294033] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
635 23:50:57.596272 <6>[ 1.336899] msm_serial: driver initialized
636 23:50:57.601976 <6>[ 1.341929] SuperH (H)SCI(F) driver initialized
637 23:50:57.608379 <6>[ 1.347074] STMicroelectronics ASC driver initialized
638 23:50:57.612671 <6>[ 1.352747] STM32 USART driver initialized
639 23:50:57.734281 <6>[ 1.474619] brd: module loaded
640 23:50:57.770955 <6>[ 1.511230] loop: module loaded
641 23:50:57.797839 <6>[ 1.537821] CAN device driver interface
642 23:50:57.804599 <6>[ 1.543156] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
643 23:50:57.810317 <6>[ 1.550289] e1000e: Intel(R) PRO/1000 Network Driver
644 23:50:57.817012 <6>[ 1.555673] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
645 23:50:57.822763 <6>[ 1.562129] igb: Intel(R) Gigabit Ethernet Network Driver
646 23:50:57.830443 <6>[ 1.567947] igb: Copyright (c) 2007-2014 Intel Corporation.
647 23:50:57.842121 <6>[ 1.577349] pegasus: Pegasus/Pegasus II USB Ethernet driver
648 23:50:57.847724 <6>[ 1.583522] usbcore: registered new interface driver pegasus
649 23:50:57.853538 <6>[ 1.589650] usbcore: registered new interface driver asix
650 23:50:57.859485 <6>[ 1.595535] usbcore: registered new interface driver ax88179_178a
651 23:50:57.865326 <6>[ 1.602123] usbcore: registered new interface driver cdc_ether
652 23:50:57.871169 <6>[ 1.608423] usbcore: registered new interface driver smsc75xx
653 23:50:57.876887 <6>[ 1.614665] usbcore: registered new interface driver smsc95xx
654 23:50:57.882360 <6>[ 1.620897] usbcore: registered new interface driver net1080
655 23:50:57.888601 <6>[ 1.627018] usbcore: registered new interface driver cdc_subset
656 23:50:57.894168 <6>[ 1.633426] usbcore: registered new interface driver zaurus
657 23:50:57.901455 <6>[ 1.639495] usbcore: registered new interface driver cdc_ncm
658 23:50:57.911506 <6>[ 1.649184] usbcore: registered new interface driver usb-storage
659 23:50:58.010989 <6>[ 1.750098] i2c_dev: i2c /dev entries driver
660 23:50:58.072347 <5>[ 1.805213] cpuidle: enable-method property 'ti,am3352' found operations
661 23:50:58.078133 <6>[ 1.814919] sdhci: Secure Digital Host Controller Interface driver
662 23:50:58.085908 <6>[ 1.821709] sdhci: Copyright(c) Pierre Ossman
663 23:50:58.093122 <6>[ 1.828284] Synopsys Designware Multimedia Card Interface Driver
664 23:50:58.098659 <6>[ 1.836403] sdhci-pltfm: SDHCI platform and OF driver helper
665 23:50:58.170850 <6>[ 1.908167] ledtrig-cpu: registered to indicate activity on CPUs
666 23:50:58.187628 <6>[ 1.921161] usbcore: registered new interface driver usbhid
667 23:50:58.188019 <6>[ 1.927202] usbhid: USB HID core driver
668 23:50:58.231546 <6>[ 1.969946] NET: Registered PF_INET6 protocol family
669 23:50:58.279575 <6>[ 2.020734] Segment Routing with IPv6
670 23:50:58.285495 <6>[ 2.024879] In-situ OAM (IOAM) with IPv6
671 23:50:58.292243 <6>[ 2.029274] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 23:50:58.298359 <6>[ 2.036704] NET: Registered PF_PACKET protocol family
673 23:50:58.303858 <6>[ 2.042262] can: controller area network core
674 23:50:58.309625 <6>[ 2.047088] NET: Registered PF_CAN protocol family
675 23:50:58.310008 <6>[ 2.052316] can: raw protocol
676 23:50:58.315388 <6>[ 2.055640] can: broadcast manager protocol
677 23:50:58.321901 <6>[ 2.060234] can: netlink gateway - max_hops=1
678 23:50:58.328171 <5>[ 2.065736] Key type dns_resolver registered
679 23:50:58.334161 <6>[ 2.070805] ThumbEE CPU extension supported.
680 23:50:58.334467 <5>[ 2.075496] Registering SWP/SWPB emulation handler
681 23:50:58.344451 <3>[ 2.081199] omap_voltage_late_init: Voltage driver support not added
682 23:50:58.419630 <5>[ 2.158332] Loading compiled-in X.509 certificates
683 23:50:58.601199 <6>[ 2.329313] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 23:50:58.608483 <6>[ 2.346056] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 23:50:58.635440 <3>[ 2.370375] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 23:50:58.729620 <3>[ 2.464565] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 23:50:58.821242 <6>[ 2.560614] OMAP GPIO hardware version 0.1
688 23:50:58.842251 <6>[ 2.579605] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 23:50:58.895732 <4>[ 2.632690] at24 2-0054: supply vcc not found, using dummy regulator
690 23:50:58.968427 <4>[ 2.705461] at24 2-0055: supply vcc not found, using dummy regulator
691 23:50:59.029559 <4>[ 2.766568] at24 2-0056: supply vcc not found, using dummy regulator
692 23:50:59.077546 <4>[ 2.814616] at24 2-0057: supply vcc not found, using dummy regulator
693 23:50:59.147086 <6>[ 2.884993] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 23:50:59.229857 <3>[ 2.963619] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 23:50:59.254776 <6>[ 2.984905] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 23:50:59.276156 <4>[ 3.011904] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 23:50:59.334497 <4>[ 3.070278] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 23:50:59.393394 <6>[ 3.130448] omap_rng 48310000.rng: Random Number Generator ver. 20
699 23:50:59.416931 <5>[ 3.157004] random: crng init done
700 23:50:59.504900 <6>[ 3.240573] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 23:50:59.984459 <6>[ 3.723844] Freeing initrd memory: 14984K
702 23:51:00.027515 <6>[ 3.762332] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 23:51:00.033182 <6>[ 3.772558] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
704 23:51:00.044922 <6>[ 3.779900] cpsw-switch 4a100000.switch: ALE Table size 1024
705 23:51:00.050748 <6>[ 3.786315] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
706 23:51:00.062333 <6>[ 3.794454] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
707 23:51:00.069834 <6>[ 3.806091] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5c:d5:d8
708 23:51:00.081734 <5>[ 3.815257] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
709 23:51:00.110395 <3>[ 3.845762] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
710 23:51:00.116118 <6>[ 3.854349] edma 49000000.dma: TI EDMA DMA engine driver
711 23:51:00.188902 <3>[ 3.923499] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
712 23:51:00.202618 <6>[ 3.937942] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
713 23:51:00.221674 <3>[ 3.960179] l3-aon-clkctrl:0000:0: failed to disable
714 23:51:00.255736 <6>[ 3.991046] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
715 23:51:00.261372 <6>[ 4.000521] printk: legacy console [ttyS0] enabled
716 23:51:00.266998 <6>[ 4.000521] printk: legacy console [ttyS0] enabled
717 23:51:00.272832 <6>[ 4.010838] printk: legacy bootconsole [omap8250] disabled
718 23:51:00.278526 <6>[ 4.010838] printk: legacy bootconsole [omap8250] disabled
719 23:51:00.336143 <4>[ 4.070541] tps65217-pmic: Failed to locate of_node [id: -1]
720 23:51:00.339763 <4>[ 4.077940] tps65217-bl: Failed to locate of_node [id: -1]
721 23:51:00.356315 <6>[ 4.097673] tps65217 0-0024: TPS65217 ID 0xe version 1.2
722 23:51:00.374919 <6>[ 4.104677] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
723 23:51:00.386481 <6>[ 4.118441] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
724 23:51:00.392269 <6>[ 4.130337] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
725 23:51:00.416294 <6>[ 4.151929] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
726 23:51:00.422064 <6>[ 4.161097] sdhci-omap 48060000.mmc: Got CD GPIO
727 23:51:00.430216 <4>[ 4.166221] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
728 23:51:00.445100 <4>[ 4.179420] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
729 23:51:00.451543 <4>[ 4.188754] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
730 23:51:00.461457 <4>[ 4.197532] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
731 23:51:00.558281 <6>[ 4.294974] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
732 23:51:00.596863 <6>[ 4.332757] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
733 23:51:00.620028 <6>[ 4.354921] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 23:51:00.626505 <6>[ 4.363812] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
735 23:51:00.677353 <6>[ 4.409103] mmc0: new high speed SDHC card at address 0001
736 23:51:00.677744 <6>[ 4.416593] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
737 23:51:00.684594 <6>[ 4.425229] mmcblk0: p1
738 23:51:00.692157 <6>[ 4.428770] mmc1: new high speed MMC card at address 0001
739 23:51:00.697467 <6>[ 4.436630] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
740 23:51:00.705906 <6>[ 4.446543] mmcblk1:
741 23:51:00.713687 <6>[ 4.449678] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
742 23:51:00.721144 <6>[ 4.457131] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
743 23:51:00.727201 <6>[ 4.464173] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
744 23:51:00.738145 <6>[ 4.471173] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
745 23:51:02.855520 <6>[ 6.590878] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 23:51:08.818008 <5>[ 6.639889] Sending DHCP requests ..., OK
747 23:51:08.829346 <6>[ 12.564411] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.2
748 23:51:08.829594 <6>[ 12.572830] IP-Config: Complete:
749 23:51:08.840643 <6>[ 12.576366] device=eth0, hwaddr=90:59:af:5c:d5:d8, ipaddr=192.168.56.2, mask=255.255.255.0, gw=192.168.56.254
750 23:51:08.851997 <6>[ 12.587145] host=192.168.56.2, domain=mayfield.sirena.org.uk, nis-domain=(none)
751 23:51:08.857625 <6>[ 12.595272] bootserver=192.168.56.254, rootserver=192.168.56.76, rootpath=
752 23:51:08.863268 <6>[ 12.595306] nameserver0=192.168.56.254
753 23:51:08.869990 <6>[ 12.607479] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
754 23:51:08.876118 <6>[ 12.615135] clk: Disabling unused clocks
755 23:51:08.880564 <6>[ 12.619747] PM: genpd: Disabling unused power domains
756 23:51:08.899233 <6>[ 12.637689] Freeing unused kernel image (initmem) memory: 2048K
757 23:51:08.906645 <6>[ 12.647419] Run /init as init process
758 23:51:08.929527 Loading, please wait...
759 23:51:09.005942 Starting systemd-udevd version 252.22-1~deb12u1
760 23:51:12.026488 <4>[ 15.761307] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 23:51:12.246625 <4>[ 15.981377] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 23:51:12.407010 <6>[ 16.149295] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
763 23:51:12.418164 <6>[ 16.155189] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
764 23:51:12.561651 <6>[ 16.302461] hub 1-0:1.0: USB hub found
765 23:51:12.608823 <6>[ 16.349460] hub 1-0:1.0: 1 port detected
766 23:51:12.723221 <6>[ 16.463575] tda998x 0-0070: found TDA19988
767 23:51:15.560105 Begin: Loading essential drivers ... done.
768 23:51:15.565546 Begin: Running /scripts/init-premount ... done.
769 23:51:15.571149 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 23:51:15.581597 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 23:51:15.593223 Device /sys/class/net/eth0 found
772 23:51:15.593498 done.
773 23:51:15.672506 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 23:51:15.740985 IP-Config: eth0 hardware address 90:59:af:5c:d5:d8 mtu 1500 DHCP
775 23:51:15.826685 IP-Config: eth0 complete (dhcp from 192.168.56.254):
776 23:51:15.837839 address: 192.168.56.2 broadcast: 192.168.56.255 netmask: 255.255.255.0
777 23:51:15.843704 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
778 23:51:15.849117 domain : mayfield.sirena.org.uk
779 23:51:15.854666 rootserver: 192.168.56.254 rootpath:
780 23:51:15.854924 filename :
781 23:51:15.926263 done.
782 23:51:15.949707 Begin: Running /scripts/nfs-bottom ... done.
783 23:51:16.015648 Begin: Running /scripts/init-bottom ... done.
784 23:51:17.371090 <30>[ 21.108872] systemd[1]: System time before build time, advancing clock.
785 23:51:17.583946 <30>[ 21.295545] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
786 23:51:17.592837 <30>[ 21.332475] systemd[1]: Detected architecture arm.
787 23:51:17.605029
788 23:51:17.605278 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
789 23:51:17.605409
790 23:51:17.641705 <30>[ 21.380184] systemd[1]: Hostname set to <debian-bookworm-armhf>.
791 23:51:19.729684 <30>[ 23.467955] systemd[1]: Queued start job for default target graphical.target.
792 23:51:19.747581 <30>[ 23.482999] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
793 23:51:19.754713 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
794 23:51:19.784970 <30>[ 23.522723] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
795 23:51:19.795838 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
796 23:51:19.830946 <30>[ 23.565786] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
797 23:51:19.838286 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
798 23:51:19.875608 <30>[ 23.611662] systemd[1]: Created slice user.slice - User and Session Slice.
799 23:51:19.881378 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
800 23:51:19.922802 <30>[ 23.652174] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
801 23:51:19.928146 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
802 23:51:19.965898 <30>[ 23.700959] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
803 23:51:19.977241 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
804 23:51:20.015980 <30>[ 23.740870] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
805 23:51:20.022427 <30>[ 23.761429] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
806 23:51:20.029982 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
807 23:51:20.063909 <30>[ 23.800254] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
808 23:51:20.071405 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
809 23:51:20.105024 <30>[ 23.840831] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
810 23:51:20.113456 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
811 23:51:20.146082 <30>[ 23.881632] systemd[1]: Reached target paths.target - Path Units.
812 23:51:20.150463 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
813 23:51:20.184435 <30>[ 23.920432] systemd[1]: Reached target remote-fs.target - Remote File Systems.
814 23:51:20.190790 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
815 23:51:20.225500 <30>[ 23.960955] systemd[1]: Reached target slices.target - Slice Units.
816 23:51:20.229968 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
817 23:51:20.264409 <30>[ 24.000595] systemd[1]: Reached target swap.target - Swaps.
818 23:51:20.267804 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
819 23:51:20.304919 <30>[ 24.040657] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
820 23:51:20.312690 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
821 23:51:20.345430 <30>[ 24.081347] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
822 23:51:20.353531 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
823 23:51:20.452567 <30>[ 24.184532] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
824 23:51:20.466317 <30>[ 24.202187] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
825 23:51:20.474182 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
826 23:51:20.505533 <30>[ 24.243855] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
827 23:51:20.519318 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
828 23:51:20.557814 <30>[ 24.293513] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
829 23:51:20.565572 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
830 23:51:20.599066 <30>[ 24.334723] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
831 23:51:20.604682 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
832 23:51:20.648363 <30>[ 24.383529] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
833 23:51:20.656051 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
834 23:51:20.691316 <30>[ 24.421318] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
835 23:51:20.709754 <30>[ 24.439643] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
836 23:51:20.754645 <30>[ 24.492390] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
837 23:51:20.777634 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
838 23:51:20.846136 <30>[ 24.583773] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
839 23:51:20.859662 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
840 23:51:20.935219 <30>[ 24.670950] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
841 23:51:20.964409 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
842 23:51:21.028457 <30>[ 24.764747] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
843 23:51:21.054516 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
844 23:51:21.118442 <30>[ 24.855012] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
845 23:51:21.144877 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
846 23:51:21.207569 <30>[ 24.944808] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
847 23:51:21.223857 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
848 23:51:21.255510 <30>[ 24.991522] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
849 23:51:21.284346 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
850 23:51:21.345608 <30>[ 25.082736] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
851 23:51:21.368078 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
852 23:51:21.426882 <30>[ 25.163887] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
853 23:51:21.453366 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
854 23:51:21.491507 <28>[ 25.222064] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
855 23:51:21.500008 <28>[ 25.236241] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
856 23:51:21.550354 <30>[ 25.287931] systemd[1]: Starting systemd-journald.service - Journal Service...
857 23:51:21.573916 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
858 23:51:21.656113 <30>[ 25.392967] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
859 23:51:21.668524 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
860 23:51:21.694852 <30>[ 25.431904] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
861 23:51:21.746055 Starting [0;1;39msystemd-network-g… units from Kernel command line...
862 23:51:21.785749 <30>[ 25.521306] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
863 23:51:21.828712 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
864 23:51:21.901072 <30>[ 25.636936] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
865 23:51:21.973259 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
866 23:51:21.992356 <30>[ 25.729519] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
867 23:51:22.084358 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
868 23:51:22.126646 <30>[ 25.863601] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
869 23:51:22.183819 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
870 23:51:22.218147 <30>[ 25.954108] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
871 23:51:22.246452 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
872 23:51:22.355975 <30>[ 26.093560] systemd[1]: modprobe@configfs.service: Deactivated successfully.
873 23:51:22.385052 <30>[ 26.121555] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
874 23:51:22.413314 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
875 23:51:22.424758 <30>[ 26.162833] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
876 23:51:22.455237 <30>[ 26.191681] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
877 23:51:22.484161 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
878 23:51:22.515898 <30>[ 26.251714] systemd[1]: Started systemd-journald.service - Journal Service.
879 23:51:22.522784 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
880 23:51:22.550906 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
881 23:51:22.589634 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
882 23:51:22.635851 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
883 23:51:22.680082 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
884 23:51:22.716762 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
885 23:51:22.757029 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
886 23:51:22.796620 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
887 23:51:22.834385 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
888 23:51:22.893903 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
889 23:51:22.955302 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
890 23:51:23.046199 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
891 23:51:23.140111 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
892 23:51:23.227170 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
893 23:51:23.256045 <46>[ 26.992720] systemd-journald[164]: Received client request to flush runtime journal.
894 23:51:23.339000 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
895 23:51:23.424887 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
896 23:51:24.296735 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
897 23:51:24.351758 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
898 23:51:24.435936 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
899 23:51:25.144585 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
900 23:51:25.296248 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
901 23:51:25.343309 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
902 23:51:25.373169 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
903 23:51:25.464549 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
904 23:51:25.506869 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
905 23:51:26.430857 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
906 23:51:26.544271 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
907 23:51:27.090758 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
908 23:51:28.589386 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
909 23:51:29.330495 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
910 23:51:29.693929 <5>[ 33.431086] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 23:51:30.979391 <5>[ 34.718748] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
912 23:51:31.004010 <5>[ 34.742340] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
913 23:51:31.033406 <4>[ 34.770207] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
914 23:51:31.038050 <6>[ 34.779187] cfg80211: failed to load regulatory.db
915 23:51:31.677901 [[0m[0;31m* [0m] Job systemd-networkd.service/start running (11s / 1min 36s)
916 23:51:31.830627 M
[K[[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
917 23:51:38.973598 [K[[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
918 23:51:39.011811 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
919 23:51:39.044837 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
920 23:51:39.136087 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
921 23:51:39.205945 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
922 23:51:39.254823 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
923 23:51:39.285132 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
924 23:51:39.428535 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
925 23:51:39.485579 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
926 23:51:39.522170 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
927 23:51:39.584256 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
928 23:51:39.623857 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
929 23:51:39.651145 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
930 23:51:39.833966 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
931 23:51:40.157906 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
932 23:51:40.203873 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
933 23:51:40.234735 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
934 23:51:40.268593 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
935 23:51:40.414218 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
936 23:51:40.574444 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
937 23:51:40.608260 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
938 23:51:40.703643 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
939 23:51:40.758710 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
940 23:51:40.796208 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 23:51:40.850030 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 23:51:40.883389 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 23:51:40.915578 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 23:51:41.013818 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 23:51:41.077861 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 23:51:41.286296 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 23:51:41.394069 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 23:51:41.452628 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 23:51:41.508539 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 23:51:41.526548 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
951 23:51:41.633868 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
952 23:51:41.734867 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
953 23:51:41.784841 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
954 23:51:41.855734 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
955 23:51:41.884209 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
956 23:51:42.006658 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
957 23:51:42.123440 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
958 23:51:42.531079 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
959 23:51:42.788974 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
960 23:51:42.826816 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
961 23:51:42.879484 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
962 23:51:42.978014 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
963 23:51:43.164272 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
964 23:51:43.307959
965 23:51:43.312411 Debian GNU/Linux 12 debian-worm-armhf login: root (automatic login)
966 23:51:43.312711
967 23:51:43.684996 Linux debian-bookworm-armhf 6.11.0-rc5 #1 SMP Sat Aug 31 23:07:00 UTC 2024 armv7l
968 23:51:43.685301
969 23:51:43.690741 The programs included with the Debian GNU/Linux system are free software;
970 23:51:43.694159 the exact distribution terms for each program are described in the
971 23:51:43.699595 individual files in /usr/share/doc/*/copyright.
972 23:51:43.699833
973 23:51:43.705323 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
974 23:51:43.709846 permitted by applicable law.
975 23:51:48.598283 Unable to match end of the kernel message
977 23:51:48.598904 Setting prompt string to ['/ #']
978 23:51:48.599129 end: 2.4.4.1 login-action (duration 00:00:53) [common]
980 23:51:48.599613 end: 2.4.4 auto-login-action (duration 00:00:54) [common]
981 23:51:48.599809 start: 2.4.5 expect-shell-connection (timeout 00:03:05) [common]
982 23:51:48.599967 Setting prompt string to ['/ #']
983 23:51:48.600110 Forcing a shell prompt, looking for ['/ #']
985 23:51:48.650751 / #
986 23:51:48.651172 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
987 23:51:48.651369 Waiting using forced prompt support (timeout 00:02:30)
988 23:51:48.655269
989 23:51:48.662490 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
990 23:51:48.662849 start: 2.4.6 export-device-env (timeout 00:03:05) [common]
991 23:51:48.663045 Sending with 10 millisecond of delay
993 23:51:53.668365 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9'
994 23:51:53.678871 export NFS_ROOTFS='/var/lib/<46>[ 54.108491] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
995 23:51:53.679103 <46>[ 54.152677] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
996 23:51:53.679235 lava/dispatcher/tmp/683458/extract-nfsrootfs-k_o_h4e9'
997 23:51:53.681164 Sending with 10 millisecond of delay
999 23:51:55.907577 / # export NFS_SERVER_IP='192.168.56.76'
1000 23:51:55.918487 export NFS_SERVER_IP='192.168.56.76'
1001 23:51:55.919497 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1002 23:51:55.919763 end: 2.4 uboot-commands (duration 00:02:03) [common]
1003 23:51:55.920000 end: 2 uboot-action (duration 00:02:03) [common]
1004 23:51:55.920224 start: 3 lava-test-retry (timeout 00:07:08) [common]
1005 23:51:55.920453 start: 3.1 lava-test-shell (timeout 00:07:08) [common]
1006 23:51:55.920632 Using namespace: common
1008 23:51:56.021484 / # #
1009 23:51:56.022038 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1010 23:51:56.026948 #
1011 23:51:56.033063 Using /lava-683458
1013 23:51:56.134133 / # export SHELL=/bin/bash
1014 23:51:56.139461 export SHELL=/bin/bash
1016 23:51:56.246867 / # . /lava-683458/environment
1017 23:51:56.251887 . /lava-683458/environment
1019 23:51:56.365406 / # /lava-683458/bin/lava-test-runner /lava-683458/0
1020 23:51:56.365946 Test shell timeout: 10s (minimum of the action and connection timeout)
1021 23:51:56.369588 /lava-683458/bin/lava-test-runner /lava-683458/0
1022 23:51:58.472294 + export TESTRUN_ID=0_timesync-off
1023 23:51:58.480355 + TESTRUN_ID=0_timesync-off
1024 23:51:58.480594 + cd /lava-683458/0/tests/0_timesync-off
1025 23:51:58.480768 ++ cat uuid
1026 23:51:58.511853 + UUID=683458_1.6.2.4.1
1027 23:51:58.512134 + set +x
1028 23:51:58.520326 <LAVA_SIGNAL_STARTRUN 0_timesync-off 683458_1.6.2.4.1>
1029 23:51:58.520566 + systemctl stop systemd-timesyncd
1030 23:51:58.520960 Received signal: <STARTRUN> 0_timesync-off 683458_1.6.2.4.1
1031 23:51:58.521130 Starting test lava.0_timesync-off (683458_1.6.2.4.1)
1032 23:51:58.521337 Skipping test definition patterns.
1033 23:51:58.942723 + set +x
1034 23:51:58.943000 <LAVA_SIGNAL_ENDRUN 0_timesync-off 683458_1.6.2.4.1>
1035 23:51:58.943376 Received signal: <ENDRUN> 0_timesync-off 683458_1.6.2.4.1
1036 23:51:58.943564 Ending use of test pattern.
1037 23:51:58.943712 Ending test lava.0_timesync-off (683458_1.6.2.4.1), duration 0.42
1039 23:51:59.133514 + export TESTRUN_ID=1_kselftest-dt
1040 23:51:59.141433 + TESTRUN_ID=1_kselftest-dt
1041 23:51:59.141689 + cd /lava-683458/0/tests/1_kselftest-dt
1042 23:51:59.141883 ++ cat uuid
1043 23:51:59.157386 + UUID=683458_1.6.2.4.5
1044 23:51:59.157678 + set +x
1045 23:51:59.163088 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 683458_1.6.2.4.5>
1046 23:51:59.163362 + cd ./automated/linux/kselftest/
1047 23:51:59.163748 Received signal: <STARTRUN> 1_kselftest-dt 683458_1.6.2.4.5
1048 23:51:59.163912 Starting test lava.1_kselftest-dt (683458_1.6.2.4.5)
1049 23:51:59.164099 Skipping test definition patterns.
1050 23:51:59.191007 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1051 23:51:59.282576 INFO: install_deps skipped
1052 23:51:59.926682 --2024-08-31 23:51:59-- http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1053 23:51:59.959793 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1054 23:52:00.098446 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1055 23:52:00.233955 HTTP request sent, awaiting response... 200 OK
1056 23:52:00.234225 Length: 2274528 (2.2M) [application/octet-stream]
1057 23:52:00.239370 Saving to: 'kselftest_armhf.tar.gz'
1058 23:52:00.239600
1059 23:52:01.377850
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 2%[ ] 49.92K 186KB/s
kselftest_armhf.tar 9%[> ] 218.67K 400KB/s
kselftest_armhf.tar 38%[======> ] 858.95K 1.12MB/s
kselftest_armhf.tar 56%[==========> ] 1.23M 1.23MB/s
kselftest_armhf.tar 100%[===================>] 2.17M 1.90MB/s in 1.1s
1060 23:52:01.378186
1061 23:52:01.798168 2024-08-31 23:52:01 (1.90 MB/s) - 'kselftest_armhf.tar.gz' saved [2274528/2274528]
1062 23:52:01.798412
1063 23:55:05.003572 skiplist:
1064 23:55:05.003940 ========================================
1065 23:55:05.009202 ========================================
1066 23:55:05.443387 dt:test_unprobed_devices.sh
1067 23:55:05.486722 ============== Tests to run ===============
1068 23:55:05.494528 dt:test_unprobed_devices.sh
1069 23:55:05.498532 ===========End Tests to run ===============
1070 23:55:05.513117 shardfile-dt pass
1071 23:55:05.762170 <12>[ 249.511436] kselftest: Running tests in dt
1072 23:55:05.792818 TAP version 13
1073 23:55:05.816370 1..1
1074 23:55:05.871038 # timeout set to 45
1075 23:55:05.871352 # selftests: dt: test_unprobed_devices.sh
1076 23:55:06.604122 # TAP version 13
1077 23:55:19.039802 # 1..255
1078 23:55:19.248150 # ok 1 / # SKIP
1079 23:55:19.265927 # ok 2 /clk_mcasp0
1080 23:55:19.339394 # ok 3 /clk_mcasp0_fixed # SKIP
1081 23:55:19.408790 # ok 4 /cpus/cpu@0 # SKIP
1082 23:55:19.480020 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1083 23:55:19.500124 # ok 6 /fixedregulator0
1084 23:55:19.524320 # ok 7 /leds
1085 23:55:19.540208 # ok 8 /ocp
1086 23:55:19.565263 # ok 9 /ocp/interconnect@44c00000
1087 23:55:19.590486 # ok 10 /ocp/interconnect@44c00000/segment@0
1088 23:55:19.616266 # ok 11 /ocp/interconnect@44c00000/segment@100000
1089 23:55:19.636697 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1090 23:55:19.712391 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1091 23:55:19.732982 # ok 14 /ocp/interconnect@44c00000/segment@200000
1092 23:55:19.751116 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1093 23:55:19.856139 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1094 23:55:19.936175 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1095 23:55:20.011086 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1096 23:55:20.095714 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1097 23:55:20.175812 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1098 23:55:20.248344 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1099 23:55:20.328934 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1100 23:55:20.396905 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1101 23:55:20.476563 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1102 23:55:20.555818 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1103 23:55:20.626451 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1104 23:55:20.708654 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1105 23:55:20.788323 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1106 23:55:20.863918 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1107 23:55:20.928920 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1108 23:55:21.018531 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1109 23:55:21.088557 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1110 23:55:21.167828 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1111 23:55:21.246479 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1112 23:55:21.323834 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1113 23:55:21.402202 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1114 23:55:21.477421 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1115 23:55:21.554229 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1116 23:55:21.620497 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1117 23:55:21.697321 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1118 23:55:21.765398 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1119 23:55:21.846066 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1120 23:55:21.918381 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1121 23:55:21.991369 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1122 23:55:22.073521 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1123 23:55:22.150292 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1124 23:55:22.228547 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1125 23:55:22.307409 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1126 23:55:22.389133 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1127 23:55:22.459753 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1128 23:55:22.537568 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1129 23:55:22.610271 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1130 23:55:22.673186 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1131 23:55:22.748023 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1132 23:55:22.823530 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1133 23:55:22.886138 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1134 23:55:22.966726 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1135 23:55:23.037244 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1136 23:55:23.110664 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1137 23:55:23.185419 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1138 23:55:23.248233 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1139 23:55:23.325497 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1140 23:55:23.400442 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1141 23:55:23.474352 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1142 23:55:23.546754 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1143 23:55:23.620172 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1144 23:55:23.702621 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1145 23:55:23.777867 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1146 23:55:23.854385 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1147 23:55:23.925754 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1148 23:55:24.006513 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1149 23:55:24.073740 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1150 23:55:24.156208 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1151 23:55:24.227434 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1152 23:55:24.308361 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1153 23:55:24.375871 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1154 23:55:24.451683 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1155 23:55:24.534433 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1156 23:55:24.610054 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1157 23:55:24.688435 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1158 23:55:24.758439 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1159 23:55:24.839338 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1160 23:55:24.909596 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1161 23:55:24.983699 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1162 23:55:25.055657 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1163 23:55:25.120813 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1164 23:55:25.204256 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1165 23:55:25.269084 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1166 23:55:25.350184 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1167 23:55:25.417097 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1168 23:55:25.486705 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1169 23:55:25.567552 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1170 23:55:25.632523 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1171 23:55:25.715688 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1172 23:55:25.733166 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1173 23:55:25.762205 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1174 23:55:25.776435 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1175 23:55:25.804345 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1176 23:55:25.825155 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1177 23:55:25.853481 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1178 23:55:25.877067 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1179 23:55:25.894110 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1180 23:55:26.003400 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1181 23:55:26.024085 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1182 23:55:26.046287 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1183 23:55:26.077613 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1184 23:55:26.178083 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1185 23:55:26.256062 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1186 23:55:26.326164 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1187 23:55:26.391980 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1188 23:55:26.469920 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1189 23:55:26.541142 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1190 23:55:26.608001 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1191 23:55:26.677836 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1192 23:55:26.754954 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1193 23:55:26.819687 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1194 23:55:26.898933 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1195 23:55:26.970740 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1196 23:55:27.037323 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1197 23:55:27.116682 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1198 23:55:27.189605 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1199 23:55:27.262202 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1200 23:55:27.283472 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1201 23:55:27.345845 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1202 23:55:27.419511 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1203 23:55:27.491351 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1204 23:55:27.515242 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1205 23:55:27.578711 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1206 23:55:27.605025 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1207 23:55:27.672190 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1208 23:55:27.701726 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1209 23:55:27.718303 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1210 23:55:27.743244 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1211 23:55:27.772749 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1212 23:55:27.795124 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1213 23:55:27.818417 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1214 23:55:27.843673 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1215 23:55:27.867357 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1216 23:55:27.891437 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1217 23:55:27.964696 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1218 23:55:28.034013 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1219 23:55:28.055379 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1220 23:55:28.122775 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1221 23:55:28.196924 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1222 23:55:28.289894 # not ok 145 /ocp/interconnect@47c00000
1223 23:55:28.364156 # not ok 146 /ocp/interconnect@47c00000/segment@0
1224 23:55:28.384182 # ok 147 /ocp/interconnect@48000000
1225 23:55:28.407220 # ok 148 /ocp/interconnect@48000000/segment@0
1226 23:55:28.431680 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1227 23:55:28.455257 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1228 23:55:28.473512 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1229 23:55:28.501969 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1230 23:55:28.521958 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1231 23:55:28.552526 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1232 23:55:28.567373 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1233 23:55:28.637050 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1234 23:55:28.716088 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1235 23:55:28.730300 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1236 23:55:28.760295 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1237 23:55:28.782902 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1238 23:55:28.809946 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1239 23:55:28.823997 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1240 23:55:28.854164 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1241 23:55:28.876549 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1242 23:55:28.902778 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1243 23:55:28.925020 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1244 23:55:28.944743 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1245 23:55:28.971926 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1246 23:55:28.992511 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1247 23:55:29.017851 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1248 23:55:29.040872 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1249 23:55:29.065341 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1250 23:55:29.086826 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1251 23:55:29.116082 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1252 23:55:29.132721 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1253 23:55:29.162013 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1254 23:55:29.176092 # ok 177 /ocp/interconnect@48000000/segment@100000
1255 23:55:29.203662 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1256 23:55:29.225909 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1257 23:55:29.301501 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1258 23:55:29.374180 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1259 23:55:29.440622 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1260 23:55:29.513831 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1261 23:55:29.532431 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1262 23:55:29.555755 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1263 23:55:29.574260 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1264 23:55:29.602082 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1265 23:55:29.625715 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1266 23:55:29.645049 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1267 23:55:29.671799 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1268 23:55:29.696561 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1269 23:55:29.713477 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1270 23:55:29.741288 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1271 23:55:29.762287 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1272 23:55:29.788607 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1273 23:55:29.810568 # ok 196 /ocp/interconnect@48000000/segment@200000
1274 23:55:29.827853 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1275 23:55:29.899921 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1276 23:55:29.923449 # ok 199 /ocp/interconnect@48000000/segment@300000
1277 23:55:29.948597 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1278 23:55:29.974668 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1279 23:55:29.990704 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1280 23:55:30.014067 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1281 23:55:30.041393 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1282 23:55:30.065356 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1283 23:55:30.131830 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1284 23:55:30.158020 # ok 207 /ocp/interconnect@4a000000
1285 23:55:30.174095 # ok 208 /ocp/interconnect@4a000000/segment@0
1286 23:55:30.201811 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1287 23:55:30.229560 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1288 23:55:30.256641 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1289 23:55:30.277929 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1290 23:55:30.349811 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1291 23:55:30.449986 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1292 23:55:30.528703 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1293 23:55:30.631843 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1294 23:55:30.703865 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1295 23:55:30.772509 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1296 23:55:30.869536 # not ok 219 /ocp/interconnect@4b140000
1297 23:55:30.939749 # not ok 220 /ocp/interconnect@4b140000/segment@0
1298 23:55:31.009951 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1299 23:55:31.025802 # ok 222 /ocp/target-module@40300000
1300 23:55:31.051138 # ok 223 /ocp/target-module@40300000/sram@0
1301 23:55:31.122379 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1302 23:55:31.197229 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1303 23:55:31.216410 # ok 226 /ocp/target-module@47400000
1304 23:55:31.240353 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1305 23:55:31.260519 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1306 23:55:31.282158 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1307 23:55:31.308011 # ok 230 /ocp/target-module@47400000/usb@1400
1308 23:55:31.330033 # ok 231 /ocp/target-module@47400000/usb@1800
1309 23:55:31.350482 # ok 232 /ocp/target-module@47810000
1310 23:55:31.369846 # ok 233 /ocp/target-module@49000000
1311 23:55:31.397850 # ok 234 /ocp/target-module@49000000/dma@0
1312 23:55:31.418477 # ok 235 /ocp/target-module@49800000
1313 23:55:31.440942 # ok 236 /ocp/target-module@49800000/dma@0
1314 23:55:31.460582 # ok 237 /ocp/target-module@49900000
1315 23:55:31.488320 # ok 238 /ocp/target-module@49900000/dma@0
1316 23:55:31.509434 # ok 239 /ocp/target-module@49a00000
1317 23:55:31.530390 # ok 240 /ocp/target-module@49a00000/dma@0
1318 23:55:31.549818 # ok 241 /ocp/target-module@4c000000
1319 23:55:31.619863 # not ok 242 /ocp/target-module@4c000000/emif@0
1320 23:55:31.641614 # ok 243 /ocp/target-module@50000000
1321 23:55:31.668456 # ok 244 /ocp/target-module@53100000
1322 23:55:31.740529 # not ok 245 /ocp/target-module@53100000/sham@0
1323 23:55:31.759185 # ok 246 /ocp/target-module@53500000
1324 23:55:31.829632 # not ok 247 /ocp/target-module@53500000/aes@0
1325 23:55:31.851149 # ok 248 /ocp/target-module@56000000
1326 23:55:31.954466 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1327 23:55:32.028096 # ok 250 /opp-table # SKIP
1328 23:55:32.096063 # ok 251 /soc # SKIP
1329 23:55:32.117751 # ok 252 /sound
1330 23:55:32.137624 # ok 253 /target-module@4b000000
1331 23:55:32.167872 # ok 254 /target-module@4b000000/target-module@140000
1332 23:55:32.184159 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1333 23:55:32.192627 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1334 23:55:32.199562 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1335 23:55:49.730115 dt_test_unprobed_devices_sh_ skip
1336 23:55:49.735520 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1337 23:55:49.741180 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1338 23:55:49.741403 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1339 23:55:49.746685 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1340 23:55:49.752337 dt_test_unprobed_devices_sh_fixedregulator0 pass
1341 23:55:49.757948 dt_test_unprobed_devices_sh_leds pass
1342 23:55:49.758163 dt_test_unprobed_devices_sh_ocp pass
1343 23:55:49.763514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1344 23:55:49.769142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1345 23:55:49.774707 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1346 23:55:49.785977 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1347 23:55:49.791713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1348 23:55:49.797266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1349 23:55:49.808317 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1350 23:55:49.814019 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1351 23:55:49.825350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1352 23:55:49.836368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1353 23:55:49.847888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1354 23:55:49.853342 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1355 23:55:49.864375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1356 23:55:49.875615 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1357 23:55:49.886910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1358 23:55:49.898168 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1359 23:55:49.903783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1360 23:55:49.914793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1361 23:55:49.926096 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1362 23:55:49.937280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1363 23:55:49.948484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1364 23:55:49.953956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1365 23:55:49.965160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1366 23:55:49.976385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1367 23:55:49.987618 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1368 23:55:49.993198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1369 23:55:50.004554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1370 23:55:50.015638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1371 23:55:50.026871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1372 23:55:50.038091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1373 23:55:50.043700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1374 23:55:50.054888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1375 23:55:50.066100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1376 23:55:50.077416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1377 23:55:50.088438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1378 23:55:50.099792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1379 23:55:50.110969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1380 23:55:50.122040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1381 23:55:50.133406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1382 23:55:50.144532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1383 23:55:50.155806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1384 23:55:50.166901 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1385 23:55:50.178213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1386 23:55:50.189227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1387 23:55:50.200597 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1388 23:55:50.211683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1389 23:55:50.222856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1390 23:55:50.234049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1391 23:55:50.245238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1392 23:55:50.256424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1393 23:55:50.267563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1394 23:55:50.278729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1395 23:55:50.290044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1396 23:55:50.301089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1397 23:55:50.312332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1398 23:55:50.323512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1399 23:55:50.329101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1400 23:55:50.340297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1401 23:55:50.351505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1402 23:55:50.362640 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1403 23:55:50.374270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1404 23:55:50.385400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1405 23:55:50.396591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1406 23:55:50.407847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1407 23:55:50.419032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1408 23:55:50.430237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1409 23:55:50.441401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1410 23:55:50.452558 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1411 23:55:50.463850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1412 23:55:50.475034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1413 23:55:50.486297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1414 23:55:50.497357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1415 23:55:50.508537 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1416 23:55:50.519722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1417 23:55:50.525582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1418 23:55:50.536517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1419 23:55:50.547794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1420 23:55:50.558996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1421 23:55:50.570138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1422 23:55:50.575702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1423 23:55:50.592620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1424 23:55:50.603684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1425 23:55:50.609269 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1426 23:55:50.625797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1427 23:55:50.636975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1428 23:55:50.648185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1429 23:55:50.653828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1430 23:55:50.664975 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1431 23:55:50.676152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1432 23:55:50.681751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1433 23:55:50.692920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1434 23:55:50.704121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1435 23:55:50.709706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1436 23:55:50.720755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1437 23:55:50.726340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1438 23:55:50.737682 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1439 23:55:50.748915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1440 23:55:50.759916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1441 23:55:50.771129 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1442 23:55:50.782306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1443 23:55:50.793680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1444 23:55:50.804808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1445 23:55:50.815890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1446 23:55:50.827068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1447 23:55:50.838267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1448 23:55:50.849591 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1449 23:55:50.860820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1450 23:55:50.877577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1451 23:55:50.888851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1452 23:55:50.899958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1453 23:55:50.911138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1454 23:55:50.922177 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1455 23:55:50.938963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1456 23:55:50.950147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1457 23:55:50.961330 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1458 23:55:50.972657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1459 23:55:50.978127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1460 23:55:50.989308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1461 23:55:51.000559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1462 23:55:51.006106 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1463 23:55:51.017441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1464 23:55:51.023091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1465 23:55:51.034195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1466 23:55:51.039644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1467 23:55:51.051146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1468 23:55:51.056583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1469 23:55:51.067786 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1470 23:55:51.073378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1471 23:55:51.084463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1472 23:55:51.095638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1473 23:55:51.106867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1474 23:55:51.112580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1475 23:55:51.123621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1476 23:55:51.134818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1477 23:55:51.140578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1478 23:55:51.151748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1479 23:55:51.157379 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1480 23:55:51.162834 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1481 23:55:51.168450 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1482 23:55:51.174008 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1483 23:55:51.185441 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1484 23:55:51.190835 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1485 23:55:51.196378 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1486 23:55:51.207578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1487 23:55:51.213280 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1488 23:55:51.224347 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1489 23:55:51.229970 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1490 23:55:51.241265 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1491 23:55:51.246861 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1492 23:55:51.252439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1493 23:55:51.263521 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1494 23:55:51.269220 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1495 23:55:51.280440 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1496 23:55:51.286038 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1497 23:55:51.297245 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1498 23:55:51.302813 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1499 23:55:51.314059 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1500 23:55:51.319581 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1501 23:55:51.330634 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1502 23:55:51.336354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1503 23:55:51.347396 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1504 23:55:51.352952 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1505 23:55:51.364349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1506 23:55:51.369832 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1507 23:55:51.375372 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1508 23:55:51.386574 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1509 23:55:51.392320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1510 23:55:51.403365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1511 23:55:51.409119 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1512 23:55:51.420285 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1513 23:55:51.425899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1514 23:55:51.437074 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1515 23:55:51.448094 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1516 23:55:51.459261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1517 23:55:51.464891 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1518 23:55:51.476223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 23:55:51.481692 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 23:55:51.493041 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 23:55:51.498489 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 23:55:51.509957 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 23:55:51.515271 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 23:55:51.526468 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 23:55:51.537664 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 23:55:51.543386 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 23:55:51.554433 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 23:55:51.560088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 23:55:51.571233 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 23:55:51.576878 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 23:55:51.582499 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 23:55:51.593614 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 23:55:51.599240 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 23:55:51.604846 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 23:55:51.616157 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 23:55:51.621589 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 23:55:51.632883 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 23:55:51.638535 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 23:55:51.649713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 23:55:51.655320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 23:55:51.660899 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 23:55:51.666511 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 23:55:51.677698 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 23:55:51.683287 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 23:55:51.694337 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 23:55:51.700084 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 23:55:51.711342 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 23:55:51.722299 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 23:55:51.733478 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 23:55:51.739397 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 23:55:51.750281 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 23:55:51.761620 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 23:55:51.767067 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 23:55:51.772795 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 23:55:51.778269 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 23:55:51.783873 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 23:55:51.789431 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 23:55:51.795089 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 23:55:51.806261 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 23:55:51.812030 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 23:55:51.817582 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 23:55:51.823015 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 23:55:51.828773 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 23:55:51.834249 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 23:55:51.839888 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 23:55:51.845611 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 23:55:51.851080 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 23:55:51.856826 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 23:55:51.862310 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 23:55:51.867913 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 23:55:51.873499 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 23:55:51.879109 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 23:55:51.884683 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 23:55:51.890439 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 23:55:51.895903 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 23:55:51.901501 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 23:55:51.907082 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 23:55:51.912698 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 23:55:51.918300 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 23:55:51.924022 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 23:55:51.929509 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 23:55:51.935127 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 23:55:51.940746 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 23:55:51.946331 dt_test_unprobed_devices_sh_opp-table skip
1585 23:55:51.951945 dt_test_unprobed_devices_sh_soc skip
1586 23:55:51.952206 dt_test_unprobed_devices_sh_sound pass
1587 23:55:51.957493 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 23:55:51.963104 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 23:55:51.974283 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 23:55:51.974527 dt_test_unprobed_devices_sh fail
1591 23:55:51.979969 + ../../utils/send-to-lava.sh ./output/result.txt
1592 23:55:51.990888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 23:55:51.991394 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 23:55:52.103546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 23:55:52.104042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 23:55:52.214313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 23:55:52.214829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 23:55:52.322838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 23:55:52.323330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 23:55:52.432946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 23:55:52.433453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 23:55:52.552426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 23:55:52.552927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 23:55:52.667066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 23:55:52.667576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 23:55:52.804279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 23:55:52.804795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 23:55:52.917611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 23:55:52.918144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 23:55:53.031098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 23:55:53.031629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 23:55:53.220364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 23:55:53.220899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 23:55:53.344354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 23:55:53.344880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 23:55:53.494188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 23:55:53.494806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 23:55:53.627099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 23:55:53.627627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 23:55:53.746994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 23:55:53.747521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 23:55:53.898772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 23:55:53.899305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 23:55:54.102033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 23:55:54.102545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 23:55:54.256259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 23:55:54.256776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 23:55:54.413769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 23:55:54.414352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 23:55:54.537296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 23:55:54.537875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 23:55:54.668532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 23:55:54.669138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 23:55:54.799499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 23:55:54.800022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 23:55:54.930153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 23:55:54.930748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 23:55:55.053501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 23:55:55.054041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 23:55:55.177392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 23:55:55.177915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 23:55:55.293290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 23:55:55.293814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 23:56:08.392316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 23:56:08.392815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 23:56:08.521333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 23:56:08.521859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 23:56:08.638067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 23:56:08.638586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 23:56:08.779935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 23:56:08.780450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 23:56:08.933095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 23:56:08.933610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 23:56:09.074534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 23:56:09.075049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 23:56:09.252171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 23:56:09.252682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 23:56:09.395389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 23:56:09.395896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 23:56:09.600417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 23:56:09.600921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 23:56:09.717181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 23:56:09.717680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 23:56:09.901597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 23:56:09.902119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 23:56:10.020706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 23:56:10.021151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 23:56:10.147598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 23:56:10.148106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 23:56:10.272645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 23:56:10.273140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 23:56:10.379861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 23:56:10.380377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 23:56:10.493864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 23:56:10.494395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 23:56:10.612767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 23:56:10.613251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 23:56:10.725710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 23:56:10.726246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 23:56:10.851960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 23:56:10.852470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 23:56:10.970887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 23:56:10.971425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 23:56:11.084454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 23:56:11.084947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 23:56:11.190964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 23:56:11.191504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 23:56:11.311898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 23:56:11.312388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 23:56:11.424075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 23:56:11.424588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 23:56:11.540418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 23:56:11.540926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 23:56:11.661383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 23:56:11.661871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 23:56:11.773198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 23:56:11.773693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 23:56:11.883359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 23:56:11.883883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 23:56:12.006471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 23:56:12.006990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 23:56:12.121814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 23:56:12.122331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 23:56:12.236162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 23:56:12.236689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 23:56:12.352764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 23:56:12.353267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 23:56:12.468146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 23:56:12.468649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 23:56:12.588896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 23:56:12.589443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 23:56:12.707603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 23:56:12.708110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 23:56:12.822858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 23:56:12.823379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 23:56:12.936233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 23:56:12.936720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 23:56:13.051431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 23:56:13.051952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 23:56:13.162750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 23:56:13.163313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 23:56:13.289372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 23:56:13.289919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 23:56:13.414309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 23:56:13.414841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 23:56:13.572613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 23:56:13.573134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 23:56:13.708361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 23:56:13.708860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 23:56:13.839250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 23:56:13.839778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 23:56:13.960261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 23:56:13.960798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 23:56:14.082487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 23:56:14.083124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 23:56:14.208106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 23:56:14.208586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 23:56:14.326752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 23:56:14.327286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 23:56:14.443823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 23:56:14.444297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 23:56:14.567707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 23:56:14.568302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 23:56:14.682939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 23:56:14.683521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 23:56:14.951816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 23:56:14.952367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 23:56:15.123113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 23:56:15.123643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 23:56:15.297058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 23:56:15.297569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 23:56:15.414774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 23:56:15.415268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 23:56:15.531709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 23:56:15.532235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 23:56:15.661028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 23:56:15.661523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 23:56:15.772406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 23:56:15.772894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 23:56:15.881604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 23:56:15.882123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 23:56:15.995139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 23:56:15.995666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 23:56:16.183074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 23:56:16.183556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 23:56:16.332513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 23:56:16.333066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 23:56:16.451646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 23:56:16.452145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 23:56:16.576220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 23:56:16.576719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 23:56:16.696723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 23:56:16.697211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 23:56:16.819560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 23:56:16.820085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 23:56:16.947679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 23:56:16.948206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 23:56:17.070720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 23:56:17.071243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 23:56:17.187303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 23:56:17.187831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 23:56:17.318016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 23:56:17.318552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 23:56:17.450305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 23:56:17.450830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 23:56:17.582617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 23:56:17.583142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 23:56:17.713956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 23:56:17.714561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 23:56:17.844565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 23:56:17.845089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 23:56:17.983373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 23:56:17.983923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 23:56:18.123472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 23:56:18.123995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 23:56:18.263505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 23:56:18.264029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 23:56:18.385678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 23:56:18.386306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 23:56:18.521232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 23:56:18.521823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 23:56:18.762810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 23:56:18.763333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 23:56:18.941192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 23:56:18.941671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 23:56:19.062991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 23:56:19.063514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 23:56:19.214144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 23:56:19.214757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 23:56:19.357939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 23:56:19.358493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 23:56:19.662524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 23:56:19.663066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 23:56:19.884668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 23:56:19.885174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 23:56:20.009321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 23:56:20.009937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 23:56:20.229087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 23:56:20.229588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 23:56:20.377119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 23:56:20.377670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 23:56:20.502760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 23:56:20.503352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 23:56:20.655730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 23:56:20.656245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 23:56:20.775309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 23:56:20.775829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 23:56:20.906152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 23:56:20.906653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 23:56:21.027447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 23:56:21.027968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 23:56:21.141864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 23:56:21.144645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 23:56:21.262566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 23:56:21.265672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 23:56:21.404566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 23:56:21.407499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 23:56:21.514350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 23:56:21.514833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 23:56:21.623400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 23:56:21.623923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 23:56:21.747431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 23:56:21.747960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 23:56:21.872493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 23:56:21.873091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 23:56:21.990104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 23:56:21.990629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 23:56:22.101617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 23:56:22.102181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 23:56:22.235005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 23:56:22.235526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 23:56:22.361236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 23:56:22.361752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 23:56:22.469807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 23:56:22.470308 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 23:56:22.583375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 23:56:22.583854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 23:56:22.736891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 23:56:22.737511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 23:56:22.878794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 23:56:22.879319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 23:56:22.998744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 23:56:22.999259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 23:56:23.130863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 23:56:23.131389 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 23:56:23.254197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 23:56:23.254790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 23:56:23.388948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2007 23:56:23.389470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2009 23:56:23.524364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2010 23:56:23.524971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2012 23:56:23.656532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2013 23:56:23.657047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2015 23:56:23.787190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2016 23:56:23.787735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2018 23:56:23.933233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2019 23:56:23.933834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2021 23:56:24.064811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2022 23:56:24.065349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2024 23:56:24.182059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2025 23:56:24.182585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2027 23:56:24.297235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2028 23:56:24.297886 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2030 23:56:24.418105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2031 23:56:24.418637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2033 23:56:24.530367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2034 23:56:24.530939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2036 23:56:24.666871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2037 23:56:24.667512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2039 23:56:24.803993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2040 23:56:24.804530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2042 23:56:24.928780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2043 23:56:24.929327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2045 23:56:25.038084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2046 23:56:25.038639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2048 23:56:25.151484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2049 23:56:25.151986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2051 23:56:25.264684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2052 23:56:25.265203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2054 23:56:25.383750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2055 23:56:25.384211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2057 23:56:25.498259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2058 23:56:25.498763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2060 23:56:25.648230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2061 23:56:25.648835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2063 23:56:25.829172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2064 23:56:25.829619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2066 23:56:25.976136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2067 23:56:25.976576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2069 23:56:26.095937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2070 23:56:26.096373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2072 23:56:26.217497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2073 23:56:26.218020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2075 23:56:26.334080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2076 23:56:26.334580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2078 23:56:26.456336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2079 23:56:26.456834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2081 23:56:26.584459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2082 23:56:26.584950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2084 23:56:26.696078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2085 23:56:26.696564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2087 23:56:26.817861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2088 23:56:26.818348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2090 23:56:26.931491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2091 23:56:26.932033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2093 23:56:27.051736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2094 23:56:27.052242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2096 23:56:27.166427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2097 23:56:27.166918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2099 23:56:27.285814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2100 23:56:27.286344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2102 23:56:27.421738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2103 23:56:27.422255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2105 23:56:27.533050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2106 23:56:27.533549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2108 23:56:27.647931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2109 23:56:27.648430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2111 23:56:27.777171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2112 23:56:27.777769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2114 23:56:27.899078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2115 23:56:27.899596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2117 23:56:28.019957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2118 23:56:28.020455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2120 23:56:28.138873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2121 23:56:28.139397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2123 23:56:28.264788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2124 23:56:28.265285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2126 23:56:28.481334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2127 23:56:28.481864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2129 23:56:28.599580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2130 23:56:28.600060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2132 23:56:28.721475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2133 23:56:28.722056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2135 23:56:28.842645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2136 23:56:28.843168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2138 23:56:28.959165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 23:56:28.959659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 23:56:29.105380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2142 23:56:29.105875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2144 23:56:29.212850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2145 23:56:29.213374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2147 23:56:29.504370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2148 23:56:29.504865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2150 23:56:29.700773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2151 23:56:29.701295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2153 23:56:29.871483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2154 23:56:29.872007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2156 23:56:29.983716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2157 23:56:29.984199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2159 23:56:30.102316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2160 23:56:30.102796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2162 23:56:30.228756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2163 23:56:30.229242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2165 23:56:30.354123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2166 23:56:30.354619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2168 23:56:30.513302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2169 23:56:30.513779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2171 23:56:30.632743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2172 23:56:30.633254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2174 23:56:30.752284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2175 23:56:30.752800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2177 23:56:30.870061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2178 23:56:30.870602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2180 23:56:30.984062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2181 23:56:30.984570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2183 23:56:31.097147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2184 23:56:31.097667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2186 23:56:31.210406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2187 23:56:31.210925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2189 23:56:31.456323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2190 23:56:31.456833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2192 23:56:31.583344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2193 23:56:31.583851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2195 23:56:31.698902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2196 23:56:31.699430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2198 23:56:31.860681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2199 23:56:31.861205 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2201 23:56:31.974967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2202 23:56:31.975484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2204 23:56:32.087109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2205 23:56:32.087614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2207 23:56:32.200315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2208 23:56:32.200838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2210 23:56:32.347793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2211 23:56:32.348286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2213 23:56:32.469552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2214 23:56:32.470076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2216 23:56:32.584169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2217 23:56:32.584652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2219 23:56:32.698961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2220 23:56:32.699459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2222 23:56:32.811177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2223 23:56:32.811654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2225 23:56:32.923931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2226 23:56:32.924426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2228 23:56:33.083680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2229 23:56:33.084179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2231 23:56:33.212301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2232 23:56:33.212783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2234 23:56:33.383125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2235 23:56:33.383648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2237 23:56:33.509357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2238 23:56:33.509985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2240 23:56:33.625598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2241 23:56:33.626111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2243 23:56:33.739949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2244 23:56:33.740451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2246 23:56:33.941634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2247 23:56:33.942197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2249 23:56:34.083300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2250 23:56:34.083817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2252 23:56:34.196303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2253 23:56:34.196789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2255 23:56:34.336705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2256 23:56:34.337197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2258 23:56:34.468966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2259 23:56:34.469449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2261 23:56:34.669377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2262 23:56:34.669857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2264 23:56:34.792865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2265 23:56:34.793359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2267 23:56:34.965463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2269 23:56:34.967700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2270 23:56:35.107162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2271 23:56:35.107646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2273 23:56:35.248876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2274 23:56:35.249403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2276 23:56:35.470565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2277 23:56:35.471090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2279 23:56:35.601658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2280 23:56:35.602194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2282 23:56:35.716718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2283 23:56:35.717210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2285 23:56:35.845174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2286 23:56:35.845971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2288 23:56:35.978900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2289 23:56:35.979435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2291 23:56:36.214911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2292 23:56:36.215419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2294 23:56:36.482749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2295 23:56:36.483240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2297 23:56:36.680819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2298 23:56:36.681320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2300 23:56:36.914816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2301 23:56:36.915264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2303 23:56:37.046338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2304 23:56:37.046903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2306 23:56:37.195474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2307 23:56:37.195986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2309 23:56:37.355429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2310 23:56:37.355953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2312 23:56:37.511667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2313 23:56:37.512182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2315 23:56:37.654485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2316 23:56:37.655001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2318 23:56:37.840733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2319 23:56:37.841264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2321 23:56:37.974679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2322 23:56:37.975230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2324 23:56:38.087839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2325 23:56:38.088328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2327 23:56:38.197453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2328 23:56:38.197964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2330 23:56:38.308340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2331 23:56:38.308887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2333 23:56:38.422547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2334 23:56:38.423096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2336 23:56:38.554247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2337 23:56:38.554877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2339 23:56:38.696365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2340 23:56:38.696854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2342 23:56:38.961918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2343 23:56:38.962453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2345 23:56:39.080073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2346 23:56:39.080599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2348 23:56:39.213986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2349 23:56:39.214516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2351 23:56:39.352947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2352 23:56:39.353424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2354 23:56:39.509766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2355 23:56:39.510340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2357 23:56:39.628987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2358 23:56:39.629473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2360 23:56:39.772066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2361 23:56:39.772340 + set +x
2362 23:56:39.772710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2364 23:56:39.776358 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 683458_1.6.2.4.5>
2365 23:56:39.776753 Received signal: <ENDRUN> 1_kselftest-dt 683458_1.6.2.4.5
2366 23:56:39.776924 Ending use of test pattern.
2367 23:56:39.777073 Ending test lava.1_kselftest-dt (683458_1.6.2.4.5), duration 280.61
2369 23:56:39.817555 <LAVA_TEST_RUNNER EXIT>
2370 23:56:39.818108 ok: lava_test_shell seems to have completed
2371 23:56:39.822257 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2372 23:56:39.823086 end: 3.1 lava-test-shell (duration 00:04:44) [common]
2373 23:56:39.823304 end: 3 lava-test-retry (duration 00:04:44) [common]
2374 23:56:39.823515 start: 4 finalize (timeout 00:02:24) [common]
2375 23:56:39.823733 start: 4.1 power-off (timeout 00:00:30) [common]
2376 23:56:39.824088 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-03'
2377 23:56:39.838910 >> OK - accepted request
2378 23:56:39.840119 Returned 0 in 0 seconds
2379 23:56:39.940769 end: 4.1 power-off (duration 00:00:00) [common]
2381 23:56:39.941578 start: 4.2 read-feedback (timeout 00:02:24) [common]
2382 23:56:39.942094 Listened to connection for namespace 'common' for up to 1s
2383 23:56:39.942493 Listened to connection for namespace 'common' for up to 1s
2384 23:56:40.942301 Finalising connection for namespace 'common'
2385 23:56:40.942753 Disconnecting from shell: Finalise
2386 23:56:40.942989 / #
2387 23:56:41.043563 end: 4.2 read-feedback (duration 00:00:01) [common]
2388 23:56:41.043944 end: 4 finalize (duration 00:00:01) [common]
2389 23:56:41.044210 Cleaning after the job
2390 23:56:41.044449 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/ramdisk
2391 23:56:41.049665 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/kernel
2392 23:56:41.050746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/dtb
2393 23:56:41.051130 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/nfsrootfs
2394 23:56:41.095001 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683458/tftp-deploy-9yflne41/modules
2395 23:56:41.099131 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/683458
2396 23:56:41.638644 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/683458
2397 23:56:41.638879 Job finished correctly