Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 00:28:12.814651 lava-dispatcher, installed at version: 2024.01
2 00:28:12.814973 start: 0 validate
3 00:28:12.815114 Start time: 2024-09-01 00:28:12.815107+00:00 (UTC)
4 00:28:12.815282 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 00:28:13.992939 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 00:28:14.129618 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 00:28:14.267840 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 00:28:14.405018 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 00:28:14.546366 validate duration: 1.73
11 00:28:14.547091 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 00:28:14.547329 start: 1.1 download-retry (timeout 00:10:00) [common]
13 00:28:14.547547 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 00:28:14.548001 Not decompressing ramdisk as can be used compressed.
15 00:28:14.548297 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 00:28:14.548490 saving as /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/ramdisk/initrd.cpio.gz
17 00:28:14.548650 total size: 4775763 (4 MB)
18 00:28:14.819240 progress 0 % (0 MB)
19 00:28:15.232122 progress 5 % (0 MB)
20 00:28:15.361559 progress 10 % (0 MB)
21 00:28:15.372810 progress 15 % (0 MB)
22 00:28:15.494923 progress 20 % (0 MB)
23 00:28:15.505382 progress 25 % (1 MB)
24 00:28:15.508970 progress 30 % (1 MB)
25 00:28:15.512874 progress 35 % (1 MB)
26 00:28:15.629717 progress 40 % (1 MB)
27 00:28:15.637527 progress 45 % (2 MB)
28 00:28:15.641356 progress 50 % (2 MB)
29 00:28:15.645351 progress 55 % (2 MB)
30 00:28:15.648860 progress 60 % (2 MB)
31 00:28:15.652264 progress 65 % (2 MB)
32 00:28:15.656140 progress 70 % (3 MB)
33 00:28:15.659298 progress 75 % (3 MB)
34 00:28:15.765127 progress 80 % (3 MB)
35 00:28:15.768663 progress 85 % (3 MB)
36 00:28:15.773112 progress 90 % (4 MB)
37 00:28:15.776735 progress 95 % (4 MB)
38 00:28:15.780197 progress 100 % (4 MB)
39 00:28:15.780796 4 MB downloaded in 1.23 s (3.70 MB/s)
40 00:28:15.781180 end: 1.1.1 http-download (duration 00:00:01) [common]
42 00:28:15.781792 end: 1.1 download-retry (duration 00:00:01) [common]
43 00:28:15.781993 start: 1.2 download-retry (timeout 00:09:59) [common]
44 00:28:15.782180 start: 1.2.1 http-download (timeout 00:09:59) [common]
45 00:28:15.782566 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 00:28:15.782731 saving as /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/kernel/zImage
47 00:28:15.782877 total size: 11354624 (10 MB)
48 00:28:15.783019 No compression specified
49 00:28:15.920599 progress 0 % (0 MB)
50 00:28:15.928652 progress 5 % (0 MB)
51 00:28:15.936621 progress 10 % (1 MB)
52 00:28:15.944602 progress 15 % (1 MB)
53 00:28:15.953042 progress 20 % (2 MB)
54 00:28:15.960504 progress 25 % (2 MB)
55 00:28:16.059399 progress 30 % (3 MB)
56 00:28:16.068043 progress 35 % (3 MB)
57 00:28:16.076082 progress 40 % (4 MB)
58 00:28:16.083968 progress 45 % (4 MB)
59 00:28:16.092397 progress 50 % (5 MB)
60 00:28:16.189274 progress 55 % (5 MB)
61 00:28:16.198885 progress 60 % (6 MB)
62 00:28:16.207576 progress 65 % (7 MB)
63 00:28:16.224881 progress 70 % (7 MB)
64 00:28:16.232913 progress 75 % (8 MB)
65 00:28:16.241326 progress 80 % (8 MB)
66 00:28:16.330685 progress 85 % (9 MB)
67 00:28:16.338827 progress 90 % (9 MB)
68 00:28:16.359825 progress 95 % (10 MB)
69 00:28:16.461066 progress 100 % (10 MB)
70 00:28:16.461808 10 MB downloaded in 0.68 s (15.95 MB/s)
71 00:28:16.462222 end: 1.2.1 http-download (duration 00:00:01) [common]
73 00:28:16.462793 end: 1.2 download-retry (duration 00:00:01) [common]
74 00:28:16.463005 start: 1.3 download-retry (timeout 00:09:58) [common]
75 00:28:16.463201 start: 1.3.1 http-download (timeout 00:09:58) [common]
76 00:28:16.463642 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 00:28:16.463826 saving as /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/dtb/am335x-boneblack.dtb
78 00:28:16.463975 total size: 70308 (0 MB)
79 00:28:16.464123 No compression specified
80 00:28:16.600978 progress 46 % (0 MB)
81 00:28:16.601760 progress 93 % (0 MB)
82 00:28:16.602385 progress 100 % (0 MB)
83 00:28:16.602662 0 MB downloaded in 0.14 s (0.48 MB/s)
84 00:28:16.603001 end: 1.3.1 http-download (duration 00:00:00) [common]
86 00:28:16.603561 end: 1.3 download-retry (duration 00:00:00) [common]
87 00:28:16.603755 start: 1.4 download-retry (timeout 00:09:58) [common]
88 00:28:16.603946 start: 1.4.1 http-download (timeout 00:09:58) [common]
89 00:28:16.604319 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 00:28:16.604481 saving as /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/nfsrootfs/full.rootfs.tar
91 00:28:16.604626 total size: 117747780 (112 MB)
92 00:28:16.604775 Using unxz to decompress xz
93 00:28:16.742649 progress 0 % (0 MB)
94 00:28:17.104040 progress 5 % (5 MB)
95 00:28:17.470242 progress 10 % (11 MB)
96 00:28:17.839732 progress 15 % (16 MB)
97 00:28:18.192638 progress 20 % (22 MB)
98 00:28:18.542566 progress 25 % (28 MB)
99 00:28:18.936436 progress 30 % (33 MB)
100 00:28:19.306748 progress 35 % (39 MB)
101 00:28:19.610737 progress 40 % (44 MB)
102 00:28:19.885065 progress 45 % (50 MB)
103 00:28:20.278036 progress 50 % (56 MB)
104 00:28:20.662345 progress 55 % (61 MB)
105 00:28:21.024581 progress 60 % (67 MB)
106 00:28:21.384979 progress 65 % (73 MB)
107 00:28:21.754417 progress 70 % (78 MB)
108 00:28:22.125402 progress 75 % (84 MB)
109 00:28:22.479837 progress 80 % (89 MB)
110 00:28:22.836715 progress 85 % (95 MB)
111 00:28:23.201281 progress 90 % (101 MB)
112 00:28:23.555280 progress 95 % (106 MB)
113 00:28:23.930787 progress 100 % (112 MB)
114 00:28:23.936948 112 MB downloaded in 7.33 s (15.31 MB/s)
115 00:28:23.937340 end: 1.4.1 http-download (duration 00:00:07) [common]
117 00:28:23.937829 end: 1.4 download-retry (duration 00:00:07) [common]
118 00:28:23.937982 start: 1.5 download-retry (timeout 00:09:51) [common]
119 00:28:23.938130 start: 1.5.1 http-download (timeout 00:09:51) [common]
120 00:28:23.938428 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 00:28:23.938556 saving as /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/modules/modules.tar
122 00:28:23.938667 total size: 6607612 (6 MB)
123 00:28:23.938781 Using unxz to decompress xz
124 00:28:24.075802 progress 0 % (0 MB)
125 00:28:24.094865 progress 5 % (0 MB)
126 00:28:24.114999 progress 10 % (0 MB)
127 00:28:24.135770 progress 15 % (0 MB)
128 00:28:24.158268 progress 20 % (1 MB)
129 00:28:24.178800 progress 25 % (1 MB)
130 00:28:24.200885 progress 30 % (1 MB)
131 00:28:24.221863 progress 35 % (2 MB)
132 00:28:24.242692 progress 40 % (2 MB)
133 00:28:24.263217 progress 45 % (2 MB)
134 00:28:24.284251 progress 50 % (3 MB)
135 00:28:24.304412 progress 55 % (3 MB)
136 00:28:24.325020 progress 60 % (3 MB)
137 00:28:24.348358 progress 65 % (4 MB)
138 00:28:24.371118 progress 70 % (4 MB)
139 00:28:24.394911 progress 75 % (4 MB)
140 00:28:24.419098 progress 80 % (5 MB)
141 00:28:24.443348 progress 85 % (5 MB)
142 00:28:24.465957 progress 90 % (5 MB)
143 00:28:24.488743 progress 95 % (6 MB)
144 00:28:24.511872 progress 100 % (6 MB)
145 00:28:24.518626 6 MB downloaded in 0.58 s (10.87 MB/s)
146 00:28:24.519022 end: 1.5.1 http-download (duration 00:00:01) [common]
148 00:28:24.519264 end: 1.5 download-retry (duration 00:00:01) [common]
149 00:28:24.519340 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
150 00:28:24.519419 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
151 00:28:29.618581 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws
152 00:28:29.618876 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
153 00:28:29.618962 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
154 00:28:29.619222 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg
155 00:28:29.619357 makedir: /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin
156 00:28:29.619456 makedir: /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/tests
157 00:28:29.619550 makedir: /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/results
158 00:28:29.619649 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-add-keys
159 00:28:29.619808 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-add-sources
160 00:28:29.619938 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-background-process-start
161 00:28:29.620069 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-background-process-stop
162 00:28:29.620208 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-common-functions
163 00:28:29.620340 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-echo-ipv4
164 00:28:29.620469 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-install-packages
165 00:28:29.620596 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-installed-packages
166 00:28:29.620722 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-os-build
167 00:28:29.620849 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-probe-channel
168 00:28:29.620976 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-probe-ip
169 00:28:29.621104 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-target-ip
170 00:28:29.621232 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-target-mac
171 00:28:29.621365 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-target-storage
172 00:28:29.621498 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-test-case
173 00:28:29.621858 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-test-event
174 00:28:29.621991 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-test-feedback
175 00:28:29.622119 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-test-raise
176 00:28:29.622249 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-test-reference
177 00:28:29.622378 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-test-runner
178 00:28:29.622507 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-test-set
179 00:28:29.622634 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-test-shell
180 00:28:29.622766 Updating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-add-keys (debian)
181 00:28:29.622943 Updating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-add-sources (debian)
182 00:28:29.623089 Updating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-install-packages (debian)
183 00:28:29.623235 Updating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-installed-packages (debian)
184 00:28:29.623382 Updating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/bin/lava-os-build (debian)
185 00:28:29.623508 Creating /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/environment
186 00:28:29.623613 LAVA metadata
187 00:28:29.623679 - LAVA_JOB_ID=683574
188 00:28:29.623732 - LAVA_DISPATCHER_IP=192.168.56.193
189 00:28:29.623834 start: 1.6.2.1 ssh-authorize (timeout 00:09:45) [common]
190 00:28:29.624114 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 00:28:29.624193 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:45) [common]
192 00:28:29.624250 skipped lava-vland-overlay
193 00:28:29.624312 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 00:28:29.624377 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:45) [common]
195 00:28:29.624428 skipped lava-multinode-overlay
196 00:28:29.624487 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 00:28:29.624552 start: 1.6.2.4 test-definition (timeout 00:09:45) [common]
198 00:28:29.624614 Loading test definitions
199 00:28:29.624684 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:45) [common]
200 00:28:29.624740 Using /lava-683574 at stage 0
201 00:28:29.625090 uuid=683574_1.6.2.4.1 testdef=None
202 00:28:29.625166 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 00:28:29.625233 start: 1.6.2.4.2 test-overlay (timeout 00:09:45) [common]
204 00:28:29.625685 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 00:28:29.625889 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:45) [common]
207 00:28:29.626445 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 00:28:29.626648 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:45) [common]
210 00:28:29.631657 runner path: /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/0/tests/0_timesync-off test_uuid 683574_1.6.2.4.1
211 00:28:29.631823 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 00:28:29.632022 start: 1.6.2.4.5 git-repo-action (timeout 00:09:45) [common]
214 00:28:29.632079 Using /lava-683574 at stage 0
215 00:28:29.632169 Fetching tests from https://github.com/kernelci/test-definitions.git
216 00:28:29.632247 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/0/tests/1_kselftest-dt'
217 00:28:31.428988 Running '/usr/bin/git checkout kernelci.org
218 00:28:31.597165 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 00:28:31.597990 uuid=683574_1.6.2.4.5 testdef=None
220 00:28:31.598202 end: 1.6.2.4.5 git-repo-action (duration 00:00:02) [common]
222 00:28:31.598610 start: 1.6.2.4.6 test-overlay (timeout 00:09:43) [common]
223 00:28:31.599568 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 00:28:31.599776 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:43) [common]
226 00:28:31.600790 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 00:28:31.601013 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:43) [common]
229 00:28:31.602025 runner path: /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/0/tests/1_kselftest-dt test_uuid 683574_1.6.2.4.5
230 00:28:31.602114 BOARD='beaglebone-black'
231 00:28:31.602168 BRANCH='mainline'
232 00:28:31.602218 SKIPFILE='/dev/null'
233 00:28:31.602267 SKIP_INSTALL='True'
234 00:28:31.602315 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 00:28:31.602367 TST_CASENAME=''
236 00:28:31.602416 TST_CMDFILES='dt'
237 00:28:31.602583 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 00:28:31.602785 Creating lava-test-runner.conf files
240 00:28:31.602840 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/683574/lava-overlay-84d63zrg/lava-683574/0 for stage 0
241 00:28:31.602934 - 0_timesync-off
242 00:28:31.602995 - 1_kselftest-dt
243 00:28:31.603087 end: 1.6.2.4 test-definition (duration 00:00:02) [common]
244 00:28:31.603166 start: 1.6.2.5 compress-overlay (timeout 00:09:43) [common]
245 00:28:39.642932 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 00:28:39.643088 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:35) [common]
247 00:28:39.643161 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 00:28:39.643237 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
249 00:28:39.643312 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
250 00:28:39.770373 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 00:28:39.770666 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
252 00:28:39.770819 extracting modules file /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws
253 00:28:40.050528 extracting modules file /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/683574/extract-overlay-ramdisk-mtxr6c4h/ramdisk
254 00:28:40.340163 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 00:28:40.340343 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
256 00:28:40.340429 [common] Applying overlay to NFS
257 00:28:40.340483 [common] Applying overlay /var/lib/lava/dispatcher/tmp/683574/compress-overlay-3b17ip9l/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws
258 00:28:41.329525 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 00:28:41.329714 start: 1.6.6 prepare-kernel (timeout 00:09:33) [common]
260 00:28:41.329791 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:33) [common]
261 00:28:41.329869 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 00:28:41.329943 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 00:28:41.330010 start: 1.6.7 configure-preseed-file (timeout 00:09:33) [common]
264 00:28:41.330083 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 00:28:41.330149 start: 1.6.8 compress-ramdisk (timeout 00:09:33) [common]
266 00:28:41.330215 Building ramdisk /var/lib/lava/dispatcher/tmp/683574/extract-overlay-ramdisk-mtxr6c4h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/683574/extract-overlay-ramdisk-mtxr6c4h/ramdisk
267 00:28:41.637645 >> 74799 blocks
268 00:28:43.333796 Adding RAMdisk u-boot header.
269 00:28:43.334086 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/683574/extract-overlay-ramdisk-mtxr6c4h/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/683574/extract-overlay-ramdisk-mtxr6c4h/ramdisk.cpio.gz.uboot
270 00:28:43.451578 output: Image Name:
271 00:28:43.451831 output: Created: Sun Sep 1 00:28:43 2024
272 00:28:43.451958 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 00:28:43.452072 output: Data Size: 14798271 Bytes = 14451.44 KiB = 14.11 MiB
274 00:28:43.452184 output: Load Address: 00000000
275 00:28:43.452288 output: Entry Point: 00000000
276 00:28:43.452399 output:
277 00:28:43.452629 rename /var/lib/lava/dispatcher/tmp/683574/extract-overlay-ramdisk-mtxr6c4h/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/ramdisk/ramdisk.cpio.gz.uboot
278 00:28:43.452833 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 00:28:43.452995 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
280 00:28:43.453145 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
281 00:28:43.453279 No LXC device requested
282 00:28:43.453422 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 00:28:43.453563 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
284 00:28:43.453721 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 00:28:43.453836 Checking files for TFTP limit of 4294967296 bytes.
286 00:28:43.454759 end: 1 tftp-deploy (duration 00:00:29) [common]
287 00:28:43.454981 start: 2 uboot-action (timeout 00:05:00) [common]
288 00:28:43.455175 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 00:28:43.455353 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 00:28:43.455537 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 00:28:43.455830 substitutions:
292 00:28:43.455980 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 00:28:43.456123 - {DTB_ADDR}: 0x88000000
294 00:28:43.456258 - {DTB}: 683574/tftp-deploy-2evzdv8f/dtb/am335x-boneblack.dtb
295 00:28:43.456393 - {INITRD}: 683574/tftp-deploy-2evzdv8f/ramdisk/ramdisk.cpio.gz.uboot
296 00:28:43.456528 - {KERNEL_ADDR}: 0x82000000
297 00:28:43.456666 - {KERNEL}: 683574/tftp-deploy-2evzdv8f/kernel/zImage
298 00:28:43.456807 - {LAVA_MAC}: None
299 00:28:43.456966 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws
300 00:28:43.457113 - {NFS_SERVER_IP}: 192.168.56.193
301 00:28:43.457246 - {PRESEED_CONFIG}: None
302 00:28:43.457378 - {PRESEED_LOCAL}: None
303 00:28:43.457516 - {RAMDISK_ADDR}: 0x83000000
304 00:28:43.457667 - {RAMDISK}: 683574/tftp-deploy-2evzdv8f/ramdisk/ramdisk.cpio.gz.uboot
305 00:28:43.457803 - {ROOT_PART}: None
306 00:28:43.457938 - {ROOT}: None
307 00:28:43.458075 - {SERVER_IP}: 192.168.56.193
308 00:28:43.458214 - {TEE_ADDR}: 0x83000000
309 00:28:43.458347 - {TEE}: None
310 00:28:43.458489 Parsed boot commands:
311 00:28:43.458619 - setenv autoload no
312 00:28:43.458754 - setenv initrd_high 0xffffffff
313 00:28:43.458892 - setenv fdt_high 0xffffffff
314 00:28:43.459022 - dhcp
315 00:28:43.459151 - setenv serverip 192.168.56.193
316 00:28:43.459284 - tftp 0x82000000 683574/tftp-deploy-2evzdv8f/kernel/zImage
317 00:28:43.459416 - tftp 0x83000000 683574/tftp-deploy-2evzdv8f/ramdisk/ramdisk.cpio.gz.uboot
318 00:28:43.459552 - setenv initrd_size ${filesize}
319 00:28:43.459682 - tftp 0x88000000 683574/tftp-deploy-2evzdv8f/dtb/am335x-boneblack.dtb
320 00:28:43.459811 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 00:28:43.459956 - bootz 0x82000000 0x83000000 0x88000000
322 00:28:43.460133 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 00:28:43.460634 start: 2.3 connect-device (timeout 00:05:00) [common]
325 00:28:43.460789 [common] connect-device Connecting to device using 'telnet conserv3 3002'
326 00:28:43.469153 Setting prompt string to ['lava-test: # ']
327 00:28:43.469908 end: 2.3 connect-device (duration 00:00:00) [common]
328 00:28:43.470131 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 00:28:43.470364 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 00:28:43.470585 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 00:28:43.471000 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
332 00:28:43.492466 >> OK - accepted request
333 00:28:43.493392 Returned 0 in 0 seconds
334 00:28:43.594126 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 00:28:43.594957 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 00:28:43.595148 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 00:28:43.595326 Setting prompt string to ['Hit any key to stop autoboot']
339 00:28:43.595477 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 00:28:43.596163 Trying 192.168.56.22...
341 00:28:43.596318 Connected to conserv3.
342 00:28:43.596436 Escape character is '^]'.
343 00:28:43.596563
344 00:28:43.596675 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
345 00:28:43.596791
346 00:28:52.107832
347 00:28:52.114521 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
348 00:28:52.114835 Trying to boot from MMC1
349 00:28:56.167745
350 00:28:56.174678 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
351 00:28:56.174914 Trying to boot from MMC1
352 00:28:58.860033
353 00:28:58.867036 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
354 00:28:58.867384 Trying to boot from MMC1
355 00:28:59.449864
356 00:28:59.450117
357 00:28:59.455376 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
358 00:28:59.455590
359 00:28:59.455762 CPU : AM335X-GP rev 2.0
360 00:28:59.460560 Model: TI AM335x BeagleBone Black
361 00:28:59.460772 DRAM: 512 MiB
362 00:28:59.540107 Core: 160 devices, 18 uclasses, devicetree: separate
363 00:28:59.554033 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
364 00:28:59.954799 NAND: 0 MiB
365 00:28:59.965165 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
366 00:29:00.081858 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
367 00:29:00.103381 <ethaddr> not set. Validating first E-fuse MAC
368 00:29:00.133786 Net: eth2: ethernet@4a100000, eth3: usb_ether
370 00:29:00.192150 Hit any key to stop autoboot: 2
371 00:29:00.192594 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
372 00:29:00.192823 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
373 00:29:00.192990 Setting prompt string to ['=>']
374 00:29:00.193167 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
375 00:29:00.202178 0
376 00:29:00.202691 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
377 00:29:00.202865 Sending with 10 millisecond of delay
379 00:29:01.341122 => setenv autoload no
380 00:29:01.351521 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
381 00:29:01.353073 setenv autoload no
382 00:29:01.353421 Sending with 10 millisecond of delay
384 00:29:03.156428 => setenv initrd_high 0xffffffff
385 00:29:03.166818 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
386 00:29:03.167238 setenv initrd_high 0xffffffff
387 00:29:03.167591 Sending with 10 millisecond of delay
389 00:29:04.785813 => setenv fdt_high 0xffffffff
390 00:29:04.796171 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
391 00:29:04.796521 setenv fdt_high 0xffffffff
392 00:29:04.796869 Sending with 10 millisecond of delay
394 00:29:05.087986 => dhcp
395 00:29:05.098337 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 00:29:05.098687 dhcp
397 00:29:05.100905 link up on port 0, speed 100, full duplex
398 00:29:05.101075 BOOTP broadcast 1
399 00:29:05.353262 BOOTP broadcast 2
400 00:29:05.855134 BOOTP broadcast 3
401 00:29:06.857102 BOOTP broadcast 4
402 00:29:06.879563 *** Unhandled DHCP Option in OFFER/ACK: 42
403 00:29:06.909559 *** Unhandled DHCP Option in OFFER/ACK: 42
404 00:29:06.915826 DHCP client bound to address 192.168.56.5 (1812 ms)
405 00:29:06.916251 Sending with 10 millisecond of delay
407 00:29:08.773260 => setenv serverip 192.168.56.193
408 00:29:08.783652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
409 00:29:08.784073 setenv serverip 192.168.56.193
410 00:29:08.784433 Sending with 10 millisecond of delay
412 00:29:12.270149 => tftp 0x82000000 683574/tftp-deploy-2evzdv8f/kernel/zImage
413 00:29:12.280586 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
414 00:29:12.280955 tftp 0x82000000 683574/tftp-deploy-2evzdv8f/kernel/zImage
415 00:29:12.281095 link up on port 0, speed 100, full duplex
416 00:29:12.285651 Using ethernet@4a100000 device
417 00:29:12.291031 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
418 00:29:12.298513 Filename '683574/tftp-deploy-2evzdv8f/kernel/zImage'.
419 00:29:12.298722 Load address: 0x82000000
420 00:29:14.086545 Loading: *################################################## 10.8 MiB
421 00:29:14.086817 6.1 MiB/s
422 00:29:14.086888 done
423 00:29:14.090595 Bytes transferred = 11354624 (ad4200 hex)
424 00:29:14.090873 Sending with 10 millisecond of delay
426 00:29:18.534422 => tftp 0x83000000 683574/tftp-deploy-2evzdv8f/ramdisk/ramdisk.cpio.gz.uboot
427 00:29:18.544799 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
428 00:29:18.545162 tftp 0x83000000 683574/tftp-deploy-2evzdv8f/ramdisk/ramdisk.cpio.gz.uboot
429 00:29:18.545298 link up on port 0, speed 100, full duplex
430 00:29:18.550086 Using ethernet@4a100000 device
431 00:29:18.555320 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
432 00:29:18.564302 Filename '683574/tftp-deploy-2evzdv8f/ramdisk/ramdisk.cpio.gz.uboot'.
433 00:29:18.564504 Load address: 0x83000000
434 00:29:20.884316 Loading: *################################################## 14.1 MiB
435 00:29:20.884560 6.1 MiB/s
436 00:29:20.884684 done
437 00:29:20.888732 Bytes transferred = 14798335 (e1cdff hex)
438 00:29:20.889116 Sending with 10 millisecond of delay
440 00:29:22.745117 => setenv initrd_size ${filesize}
441 00:29:22.755483 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
442 00:29:22.755781 setenv initrd_size ${filesize}
443 00:29:22.756110 Sending with 10 millisecond of delay
445 00:29:26.931580 => tftp 0x88000000 683574/tftp-deploy-2evzdv8f/dtb/am335x-boneblack.dtb
446 00:29:26.942129 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
447 00:29:26.942729 tftp 0x88000000 683574/tftp-deploy-2evzdv8f/dtb/am335x-boneblack.dtb
448 00:29:26.942909 link up on port 0, speed 100, full duplex
449 00:29:26.947221 Using ethernet@4a100000 device
450 00:29:26.952864 TFTP from server 192.168.56.193; our IP address is 192.168.56.5
451 00:29:26.963134 Filename '683574/tftp-deploy-2evzdv8f/dtb/am335x-boneblack.dtb'.
452 00:29:26.963383 Load address: 0x88000000
453 00:29:26.973269 Loading: *################################################## 68.7 KiB
454 00:29:26.973441 4.8 MiB/s
455 00:29:26.981355 done
456 00:29:26.981749 Bytes transferred = 70308 (112a4 hex)
457 00:29:26.982129 Sending with 10 millisecond of delay
459 00:29:40.436373 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
460 00:29:40.446808 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
461 00:29:40.447249 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
462 00:29:40.447591 Sending with 10 millisecond of delay
464 00:29:42.803966 => bootz 0x82000000 0x83000000 0x88000000
465 00:29:42.814786 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
466 00:29:42.815208 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
467 00:29:42.815709 bootz 0x82000000 0x83000000 0x88000000
468 00:29:42.815879 Kernel image @ 0x82000000 [ 0x000000 - 0xad4200 ]
469 00:29:42.816716 ## Loading init Ramdisk from Legacy Image at 83000000 ...
470 00:29:42.822505 Image Name:
471 00:29:42.822821 Created: 2024-09-01 0:28:43 UTC
472 00:29:42.831400 Image Type: ARM Linux RAMDisk Image (uncompressed)
473 00:29:42.831786 Data Size: 14798271 Bytes = 14.1 MiB
474 00:29:42.839903 Load Address: 00000000
475 00:29:42.840287 Entry Point: 00000000
476 00:29:43.008156 Verifying Checksum ... OK
477 00:29:43.008539 ## Flattened Device Tree blob at 88000000
478 00:29:43.014764 Booting using the fdt blob at 0x88000000
479 00:29:43.015156 Working FDT set to 88000000
480 00:29:43.020220 Using Device Tree in place at 88000000, end 880142a3
481 00:29:43.024856 Working FDT set to 88000000
482 00:29:43.038069
483 00:29:43.038453 Starting kernel ...
484 00:29:43.038608
485 00:29:43.039102 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
486 00:29:43.039325 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
487 00:29:43.039498 Setting prompt string to ['Linux version [0-9]']
488 00:29:43.039663 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
489 00:29:43.039826 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
490 00:29:43.871500 [ 0.000000] Booting Linux on physical CPU 0x0
491 00:29:43.877723 start: 2.4.4.1 login-action (timeout 00:04:00) [common]
492 00:29:43.878133 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
493 00:29:43.878331 Setting prompt string to []
494 00:29:43.878526 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
495 00:29:43.878700 Using line separator: #'\n'#
496 00:29:43.878843 No login prompt set.
497 00:29:43.878995 Parsing kernel messages
498 00:29:43.879126 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
499 00:29:43.879410 [login-action] Waiting for messages, (timeout 00:04:00)
500 00:29:43.879568 Waiting using forced prompt support (timeout 00:02:00)
501 00:29:43.894246 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j303542-arm-gcc-12-multi-v7-defconfig-vhqmp) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Aug 31 23:24:39 UTC 2024
502 00:29:43.900188 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
503 00:29:43.905876 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
504 00:29:43.917260 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
505 00:29:43.922893 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
506 00:29:43.928697 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
507 00:29:43.929030 [ 0.000000] Memory policy: Data cache writeback
508 00:29:43.935226 [ 0.000000] efi: UEFI not found.
509 00:29:43.940710 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
510 00:29:43.946219 [ 0.000000] Zone ranges:
511 00:29:43.952135 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
512 00:29:43.957880 [ 0.000000] Normal empty
513 00:29:43.958265 [ 0.000000] HighMem empty
514 00:29:43.960804 [ 0.000000] Movable zone start for each node
515 00:29:43.966410 [ 0.000000] Early memory node ranges
516 00:29:43.972340 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
517 00:29:43.980456 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
518 00:29:44.005162 [ 0.000000] CPU: All CPU(s) started in SVC mode.
519 00:29:44.010793 [ 0.000000] AM335X ES2.0 (sgx neon)
520 00:29:44.022544 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
521 00:29:44.040096 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
522 00:29:44.051662 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
523 00:29:44.057415 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
524 00:29:44.063102 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
525 00:29:44.073517 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
526 00:29:44.102526 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
527 00:29:44.108407 <6>[ 0.000000] trace event string verifier disabled
528 00:29:44.108708 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
529 00:29:44.116603 <6>[ 0.000000] rcu: RCU event tracing is enabled.
530 00:29:44.122240 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
531 00:29:44.133886 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
532 00:29:44.138646 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
533 00:29:44.153478 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
534 00:29:44.170738 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
535 00:29:44.177490 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
536 00:29:44.270248 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
537 00:29:44.278935 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
538 00:29:44.291302 <6>[ 0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
539 00:29:44.299535 <6>[ 0.019159] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
540 00:29:44.308918 <6>[ 0.033975] Console: colour dummy device 80x30
541 00:29:44.314655 Matched prompt #6: WARNING:
542 00:29:44.315054 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
543 00:29:44.320332 <3>[ 0.038871] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
544 00:29:44.326239 <3>[ 0.045947] This ensures that you still see kernel messages. Please
545 00:29:44.329297 <3>[ 0.052673] update your kernel commandline.
546 00:29:44.370083 <6>[ 0.057285] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
547 00:29:44.375830 <6>[ 0.096164] CPU: Testing write buffer coherency: ok
548 00:29:44.381736 <6>[ 0.101532] CPU0: Spectre v2: using BPIALL workaround
549 00:29:44.382122 <6>[ 0.106997] pid_max: default: 32768 minimum: 301
550 00:29:44.393195 <6>[ 0.112185] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
551 00:29:44.400026 <6>[ 0.120006] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
552 00:29:44.407027 <6>[ 0.129295] CPU0: thread -1, cpu 0, socket -1, mpidr 0
553 00:29:44.415540 <6>[ 0.136132] Setting up static identity map for 0x80300000 - 0x803000ac
554 00:29:44.421176 <6>[ 0.145719] rcu: Hierarchical SRCU implementation.
555 00:29:44.428795 <6>[ 0.150998] rcu: Max phase no-delay instances is 1000.
556 00:29:44.437219 <6>[ 0.162046] EFI services will not be available.
557 00:29:44.443033 <6>[ 0.167287] smp: Bringing up secondary CPUs ...
558 00:29:44.448784 <6>[ 0.172323] smp: Brought up 1 node, 1 CPU
559 00:29:44.454549 <6>[ 0.176723] SMP: Total of 1 processors activated (996.14 BogoMIPS).
560 00:29:44.460503 <6>[ 0.183477] CPU: All CPU(s) started in SVC mode.
561 00:29:44.480742 <6>[ 0.188658] Memory: 407008K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48028K reserved, 65536K cma-reserved, 0K highmem)
562 00:29:44.481130 <6>[ 0.204891] devtmpfs: initialized
563 00:29:44.502614 <6>[ 0.221623] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
564 00:29:44.510981 <6>[ 0.230188] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
565 00:29:44.519958 <6>[ 0.240622] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
566 00:29:44.530796 <6>[ 0.252930] pinctrl core: initialized pinctrl subsystem
567 00:29:44.539934 <6>[ 0.263629] DMI not present or invalid.
568 00:29:44.548213 <6>[ 0.269365] NET: Registered PF_NETLINK/PF_ROUTE protocol family
569 00:29:44.557817 <6>[ 0.278278] DMA: preallocated 256 KiB pool for atomic coherent allocations
570 00:29:44.571772 <6>[ 0.289685] thermal_sys: Registered thermal governor 'step_wise'
571 00:29:44.572188 <6>[ 0.289826] cpuidle: using governor menu
572 00:29:44.599427 <6>[ 0.324978] No ATAGs?
573 00:29:44.606088 <6>[ 0.327620] hw-breakpoint: debug architecture 0x4 unsupported.
574 00:29:44.616165 <6>[ 0.339594] Serial: AMBA PL011 UART driver
575 00:29:44.657903 <6>[ 0.382964] iommu: Default domain type: Translated
576 00:29:44.666981 <6>[ 0.388194] iommu: DMA domain TLB invalidation policy: strict mode
577 00:29:44.676533 <5>[ 0.400494] SCSI subsystem initialized
578 00:29:44.700791 <6>[ 0.420196] usbcore: registered new interface driver usbfs
579 00:29:44.707654 <6>[ 0.426149] usbcore: registered new interface driver hub
580 00:29:44.708043 <6>[ 0.431972] usbcore: registered new device driver usb
581 00:29:44.713191 <6>[ 0.438453] pps_core: LinuxPPS API ver. 1 registered
582 00:29:44.725007 <6>[ 0.443883] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
583 00:29:44.730104 <6>[ 0.453580] PTP clock support registered
584 00:29:44.755130 <6>[ 0.479625] EDAC MC: Ver: 3.0.0
585 00:29:44.761242 <6>[ 0.483792] scmi_core: SCMI protocol bus registered
586 00:29:44.789000 <6>[ 0.513767] vgaarb: loaded
587 00:29:44.801526 <6>[ 0.526700] clocksource: Switched to clocksource dmtimer
588 00:29:44.837663 <6>[ 0.562440] NET: Registered PF_INET protocol family
589 00:29:44.850237 <6>[ 0.568098] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
590 00:29:44.856028 <6>[ 0.576930] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
591 00:29:44.867470 <6>[ 0.585819] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
592 00:29:44.873295 <6>[ 0.594090] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
593 00:29:44.884726 <6>[ 0.602377] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
594 00:29:44.890667 <6>[ 0.610092] TCP: Hash tables configured (established 4096 bind 4096)
595 00:29:44.896417 <6>[ 0.617014] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
596 00:29:44.902356 <6>[ 0.624025] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
597 00:29:44.909912 <6>[ 0.631644] NET: Registered PF_UNIX/PF_LOCAL protocol family
598 00:29:44.946787 <6>[ 0.666087] RPC: Registered named UNIX socket transport module.
599 00:29:44.947171 <6>[ 0.672513] RPC: Registered udp transport module.
600 00:29:44.952367 <6>[ 0.677644] RPC: Registered tcp transport module.
601 00:29:44.958233 <6>[ 0.682749] RPC: Registered tcp-with-tls transport module.
602 00:29:44.971197 <6>[ 0.688680] RPC: Registered tcp NFSv4.1 backchannel transport module.
603 00:29:44.971581 <6>[ 0.695587] PCI: CLS 0 bytes, default 64
604 00:29:44.978509 <5>[ 0.701377] Initialise system trusted keyrings
605 00:29:45.003315 <6>[ 0.725316] Trying to unpack rootfs image as initramfs...
606 00:29:45.028387 <6>[ 0.747261] workingset: timestamp_bits=30 max_order=17 bucket_order=0
607 00:29:45.033083 <6>[ 0.754733] squashfs: version 4.0 (2009/01/31) Phillip Lougher
608 00:29:45.072521 <5>[ 0.797576] NFS: Registering the id_resolver key type
609 00:29:45.078369 <5>[ 0.803165] Key type id_resolver registered
610 00:29:45.084139 <5>[ 0.807857] Key type id_legacy registered
611 00:29:45.089949 <6>[ 0.812296] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
612 00:29:45.098559 <6>[ 0.819507] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
613 00:29:45.145182 <5>[ 0.870321] Key type asymmetric registered
614 00:29:45.151125 <5>[ 0.874841] Asymmetric key parser 'x509' registered
615 00:29:45.162628 <6>[ 0.880333] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
616 00:29:45.163015 <6>[ 0.888271] io scheduler mq-deadline registered
617 00:29:45.168432 <6>[ 0.893204] io scheduler kyber registered
618 00:29:45.173888 <6>[ 0.897674] io scheduler bfq registered
619 00:29:45.594636 <6>[ 1.316588] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
620 00:29:45.630165 <6>[ 1.354870] msm_serial: driver initialized
621 00:29:45.636060 <6>[ 1.359866] SuperH (H)SCI(F) driver initialized
622 00:29:45.642045 <6>[ 1.364983] STMicroelectronics ASC driver initialized
623 00:29:45.647114 <6>[ 1.370646] STM32 USART driver initialized
624 00:29:45.748762 <6>[ 1.473250] brd: module loaded
625 00:29:45.789145 <6>[ 1.513731] loop: module loaded
626 00:29:45.820274 <6>[ 1.544755] CAN device driver interface
627 00:29:45.827041 <6>[ 1.550081] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
628 00:29:45.832883 <6>[ 1.557181] e1000e: Intel(R) PRO/1000 Network Driver
629 00:29:45.839344 <6>[ 1.562566] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
630 00:29:45.844999 <6>[ 1.569025] igb: Intel(R) Gigabit Ethernet Network Driver
631 00:29:45.852737 <6>[ 1.574847] igb: Copyright (c) 2007-2014 Intel Corporation.
632 00:29:45.864456 <6>[ 1.584255] pegasus: Pegasus/Pegasus II USB Ethernet driver
633 00:29:45.870202 <6>[ 1.590397] usbcore: registered new interface driver pegasus
634 00:29:45.876102 <6>[ 1.596520] usbcore: registered new interface driver asix
635 00:29:45.882152 <6>[ 1.602400] usbcore: registered new interface driver ax88179_178a
636 00:29:45.887968 <6>[ 1.608987] usbcore: registered new interface driver cdc_ether
637 00:29:45.893780 <6>[ 1.615283] usbcore: registered new interface driver smsc75xx
638 00:29:45.899566 <6>[ 1.621521] usbcore: registered new interface driver smsc95xx
639 00:29:45.905375 <6>[ 1.627752] usbcore: registered new interface driver net1080
640 00:29:45.911277 <6>[ 1.633870] usbcore: registered new interface driver cdc_subset
641 00:29:45.916916 <6>[ 1.640273] usbcore: registered new interface driver zaurus
642 00:29:45.924549 <6>[ 1.646343] usbcore: registered new interface driver cdc_ncm
643 00:29:45.934425 <6>[ 1.656026] usbcore: registered new interface driver usb-storage
644 00:29:46.018736 <6>[ 1.742084] i2c_dev: i2c /dev entries driver
645 00:29:46.076726 <5>[ 1.793643] cpuidle: enable-method property 'ti,am3352' found operations
646 00:29:46.082378 <6>[ 1.803357] sdhci: Secure Digital Host Controller Interface driver
647 00:29:46.090189 <6>[ 1.810124] sdhci: Copyright(c) Pierre Ossman
648 00:29:46.097391 <6>[ 1.816627] Synopsys Designware Multimedia Card Interface Driver
649 00:29:46.102319 <6>[ 1.824665] sdhci-pltfm: SDHCI platform and OF driver helper
650 00:29:46.156145 <6>[ 1.876937] ledtrig-cpu: registered to indicate activity on CPUs
651 00:29:46.220007 <6>[ 1.937638] usbcore: registered new interface driver usbhid
652 00:29:46.220396 <6>[ 1.943678] usbhid: USB HID core driver
653 00:29:46.250529 <6>[ 1.973976] NET: Registered PF_INET6 protocol family
654 00:29:46.322518 <6>[ 2.047822] Segment Routing with IPv6
655 00:29:46.328544 <6>[ 2.051967] In-situ OAM (IOAM) with IPv6
656 00:29:46.335180 <6>[ 2.056362] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
657 00:29:46.341188 <6>[ 2.063708] NET: Registered PF_PACKET protocol family
658 00:29:46.346883 <6>[ 2.069259] can: controller area network core
659 00:29:46.352576 <6>[ 2.074087] NET: Registered PF_CAN protocol family
660 00:29:46.352880 <6>[ 2.079313] can: raw protocol
661 00:29:46.358284 <6>[ 2.082638] can: broadcast manager protocol
662 00:29:46.364889 <6>[ 2.087232] can: netlink gateway - max_hops=1
663 00:29:46.371002 <5>[ 2.092702] Key type dns_resolver registered
664 00:29:46.377217 <6>[ 2.097763] ThumbEE CPU extension supported.
665 00:29:46.377613 <5>[ 2.102449] Registering SWP/SWPB emulation handler
666 00:29:46.387279 <3>[ 2.108140] omap_voltage_late_init: Voltage driver support not added
667 00:29:46.455950 <5>[ 2.178591] Loading compiled-in X.509 certificates
668 00:29:46.612751 <6>[ 2.325143] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
669 00:29:46.620142 <6>[ 2.341802] pinctrl-single 44e10800.pinmux: 142 pins, size 568
670 00:29:46.646395 <3>[ 2.365360] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
671 00:29:46.734430 <3>[ 2.454637] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
672 00:29:46.826629 <6>[ 2.550009] OMAP GPIO hardware version 0.1
673 00:29:46.847368 <6>[ 2.568677] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
674 00:29:46.907829 <4>[ 2.628959] at24 2-0054: supply vcc not found, using dummy regulator
675 00:29:46.973995 <4>[ 2.695296] at24 2-0055: supply vcc not found, using dummy regulator
676 00:29:47.009938 <4>[ 2.730997] at24 2-0056: supply vcc not found, using dummy regulator
677 00:29:47.097939 <4>[ 2.819794] at24 2-0057: supply vcc not found, using dummy regulator
678 00:29:47.141304 <6>[ 2.863187] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
679 00:29:47.218439 <3>[ 2.937115] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
680 00:29:47.243624 <6>[ 2.957793] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
681 00:29:47.264456 <4>[ 2.984257] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
682 00:29:47.297721 <4>[ 3.017545] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
683 00:29:47.372709 <6>[ 3.093976] omap_rng 48310000.rng: Random Number Generator ver. 20
684 00:29:47.395887 <5>[ 3.120009] random: crng init done
685 00:29:47.511094 <6>[ 3.230834] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
686 00:29:48.065306 <6>[ 3.789709] Freeing initrd memory: 14452K
687 00:29:48.109804 <6>[ 3.828832] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
688 00:29:48.115517 <6>[ 3.839052] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
689 00:29:48.127286 <6>[ 3.846317] cpsw-switch 4a100000.switch: ALE Table size 1024
690 00:29:48.132992 <6>[ 3.852722] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
691 00:29:48.144618 <6>[ 3.860856] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
692 00:29:48.151989 <6>[ 3.872486] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
693 00:29:48.164090 <5>[ 3.881518] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
694 00:29:48.191667 <3>[ 3.911121] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
695 00:29:48.197540 <6>[ 3.919687] edma 49000000.dma: TI EDMA DMA engine driver
696 00:29:48.267870 <3>[ 3.986577] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
697 00:29:48.281638 <6>[ 4.000907] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
698 00:29:48.299583 <3>[ 4.022474] l3-aon-clkctrl:0000:0: failed to disable
699 00:29:48.328487 <6>[ 4.047839] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
700 00:29:48.334101 <6>[ 4.057280] printk: legacy console [ttyS0] enabled
701 00:29:48.336873 <6>[ 4.057280] printk: legacy console [ttyS0] enabled
702 00:29:48.342333 <6>[ 4.067604] printk: legacy bootconsole [omap8250] disabled
703 00:29:48.348149 <6>[ 4.067604] printk: legacy bootconsole [omap8250] disabled
704 00:29:48.409237 <4>[ 4.127599] tps65217-pmic: Failed to locate of_node [id: -1]
705 00:29:48.412836 <4>[ 4.134987] tps65217-bl: Failed to locate of_node [id: -1]
706 00:29:48.428625 <6>[ 4.154235] tps65217 0-0024: TPS65217 ID 0xe version 1.2
707 00:29:48.447273 <6>[ 4.161172] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
708 00:29:48.458967 <6>[ 4.174864] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
709 00:29:48.464664 <6>[ 4.186747] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
710 00:29:48.487005 <6>[ 4.206602] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
711 00:29:48.492608 <6>[ 4.215844] sdhci-omap 48060000.mmc: Got CD GPIO
712 00:29:48.500904 <4>[ 4.221009] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
713 00:29:48.515552 <4>[ 4.234264] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
714 00:29:48.522330 <4>[ 4.243222] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
715 00:29:48.531931 <4>[ 4.252079] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
716 00:29:48.629518 <6>[ 4.350285] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
717 00:29:48.673078 <6>[ 4.392951] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
718 00:29:48.696691 <6>[ 4.415027] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
719 00:29:48.703410 <6>[ 4.424546] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
720 00:29:48.758718 <6>[ 4.473911] mmc1: new high speed MMC card at address 0001
721 00:29:48.759120 <6>[ 4.481903] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
722 00:29:48.772315 <6>[ 4.495058] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
723 00:29:48.783183 <6>[ 4.505944] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
724 00:29:48.795670 <6>[ 4.514346] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
725 00:29:48.804107 <6>[ 4.522309] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
726 00:29:48.828290 <6>[ 4.544590] mmc0: new high speed SDHC card at address aaaa
727 00:29:48.828680 <6>[ 4.551587] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
728 00:29:48.851395 <6>[ 4.574595] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
729 00:29:50.888405 <6>[ 6.607691] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
730 00:29:56.981555 <5>[ 6.666828] Sending DHCP requests ..., OK
731 00:29:56.992799 <6>[ 12.711331] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.5
732 00:29:56.993157 <6>[ 12.719751] IP-Config: Complete:
733 00:29:57.004167 <6>[ 12.723289] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.56.5, mask=255.255.255.0, gw=192.168.56.254
734 00:29:57.015437 <6>[ 12.734054] host=192.168.56.5, domain=mayfield.sirena.org.uk, nis-domain=(none)
735 00:29:57.021178 <6>[ 12.742179] bootserver=192.168.56.254, rootserver=192.168.56.193, rootpath=
736 00:29:57.026899 <6>[ 12.742211] nameserver0=192.168.56.254
737 00:29:57.033508 <6>[ 12.754470] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
738 00:29:57.039701 <6>[ 12.762078] clk: Disabling unused clocks
739 00:29:57.044491 <6>[ 12.766859] PM: genpd: Disabling unused power domains
740 00:29:57.064543 <6>[ 12.786375] Freeing unused kernel image (initmem) memory: 2048K
741 00:29:57.071089 <6>[ 12.796168] Run /init as init process
742 00:29:57.094372 Loading, please wait...
743 00:29:57.169011 Starting systemd-udevd version 252.22-1~deb12u1
744 00:30:00.069906 <4>[ 15.788487] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
745 00:30:00.209732 <4>[ 15.928280] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
746 00:30:00.373610 <6>[ 16.099686] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
747 00:30:00.384435 <6>[ 16.105359] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
748 00:30:00.493675 <6>[ 16.218280] hub 1-0:1.0: USB hub found
749 00:30:00.572417 <6>[ 16.296866] hub 1-0:1.0: 1 port detected
750 00:30:00.909608 <6>[ 16.633816] tda998x 0-0070: found TDA19988
751 00:30:03.853253 Begin: Loading essential drivers ... done.
752 00:30:03.858562 Begin: Running /scripts/init-premount ... done.
753 00:30:03.864547 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
754 00:30:03.874740 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
755 00:30:03.885458 Device /sys/class/net/eth0 found
756 00:30:03.885865 done.
757 00:30:03.943132 Begin: Waiting up to 180 secs for any network device to become available ... done.
758 00:30:04.014203 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
759 00:30:04.084258 IP-Config: eth0 complete (dhcp from 192.168.56.254):
760 00:30:04.095428 address: 192.168.56.5 broadcast: 192.168.56.255 netmask: 255.255.255.0
761 00:30:04.098657 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
762 00:30:04.112255 domain : mayfield.sirena.org.uk
763 00:30:04.112646 rootserver: 192.168.56.254 rootpath:
764 00:30:04.112856 filename :
765 00:30:04.216227 done.
766 00:30:04.225885 Begin: Running /scripts/nfs-bottom ... done.
767 00:30:04.288455 Begin: Running /scripts/init-bottom ... done.
768 00:30:05.650504 <30>[ 21.373008] systemd[1]: System time before build time, advancing clock.
769 00:30:05.803833 <30>[ 21.500333] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
770 00:30:05.812878 <30>[ 21.537394] systemd[1]: Detected architecture arm.
771 00:30:05.828272
772 00:30:05.828586 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
773 00:30:05.828801
774 00:30:05.865668 <30>[ 21.587953] systemd[1]: Hostname set to <debian-bookworm-armhf>.
775 00:30:08.249810 <30>[ 23.970683] systemd[1]: Queued start job for default target graphical.target.
776 00:30:08.268072 <30>[ 23.987212] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
777 00:30:08.275627 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
778 00:30:08.311083 <30>[ 24.029047] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
779 00:30:08.318231 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
780 00:30:08.354028 <30>[ 24.072504] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
781 00:30:08.361271 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
782 00:30:08.399044 <30>[ 24.118515] systemd[1]: Created slice user.slice - User and Session Slice.
783 00:30:08.405646 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
784 00:30:08.441942 <30>[ 24.158931] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
785 00:30:08.454111 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
786 00:30:08.488591 <30>[ 24.208037] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
787 00:30:08.498681 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
788 00:30:08.539550 <30>[ 24.247925] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
789 00:30:08.545770 <30>[ 24.268373] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
790 00:30:08.554368 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
791 00:30:08.587480 <30>[ 24.307138] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
792 00:30:08.595663 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
793 00:30:08.628118 <30>[ 24.347590] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
794 00:30:08.636605 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
795 00:30:08.668202 <30>[ 24.387750] systemd[1]: Reached target paths.target - Path Units.
796 00:30:08.673273 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
797 00:30:08.707802 <30>[ 24.427386] systemd[1]: Reached target remote-fs.target - Remote File Systems.
798 00:30:08.715157 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
799 00:30:08.747616 <30>[ 24.467213] systemd[1]: Reached target slices.target - Slice Units.
800 00:30:08.752867 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
801 00:30:08.789155 <30>[ 24.508173] systemd[1]: Reached target swap.target - Swaps.
802 00:30:08.793199 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
803 00:30:08.828434 <30>[ 24.548099] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
804 00:30:08.840675 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
805 00:30:08.869885 <30>[ 24.588284] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
806 00:30:08.876708 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
807 00:30:08.982563 <30>[ 24.697899] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
808 00:30:08.996337 <30>[ 24.715675] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
809 00:30:09.004769 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
810 00:30:09.039148 <30>[ 24.760942] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
811 00:30:09.051408 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
812 00:30:09.091587 <30>[ 24.810612] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
813 00:30:09.099625 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
814 00:30:09.133501 <30>[ 24.852614] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
815 00:30:09.139105 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
816 00:30:09.180158 <30>[ 24.900290] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
817 00:30:09.191849 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
818 00:30:09.235445 <30>[ 24.948564] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
819 00:30:09.251954 <30>[ 24.965259] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
820 00:30:09.287729 <30>[ 25.009210] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
821 00:30:09.307803 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
822 00:30:09.415474 <30>[ 25.135525] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
823 00:30:09.428270 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
824 00:30:09.473462 <30>[ 25.193538] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
825 00:30:09.506587 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
826 00:30:09.577534 <30>[ 25.298049] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
827 00:30:09.589147 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
828 00:30:09.657337 <30>[ 25.377759] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
829 00:30:09.674151 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
830 00:30:09.708049 <30>[ 25.429579] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
831 00:30:09.737385 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
832 00:30:09.800345 <30>[ 25.519994] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
833 00:30:09.812118 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
834 00:30:09.837477 <30>[ 25.557187] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
835 00:30:09.844984 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
836 00:30:09.927138 <30>[ 25.647878] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
837 00:30:09.940025 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
838 00:30:09.986267 <28>[ 25.700731] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
839 00:30:09.994753 <28>[ 25.714378] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
840 00:30:10.032692 <30>[ 25.753662] systemd[1]: Starting systemd-journald.service - Journal Service...
841 00:30:10.057364 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
842 00:30:10.140386 <30>[ 25.860873] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
843 00:30:10.167998 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
844 00:30:10.221963 <30>[ 25.942349] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
845 00:30:10.263089 Starting [0;1;39msystemd-network-g… units from Kernel command line...
846 00:30:10.342412 <30>[ 26.061377] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
847 00:30:10.392390 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
848 00:30:10.459420 <30>[ 26.179415] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
849 00:30:10.507315 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
850 00:30:10.580258 <30>[ 26.300725] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
851 00:30:10.608454 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
852 00:30:10.638253 <30>[ 26.358844] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
853 00:30:10.668500 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
854 00:30:10.700102 <30>[ 26.419523] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
855 00:30:10.730984 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
856 00:30:10.888927 <30>[ 26.610035] systemd[1]: Started systemd-journald.service - Journal Service.
857 00:30:10.915701 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
858 00:30:10.969109 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
859 00:30:11.007819 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
860 00:30:11.027565 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
861 00:30:11.063301 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
862 00:30:11.108812 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
863 00:30:11.148838 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
864 00:30:11.197790 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
865 00:30:11.229965 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
866 00:30:11.267665 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
867 00:30:11.301990 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
868 00:30:11.366864 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
869 00:30:11.440635 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
870 00:30:11.519368 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
871 00:30:11.604980 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
872 00:30:11.690394 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
873 00:30:11.772130 <46>[ 27.492571] systemd-journald[165]: Received client request to flush runtime journal.
874 00:30:11.805521 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
875 00:30:11.997458 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
876 00:30:12.611361 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
877 00:30:13.189474 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
878 00:30:13.270818 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
879 00:30:13.579172 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
880 00:30:13.830228 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
881 00:30:13.868450 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
882 00:30:13.908631 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
883 00:30:13.989874 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
884 00:30:14.056518 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
885 00:30:15.021592 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
886 00:30:15.113790 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
887 00:30:15.459797 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
888 00:30:15.489046 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
889 00:30:15.607864 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
890 00:30:15.687352 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
891 00:30:17.697717 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
892 00:30:18.139947 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
893 00:30:18.199215 <5>[ 33.919760] cfg80211: Loading compiled-in X.509 certificates for regulatory database
894 00:30:19.419409 <5>[ 35.142076] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
895 00:30:19.507511 <5>[ 35.229016] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
896 00:30:19.533923 <4>[ 35.254380] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
897 00:30:19.539757 <6>[ 35.263496] cfg80211: failed to load regulatory.db
898 00:30:19.890116 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
899 00:30:19.962775 <46>[ 35.674244] systemd-journald[165]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
900 00:30:20.185903 <46>[ 35.899906] systemd-journald[165]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
901 00:30:20.622543 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
902 00:30:29.485418 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
903 00:30:29.516890 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
904 00:30:29.551557 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
905 00:30:29.587304 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
906 00:30:29.678561 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
907 00:30:29.747572 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
908 00:30:29.798870 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
909 00:30:29.849331 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
910 00:30:29.915974 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
911 00:30:29.953538 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
912 00:30:30.001545 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
913 00:30:30.063559 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
914 00:30:30.085141 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
915 00:30:30.131044 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
916 00:30:30.177029 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
917 00:30:30.209887 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
918 00:30:30.245536 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
919 00:30:30.285368 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
920 00:30:30.324362 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
921 00:30:30.355917 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
922 00:30:30.398249 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
923 00:30:30.427313 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
924 00:30:30.462319 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
925 00:30:30.542537 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
926 00:30:30.594909 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
927 00:30:30.717230 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
928 00:30:30.827780 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
929 00:30:30.907041 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
930 00:30:30.961371 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
931 00:30:30.996966 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
932 00:30:31.181192 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
933 00:30:31.205586 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
934 00:30:31.337392 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
935 00:30:31.410366 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
936 00:30:31.455671 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
937 00:30:31.586463 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
938 00:30:31.636630 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
939 00:30:32.108206 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
940 00:30:32.411280 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
941 00:30:32.486291 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
942 00:30:32.532132 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
943 00:30:32.608375 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
944 00:30:32.803823 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
945 00:30:32.947342
946 00:30:32.947651 Debian GNU/Linux 1worm-armhf login: root (automatic login)
947 00:30:32.950614
948 00:30:33.274443 Linux debian-bookworm-armhf 6.11.0-rc5 #1 SMP Sat Aug 31 23:24:39 UTC 2024 armv7l
949 00:30:33.274731
950 00:30:33.280131 The programs included with the Debian GNU/Linux system are free software;
951 00:30:33.285640 the exact distribution terms for each program are described in the
952 00:30:33.291365 individual files in /usr/share/doc/*/copyright.
953 00:30:33.291579
954 00:30:33.298681 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
955 00:30:33.298981 permitted by applicable law.
956 00:30:38.453981 Unable to match end of the kernel message
958 00:30:38.454474 Setting prompt string to ['/ #']
959 00:30:38.454651 end: 2.4.4.1 login-action (duration 00:00:55) [common]
961 00:30:38.455024 end: 2.4.4 auto-login-action (duration 00:00:55) [common]
962 00:30:38.455181 start: 2.4.5 expect-shell-connection (timeout 00:03:05) [common]
963 00:30:38.455302 Setting prompt string to ['/ #']
964 00:30:38.455413 Forcing a shell prompt, looking for ['/ #']
966 00:30:38.505719 / #
967 00:30:38.506126 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
968 00:30:38.506312 Waiting using forced prompt support (timeout 00:02:30)
969 00:30:38.509756
970 00:30:38.516778 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
971 00:30:38.517051 start: 2.4.6 export-device-env (timeout 00:03:05) [common]
972 00:30:38.517209 Sending with 10 millisecond of delay
974 00:30:43.509277 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws'
975 00:30:43.520167 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/683574/extract-nfsrootfs-1cc8o2ws'
976 00:30:43.521142 Sending with 10 millisecond of delay
978 00:30:45.816362 / # export NFS_SERVER_IP='192.168.56.193'
979 00:30:45.826974 export NFS_SERVER_IP='192.168.56.193'
980 00:30:45.827546 end: 2.4.6 export-device-env (duration 00:00:07) [common]
981 00:30:45.827786 end: 2.4 uboot-commands (duration 00:02:02) [common]
982 00:30:45.828020 end: 2 uboot-action (duration 00:02:02) [common]
983 00:30:45.828225 start: 3 lava-test-retry (timeout 00:07:29) [common]
984 00:30:45.828445 start: 3.1 lava-test-shell (timeout 00:07:29) [common]
985 00:30:45.828626 Using namespace: common
987 00:30:45.929742 / # #
988 00:30:45.930235 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
989 00:30:45.935312 #
990 00:30:45.941350 Using /lava-683574
992 00:30:46.042724 / # export SHELL=/bin/bash
993 00:30:46.048372 export SHELL=/bin/bash
995 00:30:46.154056 / # . /lava-683574/environment
996 00:30:46.159244 . /lava-683574/environment
998 00:30:46.272481 / # /lava-683574/bin/lava-test-runner /lava-683574/0
999 00:30:46.272940 Test shell timeout: 10s (minimum of the action and connection timeout)
1000 00:30:46.277763 /lava-683574/bin/lava-test-runner /lava-683574/0
1001 00:30:46.723101 + export TESTRUN_ID=0_timesync-off
1002 00:30:46.730960 + TESTRUN_ID=0_timesync-off
1003 00:30:46.731202 + cd /lava-683574/0/tests/0_timesync-off
1004 00:30:46.731362 ++ cat uuid
1005 00:30:46.745035 + UUID=683574_1.6.2.4.1
1006 00:30:46.745272 + set +x
1007 00:30:46.753595 <LAVA_SIGNAL_STARTRUN 0_timesync-off 683574_1.6.2.4.1>
1008 00:30:46.753825 + systemctl stop systemd-timesyncd
1009 00:30:46.754207 Received signal: <STARTRUN> 0_timesync-off 683574_1.6.2.4.1
1010 00:30:46.754371 Starting test lava.0_timesync-off (683574_1.6.2.4.1)
1011 00:30:46.754572 Skipping test definition patterns.
1012 00:30:47.056338 + set +x
1013 00:30:47.056640 <LAVA_SIGNAL_ENDRUN 0_timesync-off 683574_1.6.2.4.1>
1014 00:30:47.057007 Received signal: <ENDRUN> 0_timesync-off 683574_1.6.2.4.1
1015 00:30:47.057191 Ending use of test pattern.
1016 00:30:47.057333 Ending test lava.0_timesync-off (683574_1.6.2.4.1), duration 0.30
1018 00:30:47.216188 + export TESTRUN_ID=1_kselftest-dt
1019 00:30:47.224061 + TESTRUN_ID=1_kselftest-dt
1020 00:30:47.224286 + cd /lava-683574/0/tests/1_kselftest-dt
1021 00:30:47.224445 ++ cat uuid
1022 00:30:47.238530 + UUID=683574_1.6.2.4.5
1023 00:30:47.238834 + set +x
1024 00:30:47.244058 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 683574_1.6.2.4.5>
1025 00:30:47.244366 + cd ./automated/linux/kselftest/
1026 00:30:47.244742 Received signal: <STARTRUN> 1_kselftest-dt 683574_1.6.2.4.5
1027 00:30:47.244898 Starting test lava.1_kselftest-dt (683574_1.6.2.4.5)
1028 00:30:47.245077 Skipping test definition patterns.
1029 00:30:47.272102 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1030 00:30:47.404492 INFO: install_deps skipped
1031 00:30:48.056636 --2024-09-01 00:30:48-- http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1032 00:30:48.079639 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1033 00:30:48.220753 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1034 00:30:48.362623 HTTP request sent, awaiting response... 200 OK
1035 00:30:48.362961 Length: 3606188 (3.4M) [application/octet-stream]
1036 00:30:48.368285 Saving to: 'kselftest_armhf.tar.gz'
1037 00:30:48.368678
1038 00:30:50.580940
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 5%[> ] 194.76K 348KB/s
kselftest_armhf.tar 18%[==> ] 643.79K 728KB/s
kselftest_armhf.tar 28%[====> ] 1016K 915KB/s
kselftest_armhf.tar 35%[======> ] 1.22M 935KB/s
kselftest_armhf.tar 53%[=========> ] 1.83M 1.19MB/s
kselftest_armhf.tar 66%[============> ] 2.27M 1.31MB/s
kselftest_armhf.tar 80%[===============> ] 2.77M 1.42MB/s
kselftest_armhf.tar 95%[==================> ] 3.28M 1.52MB/s
kselftest_armhf.tar 100%[===================>] 3.44M 1.55MB/s in 2.2s
1039 00:30:50.581272
1040 00:30:51.104164 2024-09-01 00:30:50 (1.55 MB/s) - 'kselftest_armhf.tar.gz' saved [3606188/3606188]
1041 00:30:51.104468
1042 00:31:06.797556 skiplist:
1043 00:31:06.797893 ========================================
1044 00:31:06.802685 ========================================
1045 00:31:06.902901 dt:test_unprobed_devices.sh
1046 00:31:06.934397 ============== Tests to run ===============
1047 00:31:06.943131 dt:test_unprobed_devices.sh
1048 00:31:06.947104 ===========End Tests to run ===============
1049 00:31:06.959025 shardfile-dt pass
1050 00:31:07.199559 <12>[ 82.925110] kselftest: Running tests in dt
1051 00:31:07.226686 TAP version 13
1052 00:31:07.254586 1..1
1053 00:31:07.312279 # timeout set to 45
1054 00:31:07.312582 # selftests: dt: test_unprobed_devices.sh
1055 00:31:08.139986 # TAP version 13
1056 00:31:20.493457 # 1..255
1057 00:31:20.666939 # ok 1 / # SKIP
1058 00:31:20.689859 # ok 2 /clk_mcasp0
1059 00:31:20.765600 # ok 3 /clk_mcasp0_fixed # SKIP
1060 00:31:20.841118 # ok 4 /cpus/cpu@0 # SKIP
1061 00:31:20.922329 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1062 00:31:20.947267 # ok 6 /fixedregulator0
1063 00:31:20.971605 # ok 7 /leds
1064 00:31:20.989397 # ok 8 /ocp
1065 00:31:21.013024 # ok 9 /ocp/interconnect@44c00000
1066 00:31:21.036684 # ok 10 /ocp/interconnect@44c00000/segment@0
1067 00:31:21.064659 # ok 11 /ocp/interconnect@44c00000/segment@100000
1068 00:31:21.088792 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1069 00:31:21.171025 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1070 00:31:21.192422 # ok 14 /ocp/interconnect@44c00000/segment@200000
1071 00:31:21.211854 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1072 00:31:21.330639 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1073 00:31:21.406238 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1074 00:31:21.474435 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1075 00:31:21.553466 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1076 00:31:21.632083 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1077 00:31:21.706240 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1078 00:31:21.783513 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1079 00:31:21.865201 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1080 00:31:21.934570 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1081 00:31:22.016951 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1082 00:31:22.092963 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1083 00:31:22.178916 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1084 00:31:22.254421 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1085 00:31:22.331028 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1086 00:31:22.405811 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1087 00:31:22.474826 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1088 00:31:22.557321 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1089 00:31:22.637172 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1090 00:31:22.712838 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1091 00:31:22.792984 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1092 00:31:22.865995 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1093 00:31:22.951112 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1094 00:31:23.032074 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1095 00:31:23.104415 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1096 00:31:23.183897 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1097 00:31:23.253814 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1098 00:31:23.333987 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1099 00:31:23.404155 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1100 00:31:23.485249 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1101 00:31:23.550945 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1102 00:31:23.633812 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1103 00:31:23.714887 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1104 00:31:23.788071 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1105 00:31:23.864958 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1106 00:31:23.935730 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1107 00:31:24.009262 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1108 00:31:24.094885 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1109 00:31:24.162728 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1110 00:31:24.239225 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1111 00:31:24.316895 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1112 00:31:24.396492 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1113 00:31:24.474193 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1114 00:31:24.546087 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1115 00:31:24.619074 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1116 00:31:24.695530 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1117 00:31:24.767952 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1118 00:31:24.846037 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1119 00:31:24.915539 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1120 00:31:24.999053 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1121 00:31:25.077296 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1122 00:31:25.151961 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1123 00:31:25.228332 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1124 00:31:25.306226 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1125 00:31:25.379115 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1126 00:31:25.459909 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1127 00:31:25.535921 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1128 00:31:25.608415 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1129 00:31:25.678599 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1130 00:31:25.758563 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1131 00:31:25.828377 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1132 00:31:25.912224 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1133 00:31:25.986326 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1134 00:31:26.062118 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1135 00:31:26.140146 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1136 00:31:26.217544 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1137 00:31:26.292056 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1138 00:31:26.364417 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1139 00:31:26.443128 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1140 00:31:26.523661 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1141 00:31:26.596406 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1142 00:31:26.668332 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1143 00:31:26.750753 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1144 00:31:26.826761 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1145 00:31:26.903850 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1146 00:31:26.976667 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1147 00:31:27.056983 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1148 00:31:27.126711 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1149 00:31:27.203707 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1150 00:31:27.266996 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1151 00:31:27.294077 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1152 00:31:27.310181 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1153 00:31:27.340117 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1154 00:31:27.356180 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1155 00:31:27.380756 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1156 00:31:27.410371 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1157 00:31:27.431658 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1158 00:31:27.453052 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1159 00:31:27.548529 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1160 00:31:27.577923 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1161 00:31:27.603986 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1162 00:31:27.619958 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1163 00:31:27.725209 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1164 00:31:27.796073 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1165 00:31:27.866477 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1166 00:31:27.930209 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1167 00:31:28.006463 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1168 00:31:28.075105 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1169 00:31:28.145953 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1170 00:31:28.215736 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1171 00:31:28.283906 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1172 00:31:28.353692 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1173 00:31:28.423591 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1174 00:31:28.494647 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1175 00:31:28.564113 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1176 00:31:28.628162 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1177 00:31:28.704458 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1178 00:31:28.767404 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1179 00:31:28.793951 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1180 00:31:28.863171 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1181 00:31:28.922271 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1182 00:31:28.996496 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1183 00:31:29.020183 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1184 00:31:29.088124 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1185 00:31:29.109952 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1186 00:31:29.180714 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1187 00:31:29.200389 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1188 00:31:29.223479 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1189 00:31:29.240804 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1190 00:31:29.270605 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1191 00:31:29.289685 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1192 00:31:29.310636 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1193 00:31:29.340459 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1194 00:31:29.364979 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1195 00:31:29.379426 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1196 00:31:29.452672 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1197 00:31:29.524118 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1198 00:31:29.545374 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1199 00:31:29.612203 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1200 00:31:29.684904 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1201 00:31:29.778279 # not ok 145 /ocp/interconnect@47c00000
1202 00:31:29.845011 # not ok 146 /ocp/interconnect@47c00000/segment@0
1203 00:31:29.865834 # ok 147 /ocp/interconnect@48000000
1204 00:31:29.894831 # ok 148 /ocp/interconnect@48000000/segment@0
1205 00:31:29.917397 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1206 00:31:29.940116 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1207 00:31:29.960758 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1208 00:31:29.986520 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1209 00:31:30.003894 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1210 00:31:30.033151 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1211 00:31:30.049171 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1212 00:31:30.120429 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1213 00:31:30.192761 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1214 00:31:30.214654 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1215 00:31:30.240050 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1216 00:31:30.263208 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1217 00:31:30.278836 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1218 00:31:30.304393 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1219 00:31:30.331001 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1220 00:31:30.353192 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1221 00:31:30.372996 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1222 00:31:30.396870 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1223 00:31:30.420140 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1224 00:31:30.441041 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1225 00:31:30.468954 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1226 00:31:30.490454 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1227 00:31:30.511612 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1228 00:31:30.530801 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1229 00:31:30.560136 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1230 00:31:30.577843 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1231 00:31:30.606573 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1232 00:31:30.627644 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1233 00:31:30.648149 # ok 177 /ocp/interconnect@48000000/segment@100000
1234 00:31:30.667663 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1235 00:31:30.695462 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1236 00:31:30.763212 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1237 00:31:30.835425 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1238 00:31:30.897461 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1239 00:31:30.972074 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1240 00:31:30.991026 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1241 00:31:31.008563 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1242 00:31:31.036062 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1243 00:31:31.060095 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1244 00:31:31.076391 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1245 00:31:31.102497 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1246 00:31:31.129882 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1247 00:31:31.151554 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1248 00:31:31.172267 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1249 00:31:31.192149 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1250 00:31:31.219658 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1251 00:31:31.243478 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1252 00:31:31.258771 # ok 196 /ocp/interconnect@48000000/segment@200000
1253 00:31:31.287599 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1254 00:31:31.357260 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1255 00:31:31.378187 # ok 199 /ocp/interconnect@48000000/segment@300000
1256 00:31:31.394932 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1257 00:31:31.421696 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1258 00:31:31.442177 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1259 00:31:31.468983 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1260 00:31:31.492631 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1261 00:31:31.509293 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1262 00:31:31.580621 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1263 00:31:31.599534 # ok 207 /ocp/interconnect@4a000000
1264 00:31:31.623442 # ok 208 /ocp/interconnect@4a000000/segment@0
1265 00:31:31.646661 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1266 00:31:31.669861 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1267 00:31:31.694428 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1268 00:31:31.717709 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1269 00:31:31.794109 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1270 00:31:31.888670 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1271 00:31:31.962345 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1272 00:31:32.061003 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1273 00:31:32.130499 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1274 00:31:32.199131 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1275 00:31:32.290785 # not ok 219 /ocp/interconnect@4b140000
1276 00:31:32.354179 # not ok 220 /ocp/interconnect@4b140000/segment@0
1277 00:31:32.421032 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1278 00:31:32.445984 # ok 222 /ocp/target-module@40300000
1279 00:31:32.467630 # ok 223 /ocp/target-module@40300000/sram@0
1280 00:31:32.538512 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1281 00:31:32.609920 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1282 00:31:32.626389 # ok 226 /ocp/target-module@47400000
1283 00:31:32.648831 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1284 00:31:32.668476 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1285 00:31:32.693259 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1286 00:31:32.715567 # ok 230 /ocp/target-module@47400000/usb@1400
1287 00:31:32.737644 # ok 231 /ocp/target-module@47400000/usb@1800
1288 00:31:32.753864 # ok 232 /ocp/target-module@47810000
1289 00:31:32.777766 # ok 233 /ocp/target-module@49000000
1290 00:31:32.802631 # ok 234 /ocp/target-module@49000000/dma@0
1291 00:31:32.824331 # ok 235 /ocp/target-module@49800000
1292 00:31:32.844430 # ok 236 /ocp/target-module@49800000/dma@0
1293 00:31:32.866781 # ok 237 /ocp/target-module@49900000
1294 00:31:32.888387 # ok 238 /ocp/target-module@49900000/dma@0
1295 00:31:32.907129 # ok 239 /ocp/target-module@49a00000
1296 00:31:32.926441 # ok 240 /ocp/target-module@49a00000/dma@0
1297 00:31:32.949433 # ok 241 /ocp/target-module@4c000000
1298 00:31:33.015984 # not ok 242 /ocp/target-module@4c000000/emif@0
1299 00:31:33.042624 # ok 243 /ocp/target-module@50000000
1300 00:31:33.059677 # ok 244 /ocp/target-module@53100000
1301 00:31:33.127813 # not ok 245 /ocp/target-module@53100000/sham@0
1302 00:31:33.147938 # ok 246 /ocp/target-module@53500000
1303 00:31:33.216400 # not ok 247 /ocp/target-module@53500000/aes@0
1304 00:31:33.244375 # ok 248 /ocp/target-module@56000000
1305 00:31:33.338769 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1306 00:31:33.408813 # ok 250 /opp-table # SKIP
1307 00:31:33.469928 # ok 251 /soc # SKIP
1308 00:31:33.490470 # ok 252 /sound
1309 00:31:33.517127 # ok 253 /target-module@4b000000
1310 00:31:33.538440 # ok 254 /target-module@4b000000/target-module@140000
1311 00:31:33.559913 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1312 00:31:33.567175 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1313 00:31:33.576133 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1314 00:31:35.686395 dt_test_unprobed_devices_sh_ skip
1315 00:31:35.692060 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1316 00:31:35.697611 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1317 00:31:35.697842 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1318 00:31:35.703172 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1319 00:31:35.709129 dt_test_unprobed_devices_sh_fixedregulator0 pass
1320 00:31:35.714472 dt_test_unprobed_devices_sh_leds pass
1321 00:31:35.714692 dt_test_unprobed_devices_sh_ocp pass
1322 00:31:35.719980 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1323 00:31:35.725732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1324 00:31:35.731377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1325 00:31:35.742590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1326 00:31:35.748165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1327 00:31:35.753856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1328 00:31:35.764758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1329 00:31:35.770468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1330 00:31:35.781667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1331 00:31:35.792996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1332 00:31:35.804111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1333 00:31:35.809799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1334 00:31:35.820891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1335 00:31:35.832172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1336 00:31:35.843357 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1337 00:31:35.854507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1338 00:31:35.860127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1339 00:31:35.871271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1340 00:31:35.882466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1341 00:31:35.893772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1342 00:31:35.904869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1343 00:31:35.910518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1344 00:31:35.921646 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1345 00:31:35.932896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1346 00:31:35.944042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1347 00:31:35.949658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1348 00:31:35.960776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1349 00:31:35.972162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1350 00:31:35.983199 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1351 00:31:35.994382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1352 00:31:36.000002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1353 00:31:36.011154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1354 00:31:36.022340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1355 00:31:36.033462 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1356 00:31:36.045070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1357 00:31:36.055900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1358 00:31:36.067127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1359 00:31:36.078285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1360 00:31:36.089388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1361 00:31:36.100574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1362 00:31:36.111779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1363 00:31:36.122944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1364 00:31:36.134168 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1365 00:31:36.145355 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1366 00:31:36.156550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1367 00:31:36.167784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1368 00:31:36.178961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1369 00:31:36.190125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1370 00:31:36.201282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1371 00:31:36.212470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1372 00:31:36.223899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1373 00:31:36.234873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1374 00:31:36.246062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1375 00:31:36.257262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1376 00:31:36.268552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1377 00:31:36.279623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1378 00:31:36.285237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1379 00:31:36.296420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1380 00:31:36.307619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1381 00:31:36.318877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1382 00:31:36.330003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1383 00:31:36.341229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1384 00:31:36.352379 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1385 00:31:36.363576 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1386 00:31:36.374742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1387 00:31:36.385977 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1388 00:31:36.397163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1389 00:31:36.408338 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1390 00:31:36.419558 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1391 00:31:36.430839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1392 00:31:36.442095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1393 00:31:36.453165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1394 00:31:36.464367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1395 00:31:36.475579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1396 00:31:36.481175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1397 00:31:36.492609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1398 00:31:36.503536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1399 00:31:36.514849 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1400 00:31:36.525994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1401 00:31:36.531590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1402 00:31:36.548363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1403 00:31:36.559559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1404 00:31:36.565182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1405 00:31:36.582004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1406 00:31:36.593197 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1407 00:31:36.604387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1408 00:31:36.609956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1409 00:31:36.621279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1410 00:31:36.632472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1411 00:31:36.638053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1412 00:31:36.649122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1413 00:31:36.660399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1414 00:31:36.666008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1415 00:31:36.677073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1416 00:31:36.682626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1417 00:31:36.693858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1418 00:31:36.705060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1419 00:31:36.716240 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1420 00:31:36.727384 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1421 00:31:36.738615 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1422 00:31:36.749788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1423 00:31:36.761189 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1424 00:31:36.772216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1425 00:31:36.783585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1426 00:31:36.794976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1427 00:31:36.805916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1428 00:31:36.817004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1429 00:31:36.833915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1430 00:31:36.845351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1431 00:31:36.856393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1432 00:31:36.867505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1433 00:31:36.878746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1434 00:31:36.895328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1435 00:31:36.906622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1436 00:31:36.917703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1437 00:31:36.928989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1438 00:31:36.934902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1439 00:31:36.945706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1440 00:31:36.956942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1441 00:31:36.962862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1442 00:31:36.973672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1443 00:31:36.979615 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1444 00:31:36.990581 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1445 00:31:36.996163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1446 00:31:37.007503 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1447 00:31:37.012769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1448 00:31:37.024167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1449 00:31:37.029758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1450 00:31:37.040996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1451 00:31:37.052099 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1452 00:31:37.063217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1453 00:31:37.068952 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1454 00:31:37.080191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1455 00:31:37.091219 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1456 00:31:37.096859 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1457 00:31:37.108061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1458 00:31:37.113750 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1459 00:31:37.119322 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1460 00:31:37.124902 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1461 00:31:37.130365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1462 00:31:37.141766 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1463 00:31:37.147100 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1464 00:31:37.152846 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1465 00:31:37.163998 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1466 00:31:37.169769 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1467 00:31:37.180924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1468 00:31:37.186395 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1469 00:31:37.197713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1470 00:31:37.203426 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1471 00:31:37.208777 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1472 00:31:37.219963 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1473 00:31:37.225645 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1474 00:31:37.236727 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1475 00:31:37.242597 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1476 00:31:37.253916 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1477 00:31:37.259104 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1478 00:31:37.270237 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1479 00:31:37.275905 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1480 00:31:37.287109 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1481 00:31:37.292785 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1482 00:31:37.303885 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1483 00:31:37.309532 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1484 00:31:37.320792 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1485 00:31:37.326630 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1486 00:31:37.331880 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1487 00:31:37.343354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1488 00:31:37.348637 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1489 00:31:37.359840 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1490 00:31:37.365354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1491 00:31:37.376964 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1492 00:31:37.382218 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1493 00:31:37.393515 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1494 00:31:37.404666 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1495 00:31:37.415770 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1496 00:31:37.421427 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1497 00:31:37.432565 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1498 00:31:37.438448 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1499 00:31:37.449392 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1500 00:31:37.454914 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1501 00:31:37.466365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1502 00:31:37.471767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1503 00:31:37.482945 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1504 00:31:37.494440 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1505 00:31:37.499765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1506 00:31:37.511199 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1507 00:31:37.516415 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1508 00:31:37.527695 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1509 00:31:37.533180 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1510 00:31:37.539104 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1511 00:31:37.549992 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1512 00:31:37.555705 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1513 00:31:37.561245 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1514 00:31:37.572528 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1515 00:31:37.577966 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1516 00:31:37.589251 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1517 00:31:37.594754 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1518 00:31:37.605949 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1519 00:31:37.611678 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1520 00:31:37.617170 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1521 00:31:37.622846 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1522 00:31:37.634310 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1523 00:31:37.639735 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1524 00:31:37.650864 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1525 00:31:37.656348 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1526 00:31:37.667665 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1527 00:31:37.678817 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1528 00:31:37.690012 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1529 00:31:37.695895 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1530 00:31:37.706923 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1531 00:31:37.718303 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1532 00:31:37.723825 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1533 00:31:37.729150 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1534 00:31:37.734700 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1535 00:31:37.740338 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1536 00:31:37.745918 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1537 00:31:37.751858 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1538 00:31:37.762773 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1539 00:31:37.768508 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1540 00:31:37.774151 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1541 00:31:37.779888 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1542 00:31:37.785176 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1543 00:31:37.790769 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1544 00:31:37.796532 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1545 00:31:37.802086 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1546 00:31:37.807589 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1547 00:31:37.813282 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1548 00:31:37.818902 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1549 00:31:37.824495 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1550 00:31:37.829891 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1551 00:31:37.835680 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1552 00:31:37.841339 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1553 00:31:37.846946 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1554 00:31:37.852517 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1555 00:31:37.858292 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1556 00:31:37.863722 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1557 00:31:37.869292 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1558 00:31:37.874975 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1559 00:31:37.880454 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1560 00:31:37.886505 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1561 00:31:37.891713 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1562 00:31:37.897369 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1563 00:31:37.902809 dt_test_unprobed_devices_sh_opp-table skip
1564 00:31:37.908506 dt_test_unprobed_devices_sh_soc skip
1565 00:31:37.908725 dt_test_unprobed_devices_sh_sound pass
1566 00:31:37.913954 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1567 00:31:37.919691 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1568 00:31:37.930835 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1569 00:31:37.931107 dt_test_unprobed_devices_sh fail
1570 00:31:37.936522 + ../../utils/send-to-lava.sh ./output/result.txt
1571 00:31:37.940978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1572 00:31:37.941473 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1574 00:31:37.968670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1575 00:31:37.969178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1577 00:31:38.053552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1578 00:31:38.053988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1580 00:31:38.142916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1581 00:31:38.143330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1583 00:31:38.228699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1584 00:31:38.229203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1586 00:31:38.317163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1587 00:31:38.317623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1589 00:31:38.401361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1590 00:31:38.401828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1592 00:31:38.491119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1593 00:31:38.491621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1595 00:31:38.576053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1596 00:31:38.576604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1598 00:31:38.664627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1599 00:31:38.665071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1601 00:31:38.754271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1602 00:31:38.754715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1604 00:31:38.840061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1605 00:31:38.840498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1607 00:31:38.922695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1608 00:31:38.923223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1610 00:31:39.013082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1611 00:31:39.013646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1613 00:31:39.097530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1614 00:31:39.098078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1616 00:31:39.189236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1617 00:31:39.189825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1619 00:31:39.281280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1620 00:31:39.281770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1622 00:31:39.365298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1623 00:31:39.365835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1625 00:31:39.454116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1626 00:31:39.454614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1628 00:31:39.542081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1629 00:31:39.542576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1631 00:31:39.626656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1632 00:31:39.627140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1634 00:31:39.712703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1635 00:31:39.713143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1637 00:31:39.801084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1638 00:31:39.801593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1640 00:31:39.887307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1641 00:31:39.887734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1643 00:31:39.976971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1644 00:31:39.977464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1646 00:31:40.063852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1647 00:31:40.064285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1649 00:31:40.148888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1650 00:31:40.149248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1652 00:31:40.235811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1653 00:31:40.236239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1655 00:31:40.321845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1656 00:31:40.322273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1658 00:31:40.401654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1659 00:31:40.402143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1661 00:31:40.481517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1662 00:31:40.482062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1664 00:31:40.567675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1665 00:31:40.568201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1667 00:31:40.653992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1668 00:31:40.654486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1670 00:31:40.742403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1671 00:31:40.742923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1673 00:31:40.826644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1674 00:31:40.827130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1676 00:31:40.913666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1677 00:31:40.914132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1679 00:31:41.003302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1680 00:31:41.003628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1682 00:31:41.095088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1683 00:31:41.095598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1685 00:31:41.181000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1686 00:31:41.181513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1688 00:31:41.268771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1689 00:31:41.269281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1691 00:31:41.359350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1692 00:31:41.359834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1694 00:31:41.456533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1695 00:31:41.456959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1697 00:31:41.542479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1698 00:31:41.543006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1700 00:31:41.629615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1701 00:31:41.630059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1703 00:31:41.718143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1704 00:31:41.718631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1706 00:31:41.804432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1707 00:31:41.804937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1709 00:31:41.893009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1710 00:31:41.893503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1712 00:31:41.985226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1713 00:31:41.985666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1715 00:31:42.076909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1716 00:31:42.077359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1718 00:31:42.164514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1719 00:31:42.165002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1721 00:31:42.251347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1722 00:31:42.251788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1724 00:31:42.341755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1725 00:31:42.342277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1727 00:31:42.428832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1728 00:31:42.429327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1730 00:31:42.517839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1731 00:31:42.518264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1733 00:31:42.607550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1734 00:31:42.608046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1736 00:31:42.696894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1737 00:31:42.697381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1739 00:31:42.783493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1740 00:31:42.783986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1742 00:31:42.872338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1743 00:31:42.872709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1745 00:31:42.956600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1746 00:31:42.957118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1748 00:31:43.046657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1749 00:31:43.047097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1751 00:31:43.133555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1752 00:31:43.134070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1754 00:31:43.220572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1755 00:31:43.221000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1757 00:31:43.308511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1758 00:31:43.308968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1760 00:31:43.395419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1761 00:31:43.395858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1763 00:31:43.485834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1764 00:31:43.486261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1766 00:31:43.569951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1767 00:31:43.570374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1769 00:31:43.656129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1770 00:31:43.656561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1772 00:31:43.747760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1773 00:31:43.748190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1775 00:31:43.832947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1776 00:31:43.833430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1778 00:31:43.918850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1779 00:31:43.919283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1781 00:31:44.005597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1782 00:31:44.006024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1784 00:31:44.088132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1785 00:31:44.088559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1787 00:31:44.176083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1788 00:31:44.176506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1790 00:31:44.263828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1791 00:31:44.264249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1793 00:31:44.350619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1794 00:31:44.351043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1796 00:31:44.437479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1797 00:31:44.437997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1799 00:31:44.523629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1800 00:31:44.524130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1802 00:31:44.614174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1803 00:31:44.614599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1805 00:31:44.698211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1806 00:31:44.698705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1808 00:31:44.786346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1809 00:31:44.786833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1811 00:31:44.872167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1812 00:31:44.872653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1814 00:31:44.960838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1815 00:31:44.961323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1817 00:31:45.046533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1818 00:31:45.046977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1820 00:31:45.126836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1821 00:31:45.127342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1823 00:31:45.218013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1824 00:31:45.218456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1826 00:31:45.306389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1827 00:31:45.306815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1829 00:31:45.391315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1830 00:31:45.391745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1832 00:31:45.479967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1833 00:31:45.480474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1835 00:31:45.569526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1836 00:31:45.570054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1838 00:31:45.664579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1839 00:31:45.665093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1841 00:31:45.762360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1842 00:31:45.762870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1844 00:31:45.859527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1845 00:31:45.860053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1847 00:31:45.957484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1848 00:31:45.957859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1850 00:31:46.052170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1851 00:31:46.052514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1853 00:31:46.139284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1854 00:31:46.139867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1856 00:31:46.231676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1857 00:31:46.232166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1859 00:31:46.324072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1860 00:31:46.324667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1862 00:31:46.414153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1863 00:31:46.414727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1865 00:31:46.501703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1866 00:31:46.502045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1868 00:31:46.585917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1869 00:31:46.586238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1871 00:31:46.672484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1872 00:31:46.672868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1874 00:31:46.759090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1875 00:31:46.759597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1877 00:31:46.848714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1878 00:31:46.849081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1880 00:31:46.937975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1881 00:31:46.938441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1883 00:31:47.025897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1884 00:31:47.026399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1886 00:31:47.114534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1887 00:31:47.115061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1889 00:31:47.201812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1890 00:31:47.202140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1892 00:31:47.286118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1893 00:31:47.286447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1895 00:31:47.376540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1896 00:31:47.376890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1898 00:31:47.463559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1899 00:31:47.463911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1901 00:31:47.547502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1902 00:31:47.547838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1904 00:31:47.634136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1905 00:31:47.634511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1907 00:31:47.722164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1908 00:31:47.722699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1910 00:31:47.808746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1911 00:31:47.809078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1913 00:31:47.896645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1914 00:31:47.896960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1916 00:31:47.985695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1917 00:31:47.986211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1919 00:31:48.075653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1920 00:31:48.076160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1922 00:31:48.171634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1923 00:31:48.172156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1925 00:31:48.268172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1926 00:31:48.268694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1928 00:31:48.357793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1929 00:31:48.358302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1931 00:31:48.448653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1933 00:31:48.451393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1934 00:31:48.541428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1936 00:31:48.544460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1937 00:31:48.636662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1939 00:31:48.639625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1940 00:31:48.732044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1941 00:31:48.732560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1943 00:31:48.819562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1944 00:31:48.820063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1946 00:31:48.908256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1947 00:31:48.908777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1949 00:31:49.001161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1950 00:31:49.001672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1952 00:31:49.097630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1953 00:31:49.098121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1955 00:31:49.192180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1956 00:31:49.192634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1958 00:31:49.277820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1959 00:31:49.278320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1961 00:31:49.372568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1962 00:31:49.373078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1964 00:31:49.465214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1965 00:31:49.465699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1967 00:31:49.555887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1968 00:31:49.556401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1970 00:31:49.661731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1971 00:31:49.662301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1973 00:31:49.768692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1974 00:31:49.769203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1976 00:31:49.863134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1977 00:31:49.863649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1979 00:31:49.955140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1980 00:31:49.955656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1982 00:31:50.048797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1983 00:31:50.049351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1985 00:31:50.137839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1986 00:31:50.138360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1988 00:31:50.228921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1989 00:31:50.229432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
1991 00:31:50.320495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
1992 00:31:50.321014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
1994 00:31:50.409510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
1995 00:31:50.410033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
1997 00:31:50.494433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
1998 00:31:50.494954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2000 00:31:50.586934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2001 00:31:50.587425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2003 00:31:50.678602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2004 00:31:50.679123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2006 00:31:50.767557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2007 00:31:50.768045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2009 00:31:50.857496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2010 00:31:50.858037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2012 00:31:50.950761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2013 00:31:50.951270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2015 00:31:51.052253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2016 00:31:51.052738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2018 00:31:51.141126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2019 00:31:51.141699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2021 00:31:51.230009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2022 00:31:51.230505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2024 00:31:51.315565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2025 00:31:51.316101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2027 00:31:51.407862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2028 00:31:51.408359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2030 00:31:51.497586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2031 00:31:51.498091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2033 00:31:51.593208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2034 00:31:51.593731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2036 00:31:51.679846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2037 00:31:51.680364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2039 00:31:51.772734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2040 00:31:51.773244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2042 00:31:51.869723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2043 00:31:51.870269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2045 00:31:51.956829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2046 00:31:51.957375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2048 00:31:52.047310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2049 00:31:52.047858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2051 00:31:52.137862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2052 00:31:52.138371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2054 00:31:52.225862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2055 00:31:52.226369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2057 00:31:52.314727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2058 00:31:52.315207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2060 00:31:52.407395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2061 00:31:52.407928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2063 00:31:52.495906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2064 00:31:52.496395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2066 00:31:52.588090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2067 00:31:52.588608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2069 00:31:52.673453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2070 00:31:52.673965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2072 00:31:52.762624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2073 00:31:52.763146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2075 00:31:52.852673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2076 00:31:52.853190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2078 00:31:52.942930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2079 00:31:52.943457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2081 00:31:53.029170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2082 00:31:53.029644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2084 00:31:53.120145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2085 00:31:53.120644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2087 00:31:53.213357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2088 00:31:53.213905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2090 00:31:53.306770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2091 00:31:53.307298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2093 00:31:53.399093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2094 00:31:53.399607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2096 00:31:53.487206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2097 00:31:53.487727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2099 00:31:53.579112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2100 00:31:53.579614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2102 00:31:53.669638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2103 00:31:53.670159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2105 00:31:53.768882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2106 00:31:53.769409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2108 00:31:53.860605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2109 00:31:53.861134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2111 00:31:53.947119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2112 00:31:53.947641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2114 00:31:54.036407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2115 00:31:54.036928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2117 00:31:54.126567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2118 00:31:54.127132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2120 00:31:54.216856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2121 00:31:54.217376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2123 00:31:54.306810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2124 00:31:54.307340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2126 00:31:54.394069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2127 00:31:54.394603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2129 00:31:54.483703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2130 00:31:54.484226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2132 00:31:54.576414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2133 00:31:54.576917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2135 00:31:54.665209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2136 00:31:54.665775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2138 00:31:54.754575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2139 00:31:54.755137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2141 00:31:54.845742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2142 00:31:54.846317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2144 00:31:54.932264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2145 00:31:54.932758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2147 00:31:55.021662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2148 00:31:55.022175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2150 00:31:55.110171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2151 00:31:55.110667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2153 00:31:55.196048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2154 00:31:55.196558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2156 00:31:55.285211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2157 00:31:55.285760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2159 00:31:55.372298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2160 00:31:55.372827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2162 00:31:55.464403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2163 00:31:55.464903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2165 00:31:55.551161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2166 00:31:55.551670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2168 00:31:55.640769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2169 00:31:55.641307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2171 00:31:55.733280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2172 00:31:55.733793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2174 00:31:55.822528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2175 00:31:55.823052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2177 00:31:55.910749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2178 00:31:55.911264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2180 00:31:56.000362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2181 00:31:56.000915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2183 00:31:56.089032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2184 00:31:56.089552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2186 00:31:56.174837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2187 00:31:56.175366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2189 00:31:56.267120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2190 00:31:56.267671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2192 00:31:56.347888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2193 00:31:56.348412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2195 00:31:56.439406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2196 00:31:56.439927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2198 00:31:56.529394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2199 00:31:56.529923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2201 00:31:56.616033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2202 00:31:56.616593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2204 00:31:56.705562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2205 00:31:56.706129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2207 00:31:56.791673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2208 00:31:56.792239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2210 00:31:56.885411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2211 00:31:56.885978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2213 00:31:56.976625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2214 00:31:56.977125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2216 00:31:57.067088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2217 00:31:57.067591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2219 00:31:57.154740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2220 00:31:57.155182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2222 00:31:57.253421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2223 00:31:57.253995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2225 00:31:57.351384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2226 00:31:57.351900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2228 00:31:57.448434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2229 00:31:57.448945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2231 00:31:57.555521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2232 00:31:57.556107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2234 00:31:57.657926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2235 00:31:57.658443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2237 00:31:57.764906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2238 00:31:57.765437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2240 00:31:57.875417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2241 00:31:57.875954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2243 00:31:57.979697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2244 00:31:57.980206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2246 00:31:58.076993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2248 00:31:58.080409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2249 00:31:58.183975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2250 00:31:58.184554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2252 00:31:58.558830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2253 00:31:58.559297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2255 00:31:58.559771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2256 00:31:58.559908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2257 00:31:58.560247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2259 00:31:58.560641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2261 00:31:58.566977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2262 00:31:58.567424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2264 00:31:58.656762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2265 00:31:58.657215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2267 00:31:58.744717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2268 00:31:58.745167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2270 00:31:58.834301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2271 00:31:58.834745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2273 00:31:58.924571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2274 00:31:58.925020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2276 00:31:59.011448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2277 00:31:59.011894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2279 00:31:59.102692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2280 00:31:59.103155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2282 00:31:59.193949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2283 00:31:59.194396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2285 00:31:59.285507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2286 00:31:59.285983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2288 00:31:59.375675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2289 00:31:59.376131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2291 00:31:59.467484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2292 00:31:59.468003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2294 00:31:59.569549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2295 00:31:59.570042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2297 00:31:59.671659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2298 00:31:59.672247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2300 00:31:59.767713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2301 00:31:59.768310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2303 00:31:59.867830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2304 00:31:59.868415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2306 00:31:59.966418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2307 00:31:59.966935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2309 00:32:00.061913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2310 00:32:00.062424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2312 00:32:00.168269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2313 00:32:00.168844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2315 00:32:00.267670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2316 00:32:00.268186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2318 00:32:00.369510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2319 00:32:00.370053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2321 00:32:00.469915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2322 00:32:00.470487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2324 00:32:00.568832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2325 00:32:00.569349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2327 00:32:00.668882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2328 00:32:00.669400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2330 00:32:00.771446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2331 00:32:00.771963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2333 00:32:00.869752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2334 00:32:00.870369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2336 00:32:00.967032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2337 00:32:00.967589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2339 00:32:01.062717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2340 00:32:01.063042 + set +x
2341 00:32:01.063409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2343 00:32:01.072847 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 683574_1.6.2.4.5>
2344 00:32:01.073228 <LAVA_TEST_RUNNER EXIT>
2345 00:32:01.073624 Received signal: <ENDRUN> 1_kselftest-dt 683574_1.6.2.4.5
2346 00:32:01.073804 Ending use of test pattern.
2347 00:32:01.073946 Ending test lava.1_kselftest-dt (683574_1.6.2.4.5), duration 73.83
2349 00:32:01.074487 ok: lava_test_shell seems to have completed
2350 00:32:01.078417 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2351 00:32:01.079205 end: 3.1 lava-test-shell (duration 00:01:15) [common]
2352 00:32:01.079399 end: 3 lava-test-retry (duration 00:01:15) [common]
2353 00:32:01.079607 start: 4 finalize (timeout 00:06:13) [common]
2354 00:32:01.079810 start: 4.1 power-off (timeout 00:00:30) [common]
2355 00:32:01.080176 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2356 00:32:01.100130 >> OK - accepted request
2357 00:32:01.102352 Returned 0 in 0 seconds
2358 00:32:01.203238 end: 4.1 power-off (duration 00:00:00) [common]
2360 00:32:01.203985 start: 4.2 read-feedback (timeout 00:06:13) [common]
2361 00:32:01.204534 Listened to connection for namespace 'common' for up to 1s
2362 00:32:01.204918 Listened to connection for namespace 'common' for up to 1s
2363 00:32:02.205716 Finalising connection for namespace 'common'
2364 00:32:02.206182 Disconnecting from shell: Finalise
2365 00:32:02.206397 / #
2366 00:32:02.307168 end: 4.2 read-feedback (duration 00:00:01) [common]
2367 00:32:02.307570 end: 4 finalize (duration 00:00:01) [common]
2368 00:32:02.307850 Cleaning after the job
2369 00:32:02.308104 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/ramdisk
2370 00:32:02.315851 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/kernel
2371 00:32:02.322015 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/dtb
2372 00:32:02.322531 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/nfsrootfs
2373 00:32:02.437215 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/683574/tftp-deploy-2evzdv8f/modules
2374 00:32:02.443687 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/683574
2375 00:32:03.398425 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/683574
2376 00:32:03.398675 Job finished correctly