Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 02:28:59.788852 lava-dispatcher, installed at version: 2023.08
2 02:28:59.789167 start: 0 validate
3 02:28:59.789352 Start time: 2024-09-01 02:28:59.789341+00:00 (UTC)
4 02:28:59.789590 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 02:29:00.318876 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 02:29:00.433251 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 02:29:00.547344 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 02:29:00.665893 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 02:29:00.784051 validate duration: 0.99
11 02:29:00.784859 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 02:29:00.785193 start: 1.1 download-retry (timeout 00:10:00) [common]
13 02:29:00.785508 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 02:29:00.785976 Not decompressing ramdisk as can be used compressed.
15 02:29:00.786273 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 02:29:00.786512 saving as /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/ramdisk/initrd.cpio.gz
17 02:29:00.786756 total size: 4775763 (4 MB)
18 02:29:01.017364 progress 0 % (0 MB)
19 02:29:01.354087 progress 5 % (0 MB)
20 02:29:01.581743 progress 10 % (0 MB)
21 02:29:01.601166 progress 15 % (0 MB)
22 02:29:01.695036 progress 20 % (0 MB)
23 02:29:01.711196 progress 25 % (1 MB)
24 02:29:01.814938 progress 30 % (1 MB)
25 02:29:01.922080 progress 35 % (1 MB)
26 02:29:02.028320 progress 40 % (1 MB)
27 02:29:02.050157 progress 45 % (2 MB)
28 02:29:02.153781 progress 50 % (2 MB)
29 02:29:02.259590 progress 55 % (2 MB)
30 02:29:02.285165 progress 60 % (2 MB)
31 02:29:02.389876 progress 65 % (2 MB)
32 02:29:02.489497 progress 70 % (3 MB)
33 02:29:02.583457 progress 75 % (3 MB)
34 02:29:02.619794 progress 80 % (3 MB)
35 02:29:02.710821 progress 85 % (3 MB)
36 02:29:02.812044 progress 90 % (4 MB)
37 02:29:02.849637 progress 95 % (4 MB)
38 02:29:02.937596 progress 100 % (4 MB)
39 02:29:02.938382 4 MB downloaded in 2.15 s (2.12 MB/s)
40 02:29:02.938860 end: 1.1.1 http-download (duration 00:00:02) [common]
42 02:29:02.939683 end: 1.1 download-retry (duration 00:00:02) [common]
43 02:29:02.939976 start: 1.2 download-retry (timeout 00:09:58) [common]
44 02:29:02.940283 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 02:29:02.940690 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 02:29:02.940918 saving as /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/kernel/zImage
47 02:29:02.941136 total size: 11354624 (10 MB)
48 02:29:02.941355 No compression specified
49 02:29:03.060683 progress 0 % (0 MB)
50 02:29:03.399658 progress 5 % (0 MB)
51 02:29:03.740466 progress 10 % (1 MB)
52 02:29:03.988308 progress 15 % (1 MB)
53 02:29:04.329708 progress 20 % (2 MB)
54 02:29:04.657996 progress 25 % (2 MB)
55 02:29:04.974156 progress 30 % (3 MB)
56 02:29:05.236183 progress 35 % (3 MB)
57 02:29:05.546857 progress 40 % (4 MB)
58 02:29:05.826639 progress 45 % (4 MB)
59 02:29:06.107642 progress 50 % (5 MB)
60 02:29:06.419377 progress 55 % (5 MB)
61 02:29:06.662272 progress 60 % (6 MB)
62 02:29:06.980011 progress 65 % (7 MB)
63 02:29:07.221088 progress 70 % (7 MB)
64 02:29:07.534178 progress 75 % (8 MB)
65 02:29:07.780015 progress 80 % (8 MB)
66 02:29:08.094383 progress 85 % (9 MB)
67 02:29:08.339831 progress 90 % (9 MB)
68 02:29:08.683095 progress 95 % (10 MB)
69 02:29:08.917160 progress 100 % (10 MB)
70 02:29:08.917806 10 MB downloaded in 5.98 s (1.81 MB/s)
71 02:29:08.918252 end: 1.2.1 http-download (duration 00:00:06) [common]
73 02:29:08.919055 end: 1.2 download-retry (duration 00:00:06) [common]
74 02:29:08.919353 start: 1.3 download-retry (timeout 00:09:52) [common]
75 02:29:08.919637 start: 1.3.1 http-download (timeout 00:09:52) [common]
76 02:29:08.920036 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 02:29:08.920286 saving as /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/dtb/am335x-boneblack.dtb
78 02:29:08.920504 total size: 70308 (0 MB)
79 02:29:08.920723 No compression specified
80 02:29:09.038173 progress 46 % (0 MB)
81 02:29:09.040979 progress 93 % (0 MB)
82 02:29:09.041962 progress 100 % (0 MB)
83 02:29:09.042353 0 MB downloaded in 0.12 s (0.55 MB/s)
84 02:29:09.042758 end: 1.3.1 http-download (duration 00:00:00) [common]
86 02:29:09.043548 end: 1.3 download-retry (duration 00:00:00) [common]
87 02:29:09.043831 start: 1.4 download-retry (timeout 00:09:52) [common]
88 02:29:09.044114 start: 1.4.1 http-download (timeout 00:09:52) [common]
89 02:29:09.044495 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 02:29:09.044720 saving as /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/nfsrootfs/full.rootfs.tar
91 02:29:09.044933 total size: 117747780 (112 MB)
92 02:29:09.045153 Using unxz to decompress xz
93 02:29:09.161321 progress 0 % (0 MB)
94 02:29:12.489443 progress 5 % (5 MB)
95 02:29:15.442789 progress 10 % (11 MB)
96 02:29:18.233102 progress 15 % (16 MB)
97 02:29:20.403815 progress 20 % (22 MB)
98 02:29:22.017802 progress 25 % (28 MB)
99 02:29:23.223884 progress 30 % (33 MB)
100 02:29:24.204453 progress 35 % (39 MB)
101 02:29:24.996242 progress 40 % (44 MB)
102 02:29:25.671670 progress 45 % (50 MB)
103 02:29:26.383856 progress 50 % (56 MB)
104 02:29:27.013764 progress 55 % (61 MB)
105 02:29:27.706620 progress 60 % (67 MB)
106 02:29:28.361164 progress 65 % (73 MB)
107 02:29:28.980117 progress 70 % (78 MB)
108 02:29:29.593031 progress 75 % (84 MB)
109 02:29:30.174540 progress 80 % (89 MB)
110 02:29:30.916194 progress 85 % (95 MB)
111 02:29:31.680052 progress 90 % (101 MB)
112 02:29:32.411253 progress 95 % (106 MB)
113 02:29:33.115825 progress 100 % (112 MB)
114 02:29:33.119345 112 MB downloaded in 24.07 s (4.66 MB/s)
115 02:29:33.119724 end: 1.4.1 http-download (duration 00:00:24) [common]
117 02:29:33.120434 end: 1.4 download-retry (duration 00:00:24) [common]
118 02:29:33.120653 start: 1.5 download-retry (timeout 00:09:28) [common]
119 02:29:33.120868 start: 1.5.1 http-download (timeout 00:09:28) [common]
120 02:29:33.121188 downloading http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 02:29:33.121360 saving as /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/modules/modules.tar
122 02:29:33.121523 total size: 6607612 (6 MB)
123 02:29:33.121689 Using unxz to decompress xz
124 02:29:33.239470 progress 0 % (0 MB)
125 02:29:33.465844 progress 5 % (0 MB)
126 02:29:33.684607 progress 10 % (0 MB)
127 02:29:33.713449 progress 15 % (0 MB)
128 02:29:33.739628 progress 20 % (1 MB)
129 02:29:33.813621 progress 25 % (1 MB)
130 02:29:33.839549 progress 30 % (1 MB)
131 02:29:33.926678 progress 35 % (2 MB)
132 02:29:34.024600 progress 40 % (2 MB)
133 02:29:34.055353 progress 45 % (2 MB)
134 02:29:34.154550 progress 50 % (3 MB)
135 02:29:34.253523 progress 55 % (3 MB)
136 02:29:34.283156 progress 60 % (3 MB)
137 02:29:34.382496 progress 65 % (4 MB)
138 02:29:34.480329 progress 70 % (4 MB)
139 02:29:34.575199 progress 75 % (4 MB)
140 02:29:34.615274 progress 80 % (5 MB)
141 02:29:34.703484 progress 85 % (5 MB)
142 02:29:34.791070 progress 90 % (5 MB)
143 02:29:34.839301 progress 95 % (6 MB)
144 02:29:34.924672 progress 100 % (6 MB)
145 02:29:34.932299 6 MB downloaded in 1.81 s (3.48 MB/s)
146 02:29:34.932730 end: 1.5.1 http-download (duration 00:00:02) [common]
148 02:29:34.933437 end: 1.5 download-retry (duration 00:00:02) [common]
149 02:29:34.933687 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
150 02:29:34.933934 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
151 02:29:40.506342 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco
152 02:29:40.506615 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 02:29:40.506743 start: 1.6.2 lava-overlay (timeout 00:09:20) [common]
154 02:29:40.507010 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd
155 02:29:40.507178 makedir: /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin
156 02:29:40.507309 makedir: /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/tests
157 02:29:40.507436 makedir: /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/results
158 02:29:40.507575 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-add-keys
159 02:29:40.507777 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-add-sources
160 02:29:40.507948 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-background-process-start
161 02:29:40.508117 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-background-process-stop
162 02:29:40.508457 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-common-functions
163 02:29:40.508625 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-echo-ipv4
164 02:29:40.508792 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-install-packages
165 02:29:40.508955 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-installed-packages
166 02:29:40.509118 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-os-build
167 02:29:40.509282 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-probe-channel
168 02:29:40.509446 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-probe-ip
169 02:29:40.509611 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-target-ip
170 02:29:40.509774 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-target-mac
171 02:29:40.509936 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-target-storage
172 02:29:40.510101 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-test-case
173 02:29:40.510266 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-test-event
174 02:29:40.510433 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-test-feedback
175 02:29:40.510594 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-test-raise
176 02:29:40.510756 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-test-reference
177 02:29:40.510920 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-test-runner
178 02:29:40.511081 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-test-set
179 02:29:40.511241 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-test-shell
180 02:29:40.511406 Updating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-add-keys (debian)
181 02:29:40.511625 Updating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-add-sources (debian)
182 02:29:40.511810 Updating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-install-packages (debian)
183 02:29:40.511994 Updating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-installed-packages (debian)
184 02:29:40.512177 Updating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/bin/lava-os-build (debian)
185 02:29:40.512390 Creating /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/environment
186 02:29:40.512513 LAVA metadata
187 02:29:40.512609 - LAVA_JOB_ID=1186838
188 02:29:40.512701 - LAVA_DISPATCHER_IP=192.168.11.5
189 02:29:40.512838 start: 1.6.2.1 ssh-authorize (timeout 00:09:20) [common]
190 02:29:40.513155 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 02:29:40.513307 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:20) [common]
192 02:29:40.513396 skipped lava-vland-overlay
193 02:29:40.513502 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 02:29:40.513616 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:20) [common]
195 02:29:40.513707 skipped lava-multinode-overlay
196 02:29:40.513814 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 02:29:40.513925 start: 1.6.2.4 test-definition (timeout 00:09:20) [common]
198 02:29:40.514021 Loading test definitions
199 02:29:40.514138 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:20) [common]
200 02:29:40.514233 Using /lava-1186838 at stage 0
201 02:29:40.514622 uuid=1186838_1.6.2.4.1 testdef=None
202 02:29:40.514740 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 02:29:40.514853 start: 1.6.2.4.2 test-overlay (timeout 00:09:20) [common]
204 02:29:40.515441 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 02:29:40.515762 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:20) [common]
207 02:29:40.516758 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 02:29:40.517085 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:20) [common]
210 02:29:40.517852 runner path: /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/0/tests/0_timesync-off test_uuid 1186838_1.6.2.4.1
211 02:29:40.518044 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 02:29:40.518369 start: 1.6.2.4.5 git-repo-action (timeout 00:09:20) [common]
214 02:29:40.518468 Using /lava-1186838 at stage 0
215 02:29:40.518601 Fetching tests from https://github.com/kernelci/test-definitions.git
216 02:29:40.518700 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/0/tests/1_kselftest-dt'
217 02:29:45.745118 Running '/usr/bin/git checkout kernelci.org
218 02:29:45.963999 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 02:29:45.965038 uuid=1186838_1.6.2.4.5 testdef=None
220 02:29:45.965301 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 02:29:45.965900 start: 1.6.2.4.6 test-overlay (timeout 00:09:15) [common]
223 02:29:45.967849 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 02:29:45.968500 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:15) [common]
226 02:29:45.971215 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 02:29:45.971865 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:15) [common]
229 02:29:45.974535 runner path: /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/0/tests/1_kselftest-dt test_uuid 1186838_1.6.2.4.5
230 02:29:45.974749 BOARD='beaglebone-black'
231 02:29:45.974922 BRANCH='mainline'
232 02:29:45.975089 SKIPFILE='/dev/null'
233 02:29:45.975253 SKIP_INSTALL='True'
234 02:29:45.975414 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 02:29:45.975579 TST_CASENAME=''
236 02:29:45.975741 TST_CMDFILES='dt'
237 02:29:45.976097 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 02:29:45.976514 Creating lava-test-runner.conf files
240 02:29:45.976605 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1186838/lava-overlay-mxtpmogd/lava-1186838/0 for stage 0
241 02:29:45.976732 - 0_timesync-off
242 02:29:45.976827 - 1_kselftest-dt
243 02:29:45.976963 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 02:29:45.977082 start: 1.6.2.5 compress-overlay (timeout 00:09:15) [common]
245 02:29:54.433688 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 02:29:54.433890 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:06) [common]
247 02:29:54.434035 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 02:29:54.434188 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 02:29:54.434332 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:06) [common]
250 02:29:54.555997 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 02:29:54.556390 start: 1.6.4 extract-modules (timeout 00:09:06) [common]
252 02:29:54.556606 extracting modules file /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco
253 02:29:54.863862 extracting modules file /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1186838/extract-overlay-ramdisk-hhm7za3v/ramdisk
254 02:29:55.169407 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 02:29:55.169627 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
256 02:29:55.169762 [common] Applying overlay to NFS
257 02:29:55.169869 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1186838/compress-overlay-k6uuz194/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco
258 02:29:56.356685 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 02:29:56.356898 start: 1.6.6 prepare-kernel (timeout 00:09:04) [common]
260 02:29:56.357045 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:04) [common]
261 02:29:56.357194 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 02:29:56.357331 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 02:29:56.357469 start: 1.6.7 configure-preseed-file (timeout 00:09:04) [common]
264 02:29:56.357603 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 02:29:56.357739 start: 1.6.8 compress-ramdisk (timeout 00:09:04) [common]
266 02:29:56.357842 Building ramdisk /var/lib/lava/dispatcher/tmp/1186838/extract-overlay-ramdisk-hhm7za3v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1186838/extract-overlay-ramdisk-hhm7za3v/ramdisk
267 02:29:56.723155 >> 74799 blocks
268 02:29:58.690160 Adding RAMdisk u-boot header.
269 02:29:58.690438 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1186838/extract-overlay-ramdisk-hhm7za3v/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1186838/extract-overlay-ramdisk-hhm7za3v/ramdisk.cpio.gz.uboot
270 02:29:58.832367 output: Image Name:
271 02:29:58.832634 output: Created: Sun Sep 1 02:29:58 2024
272 02:29:58.832785 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 02:29:58.832930 output: Data Size: 14792968 Bytes = 14446.26 KiB = 14.11 MiB
274 02:29:58.833070 output: Load Address: 00000000
275 02:29:58.833207 output: Entry Point: 00000000
276 02:29:58.833344 output:
277 02:29:58.833575 rename /var/lib/lava/dispatcher/tmp/1186838/extract-overlay-ramdisk-hhm7za3v/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/ramdisk/ramdisk.cpio.gz.uboot
278 02:29:58.833819 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 02:29:58.834012 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 02:29:58.834200 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:02) [common]
281 02:29:58.834348 No LXC device requested
282 02:29:58.834524 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 02:29:58.834708 start: 1.8 deploy-device-env (timeout 00:09:02) [common]
284 02:29:58.834885 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 02:29:58.835027 Checking files for TFTP limit of 4294967296 bytes.
286 02:29:58.835923 end: 1 tftp-deploy (duration 00:00:58) [common]
287 02:29:58.836114 start: 2 uboot-action (timeout 00:05:00) [common]
288 02:29:58.836326 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 02:29:58.836503 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 02:29:58.836683 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 02:29:58.836949 substitutions:
292 02:29:58.837092 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 02:29:58.837232 - {DTB_ADDR}: 0x88000000
294 02:29:58.837368 - {DTB}: 1186838/tftp-deploy-0kjilrvg/dtb/am335x-boneblack.dtb
295 02:29:58.837503 - {INITRD}: 1186838/tftp-deploy-0kjilrvg/ramdisk/ramdisk.cpio.gz.uboot
296 02:29:58.837638 - {KERNEL_ADDR}: 0x82000000
297 02:29:58.837771 - {KERNEL}: 1186838/tftp-deploy-0kjilrvg/kernel/zImage
298 02:29:58.837905 - {LAVA_MAC}: None
299 02:29:58.838046 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco
300 02:29:58.838179 - {NFS_SERVER_IP}: 192.168.11.5
301 02:29:58.838309 - {PRESEED_CONFIG}: None
302 02:29:58.838439 - {PRESEED_LOCAL}: None
303 02:29:58.838572 - {RAMDISK_ADDR}: 0x83000000
304 02:29:58.838703 - {RAMDISK}: 1186838/tftp-deploy-0kjilrvg/ramdisk/ramdisk.cpio.gz.uboot
305 02:29:58.838834 - {ROOT_PART}: None
306 02:29:58.838962 - {ROOT}: None
307 02:29:58.839090 - {SERVER_IP}: 192.168.11.5
308 02:29:58.839219 - {TEE_ADDR}: 0x83000000
309 02:29:58.839347 - {TEE}: None
310 02:29:58.839476 Parsed boot commands:
311 02:29:58.839602 - setenv autoload no
312 02:29:58.839731 - setenv initrd_high 0xffffffff
313 02:29:58.839859 - setenv fdt_high 0xffffffff
314 02:29:58.839986 - dhcp
315 02:29:58.840114 - setenv serverip 192.168.11.5
316 02:29:58.840253 - tftp 0x82000000 1186838/tftp-deploy-0kjilrvg/kernel/zImage
317 02:29:58.840374 - tftp 0x83000000 1186838/tftp-deploy-0kjilrvg/ramdisk/ramdisk.cpio.gz.uboot
318 02:29:58.840486 - setenv initrd_size ${filesize}
319 02:29:58.840596 - tftp 0x88000000 1186838/tftp-deploy-0kjilrvg/dtb/am335x-boneblack.dtb
320 02:29:58.840706 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 02:29:58.840821 - bootz 0x82000000 0x83000000 0x88000000
322 02:29:58.840964 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 02:29:58.841372 start: 2.3 connect-device (timeout 00:05:00) [common]
325 02:29:58.841492 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 02:29:59.203704 Setting prompt string to ['lava-test: # ']
327 02:29:59.204099 end: 2.3 connect-device (duration 00:00:00) [common]
328 02:29:59.204292 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 02:29:59.204469 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 02:29:59.204600 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 02:29:59.204915 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 02:29:59.569921 Returned 0 in 0 seconds
333 02:29:59.670826 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 02:29:59.671778 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 02:29:59.672104 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 02:29:59.672422 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 02:29:59.672676 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 02:29:59.673420 Trying 127.0.0.1...
340 02:29:59.673652 Connected to 127.0.0.1.
341 02:29:59.673863 Escape character is '^]'.
342 02:30:04.581071
343 02:30:04.584797 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 02:30:04.641299 Trying to boot from MMC2
345 02:30:04.689850 Loading Environment from EXT4... Card did not respond to voltage select!
346 02:30:04.756809
347 02:30:04.757114
348 02:30:04.762373 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 02:30:04.762639
350 02:30:04.767332 CPU : AM335X-GP rev 2.1
351 02:30:04.821261 I2C: ready
352 02:30:04.821534 DRAM: 512 MiB
353 02:30:04.875516 No match for driver 'omap_hsmmc'
354 02:30:04.881117 No match for driver 'omap_hsmmc'
355 02:30:04.881378 Some drivers were not found
356 02:30:04.887488 Reset Source: Power-on reset has occurred.
357 02:30:04.887720 RTC 32KCLK Source: External.
358 02:30:04.894924 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 02:30:04.908277 Loading Environment from EXT4... Card did not respond to voltage select!
360 02:30:04.972750 Board: BeagleBone Black
361 02:30:04.976545 <ethaddr> not set. Validating first E-fuse MAC
362 02:30:05.033270 BeagleBone Black:
363 02:30:05.033570 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 02:30:05.038854 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 02:30:05.044782 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 02:30:05.045078 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 02:30:05.049781 Net: eth0: MII MODE
368 02:30:05.059689 cpsw, usb_ether
369 02:30:05.059956 Press SPACE to abort autoboot in 2 seconds
370 02:30:05.110727 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 02:30:05.111066 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 02:30:05.111345 Setting prompt string to ['=> ']
373 02:30:05.111605 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 02:30:05.114997 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 02:30:05.115295 Sending with 10 millisecond of delay
377 02:30:06.249906 => setenv autoload no
378 02:30:06.260386 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 02:30:06.262710 setenv autoload no
380 02:30:06.263178 Sending with 10 millisecond of delay
382 02:30:08.060134 => setenv initrd_high 0xffffffff
383 02:30:08.070696 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 02:30:08.071164 setenv initrd_high 0xffffffff
385 02:30:08.071609 Sending with 10 millisecond of delay
387 02:30:09.687764 => setenv fdt_high 0xffffffff
388 02:30:09.698276 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 02:30:09.698737 setenv fdt_high 0xffffffff
390 02:30:09.699181 Sending with 10 millisecond of delay
392 02:30:09.990655 => dhcp
393 02:30:10.001134 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 02:30:10.001643 dhcp
395 02:30:10.001917 link up on port 0, speed 100, full duplex
396 02:30:10.002208 BOOTP broadcast 1
397 02:30:10.009505 DHCP client bound to address 192.168.11.7 (4 ms)
398 02:30:10.009948 Sending with 10 millisecond of delay
400 02:30:11.746634 => setenv serverip 192.168.11.5
401 02:30:11.757154 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 02:30:11.757582 setenv serverip 192.168.11.5
403 02:30:11.757997 Sending with 10 millisecond of delay
405 02:30:15.301164 => tftp 0x82000000 1186838/tftp-deploy-0kjilrvg/kernel/zImage
406 02:30:15.311649 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 02:30:15.312108 tftp 0x82000000 1186838/tftp-deploy-0kjilrvg/kernel/zImage
408 02:30:15.312362 link up on port 0, speed 100, full duplex
409 02:30:15.312575 Using cpsw device
410 02:30:15.315888 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
411 02:30:15.321385 Filename '1186838/tftp-deploy-0kjilrvg/kernel/zImage'.
412 02:30:15.331223 Load address: 0x82000000
413 02:30:15.506939 Loading: *#################################################################
414 02:30:15.679366 #################################################################
415 02:30:15.875363 #################################################################
416 02:30:16.049526 #################################################################
417 02:30:16.225035 #################################################################
418 02:30:16.397781 #################################################################
419 02:30:16.577877 #################################################################
420 02:30:16.898243 #################################################################
421 02:30:16.942817 #################################################################
422 02:30:17.115941 #################################################################
423 02:30:17.290185 #################################################################
424 02:30:17.439442 ###########################################################
425 02:30:17.439722 5.1 MiB/s
426 02:30:17.439948 done
427 02:30:17.443084 Bytes transferred = 11354624 (ad4200 hex)
428 02:30:17.443550 Sending with 10 millisecond of delay
430 02:30:21.950479 => tftp 0x83000000 1186838/tftp-deploy-0kjilrvg/ramdisk/ramdisk.cpio.gz.uboot
431 02:30:21.960971 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
432 02:30:21.961431 tftp 0x83000000 1186838/tftp-deploy-0kjilrvg/ramdisk/ramdisk.cpio.gz.uboot
433 02:30:21.961661 link up on port 0, speed 100, full duplex
434 02:30:21.961873 Using cpsw device
435 02:30:21.965138 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
436 02:30:22.028881 Filename '1186838/tftp-deploy-0kjilrvg/ramdisk/ramdisk.cpio.gz.uboot'.
437 02:30:22.029177 Load address: 0x83000000
438 02:30:22.160582 Loading: *#################################################################
439 02:30:22.335169 #################################################################
440 02:30:22.510264 #################################################################
441 02:30:22.704119 #################################################################
442 02:30:22.879454 #################################################################
443 02:30:23.054417 #################################################################
444 02:30:23.224872 #################################################################
445 02:30:23.398710 #################################################################
446 02:30:23.573832 #################################################################
447 02:30:23.764264 #################################################################
448 02:30:23.929987 #################################################################
449 02:30:24.125226 #################################################################
450 02:30:24.300110 #################################################################
451 02:30:24.467454 #################################################################
452 02:30:24.642682 #################################################################
453 02:30:24.736822 #################################
454 02:30:24.737207 5.1 MiB/s
455 02:30:24.737488 done
456 02:30:24.737746 Bytes transferred = 14793032 (e1b948 hex)
457 02:30:24.740362 Sending with 10 millisecond of delay
459 02:30:26.597532 => setenv initrd_size ${filesize}
460 02:30:26.608047 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
461 02:30:26.608568 setenv initrd_size ${filesize}
462 02:30:26.609028 Sending with 10 millisecond of delay
464 02:30:30.814550 => tftp 0x88000000 1186838/tftp-deploy-0kjilrvg/dtb/am335x-boneblack.dtb
465 02:30:30.825058 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
466 02:30:30.825513 tftp 0x88000000 1186838/tftp-deploy-0kjilrvg/dtb/am335x-boneblack.dtb
467 02:30:30.825741 link up on port 0, speed 100, full duplex
468 02:30:30.825951 Using cpsw device
469 02:30:30.829383 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
470 02:30:30.842842 Filename '1186838/tftp-deploy-0kjilrvg/dtb/am335x-boneblack.dtb'.
471 02:30:30.843116 Load address: 0x88000000
472 02:30:30.858361 Loading: *#####
473 02:30:30.858642 4.5 MiB/s
474 02:30:30.858860 done
475 02:30:30.859065 Bytes transferred = 70308 (112a4 hex)
476 02:30:30.861863 Sending with 10 millisecond of delay
478 02:30:44.161012 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 02:30:44.171521 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
480 02:30:44.171973 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 02:30:44.172441 Sending with 10 millisecond of delay
483 02:30:46.511442 => bootz 0x82000000 0x83000000 0x88000000
484 02:30:46.521926 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
485 02:30:46.522280 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
486 02:30:46.522850 bootz 0x82000000 0x83000000 0x88000000
487 02:30:46.523101 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 02:30:46.523601 Image Name:
489 02:30:46.523839 Created: 2024-09-01 2:29:58 UTC
490 02:30:46.529027 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 02:30:46.534658 Data Size: 14792968 Bytes = 14.1 MiB
492 02:30:46.534890 Load Address: 00000000
493 02:30:46.541822 Entry Point: 00000000
494 02:30:46.679195 Verifying Checksum ... OK
495 02:30:46.679488 ## Flattened Device Tree blob at 88000000
496 02:30:46.685664 Booting using the fdt blob at 0x88000000
497 02:30:46.690593 Using Device Tree in place at 88000000, end 880142a3
498 02:30:46.698308
499 02:30:46.698587 Starting kernel ...
500 02:30:46.698809
501 02:30:46.699341 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 02:30:46.699643 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
503 02:30:46.699888 Setting prompt string to ['Linux version [0-9]']
504 02:30:46.700129 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
505 02:30:46.700399 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
506 02:30:47.530971 [ 0.000000] Booting Linux on physical CPU 0x0
507 02:30:47.536873 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
508 02:30:47.537199 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 02:30:47.537477 Setting prompt string to []
510 02:30:47.537759 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 02:30:47.538039 Using line separator: #'\n'#
512 02:30:47.538282 No login prompt set.
513 02:30:47.538532 Parsing kernel messages
514 02:30:47.538753 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 02:30:47.539169 [login-action] Waiting for messages, (timeout 00:04:11)
516 02:30:47.553718 [ 0.000000] Linux version 6.11.0-rc5 (KernelCI@build-j303542-arm-gcc-12-multi-v7-defconfig-vhqmp) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Aug 31 23:24:39 UTC 2024
517 02:30:47.559341 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 02:30:47.565106 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 02:30:47.576675 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 02:30:47.582405 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 02:30:47.588167 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 02:30:47.588479 [ 0.000000] Memory policy: Data cache writeback
523 02:30:47.594778 [ 0.000000] efi: UEFI not found.
524 02:30:47.600194 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 02:30:47.606073 [ 0.000000] Zone ranges:
526 02:30:47.611697 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 02:30:47.617410 [ 0.000000] Normal empty
528 02:30:47.617700 [ 0.000000] HighMem empty
529 02:30:47.623170 [ 0.000000] Movable zone start for each node
530 02:30:47.623451 [ 0.000000] Early memory node ranges
531 02:30:47.634670 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 02:30:47.639918 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 02:30:47.664742 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 02:30:47.670216 [ 0.000000] AM335X ES2.1 (sgx neon)
535 02:30:47.682029 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
536 02:30:47.699651 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 02:30:47.711148 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 02:30:47.717137 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 02:30:47.722677 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 02:30:47.732827 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 02:30:47.761956 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 02:30:47.767891 <6>[ 0.000000] trace event string verifier disabled
543 02:30:47.768273 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 02:30:47.773634 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 02:30:47.785065 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 02:30:47.790796 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 02:30:47.798098 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 02:30:47.812987 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 02:30:47.830176 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 02:30:47.837004 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 02:30:47.929669 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 02:30:47.941186 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 02:30:47.947920 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 02:30:47.960968 <6>[ 0.019161] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 02:30:47.968326 <6>[ 0.033980] Console: colour dummy device 80x30
556 02:30:47.974363 Matched prompt #6: WARNING:
557 02:30:47.974653 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 02:30:47.979792 <3>[ 0.038876] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 02:30:47.985543 <3>[ 0.045944] This ensures that you still see kernel messages. Please
560 02:30:47.988756 <3>[ 0.052669] update your kernel commandline.
561 02:30:48.029417 <6>[ 0.057279] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 02:30:48.035164 <6>[ 0.096165] CPU: Testing write buffer coherency: ok
563 02:30:48.041184 <6>[ 0.101529] CPU0: Spectre v2: using BPIALL workaround
564 02:30:48.041459 <6>[ 0.106994] pid_max: default: 32768 minimum: 301
565 02:30:48.052537 <6>[ 0.112178] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 02:30:48.059415 <6>[ 0.119999] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 02:30:48.066415 <6>[ 0.129289] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 02:30:48.074791 <6>[ 0.136137] Setting up static identity map for 0x80300000 - 0x803000ac
569 02:30:48.080539 <6>[ 0.145705] rcu: Hierarchical SRCU implementation.
570 02:30:48.088251 <6>[ 0.150986] rcu: Max phase no-delay instances is 1000.
571 02:30:48.096556 <6>[ 0.162036] EFI services will not be available.
572 02:30:48.102411 <6>[ 0.167284] smp: Bringing up secondary CPUs ...
573 02:30:48.108165 <6>[ 0.172327] smp: Brought up 1 node, 1 CPU
574 02:30:48.114059 <6>[ 0.176728] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 02:30:48.119785 <6>[ 0.183479] CPU: All CPU(s) started in SVC mode.
576 02:30:48.140089 <6>[ 0.188659] Memory: 407012K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48024K reserved, 65536K cma-reserved, 0K highmem)
577 02:30:48.140389 <6>[ 0.204905] devtmpfs: initialized
578 02:30:48.162035 <6>[ 0.221648] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 02:30:48.173534 <6>[ 0.230218] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 02:30:48.179488 <6>[ 0.240658] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 02:30:48.190226 <6>[ 0.252989] pinctrl core: initialized pinctrl subsystem
582 02:30:48.199553 <6>[ 0.263662] DMI not present or invalid.
583 02:30:48.207787 <6>[ 0.269486] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 02:30:48.217221 <6>[ 0.278332] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 02:30:48.232113 <6>[ 0.289715] thermal_sys: Registered thermal governor 'step_wise'
586 02:30:48.232406 <6>[ 0.289856] cpuidle: using governor menu
587 02:30:48.259315 <6>[ 0.325057] No ATAGs?
588 02:30:48.265459 <6>[ 0.327698] hw-breakpoint: debug architecture 0x4 unsupported.
589 02:30:48.275722 <6>[ 0.339682] Serial: AMBA PL011 UART driver
590 02:30:48.317179 <6>[ 0.382902] iommu: Default domain type: Translated
591 02:30:48.326321 <6>[ 0.388133] iommu: DMA domain TLB invalidation policy: strict mode
592 02:30:48.336238 <5>[ 0.400606] SCSI subsystem initialized
593 02:30:48.360293 <6>[ 0.420319] usbcore: registered new interface driver usbfs
594 02:30:48.367192 <6>[ 0.426275] usbcore: registered new interface driver hub
595 02:30:48.367467 <6>[ 0.432092] usbcore: registered new device driver usb
596 02:30:48.373026 <6>[ 0.438587] pps_core: LinuxPPS API ver. 1 registered
597 02:30:48.384419 <6>[ 0.444014] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 02:30:48.389453 <6>[ 0.453714] PTP clock support registered
599 02:30:48.414596 <6>[ 0.479606] EDAC MC: Ver: 3.0.0
600 02:30:48.433477 <6>[ 0.496620] scmi_core: SCMI protocol bus registered
601 02:30:48.448466 <6>[ 0.513906] vgaarb: loaded
602 02:30:48.461154 <6>[ 0.526842] clocksource: Switched to clocksource dmtimer
603 02:30:48.497166 <6>[ 0.562586] NET: Registered PF_INET protocol family
604 02:30:48.509772 <6>[ 0.568242] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 02:30:48.515525 <6>[ 0.577081] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 02:30:48.527021 <6>[ 0.585973] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 02:30:48.532771 <6>[ 0.594243] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 02:30:48.544383 <6>[ 0.602532] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 02:30:48.550166 <6>[ 0.610248] TCP: Hash tables configured (established 4096 bind 4096)
610 02:30:48.556019 <6>[ 0.617169] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 02:30:48.561897 <6>[ 0.624180] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 02:30:48.569360 <6>[ 0.631791] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 02:30:48.606164 <6>[ 0.666233] RPC: Registered named UNIX socket transport module.
614 02:30:48.606440 <6>[ 0.672660] RPC: Registered udp transport module.
615 02:30:48.612017 <6>[ 0.677791] RPC: Registered tcp transport module.
616 02:30:48.617798 <6>[ 0.682895] RPC: Registered tcp-with-tls transport module.
617 02:30:48.630690 <6>[ 0.688824] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 02:30:48.630967 <6>[ 0.695731] PCI: CLS 0 bytes, default 64
619 02:30:48.637823 <5>[ 0.701511] Initialise system trusted keyrings
620 02:30:48.662831 <6>[ 0.725446] Trying to unpack rootfs image as initramfs...
621 02:30:48.687892 <6>[ 0.747375] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 02:30:48.692569 <6>[ 0.754854] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 02:30:48.734408 <5>[ 0.800144] NFS: Registering the id_resolver key type
624 02:30:48.740278 <5>[ 0.805727] Key type id_resolver registered
625 02:30:48.746020 <5>[ 0.810385] Key type id_legacy registered
626 02:30:48.751765 <6>[ 0.814820] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 02:30:48.761553 <6>[ 0.822035] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 02:30:48.804584 <5>[ 0.870297] Key type asymmetric registered
629 02:30:48.810371 <5>[ 0.874818] Asymmetric key parser 'x509' registered
630 02:30:48.821980 <6>[ 0.880295] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 02:30:48.822261 <6>[ 0.888231] io scheduler mq-deadline registered
632 02:30:48.827693 <6>[ 0.893161] io scheduler kyber registered
633 02:30:48.833300 <6>[ 0.897627] io scheduler bfq registered
634 02:30:49.198734 <6>[ 1.260423] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
635 02:30:49.227970 <6>[ 1.293165] msm_serial: driver initialized
636 02:30:49.233689 <6>[ 1.298181] SuperH (H)SCI(F) driver initialized
637 02:30:49.239667 <6>[ 1.303306] STMicroelectronics ASC driver initialized
638 02:30:49.244858 <6>[ 1.308971] STM32 USART driver initialized
639 02:30:49.334336 <6>[ 1.399412] brd: module loaded
640 02:30:49.377179 <6>[ 1.442191] loop: module loaded
641 02:30:49.429456 <6>[ 1.494242] CAN device driver interface
642 02:30:49.435914 <6>[ 1.499484] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
643 02:30:49.441668 <6>[ 1.506406] e1000e: Intel(R) PRO/1000 Network Driver
644 02:30:49.447539 <6>[ 1.511854] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
645 02:30:49.453289 <6>[ 1.518289] igb: Intel(R) Gigabit Ethernet Network Driver
646 02:30:49.461466 <6>[ 1.524114] igb: Copyright (c) 2007-2014 Intel Corporation.
647 02:30:49.473162 <6>[ 1.533266] pegasus: Pegasus/Pegasus II USB Ethernet driver
648 02:30:49.479062 <6>[ 1.539413] usbcore: registered new interface driver pegasus
649 02:30:49.484888 <6>[ 1.545540] usbcore: registered new interface driver asix
650 02:30:49.490552 <6>[ 1.551420] usbcore: registered new interface driver ax88179_178a
651 02:30:49.496330 <6>[ 1.558007] usbcore: registered new interface driver cdc_ether
652 02:30:49.502176 <6>[ 1.564306] usbcore: registered new interface driver smsc75xx
653 02:30:49.507922 <6>[ 1.570562] usbcore: registered new interface driver smsc95xx
654 02:30:49.513697 <6>[ 1.576770] usbcore: registered new interface driver net1080
655 02:30:49.519425 <6>[ 1.582912] usbcore: registered new interface driver cdc_subset
656 02:30:49.525323 <6>[ 1.589318] usbcore: registered new interface driver zaurus
657 02:30:49.533065 <6>[ 1.595385] usbcore: registered new interface driver cdc_ncm
658 02:30:49.542650 <6>[ 1.604778] usbcore: registered new interface driver usb-storage
659 02:30:49.635197 <6>[ 1.698964] i2c_dev: i2c /dev entries driver
660 02:30:49.695870 <5>[ 1.753494] cpuidle: enable-method property 'ti,am3352' found operations
661 02:30:49.701670 <6>[ 1.763115] sdhci: Secure Digital Host Controller Interface driver
662 02:30:49.709464 <6>[ 1.769883] sdhci: Copyright(c) Pierre Ossman
663 02:30:49.716851 <6>[ 1.776291] Synopsys Designware Multimedia Card Interface Driver
664 02:30:49.721768 <6>[ 1.784267] sdhci-pltfm: SDHCI platform and OF driver helper
665 02:30:49.785124 <6>[ 1.847009] ledtrig-cpu: registered to indicate activity on CPUs
666 02:30:49.839965 <6>[ 1.898096] usbcore: registered new interface driver usbhid
667 02:30:49.840361 <6>[ 1.904135] usbhid: USB HID core driver
668 02:30:49.884235 <6>[ 1.947279] NET: Registered PF_INET6 protocol family
669 02:30:49.931752 <6>[ 1.997534] Segment Routing with IPv6
670 02:30:49.937584 <6>[ 2.001685] In-situ OAM (IOAM) with IPv6
671 02:30:49.944344 <6>[ 2.006073] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 02:30:49.950079 <6>[ 2.013388] NET: Registered PF_PACKET protocol family
673 02:30:49.955953 <6>[ 2.018939] can: controller area network core
674 02:30:49.961667 <6>[ 2.023762] NET: Registered PF_CAN protocol family
675 02:30:49.961942 <6>[ 2.028984] can: raw protocol
676 02:30:49.967423 <6>[ 2.032308] can: broadcast manager protocol
677 02:30:49.973904 <6>[ 2.036902] can: netlink gateway - max_hops=1
678 02:30:49.980027 <5>[ 2.042382] Key type dns_resolver registered
679 02:30:49.986279 <6>[ 2.047450] ThumbEE CPU extension supported.
680 02:30:49.986549 <5>[ 2.052137] Registering SWP/SWPB emulation handler
681 02:30:49.996097 <3>[ 2.057832] omap_voltage_late_init: Voltage driver support not added
682 02:30:50.079035 <5>[ 2.142295] Loading compiled-in X.509 certificates
683 02:30:50.202674 <6>[ 2.255458] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 02:30:50.209839 <6>[ 2.272112] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 02:30:50.236031 <3>[ 2.295640] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 02:30:50.317042 <3>[ 2.376632] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 02:30:50.433276 <6>[ 2.497278] OMAP GPIO hardware version 0.1
688 02:30:50.453856 <6>[ 2.515751] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 02:30:50.517068 <4>[ 2.578637] at24 2-0054: supply vcc not found, using dummy regulator
690 02:30:50.571416 <4>[ 2.633117] at24 2-0055: supply vcc not found, using dummy regulator
691 02:30:50.610039 <4>[ 2.671779] at24 2-0056: supply vcc not found, using dummy regulator
692 02:30:50.652787 <4>[ 2.714499] at24 2-0057: supply vcc not found, using dummy regulator
693 02:30:50.687798 <6>[ 2.750314] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 02:30:50.770785 <3>[ 2.829340] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 02:30:50.795275 <6>[ 2.850135] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 02:30:50.816168 <4>[ 2.876555] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 02:30:50.857290 <4>[ 2.917709] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 02:30:50.926169 <6>[ 2.988015] omap_rng 48310000.rng: Random Number Generator ver. 20
699 02:30:50.949170 <5>[ 3.013966] random: crng init done
700 02:30:51.047275 <6>[ 3.107622] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 02:30:51.719622 <6>[ 3.783730] Freeing initrd memory: 14448K
702 02:30:51.759509 <6>[ 3.819286] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 02:30:51.765258 <6>[ 3.829456] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
704 02:30:51.777048 <6>[ 3.836721] cpsw-switch 4a100000.switch: ALE Table size 1024
705 02:30:51.783021 <6>[ 3.843134] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
706 02:30:51.794388 <6>[ 3.851259] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
707 02:30:51.801884 <6>[ 3.862889] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
708 02:30:51.813933 <5>[ 3.871921] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
709 02:30:51.841507 <3>[ 3.901574] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
710 02:30:51.847298 <6>[ 3.910144] edma 49000000.dma: TI EDMA DMA engine driver
711 02:30:51.918015 <3>[ 3.977237] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
712 02:30:51.931479 <6>[ 3.991446] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
713 02:30:51.950195 <3>[ 4.013344] l3-aon-clkctrl:0000:0: failed to disable
714 02:30:51.988097 <6>[ 4.048022] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
715 02:30:51.993687 <6>[ 4.057463] printk: legacy console [ttyS0] enabled
716 02:30:51.999261 <6>[ 4.057463] printk: legacy console [ttyS0] enabled
717 02:30:52.005025 <6>[ 4.067786] printk: legacy bootconsole [omap8250] disabled
718 02:30:52.010828 <6>[ 4.067786] printk: legacy bootconsole [omap8250] disabled
719 02:30:52.058404 <4>[ 4.117505] tps65217-pmic: Failed to locate of_node [id: -1]
720 02:30:52.062092 <4>[ 4.124876] tps65217-bl: Failed to locate of_node [id: -1]
721 02:30:52.078203 <6>[ 4.144241] tps65217 0-0024: TPS65217 ID 0xe version 1.2
722 02:30:52.098660 <6>[ 4.151139] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
723 02:30:52.110306 <6>[ 4.164827] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
724 02:30:52.113039 <6>[ 4.176663] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
725 02:30:52.136560 <6>[ 4.197016] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
726 02:30:52.142405 <6>[ 4.206071] sdhci-omap 48060000.mmc: Got CD GPIO
727 02:30:52.150493 <4>[ 4.211248] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
728 02:30:52.165811 <4>[ 4.224802] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
729 02:30:52.172026 <4>[ 4.234059] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
730 02:30:52.181955 <4>[ 4.242619] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
731 02:30:52.277866 <6>[ 4.339260] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
732 02:30:52.312989 <6>[ 4.373534] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
733 02:30:52.336020 <6>[ 4.395671] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 02:30:52.342821 <6>[ 4.404579] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
735 02:30:52.417459 <6>[ 4.473322] mmc1: new high speed MMC card at address 0001
736 02:30:52.417736 <6>[ 4.481322] mmcblk1: mmc1:0001 M62704 3.56 GiB
737 02:30:52.427284 <6>[ 4.491324] mmcblk1: p1
738 02:30:52.432568 <6>[ 4.496063] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
739 02:30:52.444256 <6>[ 4.507570] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
740 02:30:52.458514 <6>[ 4.518335] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
741 02:30:52.467703 <6>[ 4.525423] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 02:30:55.587717 <6>[ 7.647799] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
743 02:30:55.660908 <5>[ 7.686851] Sending DHCP requests ., OK
744 02:30:55.672409 <6>[ 7.731246] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.7
745 02:30:55.672681 <6>[ 7.739475] IP-Config: Complete:
746 02:30:55.683639 <6>[ 7.743013] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.7, mask=255.255.255.0, gw=192.168.11.1
747 02:30:55.689392 <6>[ 7.753606] host=192.168.11.7, domain=usen.ad.jp, nis-domain=(none)
748 02:30:55.701638 <6>[ 7.760682] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
749 02:30:55.701909 <6>[ 7.760714] nameserver0=192.168.11.1
750 02:30:55.707763 <6>[ 7.772974] clk: Disabling unused clocks
751 02:30:55.714313 <6>[ 7.777718] PM: genpd: Disabling unused power domains
752 02:30:55.733688 <6>[ 7.796184] Freeing unused kernel image (initmem) memory: 2048K
753 02:30:55.740958 <6>[ 7.805738] Run /init as init process
754 02:30:55.765450 Loading, please wait...
755 02:30:55.840049 Starting systemd-udevd version 252.22-1~deb12u1
756 02:30:58.869060 <4>[ 10.927863] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
757 02:30:59.149706 <4>[ 11.208538] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
758 02:30:59.279635 <6>[ 11.346032] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
759 02:30:59.290635 <6>[ 11.351951] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
760 02:30:59.404402 <6>[ 11.469253] hub 1-0:1.0: USB hub found
761 02:30:59.452511 <6>[ 11.517136] hub 1-0:1.0: 1 port detected
762 02:30:59.460155 <6>[ 11.524514] tda998x 0-0070: found TDA19988
763 02:31:02.342875 Begin: Loading essential drivers ... done.
764 02:31:02.348575 Begin: Running /scripts/init-premount ... done.
765 02:31:02.354019 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
766 02:31:02.364190 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
767 02:31:02.375606 Device /sys/class/net/eth0 found
768 02:31:02.375833 done.
769 02:31:02.433911 Begin: Waiting up to 180 secs for any network device to become available ... done.
770 02:31:02.516418 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
771 02:31:02.516715 IP-Config: eth0 guessed broadcast address 192.168.11.255
772 02:31:02.521926 IP-Config: eth0 complete (dhcp from 192.168.11.1):
773 02:31:02.533154 address: 192.168.11.7 broadcast: 192.168.11.255 netmask: 255.255.255.0
774 02:31:02.538760 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
775 02:31:02.544383 domain : usen.ad.jp
776 02:31:02.549228 rootserver: 192.168.11.1 rootpath:
777 02:31:02.549460 filename :
778 02:31:02.621000 done.
779 02:31:02.630059 Begin: Running /scripts/nfs-bottom ... done.
780 02:31:02.701126 Begin: Running /scripts/init-bottom ... done.
781 02:31:03.886125 <30>[ 15.948094] systemd[1]: System time before build time, advancing clock.
782 02:31:04.057917 <30>[ 16.093918] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
783 02:31:04.066633 <30>[ 16.130633] systemd[1]: Detected architecture arm.
784 02:31:04.080153
785 02:31:04.080415 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
786 02:31:04.080639
787 02:31:04.114266 <30>[ 16.176975] systemd[1]: Hostname set to <debian-bookworm-armhf>.
788 02:31:06.261480 <30>[ 18.323029] systemd[1]: Queued start job for default target graphical.target.
789 02:31:06.278385 <30>[ 18.338140] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
790 02:31:06.285933 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
791 02:31:06.321190 <30>[ 18.379850] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
792 02:31:06.328565 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
793 02:31:06.360517 <30>[ 18.420210] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
794 02:31:06.368923 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
795 02:31:06.399135 <30>[ 18.459053] systemd[1]: Created slice user.slice - User and Session Slice.
796 02:31:06.405844 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
797 02:31:06.441508 <30>[ 18.499057] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
798 02:31:06.454408 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
799 02:31:06.488019 <30>[ 18.548069] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
800 02:31:06.499011 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
801 02:31:06.538767 <30>[ 18.587901] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
802 02:31:06.545124 <30>[ 18.608368] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
803 02:31:06.553599 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
804 02:31:06.586771 <30>[ 18.647241] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
805 02:31:06.594954 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
806 02:31:06.627643 <30>[ 18.687658] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
807 02:31:06.636058 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
808 02:31:06.667521 <30>[ 18.727797] systemd[1]: Reached target paths.target - Path Units.
809 02:31:06.672572 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
810 02:31:06.707214 <30>[ 18.767538] systemd[1]: Reached target remote-fs.target - Remote File Systems.
811 02:31:06.714521 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
812 02:31:06.747084 <30>[ 18.807465] systemd[1]: Reached target slices.target - Slice Units.
813 02:31:06.752519 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
814 02:31:06.788461 <30>[ 18.848292] systemd[1]: Reached target swap.target - Swaps.
815 02:31:06.792580 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
816 02:31:06.827521 <30>[ 18.887572] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
817 02:31:06.836601 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
818 02:31:06.868486 <30>[ 18.928433] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
819 02:31:06.876706 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
820 02:31:06.966018 <30>[ 19.021260] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
821 02:31:06.978599 <30>[ 19.038677] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
822 02:31:06.986994 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
823 02:31:07.019755 <30>[ 19.079208] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
824 02:31:07.027177 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
825 02:31:07.060624 <30>[ 19.120483] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
826 02:31:07.068804 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
827 02:31:07.102144 <30>[ 19.161778] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
828 02:31:07.107770 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
829 02:31:07.149698 <30>[ 19.210613] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
830 02:31:07.162423 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
831 02:31:07.204773 <30>[ 19.258627] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
832 02:31:07.221288 <30>[ 19.275347] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
833 02:31:07.258460 <30>[ 19.319361] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
834 02:31:07.276999 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
835 02:31:07.348571 <30>[ 19.409316] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
836 02:31:07.382198 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
837 02:31:07.448178 <30>[ 19.508108] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
838 02:31:07.466071 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
839 02:31:07.499942 <30>[ 19.560492] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
840 02:31:07.516246 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
841 02:31:07.567484 <30>[ 19.628237] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
842 02:31:07.582429 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
843 02:31:07.648049 <30>[ 19.709437] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
844 02:31:07.664702 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
845 02:31:07.697953 <30>[ 19.758024] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
846 02:31:07.716959 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
847 02:31:07.776786 <30>[ 19.838026] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
848 02:31:07.794511 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
849 02:31:07.870040 <30>[ 19.931244] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
850 02:31:07.888541 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
851 02:31:07.923972 <28>[ 19.979178] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
852 02:31:07.932365 <28>[ 19.992793] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
853 02:31:07.968538 <30>[ 20.030166] systemd[1]: Starting systemd-journald.service - Journal Service...
854 02:31:07.997079 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
855 02:31:08.079104 <30>[ 20.140033] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
856 02:31:08.091198 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
857 02:31:08.158521 <30>[ 20.219542] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
858 02:31:08.202246 Starting [0;1;39msystemd-network-g… units from Kernel command line...
859 02:31:08.295594 <30>[ 20.355126] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
860 02:31:08.347293 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
861 02:31:08.413611 <30>[ 20.473902] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
862 02:31:08.462368 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
863 02:31:08.508687 <30>[ 20.569929] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
864 02:31:08.548135 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
865 02:31:08.587548 <30>[ 20.648615] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
866 02:31:08.620134 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
867 02:31:08.661640 <30>[ 20.721716] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
868 02:31:08.687005 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
869 02:31:08.807189 <30>[ 20.867613] systemd[1]: Started systemd-journald.service - Journal Service.
870 02:31:08.813958 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
871 02:31:08.857266 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
872 02:31:08.892702 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
873 02:31:08.938012 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
874 02:31:08.972128 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
875 02:31:08.991724 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
876 02:31:09.011686 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
877 02:31:09.029557 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
878 02:31:09.060499 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
879 02:31:09.107175 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
880 02:31:09.127052 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
881 02:31:09.209947 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
882 02:31:09.256822 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
883 02:31:09.318321 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
884 02:31:09.407120 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
885 02:31:09.500590 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
886 02:31:09.622020 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
887 02:31:09.653494 <46>[ 21.714687] systemd-journald[163]: Received client request to flush runtime journal.
888 02:31:09.768467 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
889 02:31:09.883449 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
890 02:31:10.629000 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
891 02:31:10.689391 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
892 02:31:11.427524 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
893 02:31:11.539769 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
894 02:31:11.576773 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
895 02:31:11.606747 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
896 02:31:11.696320 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
897 02:31:11.752288 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
898 02:31:12.672347 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
899 02:31:12.747852 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
900 02:31:12.796877 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
901 02:31:12.917009 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
902 02:31:12.966139 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
903 02:31:14.733414 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
904 02:31:15.318608 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
905 02:31:15.471832 <5>[ 27.533462] cfg80211: Loading compiled-in X.509 certificates for regulatory database
906 02:31:16.644291 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
907 02:31:17.069267 <5>[ 29.128633] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
908 02:31:17.074643 <5>[ 29.136754] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
909 02:31:17.085853 <4>[ 29.147355] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
910 02:31:17.091769 <6>[ 29.156334] cfg80211: failed to load regulatory.db
911 02:31:17.759909 <46>[ 29.811440] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
912 02:31:17.842026 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
913 02:31:17.986522 <46>[ 30.041276] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
914 02:31:18.253325 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
915 02:31:26.938243 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
916 02:31:26.979754 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
917 02:31:27.020882 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
918 02:31:27.057380 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
919 02:31:27.142066 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
920 02:31:27.179345 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
921 02:31:27.260361 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
922 02:31:27.296004 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
923 02:31:27.359532 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
924 02:31:27.409609 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
925 02:31:27.461479 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
926 02:31:27.526127 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
927 02:31:27.561282 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
928 02:31:27.612671 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
929 02:31:27.662319 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
930 02:31:27.697736 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
931 02:31:27.743973 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
932 02:31:27.785436 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
933 02:31:27.817110 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
934 02:31:27.827976 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
935 02:31:27.872725 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
936 02:31:27.909445 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
937 02:31:27.948888 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
938 02:31:28.000096 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
939 02:31:28.052695 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
940 02:31:28.176429 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
941 02:31:28.285109 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
942 02:31:28.365648 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
943 02:31:28.397097 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
944 02:31:28.420503 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
945 02:31:28.620603 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
946 02:31:28.657707 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
947 02:31:28.766578 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
948 02:31:28.828850 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
949 02:31:28.856964 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
950 02:31:28.980339 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
951 02:31:29.294056 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
952 02:31:29.343276 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
953 02:31:29.380281 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
954 02:31:29.466748 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
955 02:31:29.641039 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
956 02:31:29.764733
957 02:31:29.765010 Debian GNU/Linux 12worm-armhf login: root (automatic login)
958 02:31:29.768118
959 02:31:30.068366 Linux debian-bookworm-armhf 6.11.0-rc5 #1 SMP Sat Aug 31 23:24:39 UTC 2024 armv7l
960 02:31:30.068717
961 02:31:30.073959 The programs included with the Debian GNU/Linux system are free software;
962 02:31:30.079594 the exact distribution terms for each program are described in the
963 02:31:30.085215 individual files in /usr/share/doc/*/copyright.
964 02:31:30.085491
965 02:31:30.093151 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
966 02:31:30.093429 permitted by applicable law.
967 02:31:34.721731 Unable to match end of the kernel message
969 02:31:34.722553 Setting prompt string to ['/ #']
970 02:31:34.722855 end: 2.4.4.1 login-action (duration 00:00:47) [common]
972 02:31:34.723545 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
973 02:31:34.723833 start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
974 02:31:34.724080 Setting prompt string to ['/ #']
975 02:31:34.724329 Forcing a shell prompt, looking for ['/ #']
977 02:31:34.774863 / #
978 02:31:34.775257 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
979 02:31:34.775515 Waiting using forced prompt support (timeout 00:02:30)
980 02:31:34.779723
981 02:31:34.785470 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
982 02:31:34.785802 start: 2.4.6 export-device-env (timeout 00:03:24) [common]
983 02:31:34.786061 Sending with 10 millisecond of delay
985 02:31:39.835037 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco'
986 02:31:39.845657 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1186838/extract-nfsrootfs-kqwcrcco'
987 02:31:39.846163 Sending with 10 millisecond of delay
989 02:31:42.004330 / # export NFS_SERVER_IP='192.168.11.5'
990 02:31:42.015027 export NFS_SERVER_IP='192.168.11.5'
991 02:31:42.015696 end: 2.4.6 export-device-env (duration 00:00:07) [common]
992 02:31:42.016014 end: 2.4 uboot-commands (duration 00:01:43) [common]
993 02:31:42.016345 end: 2 uboot-action (duration 00:01:43) [common]
994 02:31:42.016659 start: 3 lava-test-retry (timeout 00:07:19) [common]
995 02:31:42.016970 start: 3.1 lava-test-shell (timeout 00:07:19) [common]
996 02:31:42.017230 Using namespace: common
998 02:31:42.117924 / # #
999 02:31:42.118297 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1000 02:31:42.122742 #
1001 02:31:42.128783 Using /lava-1186838
1003 02:31:42.229550 / # export SHELL=/bin/bash
1004 02:31:42.234528 export SHELL=/bin/bash
1006 02:31:42.340864 / # . /lava-1186838/environment
1007 02:31:42.345637 . /lava-1186838/environment
1009 02:31:42.458046 / # /lava-1186838/bin/lava-test-runner /lava-1186838/0
1010 02:31:42.458424 Test shell timeout: 10s (minimum of the action and connection timeout)
1011 02:31:42.462763 /lava-1186838/bin/lava-test-runner /lava-1186838/0
1012 02:31:42.879685 + export TESTRUN_ID=0_timesync-off
1013 02:31:42.887695 + TESTRUN_ID=0_timesync-off
1014 02:31:42.887939 + cd /lava-1186838/0/tests/0_timesync-off
1015 02:31:42.888163 ++ cat uuid
1016 02:31:42.902287 + UUID=1186838_1.6.2.4.1
1017 02:31:42.902586 + set +x
1018 02:31:42.907854 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1186838_1.6.2.4.1>
1019 02:31:42.908274 Received signal: <STARTRUN> 0_timesync-off 1186838_1.6.2.4.1
1020 02:31:42.908514 Starting test lava.0_timesync-off (1186838_1.6.2.4.1)
1021 02:31:42.908789 Skipping test definition patterns.
1022 02:31:42.911062 + systemctl stop systemd-timesyncd
1023 02:31:43.204483 + set +x
1024 02:31:43.205073 Received signal: <ENDRUN> 0_timesync-off 1186838_1.6.2.4.1
1025 02:31:43.205357 Ending use of test pattern.
1026 02:31:43.205582 Ending test lava.0_timesync-off (1186838_1.6.2.4.1), duration 0.30
1028 02:31:43.207561 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1186838_1.6.2.4.1>
1029 02:31:43.371385 + export TESTRUN_ID=1_kselftest-dt
1030 02:31:43.379489 + TESTRUN_ID=1_kselftest-dt
1031 02:31:43.379768 + cd /lava-1186838/0/tests/1_kselftest-dt
1032 02:31:43.380002 ++ cat uuid
1033 02:31:43.393666 + UUID=1186838_1.6.2.4.5
1034 02:31:43.393945 + set +x
1035 02:31:43.399268 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1186838_1.6.2.4.5>
1036 02:31:43.399545 + cd ./automated/linux/kselftest/
1037 02:31:43.399981 Received signal: <STARTRUN> 1_kselftest-dt 1186838_1.6.2.4.5
1038 02:31:43.400231 Starting test lava.1_kselftest-dt (1186838_1.6.2.4.5)
1039 02:31:43.400496 Skipping test definition patterns.
1040 02:31:43.427560 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1041 02:31:43.533459 INFO: install_deps skipped
1042 02:31:44.065867 --2024-09-01 02:31:44-- http://storage.kernelci.org/mainline/master/v6.11-rc5-316-g6cd90e5ea72f3/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1043 02:31:44.086258 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1044 02:31:44.200328 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1045 02:31:44.313912 HTTP request sent, awaiting response... 200 OK
1046 02:31:44.314189 Length: 3606188 (3.4M) [application/octet-stream]
1047 02:31:44.319475 Saving to: 'kselftest_armhf.tar.gz'
1048 02:31:44.319750
1049 02:31:45.672455 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 225KB/s kselftest_armhf.tar 5%[> ] 194.76K 432KB/s kselftest_armhf.tar 17%[==> ] 631.14K 906KB/s kselftest_armhf.tar 44%[=======> ] 1.52M 1.70MB/s kselftest_armhf.tar 67%[============> ] 2.31M 2.08MB/s kselftest_armhf.tar 94%[=================> ] 3.24M 2.43MB/s kselftest_armhf.tar 100%[===================>] 3.44M 2.54MB/s in 1.4s
1050 02:31:45.672807
1051 02:31:46.351176 2024-09-01 02:31:45 (2.54 MB/s) - 'kselftest_armhf.tar.gz' saved [3606188/3606188]
1052 02:31:46.351532
1053 02:32:05.481812 skiplist:
1054 02:32:05.482199 ========================================
1055 02:32:05.487549 ========================================
1056 02:32:05.587726 dt:test_unprobed_devices.sh
1057 02:32:05.620176 ============== Tests to run ===============
1058 02:32:05.627610 dt:test_unprobed_devices.sh
1059 02:32:05.631618 ===========End Tests to run ===============
1060 02:32:05.643721 shardfile-dt pass
1061 02:32:05.870057 <12>[ 77.937224] kselftest: Running tests in dt
1062 02:32:05.897468 TAP version 13
1063 02:32:05.920830 1..1
1064 02:32:05.973730 # timeout set to 45
1065 02:32:05.973997 # selftests: dt: test_unprobed_devices.sh
1066 02:32:06.665140 # TAP version 13
1067 02:32:18.753039 # 1..255
1068 02:32:18.931343 # ok 1 / # SKIP
1069 02:32:18.952981 # ok 2 /clk_mcasp0
1070 02:32:19.024016 # ok 3 /clk_mcasp0_fixed # SKIP
1071 02:32:19.093339 # ok 4 /cpus/cpu@0 # SKIP
1072 02:32:19.168412 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1073 02:32:19.184829 # ok 6 /fixedregulator0
1074 02:32:19.204945 # ok 7 /leds
1075 02:32:19.226196 # ok 8 /ocp
1076 02:32:19.249133 # ok 9 /ocp/interconnect@44c00000
1077 02:32:19.272480 # ok 10 /ocp/interconnect@44c00000/segment@0
1078 02:32:19.298663 # ok 11 /ocp/interconnect@44c00000/segment@100000
1079 02:32:19.321786 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1080 02:32:19.392552 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1081 02:32:19.410551 # ok 14 /ocp/interconnect@44c00000/segment@200000
1082 02:32:19.433177 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1083 02:32:19.541697 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1084 02:32:19.612564 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1085 02:32:19.677710 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1086 02:32:19.754540 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1087 02:32:19.819190 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1088 02:32:19.896952 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1089 02:32:19.960172 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1090 02:32:20.034553 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1091 02:32:20.104537 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1092 02:32:20.181210 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1093 02:32:20.243924 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1094 02:32:20.323499 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1095 02:32:20.392280 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1096 02:32:20.465193 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1097 02:32:20.526886 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1098 02:32:20.604678 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1099 02:32:20.671182 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1100 02:32:20.741939 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1101 02:32:20.814367 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1102 02:32:20.877561 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1103 02:32:20.952823 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1104 02:32:21.017425 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1105 02:32:21.095448 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1106 02:32:21.157758 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1107 02:32:21.233923 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1108 02:32:21.304274 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1109 02:32:21.376555 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1110 02:32:21.440160 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1111 02:32:21.517909 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1112 02:32:21.585904 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1113 02:32:21.655955 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1114 02:32:21.732779 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1115 02:32:21.803040 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1116 02:32:21.867951 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1117 02:32:21.946435 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1118 02:32:22.011515 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1119 02:32:22.086512 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1120 02:32:22.160385 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1121 02:32:22.233947 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1122 02:32:22.296898 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1123 02:32:22.374586 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1124 02:32:22.438466 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1125 02:32:22.514815 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1126 02:32:22.579949 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1127 02:32:22.657523 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1128 02:32:22.725598 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1129 02:32:22.795245 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1130 02:32:22.871225 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1131 02:32:22.940285 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1132 02:32:23.010746 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1133 02:32:23.085121 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1134 02:32:23.156509 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1135 02:32:23.227244 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1136 02:32:23.295366 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1137 02:32:23.365207 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1138 02:32:23.442660 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1139 02:32:23.513353 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1140 02:32:23.584122 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1141 02:32:23.647561 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1142 02:32:23.725949 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1143 02:32:23.795566 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1144 02:32:23.865662 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1145 02:32:23.937535 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1146 02:32:24.000461 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1147 02:32:24.076221 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1148 02:32:24.142598 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1149 02:32:24.221287 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1150 02:32:24.289337 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1151 02:32:24.362255 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1152 02:32:24.433551 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1153 02:32:24.504447 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1154 02:32:24.574466 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1155 02:32:24.646254 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1156 02:32:24.718277 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1157 02:32:24.783137 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1158 02:32:24.856633 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1159 02:32:24.928797 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1160 02:32:25.001647 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1161 02:32:25.072887 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1162 02:32:25.092994 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1163 02:32:25.109418 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1164 02:32:25.137921 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1165 02:32:25.161807 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1166 02:32:25.178533 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1167 02:32:25.209179 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1168 02:32:25.225149 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1169 02:32:25.253731 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1170 02:32:25.352869 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1171 02:32:25.378966 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1172 02:32:25.404083 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1173 02:32:25.424273 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1174 02:32:25.529025 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1175 02:32:25.606036 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1176 02:32:25.672783 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1177 02:32:25.746140 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1178 02:32:25.815929 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1179 02:32:25.889021 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1180 02:32:25.953262 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1181 02:32:26.026391 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1182 02:32:26.103546 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1183 02:32:26.168397 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1184 02:32:26.246920 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1185 02:32:26.315289 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1186 02:32:26.380266 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1187 02:32:26.460162 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1188 02:32:26.530233 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1189 02:32:26.607765 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1190 02:32:26.626515 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1191 02:32:26.694402 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1192 02:32:26.761949 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1193 02:32:26.835510 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1194 02:32:26.854395 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1195 02:32:26.922349 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1196 02:32:26.948400 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1197 02:32:27.019854 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1198 02:32:27.043847 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1199 02:32:27.063873 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1200 02:32:27.084559 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1201 02:32:27.113868 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1202 02:32:27.138770 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1203 02:32:27.155206 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1204 02:32:27.185214 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1205 02:32:27.214841 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1206 02:32:27.230734 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1207 02:32:27.304705 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1208 02:32:27.376956 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1209 02:32:27.392846 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1210 02:32:27.464952 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1211 02:32:27.541565 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1212 02:32:27.629852 # not ok 145 /ocp/interconnect@47c00000
1213 02:32:27.704890 # not ok 146 /ocp/interconnect@47c00000/segment@0
1214 02:32:27.724718 # ok 147 /ocp/interconnect@48000000
1215 02:32:27.747349 # ok 148 /ocp/interconnect@48000000/segment@0
1216 02:32:27.771322 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1217 02:32:27.795668 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1218 02:32:27.814079 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1219 02:32:27.837373 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1220 02:32:27.867344 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1221 02:32:27.884443 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1222 02:32:27.911326 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1223 02:32:27.981636 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1224 02:32:28.052679 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1225 02:32:28.074374 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1226 02:32:28.095208 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1227 02:32:28.123612 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1228 02:32:28.141027 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1229 02:32:28.168358 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1230 02:32:28.194561 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1231 02:32:28.209121 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1232 02:32:28.241625 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1233 02:32:28.256357 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1234 02:32:28.282089 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1235 02:32:28.302088 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1236 02:32:28.332678 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1237 02:32:28.347807 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1238 02:32:28.371892 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1239 02:32:28.398791 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1240 02:32:28.423709 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1241 02:32:28.440927 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1242 02:32:28.468502 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1243 02:32:28.494339 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1244 02:32:28.508711 # ok 177 /ocp/interconnect@48000000/segment@100000
1245 02:32:28.538983 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1246 02:32:28.561446 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1247 02:32:28.636459 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1248 02:32:28.698688 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1249 02:32:28.774185 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1250 02:32:28.842182 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1251 02:32:28.864289 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1252 02:32:28.889982 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1253 02:32:28.906313 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1254 02:32:28.932551 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1255 02:32:28.952825 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1256 02:32:28.981420 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1257 02:32:28.998672 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1258 02:32:29.023308 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1259 02:32:29.052644 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1260 02:32:29.068033 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1261 02:32:29.098422 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1262 02:32:29.121391 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1263 02:32:29.135275 # ok 196 /ocp/interconnect@48000000/segment@200000
1264 02:32:29.159850 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1265 02:32:29.236389 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1266 02:32:29.258310 # ok 199 /ocp/interconnect@48000000/segment@300000
1267 02:32:29.275408 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1268 02:32:29.298901 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1269 02:32:29.327892 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1270 02:32:29.351787 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1271 02:32:29.371417 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1272 02:32:29.391640 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1273 02:32:29.461993 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1274 02:32:29.485318 # ok 207 /ocp/interconnect@4a000000
1275 02:32:29.507953 # ok 208 /ocp/interconnect@4a000000/segment@0
1276 02:32:29.531108 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1277 02:32:29.556952 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1278 02:32:29.581663 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1279 02:32:29.595129 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1280 02:32:29.671360 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1281 02:32:29.776126 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1282 02:32:29.845386 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1283 02:32:29.944011 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1284 02:32:30.021814 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1285 02:32:30.085205 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1286 02:32:30.186263 # not ok 219 /ocp/interconnect@4b140000
1287 02:32:30.249723 # not ok 220 /ocp/interconnect@4b140000/segment@0
1288 02:32:30.340041 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1289 02:32:30.340347 # ok 222 /ocp/target-module@40300000
1290 02:32:30.362746 # ok 223 /ocp/target-module@40300000/sram@0
1291 02:32:30.442964 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1292 02:32:30.511699 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1293 02:32:30.528406 # ok 226 /ocp/target-module@47400000
1294 02:32:30.557770 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1295 02:32:30.572266 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1296 02:32:30.594585 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1297 02:32:30.620120 # ok 230 /ocp/target-module@47400000/usb@1400
1298 02:32:30.637932 # ok 231 /ocp/target-module@47400000/usb@1800
1299 02:32:30.660090 # ok 232 /ocp/target-module@47810000
1300 02:32:30.682031 # ok 233 /ocp/target-module@49000000
1301 02:32:30.708357 # ok 234 /ocp/target-module@49000000/dma@0
1302 02:32:30.728395 # ok 235 /ocp/target-module@49800000
1303 02:32:30.747758 # ok 236 /ocp/target-module@49800000/dma@0
1304 02:32:30.775777 # ok 237 /ocp/target-module@49900000
1305 02:32:30.797391 # ok 238 /ocp/target-module@49900000/dma@0
1306 02:32:30.818756 # ok 239 /ocp/target-module@49a00000
1307 02:32:30.838661 # ok 240 /ocp/target-module@49a00000/dma@0
1308 02:32:30.866299 # ok 241 /ocp/target-module@4c000000
1309 02:32:30.930126 # not ok 242 /ocp/target-module@4c000000/emif@0
1310 02:32:30.951618 # ok 243 /ocp/target-module@50000000
1311 02:32:30.973119 # ok 244 /ocp/target-module@53100000
1312 02:32:31.043780 # not ok 245 /ocp/target-module@53100000/sham@0
1313 02:32:31.064253 # ok 246 /ocp/target-module@53500000
1314 02:32:31.138825 # not ok 247 /ocp/target-module@53500000/aes@0
1315 02:32:31.158738 # ok 248 /ocp/target-module@56000000
1316 02:32:31.258652 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1317 02:32:31.332559 # ok 250 /opp-table # SKIP
1318 02:32:31.396521 # ok 251 /soc # SKIP
1319 02:32:31.416111 # ok 252 /sound
1320 02:32:31.444105 # ok 253 /target-module@4b000000
1321 02:32:31.463891 # ok 254 /target-module@4b000000/target-module@140000
1322 02:32:31.486548 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1323 02:32:31.492657 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1324 02:32:31.500336 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1325 02:32:33.747353 dt_test_unprobed_devices_sh_ skip
1326 02:32:33.752930 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1327 02:32:33.758542 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1328 02:32:33.758803 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1329 02:32:33.764040 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1330 02:32:33.769668 dt_test_unprobed_devices_sh_fixedregulator0 pass
1331 02:32:33.775416 dt_test_unprobed_devices_sh_leds pass
1332 02:32:33.775669 dt_test_unprobed_devices_sh_ocp pass
1333 02:32:33.780909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1334 02:32:33.786539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1335 02:32:33.792160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1336 02:32:33.803413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1337 02:32:33.809040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1338 02:32:33.814663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1339 02:32:33.825786 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1340 02:32:33.831412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1341 02:32:33.842677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1342 02:32:33.853923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1343 02:32:33.865048 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1344 02:32:33.870674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1345 02:32:33.881946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1346 02:32:33.893172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1347 02:32:33.904441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1348 02:32:33.915544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1349 02:32:33.921044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1350 02:32:33.932318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1351 02:32:33.943547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1352 02:32:33.954672 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1353 02:32:33.965938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1354 02:32:33.971419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1355 02:32:33.982671 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1356 02:32:33.993794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1357 02:32:34.005042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1358 02:32:34.010667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1359 02:32:34.021792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1360 02:32:34.033068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1361 02:32:34.044162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1362 02:32:34.055416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1363 02:32:34.060940 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1364 02:32:34.072167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1365 02:32:34.083414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1366 02:32:34.094555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1367 02:32:34.105792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1368 02:32:34.116935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1369 02:32:34.128165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1370 02:32:34.139413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1371 02:32:34.150626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1372 02:32:34.161662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1373 02:32:34.172935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1374 02:32:34.184142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1375 02:32:34.195263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1376 02:32:34.206537 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1377 02:32:34.217659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1378 02:32:34.228809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1379 02:32:34.240035 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1380 02:32:34.251284 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1381 02:32:34.262533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1382 02:32:34.273657 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1383 02:32:34.284929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1384 02:32:34.296158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1385 02:32:34.307407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1386 02:32:34.318533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1387 02:32:34.329785 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1388 02:32:34.340927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1389 02:32:34.346534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1390 02:32:34.357780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1391 02:32:34.368927 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1392 02:32:34.380155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1393 02:32:34.391404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1394 02:32:34.402528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1395 02:32:34.413782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1396 02:32:34.425033 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1397 02:32:34.436152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1398 02:32:34.447417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1399 02:32:34.458530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1400 02:32:34.469778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1401 02:32:34.480922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1402 02:32:34.492149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1403 02:32:34.503401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1404 02:32:34.514526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1405 02:32:34.525652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1406 02:32:34.536923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1407 02:32:34.542527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1408 02:32:34.553649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1409 02:32:34.564905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1410 02:32:34.576024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1411 02:32:34.587272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1412 02:32:34.592923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1413 02:32:34.609662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1414 02:32:34.620790 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1415 02:32:34.626396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1416 02:32:34.643271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1417 02:32:34.654395 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1418 02:32:34.665644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1419 02:32:34.671144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1420 02:32:34.682410 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1421 02:32:34.693518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1422 02:32:34.699147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1423 02:32:34.710397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1424 02:32:34.721536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1425 02:32:34.727114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1426 02:32:34.738334 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1427 02:32:34.743897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1428 02:32:34.755079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1429 02:32:34.766394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1430 02:32:34.777530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1431 02:32:34.788665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1432 02:32:34.799832 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1433 02:32:34.811032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1434 02:32:34.822264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1435 02:32:34.833391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1436 02:32:34.844684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1437 02:32:34.855762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1438 02:32:34.867014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1439 02:32:34.878134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1440 02:32:34.895014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1441 02:32:34.906139 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1442 02:32:34.917385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1443 02:32:34.928554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1444 02:32:34.939762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1445 02:32:34.956533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1446 02:32:34.967758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1447 02:32:34.978884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1448 02:32:34.990122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1449 02:32:34.995599 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1450 02:32:35.006873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1451 02:32:35.018093 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1452 02:32:35.023627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1453 02:32:35.034871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1454 02:32:35.040526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1455 02:32:35.051620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1456 02:32:35.057247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1457 02:32:35.068402 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1458 02:32:35.073967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1459 02:32:35.085245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1460 02:32:35.090742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1461 02:32:35.101960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1462 02:32:35.113248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1463 02:32:35.124404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1464 02:32:35.130004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1465 02:32:35.141084 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1466 02:32:35.152446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1467 02:32:35.157957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1468 02:32:35.169107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1469 02:32:35.174704 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1470 02:32:35.180341 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1471 02:32:35.186101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1472 02:32:35.191463 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1473 02:32:35.202700 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1474 02:32:35.208358 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1475 02:32:35.213831 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1476 02:32:35.225074 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1477 02:32:35.230702 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1478 02:32:35.241866 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1479 02:32:35.247471 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1480 02:32:35.258751 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1481 02:32:35.264384 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1482 02:32:35.269879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1483 02:32:35.281123 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1484 02:32:35.286623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1485 02:32:35.297874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1486 02:32:35.303498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1487 02:32:35.314624 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1488 02:32:35.320260 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1489 02:32:35.331336 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1490 02:32:35.336976 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1491 02:32:35.348250 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1492 02:32:35.353746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1493 02:32:35.364999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1494 02:32:35.370623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1495 02:32:35.381743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1496 02:32:35.387373 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1497 02:32:35.392998 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1498 02:32:35.404122 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1499 02:32:35.409748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1500 02:32:35.420994 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1501 02:32:35.426498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1502 02:32:35.437747 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1503 02:32:35.443371 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1504 02:32:35.454493 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1505 02:32:35.465748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1506 02:32:35.476867 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1507 02:32:35.482491 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1508 02:32:35.493742 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1509 02:32:35.499366 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1510 02:32:35.510492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1511 02:32:35.516120 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1512 02:32:35.527365 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1513 02:32:35.532865 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1514 02:32:35.544096 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1515 02:32:35.555364 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1516 02:32:35.560865 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1517 02:32:35.572122 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1518 02:32:35.577614 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1519 02:32:35.588865 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1520 02:32:35.594488 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1521 02:32:35.599987 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1522 02:32:35.611237 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1523 02:32:35.616860 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1524 02:32:35.622489 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1525 02:32:35.633615 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1526 02:32:35.639237 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1527 02:32:35.650359 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1528 02:32:35.655990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1529 02:32:35.667234 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1530 02:32:35.672739 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1531 02:32:35.678362 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1532 02:32:35.683988 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1533 02:32:35.695109 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1534 02:32:35.700738 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1535 02:32:35.711986 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1536 02:32:35.717483 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1537 02:32:35.728737 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1538 02:32:35.739856 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1539 02:32:35.751107 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1540 02:32:35.756731 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1541 02:32:35.767854 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1542 02:32:35.779106 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1543 02:32:35.784731 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1544 02:32:35.790316 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1545 02:32:35.795835 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1546 02:32:35.801488 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1547 02:32:35.807103 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1548 02:32:35.812732 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1549 02:32:35.823960 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1550 02:32:35.829610 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1551 02:32:35.835230 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1552 02:32:35.840715 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1553 02:32:35.846305 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1554 02:32:35.851943 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1555 02:32:35.857560 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1556 02:32:35.863184 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1557 02:32:35.868830 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1558 02:32:35.874450 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1559 02:32:35.879950 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1560 02:32:35.885581 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1561 02:32:35.891185 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1562 02:32:35.896829 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1563 02:32:35.902314 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1564 02:32:35.907941 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1565 02:32:35.913582 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1566 02:32:35.919187 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1567 02:32:35.924706 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1568 02:32:35.930305 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1569 02:32:35.935948 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1570 02:32:35.941581 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1571 02:32:35.947182 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1572 02:32:35.952701 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1573 02:32:35.958325 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1574 02:32:35.963949 dt_test_unprobed_devices_sh_opp-table skip
1575 02:32:35.969585 dt_test_unprobed_devices_sh_soc skip
1576 02:32:35.969828 dt_test_unprobed_devices_sh_sound pass
1577 02:32:35.975201 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1578 02:32:35.980699 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1579 02:32:35.991928 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1580 02:32:35.992177 dt_test_unprobed_devices_sh fail
1581 02:32:35.997565 + ../../utils/send-to-lava.sh ./output/result.txt
1582 02:32:36.002862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1583 02:32:36.003373 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1585 02:32:36.027737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1586 02:32:36.028232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1588 02:32:36.118747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1589 02:32:36.119218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1591 02:32:36.214149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1592 02:32:36.214702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1594 02:32:36.306762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1595 02:32:36.307239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1597 02:32:36.399225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1598 02:32:36.399699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1600 02:32:36.509049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1601 02:32:36.509523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1603 02:32:36.609641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1604 02:32:36.610134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1606 02:32:36.706867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1607 02:32:36.707340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1609 02:32:36.800529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1610 02:32:36.801002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1612 02:32:36.896636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1613 02:32:36.897109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1615 02:32:36.992394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1616 02:32:36.992872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1618 02:32:37.089806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1619 02:32:37.090291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1621 02:32:37.186737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1622 02:32:37.187303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1624 02:32:37.279376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1625 02:32:37.279918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1627 02:32:37.376563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1628 02:32:37.377038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1630 02:32:37.469008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1631 02:32:37.469486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1633 02:32:37.566355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1634 02:32:37.566837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1636 02:32:37.659021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1637 02:32:37.659502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1639 02:32:37.750113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1640 02:32:37.750598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1642 02:32:37.840858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1643 02:32:37.841344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1645 02:32:37.932516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1646 02:32:37.932992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1648 02:32:38.020996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1649 02:32:38.021474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1651 02:32:38.110755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1652 02:32:38.111233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1654 02:32:38.202356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1655 02:32:38.202930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1657 02:32:38.291527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1658 02:32:38.292016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1660 02:32:38.385953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1661 02:32:38.386442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1663 02:32:38.482472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1664 02:32:38.482959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1666 02:32:38.576292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1667 02:32:38.576764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1669 02:32:38.669984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1670 02:32:38.670470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1672 02:32:38.759846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1673 02:32:38.760329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1675 02:32:38.850191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1676 02:32:38.850679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1678 02:32:38.942570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1679 02:32:38.943060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1681 02:32:39.034344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1682 02:32:39.034831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1684 02:32:39.122344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1685 02:32:39.122824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1687 02:32:39.211321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1688 02:32:39.211889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1690 02:32:39.301932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1691 02:32:39.302415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1693 02:32:39.391150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1694 02:32:39.391636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1696 02:32:39.483442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1697 02:32:39.483939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1699 02:32:39.575962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1700 02:32:39.576477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1702 02:32:39.665680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1703 02:32:39.666182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1705 02:32:39.755720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1706 02:32:39.756219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1708 02:32:39.850857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1709 02:32:39.851332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1711 02:32:39.940674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1712 02:32:39.941158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1714 02:32:40.031223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1715 02:32:40.031692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1717 02:32:40.122217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1718 02:32:40.122691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1720 02:32:40.212671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1721 02:32:40.213233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1723 02:32:40.301015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1724 02:32:40.301495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1726 02:32:40.394272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1727 02:32:40.394754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1729 02:32:40.491055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1730 02:32:40.491536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1732 02:32:40.585888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1733 02:32:40.586378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1735 02:32:40.681009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1736 02:32:40.681523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1738 02:32:40.775985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1739 02:32:40.776532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1741 02:32:40.871879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1742 02:32:40.872373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1744 02:32:40.966051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1745 02:32:40.966571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1747 02:32:41.061688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1748 02:32:41.062201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1750 02:32:41.157702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1751 02:32:41.158187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1753 02:32:41.253428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1754 02:32:41.254024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1756 02:32:41.350414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1757 02:32:41.350900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1759 02:32:41.444927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1760 02:32:41.445423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1762 02:32:41.539577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1763 02:32:41.540079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1765 02:32:41.637790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1766 02:32:41.638272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1768 02:32:41.737439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1769 02:32:41.737949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1771 02:32:41.832146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1772 02:32:41.832652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1774 02:32:41.926059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1775 02:32:41.926548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1777 02:32:42.022749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1778 02:32:42.023226 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1780 02:32:42.113507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1781 02:32:42.113985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1783 02:32:42.209586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1784 02:32:42.210191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1786 02:32:42.302367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1787 02:32:42.302841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1789 02:32:42.396065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1790 02:32:42.396557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1792 02:32:42.490894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1793 02:32:42.491379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1795 02:32:42.587149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1796 02:32:42.587635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1798 02:32:42.684131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1799 02:32:42.684633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1801 02:32:42.777262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1802 02:32:42.777742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1804 02:32:42.871256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1805 02:32:42.871733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1807 02:32:42.965873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1808 02:32:42.966347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1810 02:32:43.061374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1811 02:32:43.061849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1813 02:32:43.154620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1814 02:32:43.155096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1816 02:32:43.250622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1817 02:32:43.251180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1819 02:32:43.345237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1820 02:32:43.345710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1822 02:32:43.440785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1823 02:32:43.441285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1825 02:32:43.535169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1826 02:32:43.535670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1828 02:32:43.631301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1829 02:32:43.631794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1831 02:32:43.725131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1832 02:32:43.725614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1834 02:32:43.820893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1835 02:32:43.821379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1837 02:32:43.916222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1838 02:32:43.916723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1840 02:32:44.013418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1841 02:32:44.013948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1843 02:32:44.110168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1844 02:32:44.110674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1846 02:32:44.206540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1847 02:32:44.207138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1849 02:32:44.303863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1850 02:32:44.304424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1852 02:32:44.399143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1853 02:32:44.399631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1855 02:32:44.492524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1856 02:32:44.493029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1858 02:32:44.592615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1859 02:32:44.593100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1861 02:32:44.690893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1862 02:32:44.691400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1864 02:32:44.784622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1865 02:32:44.785111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1867 02:32:44.873315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1868 02:32:44.873799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1870 02:32:44.962911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1871 02:32:44.963410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1873 02:32:45.054531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1874 02:32:45.055035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1876 02:32:45.148349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1877 02:32:45.148846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1879 02:32:45.242172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1880 02:32:45.242759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1882 02:32:45.333403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1883 02:32:45.333933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1885 02:32:45.426350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1886 02:32:45.426860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1888 02:32:45.518063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1889 02:32:45.518543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1891 02:32:45.610140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1892 02:32:45.610654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1894 02:32:45.704535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1895 02:32:45.705032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1897 02:32:45.802385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1898 02:32:45.802879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1900 02:32:45.894759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1901 02:32:45.895251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1903 02:32:45.992159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1904 02:32:45.992678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1906 02:32:46.086633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1907 02:32:46.087117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1909 02:32:46.180097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1910 02:32:46.180599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1912 02:32:46.270703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1913 02:32:46.271260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1915 02:32:46.362966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1916 02:32:46.363443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1918 02:32:46.452193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1919 02:32:46.452688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1921 02:32:46.544558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1922 02:32:46.545034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1924 02:32:46.637056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1925 02:32:46.637533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1927 02:32:46.729256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1928 02:32:46.729734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1930 02:32:46.821452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1931 02:32:46.821961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1933 02:32:46.916166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1934 02:32:46.916669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1936 02:32:47.010007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1937 02:32:47.010490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1939 02:32:47.104163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1940 02:32:47.104667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1942 02:32:47.198498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1944 02:32:47.201413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1945 02:32:47.292588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1947 02:32:47.295673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1948 02:32:47.381924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1950 02:32:47.385022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1951 02:32:47.474101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1952 02:32:47.474578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1954 02:32:47.564229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1955 02:32:47.564707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1957 02:32:47.651600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1958 02:32:47.652087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1960 02:32:47.745386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1961 02:32:47.745869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1963 02:32:47.839342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1964 02:32:47.839817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1966 02:32:47.934966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1967 02:32:47.935453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1969 02:32:48.029346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1970 02:32:48.029827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1972 02:32:48.125572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1973 02:32:48.126047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1975 02:32:48.221272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1976 02:32:48.221826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1978 02:32:48.315590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1979 02:32:48.316145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1981 02:32:48.411716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1982 02:32:48.412192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1984 02:32:48.504449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1985 02:32:48.504922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1987 02:32:48.598806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1988 02:32:48.599289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1990 02:32:48.689306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1991 02:32:48.689787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1993 02:32:48.784974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1994 02:32:48.785461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1996 02:32:48.875810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1997 02:32:48.876260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1999 02:32:48.968934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2000 02:32:48.969411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2002 02:32:49.064782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2003 02:32:49.065267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2005 02:32:49.159691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2006 02:32:49.160162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2008 02:32:49.251301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2009 02:32:49.251849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2011 02:32:49.344683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2012 02:32:49.345153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2014 02:32:49.438400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2015 02:32:49.438869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2017 02:32:49.522293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2018 02:32:49.522767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2020 02:32:49.616840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2021 02:32:49.617317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2023 02:32:49.707723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2024 02:32:49.708191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2026 02:32:49.804623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2027 02:32:49.805095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2029 02:32:49.902547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2030 02:32:49.903024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2032 02:32:49.997267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2033 02:32:49.997744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2035 02:32:50.092905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2036 02:32:50.093390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2038 02:32:50.187441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2039 02:32:50.187915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2041 02:32:50.280389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2042 02:32:50.280953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2044 02:32:50.372046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2045 02:32:50.372565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2047 02:32:50.462487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2048 02:32:50.462963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2050 02:32:50.554794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2051 02:32:50.555266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2053 02:32:50.649660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2054 02:32:50.650138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2056 02:32:50.738928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2057 02:32:50.739400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2059 02:32:50.831282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2060 02:32:50.831756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2062 02:32:50.920331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2063 02:32:50.920833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2065 02:32:51.010452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2066 02:32:51.010949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2068 02:32:51.101806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2069 02:32:51.102342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2071 02:32:51.197392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2072 02:32:51.197891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2074 02:32:51.287700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2075 02:32:51.288273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2077 02:32:51.379100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2078 02:32:51.379581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2080 02:32:51.469133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2081 02:32:51.469617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2083 02:32:51.562668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2084 02:32:51.563158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2086 02:32:51.651020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2087 02:32:51.651514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2089 02:32:51.747553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2090 02:32:51.748041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2092 02:32:51.872665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2093 02:32:51.873061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2095 02:32:51.970626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2096 02:32:51.971089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2098 02:32:52.066524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2099 02:32:52.067012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2101 02:32:52.160283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2102 02:32:52.160767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2104 02:32:52.258618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2105 02:32:52.259185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2107 02:32:52.350377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2108 02:32:52.350861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2110 02:32:52.439374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2111 02:32:52.439860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2113 02:32:52.528140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2114 02:32:52.528644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2116 02:32:52.623115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2117 02:32:52.623602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2119 02:32:52.718841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2120 02:32:52.719327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2122 02:32:52.814603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2123 02:32:52.815090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2125 02:32:52.906236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2126 02:32:52.906726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2128 02:32:53.000609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2129 02:32:53.001099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2131 02:32:53.095776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2132 02:32:53.096261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2134 02:32:53.189115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2135 02:32:53.189604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2137 02:32:53.279849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2138 02:32:53.280438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2140 02:32:53.371968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2141 02:32:53.372479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2143 02:32:53.464826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2144 02:32:53.465313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2146 02:32:53.560850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2147 02:32:53.561338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2149 02:32:53.653443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2150 02:32:53.653936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2152 02:32:53.747467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2153 02:32:53.747956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2155 02:32:53.843445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2156 02:32:53.843931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2158 02:32:53.936288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2159 02:32:53.936772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2161 02:32:54.030180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2162 02:32:54.030665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2164 02:32:54.125824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2165 02:32:54.126309 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2167 02:32:54.220052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2168 02:32:54.220686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2170 02:32:54.311801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2171 02:32:54.312361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2173 02:32:54.404287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2174 02:32:54.404759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2176 02:32:54.501024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2177 02:32:54.501498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2179 02:32:54.591523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2180 02:32:54.591995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2182 02:32:54.690499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2183 02:32:54.690977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2185 02:32:54.788353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2186 02:32:54.788829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2188 02:32:54.883403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2189 02:32:54.883890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2191 02:32:54.978225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2192 02:32:54.978694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2194 02:32:55.072729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2195 02:32:55.073202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2197 02:32:55.167501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2198 02:32:55.167974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2200 02:32:55.259897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2201 02:32:55.260488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2203 02:32:55.347411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2204 02:32:55.347891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2206 02:32:55.436511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2207 02:32:55.436988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2209 02:32:55.530416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2210 02:32:55.530894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2212 02:32:55.628006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2213 02:32:55.628525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2215 02:32:55.724621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2216 02:32:55.725105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2218 02:32:55.817388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2219 02:32:55.817875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2221 02:32:55.909751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2222 02:32:55.910236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2224 02:32:56.003363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2225 02:32:56.003849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2227 02:32:56.095807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2228 02:32:56.096289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2230 02:32:56.189923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2231 02:32:56.190419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2233 02:32:56.283181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2234 02:32:56.283739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2236 02:32:56.376085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2237 02:32:56.376583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2239 02:32:56.463764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2240 02:32:56.464261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2242 02:32:56.553957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2243 02:32:56.554444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2245 02:32:56.645182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2246 02:32:56.645656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2248 02:32:56.735179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2249 02:32:56.735654 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2251 02:32:56.825842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2252 02:32:56.826318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2254 02:32:56.918462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2255 02:32:56.918947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2257 02:32:57.006610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2259 02:32:57.009612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2260 02:32:57.096008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2261 02:32:57.096517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2263 02:32:57.185577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2264 02:32:57.186061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2266 02:32:57.274957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2267 02:32:57.275522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2269 02:32:57.386476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2270 02:32:57.386972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2272 02:32:57.485709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2273 02:32:57.486195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2275 02:32:57.580689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2276 02:32:57.581179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2278 02:32:57.674071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2279 02:32:57.674558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2281 02:32:57.771700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2282 02:32:57.772188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2284 02:32:57.869181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2285 02:32:57.869669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2287 02:32:57.960940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2288 02:32:57.961426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2290 02:32:58.059550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2291 02:32:58.060034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2293 02:32:58.153302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2294 02:32:58.153788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2296 02:32:58.249666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2297 02:32:58.250229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2299 02:32:58.337370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2300 02:32:58.337927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2302 02:32:58.429631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2303 02:32:58.430109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2305 02:32:58.517852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2306 02:32:58.518336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2308 02:32:58.612276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2309 02:32:58.612765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2311 02:32:58.705024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2312 02:32:58.705515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2314 02:32:58.794221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2315 02:32:58.794706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2317 02:32:58.888078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2318 02:32:58.888597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2320 02:32:58.975281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2321 02:32:58.975776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2323 02:32:59.067278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2324 02:32:59.067757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2326 02:32:59.158562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2327 02:32:59.159058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2329 02:32:59.247273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2330 02:32:59.247824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2332 02:32:59.334925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2333 02:32:59.335466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2335 02:32:59.428668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2336 02:32:59.429194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2338 02:32:59.522735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2339 02:32:59.523221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2341 02:32:59.619729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2342 02:32:59.620223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2344 02:32:59.719174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2345 02:32:59.719655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2347 02:32:59.812669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2348 02:32:59.813151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2350 02:32:59.907566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2351 02:32:59.907837 + set +x
2352 02:32:59.908262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2354 02:32:59.911801 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1186838_1.6.2.4.5>
2355 02:32:59.912261 Received signal: <ENDRUN> 1_kselftest-dt 1186838_1.6.2.4.5
2356 02:32:59.912506 Ending use of test pattern.
2357 02:32:59.912723 Ending test lava.1_kselftest-dt (1186838_1.6.2.4.5), duration 76.51
2359 02:32:59.917751 <LAVA_TEST_RUNNER EXIT>
2360 02:32:59.918226 ok: lava_test_shell seems to have completed
2361 02:32:59.923869 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2362 02:32:59.924650 end: 3.1 lava-test-shell (duration 00:01:18) [common]
2363 02:32:59.924815 end: 3 lava-test-retry (duration 00:01:18) [common]
2364 02:32:59.924975 start: 4 finalize (timeout 00:06:01) [common]
2365 02:32:59.925140 start: 4.1 power-off (timeout 00:00:30) [common]
2366 02:32:59.925354 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2367 02:33:00.293910 Returned 0 in 0 seconds
2368 02:33:00.395539 end: 4.1 power-off (duration 00:00:00) [common]
2370 02:33:00.396472 start: 4.2 read-feedback (timeout 00:06:00) [common]
2371 02:33:00.397082 Listened to connection for namespace 'common' for up to 1s
2372 02:33:00.397622 Listened to connection for namespace 'common' for up to 1s
2373 02:33:01.398014 Finalising connection for namespace 'common'
2374 02:33:01.398447 Disconnecting from shell: Finalise
2375 02:33:01.398720 / #
2376 02:33:01.499270 end: 4.2 read-feedback (duration 00:00:01) [common]
2377 02:33:01.499642 end: 4 finalize (duration 00:00:02) [common]
2378 02:33:01.499999 Cleaning after the job
2379 02:33:01.500344 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/ramdisk
2380 02:33:01.503959 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/kernel
2381 02:33:01.506916 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/dtb
2382 02:33:01.507383 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/nfsrootfs
2383 02:33:01.557632 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1186838/tftp-deploy-0kjilrvg/modules
2384 02:33:01.560896 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1186838
2385 02:33:02.199668 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1186838
2386 02:33:02.199946 Job finished correctly