Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:49:30.912162 lava-dispatcher, installed at version: 2024.01
2 06:49:30.912948 start: 0 validate
3 06:49:30.913463 Start time: 2024-09-06 06:49:30.913433+00:00 (UTC)
4 06:49:30.914024 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:49:30.914583 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 06:49:30.958074 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:49:30.958629 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:49:30.986880 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:49:30.987850 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:49:31.019507 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:49:31.020281 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 06:49:31.056399 validate duration: 0.14
14 06:49:31.057253 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 06:49:31.057608 start: 1.1 download-retry (timeout 00:10:00) [common]
16 06:49:31.057924 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 06:49:31.058587 Not decompressing ramdisk as can be used compressed.
18 06:49:31.059350 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 06:49:31.059811 saving as /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/ramdisk/rootfs.cpio.gz
20 06:49:31.060115 total size: 8181887 (7 MB)
21 06:49:31.098203 progress 0 % (0 MB)
22 06:49:31.104239 progress 5 % (0 MB)
23 06:49:31.109739 progress 10 % (0 MB)
24 06:49:31.115590 progress 15 % (1 MB)
25 06:49:31.121082 progress 20 % (1 MB)
26 06:49:31.126966 progress 25 % (1 MB)
27 06:49:31.132400 progress 30 % (2 MB)
28 06:49:31.138143 progress 35 % (2 MB)
29 06:49:31.143485 progress 40 % (3 MB)
30 06:49:31.149226 progress 45 % (3 MB)
31 06:49:31.154594 progress 50 % (3 MB)
32 06:49:31.160563 progress 55 % (4 MB)
33 06:49:31.165901 progress 60 % (4 MB)
34 06:49:31.171673 progress 65 % (5 MB)
35 06:49:31.176982 progress 70 % (5 MB)
36 06:49:31.182745 progress 75 % (5 MB)
37 06:49:31.188139 progress 80 % (6 MB)
38 06:49:31.193845 progress 85 % (6 MB)
39 06:49:31.199165 progress 90 % (7 MB)
40 06:49:31.204884 progress 95 % (7 MB)
41 06:49:31.209862 progress 100 % (7 MB)
42 06:49:31.210507 7 MB downloaded in 0.15 s (51.89 MB/s)
43 06:49:31.211072 end: 1.1.1 http-download (duration 00:00:00) [common]
45 06:49:31.212018 end: 1.1 download-retry (duration 00:00:00) [common]
46 06:49:31.212354 start: 1.2 download-retry (timeout 00:10:00) [common]
47 06:49:31.212655 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 06:49:31.213194 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
49 06:49:31.213453 saving as /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/kernel/Image
50 06:49:31.213676 total size: 45308416 (43 MB)
51 06:49:31.213899 No compression specified
52 06:49:31.251178 progress 0 % (0 MB)
53 06:49:31.282043 progress 5 % (2 MB)
54 06:49:31.313074 progress 10 % (4 MB)
55 06:49:31.343217 progress 15 % (6 MB)
56 06:49:31.373142 progress 20 % (8 MB)
57 06:49:31.403016 progress 25 % (10 MB)
58 06:49:31.432457 progress 30 % (12 MB)
59 06:49:31.462362 progress 35 % (15 MB)
60 06:49:31.492571 progress 40 % (17 MB)
61 06:49:31.522666 progress 45 % (19 MB)
62 06:49:31.552626 progress 50 % (21 MB)
63 06:49:31.582138 progress 55 % (23 MB)
64 06:49:31.612012 progress 60 % (25 MB)
65 06:49:31.642010 progress 65 % (28 MB)
66 06:49:31.671654 progress 70 % (30 MB)
67 06:49:31.702143 progress 75 % (32 MB)
68 06:49:31.731543 progress 80 % (34 MB)
69 06:49:31.762249 progress 85 % (36 MB)
70 06:49:31.791904 progress 90 % (38 MB)
71 06:49:31.821713 progress 95 % (41 MB)
72 06:49:31.851017 progress 100 % (43 MB)
73 06:49:31.851761 43 MB downloaded in 0.64 s (67.72 MB/s)
74 06:49:31.852302 end: 1.2.1 http-download (duration 00:00:01) [common]
76 06:49:31.853204 end: 1.2 download-retry (duration 00:00:01) [common]
77 06:49:31.853489 start: 1.3 download-retry (timeout 00:09:59) [common]
78 06:49:31.853757 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 06:49:31.854266 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 06:49:31.854544 saving as /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/dtb/meson-g12b-a311d-libretech-cc.dtb
81 06:49:31.854754 total size: 54667 (0 MB)
82 06:49:31.854964 No compression specified
83 06:49:31.889681 progress 59 % (0 MB)
84 06:49:31.890616 progress 100 % (0 MB)
85 06:49:31.891241 0 MB downloaded in 0.04 s (1.43 MB/s)
86 06:49:31.891771 end: 1.3.1 http-download (duration 00:00:00) [common]
88 06:49:31.892733 end: 1.3 download-retry (duration 00:00:00) [common]
89 06:49:31.893037 start: 1.4 download-retry (timeout 00:09:59) [common]
90 06:49:31.893309 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 06:49:31.893876 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
92 06:49:31.894129 saving as /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/modules/modules.tar
93 06:49:31.894336 total size: 11502724 (10 MB)
94 06:49:31.894595 Using unxz to decompress xz
95 06:49:31.933544 progress 0 % (0 MB)
96 06:49:32.001976 progress 5 % (0 MB)
97 06:49:32.079203 progress 10 % (1 MB)
98 06:49:32.162279 progress 15 % (1 MB)
99 06:49:32.242473 progress 20 % (2 MB)
100 06:49:32.318867 progress 25 % (2 MB)
101 06:49:32.401588 progress 30 % (3 MB)
102 06:49:32.477868 progress 35 % (3 MB)
103 06:49:32.557006 progress 40 % (4 MB)
104 06:49:32.629241 progress 45 % (4 MB)
105 06:49:32.707407 progress 50 % (5 MB)
106 06:49:32.783592 progress 55 % (6 MB)
107 06:49:32.863668 progress 60 % (6 MB)
108 06:49:32.950141 progress 65 % (7 MB)
109 06:49:33.027569 progress 70 % (7 MB)
110 06:49:33.123442 progress 75 % (8 MB)
111 06:49:33.213023 progress 80 % (8 MB)
112 06:49:33.293834 progress 85 % (9 MB)
113 06:49:33.364415 progress 90 % (9 MB)
114 06:49:33.440214 progress 95 % (10 MB)
115 06:49:33.515453 progress 100 % (10 MB)
116 06:49:33.525286 10 MB downloaded in 1.63 s (6.73 MB/s)
117 06:49:33.526049 end: 1.4.1 http-download (duration 00:00:02) [common]
119 06:49:33.527391 end: 1.4 download-retry (duration 00:00:02) [common]
120 06:49:33.527849 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 06:49:33.528360 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 06:49:33.528820 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 06:49:33.529259 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 06:49:33.530207 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e
125 06:49:33.530932 makedir: /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin
126 06:49:33.531525 makedir: /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/tests
127 06:49:33.532139 makedir: /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/results
128 06:49:33.532714 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-add-keys
129 06:49:33.533600 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-add-sources
130 06:49:33.534458 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-background-process-start
131 06:49:33.535353 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-background-process-stop
132 06:49:33.536281 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-common-functions
133 06:49:33.537138 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-echo-ipv4
134 06:49:33.537970 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-install-packages
135 06:49:33.538854 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-installed-packages
136 06:49:33.539668 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-os-build
137 06:49:33.540550 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-probe-channel
138 06:49:33.541633 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-probe-ip
139 06:49:33.542499 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-target-ip
140 06:49:33.543317 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-target-mac
141 06:49:33.544149 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-target-storage
142 06:49:33.545017 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-test-case
143 06:49:33.545824 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-test-event
144 06:49:33.546633 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-test-feedback
145 06:49:33.547476 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-test-raise
146 06:49:33.548269 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-test-reference
147 06:49:33.549083 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-test-runner
148 06:49:33.549926 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-test-set
149 06:49:33.550681 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-test-shell
150 06:49:33.551477 Updating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-install-packages (oe)
151 06:49:33.552344 Updating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/bin/lava-installed-packages (oe)
152 06:49:33.553027 Creating /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/environment
153 06:49:33.553615 LAVA metadata
154 06:49:33.554001 - LAVA_JOB_ID=714891
155 06:49:33.554337 - LAVA_DISPATCHER_IP=192.168.6.2
156 06:49:33.554847 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 06:49:33.556368 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 06:49:33.556844 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 06:49:33.557176 skipped lava-vland-overlay
160 06:49:33.557545 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 06:49:33.557928 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 06:49:33.558240 skipped lava-multinode-overlay
163 06:49:33.558611 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 06:49:33.558990 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 06:49:33.559363 Loading test definitions
166 06:49:33.559770 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 06:49:33.560139 Using /lava-714891 at stage 0
168 06:49:33.561844 uuid=714891_1.5.2.4.1 testdef=None
169 06:49:33.562302 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 06:49:33.562701 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 06:49:33.565401 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 06:49:33.566577 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 06:49:33.569935 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 06:49:33.571126 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 06:49:33.574501 runner path: /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/0/tests/0_dmesg test_uuid 714891_1.5.2.4.1
178 06:49:33.575349 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 06:49:33.576506 Creating lava-test-runner.conf files
181 06:49:33.576808 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714891/lava-overlay-kwpd9e8e/lava-714891/0 for stage 0
182 06:49:33.577332 - 0_dmesg
183 06:49:33.577839 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 06:49:33.578248 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 06:49:33.613240 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 06:49:33.613765 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 06:49:33.614156 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 06:49:33.614566 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 06:49:33.614956 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 06:49:34.779216 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 06:49:34.779691 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 06:49:34.779975 extracting modules file /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714891/extract-overlay-ramdisk-n64ogf95/ramdisk
193 06:49:36.132779 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 06:49:36.133247 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 06:49:36.133522 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714891/compress-overlay-o1lhf1xt/overlay-1.5.2.5.tar.gz to ramdisk
196 06:49:36.133736 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714891/compress-overlay-o1lhf1xt/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714891/extract-overlay-ramdisk-n64ogf95/ramdisk
197 06:49:36.164287 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 06:49:36.164681 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 06:49:36.164947 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 06:49:36.165174 Converting downloaded kernel to a uImage
201 06:49:36.165483 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/kernel/Image /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/kernel/uImage
202 06:49:36.712167 output: Image Name:
203 06:49:36.712567 output: Created: Fri Sep 6 06:49:36 2024
204 06:49:36.712780 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 06:49:36.712985 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
206 06:49:36.713185 output: Load Address: 01080000
207 06:49:36.713383 output: Entry Point: 01080000
208 06:49:36.713579 output:
209 06:49:36.713910 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 06:49:36.714177 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 06:49:36.714445 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 06:49:36.714698 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 06:49:36.715051 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 06:49:36.715392 Building ramdisk /var/lib/lava/dispatcher/tmp/714891/extract-overlay-ramdisk-n64ogf95/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714891/extract-overlay-ramdisk-n64ogf95/ramdisk
215 06:49:39.105893 >> 179944 blocks
216 06:49:47.802046 Adding RAMdisk u-boot header.
217 06:49:47.802717 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714891/extract-overlay-ramdisk-n64ogf95/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714891/extract-overlay-ramdisk-n64ogf95/ramdisk.cpio.gz.uboot
218 06:49:48.071460 output: Image Name:
219 06:49:48.071888 output: Created: Fri Sep 6 06:49:47 2024
220 06:49:48.072244 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 06:49:48.072653 output: Data Size: 25875861 Bytes = 25269.40 KiB = 24.68 MiB
222 06:49:48.073049 output: Load Address: 00000000
223 06:49:48.073444 output: Entry Point: 00000000
224 06:49:48.073829 output:
225 06:49:48.074932 rename /var/lib/lava/dispatcher/tmp/714891/extract-overlay-ramdisk-n64ogf95/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/ramdisk/ramdisk.cpio.gz.uboot
226 06:49:48.075651 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 06:49:48.076224 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 06:49:48.076752 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 06:49:48.077200 No LXC device requested
230 06:49:48.077693 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 06:49:48.078195 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 06:49:48.078678 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 06:49:48.079086 Checking files for TFTP limit of 4294967296 bytes.
234 06:49:48.081777 end: 1 tftp-deploy (duration 00:00:17) [common]
235 06:49:48.082345 start: 2 uboot-action (timeout 00:05:00) [common]
236 06:49:48.082862 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 06:49:48.083351 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 06:49:48.083864 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 06:49:48.084422 Using kernel file from prepare-kernel: 714891/tftp-deploy-kz62ve3e/kernel/uImage
240 06:49:48.085019 substitutions:
241 06:49:48.085419 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 06:49:48.085820 - {DTB_ADDR}: 0x01070000
243 06:49:48.086215 - {DTB}: 714891/tftp-deploy-kz62ve3e/dtb/meson-g12b-a311d-libretech-cc.dtb
244 06:49:48.086611 - {INITRD}: 714891/tftp-deploy-kz62ve3e/ramdisk/ramdisk.cpio.gz.uboot
245 06:49:48.087005 - {KERNEL_ADDR}: 0x01080000
246 06:49:48.087396 - {KERNEL}: 714891/tftp-deploy-kz62ve3e/kernel/uImage
247 06:49:48.087788 - {LAVA_MAC}: None
248 06:49:48.088255 - {PRESEED_CONFIG}: None
249 06:49:48.088654 - {PRESEED_LOCAL}: None
250 06:49:48.089041 - {RAMDISK_ADDR}: 0x08000000
251 06:49:48.089429 - {RAMDISK}: 714891/tftp-deploy-kz62ve3e/ramdisk/ramdisk.cpio.gz.uboot
252 06:49:48.089822 - {ROOT_PART}: None
253 06:49:48.090210 - {ROOT}: None
254 06:49:48.090595 - {SERVER_IP}: 192.168.6.2
255 06:49:48.090982 - {TEE_ADDR}: 0x83000000
256 06:49:48.091364 - {TEE}: None
257 06:49:48.091750 Parsed boot commands:
258 06:49:48.092153 - setenv autoload no
259 06:49:48.092540 - setenv initrd_high 0xffffffff
260 06:49:48.092922 - setenv fdt_high 0xffffffff
261 06:49:48.093302 - dhcp
262 06:49:48.093685 - setenv serverip 192.168.6.2
263 06:49:48.094064 - tftpboot 0x01080000 714891/tftp-deploy-kz62ve3e/kernel/uImage
264 06:49:48.094447 - tftpboot 0x08000000 714891/tftp-deploy-kz62ve3e/ramdisk/ramdisk.cpio.gz.uboot
265 06:49:48.094828 - tftpboot 0x01070000 714891/tftp-deploy-kz62ve3e/dtb/meson-g12b-a311d-libretech-cc.dtb
266 06:49:48.095213 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 06:49:48.095603 - bootm 0x01080000 0x08000000 0x01070000
268 06:49:48.096115 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 06:49:48.097589 start: 2.3 connect-device (timeout 00:05:00) [common]
271 06:49:48.098026 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 06:49:48.113271 Setting prompt string to ['lava-test: # ']
273 06:49:48.114779 end: 2.3 connect-device (duration 00:00:00) [common]
274 06:49:48.115377 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 06:49:48.115913 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 06:49:48.116472 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 06:49:48.117767 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 06:49:48.154371 >> OK - accepted request
279 06:49:48.156768 Returned 0 in 0 seconds
280 06:49:48.257889 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 06:49:48.259458 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 06:49:48.260061 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 06:49:48.260568 Setting prompt string to ['Hit any key to stop autoboot']
285 06:49:48.261015 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 06:49:48.262571 Trying 192.168.56.21...
287 06:49:48.263040 Connected to conserv1.
288 06:49:48.263449 Escape character is '^]'.
289 06:49:48.263858
290 06:49:48.264296 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 06:49:48.264717
292 06:50:00.166924 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 06:50:00.167550 bl2_stage_init 0x01
294 06:50:00.167971 bl2_stage_init 0x81
295 06:50:00.172626 hw id: 0x0000 - pwm id 0x01
296 06:50:00.173090 bl2_stage_init 0xc1
297 06:50:00.173507 bl2_stage_init 0x02
298 06:50:00.173913
299 06:50:00.178096 L0:00000000
300 06:50:00.178536 L1:20000703
301 06:50:00.178935 L2:00008067
302 06:50:00.179329 L3:14000000
303 06:50:00.181026 B2:00402000
304 06:50:00.181446 B1:e0f83180
305 06:50:00.181844
306 06:50:00.182239 TE: 58159
307 06:50:00.182623
308 06:50:00.192149 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 06:50:00.192572
310 06:50:00.192960 Board ID = 1
311 06:50:00.193343 Set A53 clk to 24M
312 06:50:00.193723 Set A73 clk to 24M
313 06:50:00.197683 Set clk81 to 24M
314 06:50:00.198094 A53 clk: 1200 MHz
315 06:50:00.198476 A73 clk: 1200 MHz
316 06:50:00.203317 CLK81: 166.6M
317 06:50:00.203732 smccc: 00012ab5
318 06:50:00.208958 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 06:50:00.209377 board id: 1
320 06:50:00.217676 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 06:50:00.229537 fw parse done
322 06:50:00.234080 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 06:50:00.276769 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 06:50:00.287730 PIEI prepare done
325 06:50:00.288223 fastboot data load
326 06:50:00.288616 fastboot data verify
327 06:50:00.293300 verify result: 266
328 06:50:00.298852 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 06:50:00.299265 LPDDR4 probe
330 06:50:00.299648 ddr clk to 1584MHz
331 06:50:00.306893 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 06:50:00.344246
333 06:50:00.344699 dmc_version 0001
334 06:50:00.350884 Check phy result
335 06:50:00.356756 INFO : End of CA training
336 06:50:00.357180 INFO : End of initialization
337 06:50:00.362441 INFO : Training has run successfully!
338 06:50:00.362857 Check phy result
339 06:50:00.367864 INFO : End of initialization
340 06:50:00.368312 INFO : End of read enable training
341 06:50:00.371266 INFO : End of fine write leveling
342 06:50:00.376855 INFO : End of Write leveling coarse delay
343 06:50:00.382411 INFO : Training has run successfully!
344 06:50:00.382821 Check phy result
345 06:50:00.383210 INFO : End of initialization
346 06:50:00.388073 INFO : End of read dq deskew training
347 06:50:00.391457 INFO : End of MPR read delay center optimization
348 06:50:00.397047 INFO : End of write delay center optimization
349 06:50:00.402612 INFO : End of read delay center optimization
350 06:50:00.403024 INFO : End of max read latency training
351 06:50:00.408226 INFO : Training has run successfully!
352 06:50:00.408638 1D training succeed
353 06:50:00.416374 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 06:50:00.463788 Check phy result
355 06:50:00.464267 INFO : End of initialization
356 06:50:00.485446 INFO : End of 2D read delay Voltage center optimization
357 06:50:00.505652 INFO : End of 2D read delay Voltage center optimization
358 06:50:00.557407 INFO : End of 2D write delay Voltage center optimization
359 06:50:00.606635 INFO : End of 2D write delay Voltage center optimization
360 06:50:00.612241 INFO : Training has run successfully!
361 06:50:00.612658
362 06:50:00.613051 channel==0
363 06:50:00.617840 RxClkDly_Margin_A0==88 ps 9
364 06:50:00.618266 TxDqDly_Margin_A0==98 ps 10
365 06:50:00.623458 RxClkDly_Margin_A1==88 ps 9
366 06:50:00.623870 TxDqDly_Margin_A1==98 ps 10
367 06:50:00.624306 TrainedVREFDQ_A0==74
368 06:50:00.629049 TrainedVREFDQ_A1==74
369 06:50:00.629465 VrefDac_Margin_A0==25
370 06:50:00.629850 DeviceVref_Margin_A0==40
371 06:50:00.634631 VrefDac_Margin_A1==24
372 06:50:00.635047 DeviceVref_Margin_A1==40
373 06:50:00.635437
374 06:50:00.635823
375 06:50:00.640215 channel==1
376 06:50:00.640628 RxClkDly_Margin_A0==98 ps 10
377 06:50:00.641014 TxDqDly_Margin_A0==88 ps 9
378 06:50:00.645802 RxClkDly_Margin_A1==98 ps 10
379 06:50:00.646211 TxDqDly_Margin_A1==88 ps 9
380 06:50:00.651425 TrainedVREFDQ_A0==77
381 06:50:00.651859 TrainedVREFDQ_A1==77
382 06:50:00.652282 VrefDac_Margin_A0==22
383 06:50:00.657017 DeviceVref_Margin_A0==37
384 06:50:00.657431 VrefDac_Margin_A1==22
385 06:50:00.662628 DeviceVref_Margin_A1==37
386 06:50:00.663037
387 06:50:00.663432 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 06:50:00.663816
389 06:50:00.696232 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 06:50:00.696731 2D training succeed
391 06:50:00.701869 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 06:50:00.707432 auto size-- 65535DDR cs0 size: 2048MB
393 06:50:00.707850 DDR cs1 size: 2048MB
394 06:50:00.713041 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 06:50:00.713459 cs0 DataBus test pass
396 06:50:00.718602 cs1 DataBus test pass
397 06:50:00.719010 cs0 AddrBus test pass
398 06:50:00.719394 cs1 AddrBus test pass
399 06:50:00.719776
400 06:50:00.724251 100bdlr_step_size ps== 420
401 06:50:00.724685 result report
402 06:50:00.729833 boot times 0Enable ddr reg access
403 06:50:00.735166 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 06:50:00.748674 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 06:50:01.320764 0.0;M3 CHK:0;cm4_sp_mode 0
406 06:50:01.321391 MVN_1=0x00000000
407 06:50:01.326129 MVN_2=0x00000000
408 06:50:01.331936 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 06:50:01.332401 OPS=0x10
410 06:50:01.332798 ring efuse init
411 06:50:01.333187 chipver efuse init
412 06:50:01.337680 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 06:50:01.343083 [0.018960 Inits done]
414 06:50:01.343501 secure task start!
415 06:50:01.343895 high task start!
416 06:50:01.346763 low task start!
417 06:50:01.347175 run into bl31
418 06:50:01.354323 NOTICE: BL31: v1.3(release):4fc40b1
419 06:50:01.361180 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 06:50:01.361612 NOTICE: BL31: G12A normal boot!
421 06:50:01.387515 NOTICE: BL31: BL33 decompress pass
422 06:50:01.392444 ERROR: Error initializing runtime service opteed_fast
423 06:50:02.625972
424 06:50:02.626387
425 06:50:02.634418 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 06:50:02.634830
427 06:50:02.635161 Model: Libre Computer AML-A311D-CC Alta
428 06:50:02.842810 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 06:50:02.866168 DRAM: 2 GiB (effective 3.8 GiB)
430 06:50:03.009100 Core: 408 devices, 31 uclasses, devicetree: separate
431 06:50:03.014960 WDT: Not starting watchdog@f0d0
432 06:50:03.047234 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 06:50:03.059710 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 06:50:03.064722 ** Bad device specification mmc 0 **
435 06:50:03.075008 Card did not respond to voltage select! : -110
436 06:50:03.082665 ** Bad device specification mmc 0 **
437 06:50:03.082950 Couldn't find partition mmc 0
438 06:50:03.091011 Card did not respond to voltage select! : -110
439 06:50:03.096571 ** Bad device specification mmc 0 **
440 06:50:03.096840 Couldn't find partition mmc 0
441 06:50:03.101649 Error: could not access storage.
442 06:50:04.367084 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 06:50:04.367724 bl2_stage_init 0x01
444 06:50:04.368318 bl2_stage_init 0x81
445 06:50:04.372579 hw id: 0x0000 - pwm id 0x01
446 06:50:04.373123 bl2_stage_init 0xc1
447 06:50:04.373591 bl2_stage_init 0x02
448 06:50:04.374047
449 06:50:04.378193 L0:00000000
450 06:50:04.378705 L1:20000703
451 06:50:04.379165 L2:00008067
452 06:50:04.379616 L3:14000000
453 06:50:04.383824 B2:00402000
454 06:50:04.384376 B1:e0f83180
455 06:50:04.384834
456 06:50:04.385290 TE: 58124
457 06:50:04.385742
458 06:50:04.389369 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 06:50:04.389891
460 06:50:04.390354 Board ID = 1
461 06:50:04.395081 Set A53 clk to 24M
462 06:50:04.395605 Set A73 clk to 24M
463 06:50:04.396097 Set clk81 to 24M
464 06:50:04.400610 A53 clk: 1200 MHz
465 06:50:04.401116 A73 clk: 1200 MHz
466 06:50:04.401566 CLK81: 166.6M
467 06:50:04.402006 smccc: 00012a92
468 06:50:04.406204 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 06:50:04.411808 board id: 1
470 06:50:04.417668 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 06:50:04.428313 fw parse done
472 06:50:04.434263 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 06:50:04.475966 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 06:50:04.488244 PIEI prepare done
475 06:50:04.488750 fastboot data load
476 06:50:04.489210 fastboot data verify
477 06:50:04.493498 verify result: 266
478 06:50:04.499109 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 06:50:04.499604 LPDDR4 probe
480 06:50:04.500094 ddr clk to 1584MHz
481 06:50:04.507020 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 06:50:04.544261
483 06:50:04.544770 dmc_version 0001
484 06:50:04.550035 Check phy result
485 06:50:04.556926 INFO : End of CA training
486 06:50:04.557508 INFO : End of initialization
487 06:50:04.562448 INFO : Training has run successfully!
488 06:50:04.562997 Check phy result
489 06:50:04.568182 INFO : End of initialization
490 06:50:04.568739 INFO : End of read enable training
491 06:50:04.573640 INFO : End of fine write leveling
492 06:50:04.579214 INFO : End of Write leveling coarse delay
493 06:50:04.579701 INFO : Training has run successfully!
494 06:50:04.580208 Check phy result
495 06:50:04.584858 INFO : End of initialization
496 06:50:04.585354 INFO : End of read dq deskew training
497 06:50:04.590447 INFO : End of MPR read delay center optimization
498 06:50:04.596150 INFO : End of write delay center optimization
499 06:50:04.601635 INFO : End of read delay center optimization
500 06:50:04.602119 INFO : End of max read latency training
501 06:50:04.607216 INFO : Training has run successfully!
502 06:50:04.607710 1D training succeed
503 06:50:04.615582 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 06:50:04.663109 Check phy result
505 06:50:04.663704 INFO : End of initialization
506 06:50:04.684779 INFO : End of 2D read delay Voltage center optimization
507 06:50:04.705983 INFO : End of 2D read delay Voltage center optimization
508 06:50:04.758130 INFO : End of 2D write delay Voltage center optimization
509 06:50:04.807375 INFO : End of 2D write delay Voltage center optimization
510 06:50:04.812942 INFO : Training has run successfully!
511 06:50:04.813458
512 06:50:04.813919 channel==0
513 06:50:04.818538 RxClkDly_Margin_A0==88 ps 9
514 06:50:04.819037 TxDqDly_Margin_A0==98 ps 10
515 06:50:04.824261 RxClkDly_Margin_A1==88 ps 9
516 06:50:04.824755 TxDqDly_Margin_A1==88 ps 9
517 06:50:04.825215 TrainedVREFDQ_A0==74
518 06:50:04.829821 TrainedVREFDQ_A1==74
519 06:50:04.830314 VrefDac_Margin_A0==25
520 06:50:04.830763 DeviceVref_Margin_A0==40
521 06:50:04.835351 VrefDac_Margin_A1==25
522 06:50:04.835854 DeviceVref_Margin_A1==40
523 06:50:04.836344
524 06:50:04.836792
525 06:50:04.837233 channel==1
526 06:50:04.841787 RxClkDly_Margin_A0==98 ps 10
527 06:50:04.842280 TxDqDly_Margin_A0==98 ps 10
528 06:50:04.846520 RxClkDly_Margin_A1==88 ps 9
529 06:50:04.847014 TxDqDly_Margin_A1==88 ps 9
530 06:50:04.852191 TrainedVREFDQ_A0==77
531 06:50:04.852683 TrainedVREFDQ_A1==77
532 06:50:04.853138 VrefDac_Margin_A0==22
533 06:50:04.857715 DeviceVref_Margin_A0==37
534 06:50:04.858200 VrefDac_Margin_A1==24
535 06:50:04.863321 DeviceVref_Margin_A1==37
536 06:50:04.863811
537 06:50:04.864298 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 06:50:04.864748
539 06:50:04.896920 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 06:50:04.897529 2D training succeed
541 06:50:04.902789 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 06:50:04.908197 auto size-- 65535DDR cs0 size: 2048MB
543 06:50:04.908702 DDR cs1 size: 2048MB
544 06:50:04.913756 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 06:50:04.914259 cs0 DataBus test pass
546 06:50:04.919347 cs1 DataBus test pass
547 06:50:04.919842 cs0 AddrBus test pass
548 06:50:04.920351 cs1 AddrBus test pass
549 06:50:04.920818
550 06:50:04.924946 100bdlr_step_size ps== 420
551 06:50:04.925456 result report
552 06:50:04.930548 boot times 0Enable ddr reg access
553 06:50:04.935798 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 06:50:04.949312 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 06:50:05.523211 0.0;M3 CHK:0;cm4_sp_mode 0
556 06:50:05.523833 MVN_1=0x00000000
557 06:50:05.528638 MVN_2=0x00000000
558 06:50:05.534425 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 06:50:05.535006 OPS=0x10
560 06:50:05.535473 ring efuse init
561 06:50:05.535956 chipver efuse init
562 06:50:05.542628 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 06:50:05.543202 [0.018960 Inits done]
564 06:50:05.550228 secure task start!
565 06:50:05.550708 high task start!
566 06:50:05.551135 low task start!
567 06:50:05.551557 run into bl31
568 06:50:05.556840 NOTICE: BL31: v1.3(release):4fc40b1
569 06:50:05.564667 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 06:50:05.565156 NOTICE: BL31: G12A normal boot!
571 06:50:05.589901 NOTICE: BL31: BL33 decompress pass
572 06:50:05.595682 ERROR: Error initializing runtime service opteed_fast
573 06:50:06.828692
574 06:50:06.829329
575 06:50:06.836100 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 06:50:06.836710
577 06:50:06.837178 Model: Libre Computer AML-A311D-CC Alta
578 06:50:07.045383 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 06:50:07.067698 DRAM: 2 GiB (effective 3.8 GiB)
580 06:50:07.211646 Core: 408 devices, 31 uclasses, devicetree: separate
581 06:50:07.217577 WDT: Not starting watchdog@f0d0
582 06:50:07.249764 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 06:50:07.262239 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 06:50:07.267211 ** Bad device specification mmc 0 **
585 06:50:07.277542 Card did not respond to voltage select! : -110
586 06:50:07.285204 ** Bad device specification mmc 0 **
587 06:50:07.285685 Couldn't find partition mmc 0
588 06:50:07.293545 Card did not respond to voltage select! : -110
589 06:50:07.299067 ** Bad device specification mmc 0 **
590 06:50:07.299549 Couldn't find partition mmc 0
591 06:50:07.303595 Error: could not access storage.
592 06:50:07.646637 Net: eth0: ethernet@ff3f0000
593 06:50:07.647244 starting USB...
594 06:50:07.898401 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 06:50:07.899024 Starting the controller
596 06:50:07.904556 USB XHCI 1.10
597 06:50:09.615837 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 06:50:09.616505 bl2_stage_init 0x01
599 06:50:09.616974 bl2_stage_init 0x81
600 06:50:09.621476 hw id: 0x0000 - pwm id 0x01
601 06:50:09.621969 bl2_stage_init 0xc1
602 06:50:09.622421 bl2_stage_init 0x02
603 06:50:09.622867
604 06:50:09.626982 L0:00000000
605 06:50:09.627460 L1:20000703
606 06:50:09.627909 L2:00008067
607 06:50:09.628397 L3:14000000
608 06:50:09.629920 B2:00402000
609 06:50:09.630397 B1:e0f83180
610 06:50:09.630840
611 06:50:09.631286 TE: 58124
612 06:50:09.631728
613 06:50:09.641015 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 06:50:09.641505
615 06:50:09.641960 Board ID = 1
616 06:50:09.642399 Set A53 clk to 24M
617 06:50:09.642837 Set A73 clk to 24M
618 06:50:09.646642 Set clk81 to 24M
619 06:50:09.647122 A53 clk: 1200 MHz
620 06:50:09.647568 A73 clk: 1200 MHz
621 06:50:09.650007 CLK81: 166.6M
622 06:50:09.650483 smccc: 00012a92
623 06:50:09.655564 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 06:50:09.661178 board id: 1
625 06:50:09.665595 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 06:50:09.677167 fw parse done
627 06:50:09.682149 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 06:50:09.724947 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 06:50:09.736703 PIEI prepare done
630 06:50:09.737173 fastboot data load
631 06:50:09.737625 fastboot data verify
632 06:50:09.742238 verify result: 266
633 06:50:09.747837 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 06:50:09.748359 LPDDR4 probe
635 06:50:09.748803 ddr clk to 1584MHz
636 06:50:09.754986 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 06:50:09.793039
638 06:50:09.793510 dmc_version 0001
639 06:50:09.799722 Check phy result
640 06:50:09.805635 INFO : End of CA training
641 06:50:09.806107 INFO : End of initialization
642 06:50:09.811320 INFO : Training has run successfully!
643 06:50:09.811786 Check phy result
644 06:50:09.816863 INFO : End of initialization
645 06:50:09.817333 INFO : End of read enable training
646 06:50:09.822412 INFO : End of fine write leveling
647 06:50:09.828051 INFO : End of Write leveling coarse delay
648 06:50:09.828524 INFO : Training has run successfully!
649 06:50:09.828966 Check phy result
650 06:50:09.833677 INFO : End of initialization
651 06:50:09.834146 INFO : End of read dq deskew training
652 06:50:09.839207 INFO : End of MPR read delay center optimization
653 06:50:09.844876 INFO : End of write delay center optimization
654 06:50:09.850428 INFO : End of read delay center optimization
655 06:50:09.850897 INFO : End of max read latency training
656 06:50:09.856055 INFO : Training has run successfully!
657 06:50:09.856528 1D training succeed
658 06:50:09.864331 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 06:50:09.912793 Check phy result
660 06:50:09.913269 INFO : End of initialization
661 06:50:09.934403 INFO : End of 2D read delay Voltage center optimization
662 06:50:09.955337 INFO : End of 2D read delay Voltage center optimization
663 06:50:10.007238 INFO : End of 2D write delay Voltage center optimization
664 06:50:10.056466 INFO : End of 2D write delay Voltage center optimization
665 06:50:10.062059 INFO : Training has run successfully!
666 06:50:10.062532
667 06:50:10.062983 channel==0
668 06:50:10.067627 RxClkDly_Margin_A0==88 ps 9
669 06:50:10.068131 TxDqDly_Margin_A0==98 ps 10
670 06:50:10.073275 RxClkDly_Margin_A1==88 ps 9
671 06:50:10.073750 TxDqDly_Margin_A1==98 ps 10
672 06:50:10.074207 TrainedVREFDQ_A0==74
673 06:50:10.078891 TrainedVREFDQ_A1==74
674 06:50:10.079367 VrefDac_Margin_A0==24
675 06:50:10.079813 DeviceVref_Margin_A0==40
676 06:50:10.084441 VrefDac_Margin_A1==24
677 06:50:10.084911 DeviceVref_Margin_A1==40
678 06:50:10.085354
679 06:50:10.085795
680 06:50:10.090049 channel==1
681 06:50:10.090525 RxClkDly_Margin_A0==98 ps 10
682 06:50:10.090971 TxDqDly_Margin_A0==98 ps 10
683 06:50:10.095644 RxClkDly_Margin_A1==88 ps 9
684 06:50:10.096146 TxDqDly_Margin_A1==88 ps 9
685 06:50:10.101256 TrainedVREFDQ_A0==77
686 06:50:10.101732 TrainedVREFDQ_A1==77
687 06:50:10.102177 VrefDac_Margin_A0==22
688 06:50:10.106900 DeviceVref_Margin_A0==37
689 06:50:10.107372 VrefDac_Margin_A1==24
690 06:50:10.112469 DeviceVref_Margin_A1==37
691 06:50:10.112940
692 06:50:10.113384 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 06:50:10.113820
694 06:50:10.146087 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 06:50:10.146596 2D training succeed
696 06:50:10.151651 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 06:50:10.157264 auto size-- 65535DDR cs0 size: 2048MB
698 06:50:10.157738 DDR cs1 size: 2048MB
699 06:50:10.162915 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 06:50:10.163389 cs0 DataBus test pass
701 06:50:10.168452 cs1 DataBus test pass
702 06:50:10.168927 cs0 AddrBus test pass
703 06:50:10.169370 cs1 AddrBus test pass
704 06:50:10.169807
705 06:50:10.174063 100bdlr_step_size ps== 420
706 06:50:10.174546 result report
707 06:50:10.179646 boot times 0Enable ddr reg access
708 06:50:10.184697 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 06:50:10.197552 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 06:50:10.770438 0.0;M3 CHK:0;cm4_sp_mode 0
711 06:50:10.770869 MVN_1=0x00000000
712 06:50:10.776068 MVN_2=0x00000000
713 06:50:10.781744 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 06:50:10.782095 OPS=0x10
715 06:50:10.782335 ring efuse init
716 06:50:10.782562 chipver efuse init
717 06:50:10.787321 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 06:50:10.792933 [0.018961 Inits done]
719 06:50:10.793264 secure task start!
720 06:50:10.793489 high task start!
721 06:50:10.797510 low task start!
722 06:50:10.797816 run into bl31
723 06:50:10.804124 NOTICE: BL31: v1.3(release):4fc40b1
724 06:50:10.811062 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 06:50:10.811424 NOTICE: BL31: G12A normal boot!
726 06:50:10.837329 NOTICE: BL31: BL33 decompress pass
727 06:50:10.841987 ERROR: Error initializing runtime service opteed_fast
728 06:50:12.076090
729 06:50:12.076754
730 06:50:12.083610 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 06:50:12.084194
732 06:50:12.084665 Model: Libre Computer AML-A311D-CC Alta
733 06:50:12.291892 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 06:50:12.316273 DRAM: 2 GiB (effective 3.8 GiB)
735 06:50:12.459142 Core: 408 devices, 31 uclasses, devicetree: separate
736 06:50:12.465069 WDT: Not starting watchdog@f0d0
737 06:50:12.497420 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 06:50:12.509759 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 06:50:12.513848 ** Bad device specification mmc 0 **
740 06:50:12.525043 Card did not respond to voltage select! : -110
741 06:50:12.532673 ** Bad device specification mmc 0 **
742 06:50:12.533069 Couldn't find partition mmc 0
743 06:50:12.541521 Card did not respond to voltage select! : -110
744 06:50:12.546534 ** Bad device specification mmc 0 **
745 06:50:12.547037 Couldn't find partition mmc 0
746 06:50:12.551582 Error: could not access storage.
747 06:50:12.893351 Net: eth0: ethernet@ff3f0000
748 06:50:12.893946 starting USB...
749 06:50:13.145969 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 06:50:13.146395 Starting the controller
751 06:50:13.152856 USB XHCI 1.10
752 06:50:15.316079 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 06:50:15.317211 bl2_stage_init 0x01
754 06:50:15.317542 bl2_stage_init 0x81
755 06:50:15.321633 hw id: 0x0000 - pwm id 0x01
756 06:50:15.322217 bl2_stage_init 0xc1
757 06:50:15.322642 bl2_stage_init 0x02
758 06:50:15.322931
759 06:50:15.327214 L0:00000000
760 06:50:15.327611 L1:20000703
761 06:50:15.327834 L2:00008067
762 06:50:15.328081 L3:14000000
763 06:50:15.332809 B2:00402000
764 06:50:15.333560 B1:e0f83180
765 06:50:15.333867
766 06:50:15.334113 TE: 58167
767 06:50:15.334349
768 06:50:15.338424 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 06:50:15.338979
770 06:50:15.339389 Board ID = 1
771 06:50:15.344008 Set A53 clk to 24M
772 06:50:15.344576 Set A73 clk to 24M
773 06:50:15.344974 Set clk81 to 24M
774 06:50:15.349634 A53 clk: 1200 MHz
775 06:50:15.350042 A73 clk: 1200 MHz
776 06:50:15.350291 CLK81: 166.6M
777 06:50:15.350531 smccc: 00012abe
778 06:50:15.355197 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 06:50:15.360845 board id: 1
780 06:50:15.366718 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 06:50:15.377392 fw parse done
782 06:50:15.383332 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 06:50:15.425946 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 06:50:15.436901 PIEI prepare done
785 06:50:15.437352 fastboot data load
786 06:50:15.437616 fastboot data verify
787 06:50:15.442584 verify result: 266
788 06:50:15.448149 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 06:50:15.448741 LPDDR4 probe
790 06:50:15.449168 ddr clk to 1584MHz
791 06:50:15.456144 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 06:50:15.493374
793 06:50:15.493993 dmc_version 0001
794 06:50:15.500058 Check phy result
795 06:50:15.505916 INFO : End of CA training
796 06:50:15.506516 INFO : End of initialization
797 06:50:15.511505 INFO : Training has run successfully!
798 06:50:15.511935 Check phy result
799 06:50:15.517088 INFO : End of initialization
800 06:50:15.517514 INFO : End of read enable training
801 06:50:15.520396 INFO : End of fine write leveling
802 06:50:15.526009 INFO : End of Write leveling coarse delay
803 06:50:15.531688 INFO : Training has run successfully!
804 06:50:15.532314 Check phy result
805 06:50:15.532613 INFO : End of initialization
806 06:50:15.537252 INFO : End of read dq deskew training
807 06:50:15.542806 INFO : End of MPR read delay center optimization
808 06:50:15.543244 INFO : End of write delay center optimization
809 06:50:15.548434 INFO : End of read delay center optimization
810 06:50:15.554022 INFO : End of max read latency training
811 06:50:15.554627 INFO : Training has run successfully!
812 06:50:15.559654 1D training succeed
813 06:50:15.565504 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 06:50:15.613080 Check phy result
815 06:50:15.613531 INFO : End of initialization
816 06:50:15.634777 INFO : End of 2D read delay Voltage center optimization
817 06:50:15.653207 INFO : End of 2D read delay Voltage center optimization
818 06:50:15.706345 INFO : End of 2D write delay Voltage center optimization
819 06:50:15.755553 INFO : End of 2D write delay Voltage center optimization
820 06:50:15.761176 INFO : Training has run successfully!
821 06:50:15.761814
822 06:50:15.762298 channel==0
823 06:50:15.766892 RxClkDly_Margin_A0==78 ps 8
824 06:50:15.767484 TxDqDly_Margin_A0==98 ps 10
825 06:50:15.772493 RxClkDly_Margin_A1==88 ps 9
826 06:50:15.773088 TxDqDly_Margin_A1==98 ps 10
827 06:50:15.773576 TrainedVREFDQ_A0==74
828 06:50:15.778170 TrainedVREFDQ_A1==75
829 06:50:15.778806 VrefDac_Margin_A0==25
830 06:50:15.779274 DeviceVref_Margin_A0==40
831 06:50:15.783686 VrefDac_Margin_A1==25
832 06:50:15.784376 DeviceVref_Margin_A1==39
833 06:50:15.784817
834 06:50:15.785251
835 06:50:15.789286 channel==1
836 06:50:15.789851 RxClkDly_Margin_A0==98 ps 10
837 06:50:15.790289 TxDqDly_Margin_A0==98 ps 10
838 06:50:15.794874 RxClkDly_Margin_A1==88 ps 9
839 06:50:15.795441 TxDqDly_Margin_A1==98 ps 10
840 06:50:15.800472 TrainedVREFDQ_A0==77
841 06:50:15.801057 TrainedVREFDQ_A1==78
842 06:50:15.801499 VrefDac_Margin_A0==23
843 06:50:15.806059 DeviceVref_Margin_A0==37
844 06:50:15.806617 VrefDac_Margin_A1==24
845 06:50:15.811678 DeviceVref_Margin_A1==36
846 06:50:15.812270
847 06:50:15.812710 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 06:50:15.817243
849 06:50:15.845199 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 06:50:15.845842 2D training succeed
851 06:50:15.850837 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 06:50:15.856416 auto size-- 65535DDR cs0 size: 2048MB
853 06:50:15.856942 DDR cs1 size: 2048MB
854 06:50:15.861995 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 06:50:15.862516 cs0 DataBus test pass
856 06:50:15.867590 cs1 DataBus test pass
857 06:50:15.868174 cs0 AddrBus test pass
858 06:50:15.868625 cs1 AddrBus test pass
859 06:50:15.869061
860 06:50:15.873176 100bdlr_step_size ps== 420
861 06:50:15.873697 result report
862 06:50:15.878765 boot times 0Enable ddr reg access
863 06:50:15.884347 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 06:50:15.897817 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 06:50:16.471450 0.0;M3 CHK:0;cm4_sp_mode 0
866 06:50:16.472258 MVN_1=0x00000000
867 06:50:16.476967 MVN_2=0x00000000
868 06:50:16.482779 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 06:50:16.483477 OPS=0x10
870 06:50:16.483975 ring efuse init
871 06:50:16.484531 chipver efuse init
872 06:50:16.490992 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 06:50:16.491655 [0.018961 Inits done]
874 06:50:16.498398 secure task start!
875 06:50:16.499039 high task start!
876 06:50:16.499517 low task start!
877 06:50:16.500041 run into bl31
878 06:50:16.505219 NOTICE: BL31: v1.3(release):4fc40b1
879 06:50:16.512341 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 06:50:16.512947 NOTICE: BL31: G12A normal boot!
881 06:50:16.538377 NOTICE: BL31: BL33 decompress pass
882 06:50:16.543762 ERROR: Error initializing runtime service opteed_fast
883 06:50:17.776743
884 06:50:17.777164
885 06:50:17.784325 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 06:50:17.784637
887 06:50:17.784858 Model: Libre Computer AML-A311D-CC Alta
888 06:50:17.993673 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 06:50:18.016146 DRAM: 2 GiB (effective 3.8 GiB)
890 06:50:18.160050 Core: 408 devices, 31 uclasses, devicetree: separate
891 06:50:18.165167 WDT: Not starting watchdog@f0d0
892 06:50:18.198293 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 06:50:18.210699 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 06:50:18.214968 ** Bad device specification mmc 0 **
895 06:50:18.226019 Card did not respond to voltage select! : -110
896 06:50:18.232909 ** Bad device specification mmc 0 **
897 06:50:18.233292 Couldn't find partition mmc 0
898 06:50:18.241977 Card did not respond to voltage select! : -110
899 06:50:18.247411 ** Bad device specification mmc 0 **
900 06:50:18.247788 Couldn't find partition mmc 0
901 06:50:18.252338 Error: could not access storage.
902 06:50:18.595260 Net: eth0: ethernet@ff3f0000
903 06:50:18.595681 starting USB...
904 06:50:18.847934 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 06:50:18.848342 Starting the controller
906 06:50:18.854018 USB XHCI 1.10
907 06:50:20.715741 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 06:50:20.716440 bl2_stage_init 0x01
909 06:50:20.716911 bl2_stage_init 0x81
910 06:50:20.721415 hw id: 0x0000 - pwm id 0x01
911 06:50:20.721937 bl2_stage_init 0xc1
912 06:50:20.722403 bl2_stage_init 0x02
913 06:50:20.722853
914 06:50:20.726953 L0:00000000
915 06:50:20.727464 L1:20000703
916 06:50:20.727913 L2:00008067
917 06:50:20.728402 L3:14000000
918 06:50:20.729813 B2:00402000
919 06:50:20.730313 B1:e0f83180
920 06:50:20.730762
921 06:50:20.731205 TE: 58124
922 06:50:20.731643
923 06:50:20.740921 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 06:50:20.741467
925 06:50:20.741924 Board ID = 1
926 06:50:20.742362 Set A53 clk to 24M
927 06:50:20.742797 Set A73 clk to 24M
928 06:50:20.746590 Set clk81 to 24M
929 06:50:20.747099 A53 clk: 1200 MHz
930 06:50:20.747548 A73 clk: 1200 MHz
931 06:50:20.749922 CLK81: 166.6M
932 06:50:20.750428 smccc: 00012a92
933 06:50:20.755503 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 06:50:20.761132 board id: 1
935 06:50:20.765595 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 06:50:20.777133 fw parse done
937 06:50:20.782623 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 06:50:20.824790 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 06:50:20.836702 PIEI prepare done
940 06:50:20.837269 fastboot data load
941 06:50:20.837710 fastboot data verify
942 06:50:20.842532 verify result: 266
943 06:50:20.848019 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 06:50:20.848602 LPDDR4 probe
945 06:50:20.849048 ddr clk to 1584MHz
946 06:50:20.856002 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 06:50:20.892279
948 06:50:20.892871 dmc_version 0001
949 06:50:20.898882 Check phy result
950 06:50:20.905664 INFO : End of CA training
951 06:50:20.906207 INFO : End of initialization
952 06:50:20.911219 INFO : Training has run successfully!
953 06:50:20.911742 Check phy result
954 06:50:20.916955 INFO : End of initialization
955 06:50:20.917526 INFO : End of read enable training
956 06:50:20.920283 INFO : End of fine write leveling
957 06:50:20.925702 INFO : End of Write leveling coarse delay
958 06:50:20.931374 INFO : Training has run successfully!
959 06:50:20.931892 Check phy result
960 06:50:20.932387 INFO : End of initialization
961 06:50:20.936885 INFO : End of read dq deskew training
962 06:50:20.942508 INFO : End of MPR read delay center optimization
963 06:50:20.943070 INFO : End of write delay center optimization
964 06:50:20.948146 INFO : End of read delay center optimization
965 06:50:20.953708 INFO : End of max read latency training
966 06:50:20.954223 INFO : Training has run successfully!
967 06:50:20.959304 1D training succeed
968 06:50:20.964289 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 06:50:21.012645 Check phy result
970 06:50:21.013232 INFO : End of initialization
971 06:50:21.034481 INFO : End of 2D read delay Voltage center optimization
972 06:50:21.053726 INFO : End of 2D read delay Voltage center optimization
973 06:50:21.105524 INFO : End of 2D write delay Voltage center optimization
974 06:50:21.155746 INFO : End of 2D write delay Voltage center optimization
975 06:50:21.161311 INFO : Training has run successfully!
976 06:50:21.161846
977 06:50:21.162330 channel==0
978 06:50:21.166887 RxClkDly_Margin_A0==88 ps 9
979 06:50:21.167420 TxDqDly_Margin_A0==98 ps 10
980 06:50:21.172553 RxClkDly_Margin_A1==88 ps 9
981 06:50:21.173075 TxDqDly_Margin_A1==98 ps 10
982 06:50:21.173540 TrainedVREFDQ_A0==74
983 06:50:21.178137 TrainedVREFDQ_A1==74
984 06:50:21.178660 VrefDac_Margin_A0==25
985 06:50:21.179116 DeviceVref_Margin_A0==40
986 06:50:21.183705 VrefDac_Margin_A1==25
987 06:50:21.184247 DeviceVref_Margin_A1==40
988 06:50:21.184702
989 06:50:21.185144
990 06:50:21.189292 channel==1
991 06:50:21.189806 RxClkDly_Margin_A0==98 ps 10
992 06:50:21.190258 TxDqDly_Margin_A0==98 ps 10
993 06:50:21.194883 RxClkDly_Margin_A1==88 ps 9
994 06:50:21.195399 TxDqDly_Margin_A1==88 ps 9
995 06:50:21.200529 TrainedVREFDQ_A0==77
996 06:50:21.201047 TrainedVREFDQ_A1==77
997 06:50:21.201498 VrefDac_Margin_A0==22
998 06:50:21.206050 DeviceVref_Margin_A0==37
999 06:50:21.206561 VrefDac_Margin_A1==24
1000 06:50:21.211721 DeviceVref_Margin_A1==37
1001 06:50:21.212283
1002 06:50:21.212741 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 06:50:21.213208
1004 06:50:21.245323 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1005 06:50:21.245954 2D training succeed
1006 06:50:21.250912 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 06:50:21.256557 auto size-- 65535DDR cs0 size: 2048MB
1008 06:50:21.257085 DDR cs1 size: 2048MB
1009 06:50:21.262066 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 06:50:21.262576 cs0 DataBus test pass
1011 06:50:21.267732 cs1 DataBus test pass
1012 06:50:21.268286 cs0 AddrBus test pass
1013 06:50:21.268739 cs1 AddrBus test pass
1014 06:50:21.269184
1015 06:50:21.273302 100bdlr_step_size ps== 420
1016 06:50:21.273820 result report
1017 06:50:21.278900 boot times 0Enable ddr reg access
1018 06:50:21.283316 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 06:50:21.296652 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 06:50:21.869570 0.0;M3 CHK:0;cm4_sp_mode 0
1021 06:50:21.870206 MVN_1=0x00000000
1022 06:50:21.875135 MVN_2=0x00000000
1023 06:50:21.880909 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 06:50:21.881427 OPS=0x10
1025 06:50:21.881879 ring efuse init
1026 06:50:21.882320 chipver efuse init
1027 06:50:21.889064 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 06:50:21.889595 [0.018961 Inits done]
1029 06:50:21.896676 secure task start!
1030 06:50:21.897184 high task start!
1031 06:50:21.897637 low task start!
1032 06:50:21.898078 run into bl31
1033 06:50:21.903388 NOTICE: BL31: v1.3(release):4fc40b1
1034 06:50:21.911215 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 06:50:21.911739 NOTICE: BL31: G12A normal boot!
1036 06:50:21.936579 NOTICE: BL31: BL33 decompress pass
1037 06:50:21.942150 ERROR: Error initializing runtime service opteed_fast
1038 06:50:23.175065
1039 06:50:23.175499
1040 06:50:23.183537 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 06:50:23.184053
1042 06:50:23.184373 Model: Libre Computer AML-A311D-CC Alta
1043 06:50:23.391874 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 06:50:23.415259 DRAM: 2 GiB (effective 3.8 GiB)
1045 06:50:23.558267 Core: 408 devices, 31 uclasses, devicetree: separate
1046 06:50:23.564204 WDT: Not starting watchdog@f0d0
1047 06:50:23.596419 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 06:50:23.609088 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 06:50:23.613788 ** Bad device specification mmc 0 **
1050 06:50:23.624182 Card did not respond to voltage select! : -110
1051 06:50:23.631799 ** Bad device specification mmc 0 **
1052 06:50:23.632361 Couldn't find partition mmc 0
1053 06:50:23.640128 Card did not respond to voltage select! : -110
1054 06:50:23.645726 ** Bad device specification mmc 0 **
1055 06:50:23.646219 Couldn't find partition mmc 0
1056 06:50:23.650786 Error: could not access storage.
1057 06:50:23.993180 Net: eth0: ethernet@ff3f0000
1058 06:50:23.993753 starting USB...
1059 06:50:24.244995 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 06:50:24.245593 Starting the controller
1061 06:50:24.251867 USB XHCI 1.10
1062 06:50:25.806420 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 06:50:25.814573 scanning usb for storage devices... 0 Storage Device(s) found
1065 06:50:25.866356 Hit any key to stop autoboot: 1
1066 06:50:25.867209 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1067 06:50:25.867834 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 06:50:25.868377 Setting prompt string to ['=>']
1069 06:50:25.868892 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 06:50:25.882002 0
1071 06:50:25.882922 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 06:50:25.883439 Sending with 10 millisecond of delay
1074 06:50:27.018721 => setenv autoload no
1075 06:50:27.029809 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 06:50:27.036728 setenv autoload no
1077 06:50:27.037798 Sending with 10 millisecond of delay
1079 06:50:28.836772 => setenv initrd_high 0xffffffff
1080 06:50:28.847890 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 06:50:28.849159 setenv initrd_high 0xffffffff
1082 06:50:28.850172 Sending with 10 millisecond of delay
1084 06:50:30.467723 => setenv fdt_high 0xffffffff
1085 06:50:30.478593 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 06:50:30.479539 setenv fdt_high 0xffffffff
1087 06:50:30.480349 Sending with 10 millisecond of delay
1089 06:50:30.772388 => dhcp
1090 06:50:30.783243 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1091 06:50:30.784273 dhcp
1092 06:50:30.784780 Speed: 1000, full duplex
1093 06:50:30.785241 BOOTP broadcast 1
1094 06:50:31.031072 BOOTP broadcast 2
1095 06:50:31.179181 DHCP client bound to address 192.168.6.33 (396 ms)
1096 06:50:31.180129 Sending with 10 millisecond of delay
1098 06:50:32.858799 => setenv serverip 192.168.6.2
1099 06:50:32.869838 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1100 06:50:32.871021 setenv serverip 192.168.6.2
1101 06:50:32.871871 Sending with 10 millisecond of delay
1103 06:50:36.598379 => tftpboot 0x01080000 714891/tftp-deploy-kz62ve3e/kernel/uImage
1104 06:50:36.609246 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1105 06:50:36.610272 tftpboot 0x01080000 714891/tftp-deploy-kz62ve3e/kernel/uImage
1106 06:50:36.610743 Speed: 1000, full duplex
1107 06:50:36.611181 Using ethernet@ff3f0000 device
1108 06:50:36.611945 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1109 06:50:36.617419 Filename '714891/tftp-deploy-kz62ve3e/kernel/uImage'.
1110 06:50:36.621180 Load address: 0x1080000
1111 06:50:40.483634 Loading: *################################################## 43.2 MiB
1112 06:50:40.484349 11.2 MiB/s
1113 06:50:40.484824 done
1114 06:50:40.488032 Bytes transferred = 45308480 (2b35a40 hex)
1115 06:50:40.488868 Sending with 10 millisecond of delay
1117 06:50:45.188370 => tftpboot 0x08000000 714891/tftp-deploy-kz62ve3e/ramdisk/ramdisk.cpio.gz.uboot
1118 06:50:45.199235 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1119 06:50:45.200242 tftpboot 0x08000000 714891/tftp-deploy-kz62ve3e/ramdisk/ramdisk.cpio.gz.uboot
1120 06:50:45.200718 Speed: 1000, full duplex
1121 06:50:45.201158 Using ethernet@ff3f0000 device
1122 06:50:45.201919 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1123 06:50:45.210484 Filename '714891/tftp-deploy-kz62ve3e/ramdisk/ramdisk.cpio.gz.uboot'.
1124 06:50:45.210803 Load address: 0x8000000
1125 06:50:46.815390 Loading: *################################################# UDP wrong checksum 00000005 00006bd8
1126 06:50:51.816745 T UDP wrong checksum 00000005 00006bd8
1127 06:51:01.817851 T T UDP wrong checksum 00000005 00006bd8
1128 06:51:06.053932 UDP wrong checksum 000000ff 00009702
1129 06:51:06.061613 UDP wrong checksum 000000ff 000020f5
1130 06:51:21.821010 T T T UDP wrong checksum 00000005 00006bd8
1131 06:51:41.827909 T T T T
1132 06:51:41.828368 Retry count exceeded; starting again
1134 06:51:41.830777 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1137 06:51:41.832573 end: 2.4 uboot-commands (duration 00:01:54) [common]
1139 06:51:41.833894 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 06:51:41.834865 end: 2 uboot-action (duration 00:01:54) [common]
1143 06:51:41.836445 Cleaning after the job
1144 06:51:41.836989 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/ramdisk
1145 06:51:41.838301 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/kernel
1146 06:51:41.880573 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/dtb
1147 06:51:41.881466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714891/tftp-deploy-kz62ve3e/modules
1148 06:51:41.900525 start: 4.1 power-off (timeout 00:00:30) [common]
1149 06:51:41.901171 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 06:51:41.931505 >> OK - accepted request
1151 06:51:41.933530 Returned 0 in 0 seconds
1152 06:51:42.034312 end: 4.1 power-off (duration 00:00:00) [common]
1154 06:51:42.035379 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 06:51:42.036083 Listened to connection for namespace 'common' for up to 1s
1156 06:51:43.037060 Finalising connection for namespace 'common'
1157 06:51:43.037813 Disconnecting from shell: Finalise
1158 06:51:43.038340 =>
1159 06:51:43.139321 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 06:51:43.140021 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714891
1161 06:51:43.442496 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714891
1162 06:51:43.443105 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.