Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:13:31.812270 lava-dispatcher, installed at version: 2024.01
2 07:13:31.813091 start: 0 validate
3 07:13:31.813601 Start time: 2024-09-06 07:13:31.813568+00:00 (UTC)
4 07:13:31.814172 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:13:31.814729 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 07:13:31.854472 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:13:31.855010 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:13:31.884265 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:13:31.884898 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:13:31.914616 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:13:31.915245 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 07:13:31.953661 validate duration: 0.14
14 07:13:31.954737 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 07:13:31.955171 start: 1.1 download-retry (timeout 00:10:00) [common]
16 07:13:31.955568 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 07:13:31.956378 Not decompressing ramdisk as can be used compressed.
18 07:13:31.956963 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 07:13:31.957268 saving as /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/ramdisk/rootfs.cpio.gz
20 07:13:31.957597 total size: 47897469 (45 MB)
21 07:13:31.992518 progress 0 % (0 MB)
22 07:13:32.022451 progress 5 % (2 MB)
23 07:13:32.052332 progress 10 % (4 MB)
24 07:13:32.081844 progress 15 % (6 MB)
25 07:13:32.111308 progress 20 % (9 MB)
26 07:13:32.140510 progress 25 % (11 MB)
27 07:13:32.170083 progress 30 % (13 MB)
28 07:13:32.199365 progress 35 % (16 MB)
29 07:13:32.228478 progress 40 % (18 MB)
30 07:13:32.257557 progress 45 % (20 MB)
31 07:13:32.286607 progress 50 % (22 MB)
32 07:13:32.315913 progress 55 % (25 MB)
33 07:13:32.345466 progress 60 % (27 MB)
34 07:13:32.374676 progress 65 % (29 MB)
35 07:13:32.403958 progress 70 % (32 MB)
36 07:13:32.433125 progress 75 % (34 MB)
37 07:13:32.462392 progress 80 % (36 MB)
38 07:13:32.491615 progress 85 % (38 MB)
39 07:13:32.521098 progress 90 % (41 MB)
40 07:13:32.550104 progress 95 % (43 MB)
41 07:13:32.578552 progress 100 % (45 MB)
42 07:13:32.579325 45 MB downloaded in 0.62 s (73.47 MB/s)
43 07:13:32.579894 end: 1.1.1 http-download (duration 00:00:01) [common]
45 07:13:32.580941 end: 1.1 download-retry (duration 00:00:01) [common]
46 07:13:32.581258 start: 1.2 download-retry (timeout 00:09:59) [common]
47 07:13:32.581543 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 07:13:32.582033 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
49 07:13:32.582289 saving as /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/kernel/Image
50 07:13:32.582508 total size: 45308416 (43 MB)
51 07:13:32.582723 No compression specified
52 07:13:32.620889 progress 0 % (0 MB)
53 07:13:32.649460 progress 5 % (2 MB)
54 07:13:32.678018 progress 10 % (4 MB)
55 07:13:32.705924 progress 15 % (6 MB)
56 07:13:32.733464 progress 20 % (8 MB)
57 07:13:32.761171 progress 25 % (10 MB)
58 07:13:32.788754 progress 30 % (12 MB)
59 07:13:32.816940 progress 35 % (15 MB)
60 07:13:32.844915 progress 40 % (17 MB)
61 07:13:32.872684 progress 45 % (19 MB)
62 07:13:32.900417 progress 50 % (21 MB)
63 07:13:32.928287 progress 55 % (23 MB)
64 07:13:32.956126 progress 60 % (25 MB)
65 07:13:32.984369 progress 65 % (28 MB)
66 07:13:33.012429 progress 70 % (30 MB)
67 07:13:33.040372 progress 75 % (32 MB)
68 07:13:33.068190 progress 80 % (34 MB)
69 07:13:33.095958 progress 85 % (36 MB)
70 07:13:33.124268 progress 90 % (38 MB)
71 07:13:33.152212 progress 95 % (41 MB)
72 07:13:33.179317 progress 100 % (43 MB)
73 07:13:33.180042 43 MB downloaded in 0.60 s (72.31 MB/s)
74 07:13:33.180534 end: 1.2.1 http-download (duration 00:00:01) [common]
76 07:13:33.181343 end: 1.2 download-retry (duration 00:00:01) [common]
77 07:13:33.181617 start: 1.3 download-retry (timeout 00:09:59) [common]
78 07:13:33.181878 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 07:13:33.182343 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 07:13:33.182618 saving as /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/dtb/meson-g12b-a311d-libretech-cc.dtb
81 07:13:33.182827 total size: 54667 (0 MB)
82 07:13:33.183038 No compression specified
83 07:13:33.219500 progress 59 % (0 MB)
84 07:13:33.220408 progress 100 % (0 MB)
85 07:13:33.220972 0 MB downloaded in 0.04 s (1.37 MB/s)
86 07:13:33.221439 end: 1.3.1 http-download (duration 00:00:00) [common]
88 07:13:33.222251 end: 1.3 download-retry (duration 00:00:00) [common]
89 07:13:33.222510 start: 1.4 download-retry (timeout 00:09:59) [common]
90 07:13:33.222768 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 07:13:33.223230 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
92 07:13:33.223473 saving as /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/modules/modules.tar
93 07:13:33.223680 total size: 11502724 (10 MB)
94 07:13:33.223889 Using unxz to decompress xz
95 07:13:33.268571 progress 0 % (0 MB)
96 07:13:33.339143 progress 5 % (0 MB)
97 07:13:33.414967 progress 10 % (1 MB)
98 07:13:33.497873 progress 15 % (1 MB)
99 07:13:33.578669 progress 20 % (2 MB)
100 07:13:33.655663 progress 25 % (2 MB)
101 07:13:33.736998 progress 30 % (3 MB)
102 07:13:33.811314 progress 35 % (3 MB)
103 07:13:33.889608 progress 40 % (4 MB)
104 07:13:33.961457 progress 45 % (4 MB)
105 07:13:34.039329 progress 50 % (5 MB)
106 07:13:34.115028 progress 55 % (6 MB)
107 07:13:34.194610 progress 60 % (6 MB)
108 07:13:34.280337 progress 65 % (7 MB)
109 07:13:34.357396 progress 70 % (7 MB)
110 07:13:34.452774 progress 75 % (8 MB)
111 07:13:34.542347 progress 80 % (8 MB)
112 07:13:34.622988 progress 85 % (9 MB)
113 07:13:34.693436 progress 90 % (9 MB)
114 07:13:34.769003 progress 95 % (10 MB)
115 07:13:34.844603 progress 100 % (10 MB)
116 07:13:34.854451 10 MB downloaded in 1.63 s (6.73 MB/s)
117 07:13:34.855054 end: 1.4.1 http-download (duration 00:00:02) [common]
119 07:13:34.855879 end: 1.4 download-retry (duration 00:00:02) [common]
120 07:13:34.856406 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 07:13:34.856931 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 07:13:34.857441 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 07:13:34.857941 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 07:13:34.858917 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu
125 07:13:34.859754 makedir: /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin
126 07:13:34.860437 makedir: /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/tests
127 07:13:34.861052 makedir: /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/results
128 07:13:34.861662 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-add-keys
129 07:13:34.862591 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-add-sources
130 07:13:34.863506 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-background-process-start
131 07:13:34.864497 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-background-process-stop
132 07:13:34.865502 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-common-functions
133 07:13:34.866403 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-echo-ipv4
134 07:13:34.867289 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-install-packages
135 07:13:34.868238 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-installed-packages
136 07:13:34.869126 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-os-build
137 07:13:34.870003 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-probe-channel
138 07:13:34.870876 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-probe-ip
139 07:13:34.871750 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-target-ip
140 07:13:34.872669 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-target-mac
141 07:13:34.873550 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-target-storage
142 07:13:34.874444 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-test-case
143 07:13:34.875367 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-test-event
144 07:13:34.876369 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-test-feedback
145 07:13:34.877294 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-test-raise
146 07:13:34.878171 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-test-reference
147 07:13:34.879049 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-test-runner
148 07:13:34.880014 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-test-set
149 07:13:34.880918 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-test-shell
150 07:13:34.881847 Updating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-install-packages (oe)
151 07:13:34.882896 Updating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/bin/lava-installed-packages (oe)
152 07:13:34.883720 Creating /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/environment
153 07:13:34.884467 LAVA metadata
154 07:13:34.884949 - LAVA_JOB_ID=714890
155 07:13:34.885371 - LAVA_DISPATCHER_IP=192.168.6.2
156 07:13:34.886021 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 07:13:34.887779 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 07:13:34.888400 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 07:13:34.888807 skipped lava-vland-overlay
160 07:13:34.889287 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 07:13:34.889791 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 07:13:34.890213 skipped lava-multinode-overlay
163 07:13:34.890693 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 07:13:34.891186 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 07:13:34.891655 Loading test definitions
166 07:13:34.892224 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 07:13:34.892664 Using /lava-714890 at stage 0
168 07:13:34.894758 uuid=714890_1.5.2.4.1 testdef=None
169 07:13:34.895322 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 07:13:34.895831 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 07:13:34.897762 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 07:13:34.898570 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 07:13:34.900760 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 07:13:34.901592 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 07:13:34.903678 runner path: /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/0/tests/0_igt-gpu-panfrost test_uuid 714890_1.5.2.4.1
178 07:13:34.904316 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 07:13:34.905138 Creating lava-test-runner.conf files
181 07:13:34.905346 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714890/lava-overlay-xkc5e6tu/lava-714890/0 for stage 0
182 07:13:34.905695 - 0_igt-gpu-panfrost
183 07:13:34.906051 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 07:13:34.906330 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 07:13:34.929947 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 07:13:34.930347 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 07:13:34.930613 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 07:13:34.930880 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 07:13:34.931146 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 07:13:42.071957 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 07:13:42.072705 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 07:13:42.073196 extracting modules file /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714890/extract-overlay-ramdisk-y3qsclx0/ramdisk
193 07:13:43.835200 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 07:13:43.835693 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 07:13:43.835972 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714890/compress-overlay-kzv44m0a/overlay-1.5.2.5.tar.gz to ramdisk
196 07:13:43.836217 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714890/compress-overlay-kzv44m0a/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714890/extract-overlay-ramdisk-y3qsclx0/ramdisk
197 07:13:43.870892 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 07:13:43.871376 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 07:13:43.871710 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 07:13:43.872011 Converting downloaded kernel to a uImage
201 07:13:43.872376 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/kernel/Image /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/kernel/uImage
202 07:13:44.399117 output: Image Name:
203 07:13:44.399580 output: Created: Fri Sep 6 07:13:43 2024
204 07:13:44.399795 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 07:13:44.400036 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
206 07:13:44.400251 output: Load Address: 01080000
207 07:13:44.400453 output: Entry Point: 01080000
208 07:13:44.400653 output:
209 07:13:44.400996 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 07:13:44.401272 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 07:13:44.401541 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 07:13:44.401793 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 07:13:44.402050 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 07:13:44.402303 Building ramdisk /var/lib/lava/dispatcher/tmp/714890/extract-overlay-ramdisk-y3qsclx0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714890/extract-overlay-ramdisk-y3qsclx0/ramdisk
215 07:13:51.486669 >> 500748 blocks
216 07:14:12.239351 Adding RAMdisk u-boot header.
217 07:14:12.240062 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714890/extract-overlay-ramdisk-y3qsclx0/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714890/extract-overlay-ramdisk-y3qsclx0/ramdisk.cpio.gz.uboot
218 07:14:12.901126 output: Image Name:
219 07:14:12.901540 output: Created: Fri Sep 6 07:14:12 2024
220 07:14:12.901748 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 07:14:12.901949 output: Data Size: 65536787 Bytes = 64000.77 KiB = 62.50 MiB
222 07:14:12.902147 output: Load Address: 00000000
223 07:14:12.902345 output: Entry Point: 00000000
224 07:14:12.902540 output:
225 07:14:12.903129 rename /var/lib/lava/dispatcher/tmp/714890/extract-overlay-ramdisk-y3qsclx0/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/ramdisk/ramdisk.cpio.gz.uboot
226 07:14:12.903537 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 07:14:12.903816 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 07:14:12.904254 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 07:14:12.904715 No LXC device requested
230 07:14:12.905202 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 07:14:12.905701 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 07:14:12.906183 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 07:14:12.906583 Checking files for TFTP limit of 4294967296 bytes.
234 07:14:12.909260 end: 1 tftp-deploy (duration 00:00:41) [common]
235 07:14:12.909833 start: 2 uboot-action (timeout 00:05:00) [common]
236 07:14:12.910350 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 07:14:12.910842 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 07:14:12.911333 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 07:14:12.911850 Using kernel file from prepare-kernel: 714890/tftp-deploy-26yve1ks/kernel/uImage
240 07:14:12.912485 substitutions:
241 07:14:12.912890 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 07:14:12.913287 - {DTB_ADDR}: 0x01070000
243 07:14:12.913682 - {DTB}: 714890/tftp-deploy-26yve1ks/dtb/meson-g12b-a311d-libretech-cc.dtb
244 07:14:12.914077 - {INITRD}: 714890/tftp-deploy-26yve1ks/ramdisk/ramdisk.cpio.gz.uboot
245 07:14:12.914469 - {KERNEL_ADDR}: 0x01080000
246 07:14:12.914858 - {KERNEL}: 714890/tftp-deploy-26yve1ks/kernel/uImage
247 07:14:12.915248 - {LAVA_MAC}: None
248 07:14:12.915675 - {PRESEED_CONFIG}: None
249 07:14:12.916090 - {PRESEED_LOCAL}: None
250 07:14:12.916654 - {RAMDISK_ADDR}: 0x08000000
251 07:14:12.917054 - {RAMDISK}: 714890/tftp-deploy-26yve1ks/ramdisk/ramdisk.cpio.gz.uboot
252 07:14:12.917454 - {ROOT_PART}: None
253 07:14:12.917840 - {ROOT}: None
254 07:14:12.918229 - {SERVER_IP}: 192.168.6.2
255 07:14:12.918621 - {TEE_ADDR}: 0x83000000
256 07:14:12.919013 - {TEE}: None
257 07:14:12.919402 Parsed boot commands:
258 07:14:12.919779 - setenv autoload no
259 07:14:12.920205 - setenv initrd_high 0xffffffff
260 07:14:12.920594 - setenv fdt_high 0xffffffff
261 07:14:12.920980 - dhcp
262 07:14:12.921367 - setenv serverip 192.168.6.2
263 07:14:12.921751 - tftpboot 0x01080000 714890/tftp-deploy-26yve1ks/kernel/uImage
264 07:14:12.922140 - tftpboot 0x08000000 714890/tftp-deploy-26yve1ks/ramdisk/ramdisk.cpio.gz.uboot
265 07:14:12.922527 - tftpboot 0x01070000 714890/tftp-deploy-26yve1ks/dtb/meson-g12b-a311d-libretech-cc.dtb
266 07:14:12.922913 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 07:14:12.923303 - bootm 0x01080000 0x08000000 0x01070000
268 07:14:12.923795 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 07:14:12.925297 start: 2.3 connect-device (timeout 00:05:00) [common]
271 07:14:12.925737 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 07:14:12.939347 Setting prompt string to ['lava-test: # ']
273 07:14:12.940852 end: 2.3 connect-device (duration 00:00:00) [common]
274 07:14:12.941434 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 07:14:12.941976 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 07:14:12.942482 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 07:14:12.943609 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 07:14:12.979896 >> OK - accepted request
279 07:14:12.982139 Returned 0 in 0 seconds
280 07:14:13.083187 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 07:14:13.084747 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 07:14:13.085298 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 07:14:13.085795 Setting prompt string to ['Hit any key to stop autoboot']
285 07:14:13.086235 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 07:14:13.087765 Trying 192.168.56.21...
287 07:14:13.088254 Connected to conserv1.
288 07:14:13.088667 Escape character is '^]'.
289 07:14:13.089064
290 07:14:13.089487 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 07:14:13.089915
292 07:14:24.035273 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 07:14:24.035901 bl2_stage_init 0x01
294 07:14:24.036376 bl2_stage_init 0x81
295 07:14:24.040962 hw id: 0x0000 - pwm id 0x01
296 07:14:24.041424 bl2_stage_init 0xc1
297 07:14:24.041835 bl2_stage_init 0x02
298 07:14:24.042236
299 07:14:24.046439 L0:00000000
300 07:14:24.046857 L1:20000703
301 07:14:24.047244 L2:00008067
302 07:14:24.047626 L3:14000000
303 07:14:24.052115 B2:00402000
304 07:14:24.052577 B1:e0f83180
305 07:14:24.052966
306 07:14:24.053375 TE: 58159
307 07:14:24.053776
308 07:14:24.057598 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 07:14:24.058021
310 07:14:24.058407 Board ID = 1
311 07:14:24.063294 Set A53 clk to 24M
312 07:14:24.063707 Set A73 clk to 24M
313 07:14:24.064123 Set clk81 to 24M
314 07:14:24.068767 A53 clk: 1200 MHz
315 07:14:24.069176 A73 clk: 1200 MHz
316 07:14:24.069562 CLK81: 166.6M
317 07:14:24.069940 smccc: 00012ab4
318 07:14:24.074317 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 07:14:24.079921 board id: 1
320 07:14:24.085846 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 07:14:24.096428 fw parse done
322 07:14:24.102448 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 07:14:24.145107 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 07:14:24.155952 PIEI prepare done
325 07:14:24.156403 fastboot data load
326 07:14:24.156795 fastboot data verify
327 07:14:24.161618 verify result: 266
328 07:14:24.167172 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 07:14:24.167580 LPDDR4 probe
330 07:14:24.168004 ddr clk to 1584MHz
331 07:14:24.174391 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 07:14:24.212471
333 07:14:24.212903 dmc_version 0001
334 07:14:24.219154 Check phy result
335 07:14:24.225027 INFO : End of CA training
336 07:14:24.225443 INFO : End of initialization
337 07:14:24.230625 INFO : Training has run successfully!
338 07:14:24.231067 Check phy result
339 07:14:24.236240 INFO : End of initialization
340 07:14:24.236678 INFO : End of read enable training
341 07:14:24.241807 INFO : End of fine write leveling
342 07:14:24.247409 INFO : End of Write leveling coarse delay
343 07:14:24.247822 INFO : Training has run successfully!
344 07:14:24.248254 Check phy result
345 07:14:24.253014 INFO : End of initialization
346 07:14:24.253431 INFO : End of read dq deskew training
347 07:14:24.258591 INFO : End of MPR read delay center optimization
348 07:14:24.264200 INFO : End of write delay center optimization
349 07:14:24.269789 INFO : End of read delay center optimization
350 07:14:24.270201 INFO : End of max read latency training
351 07:14:24.275406 INFO : Training has run successfully!
352 07:14:24.275814 1D training succeed
353 07:14:24.284581 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 07:14:24.332229 Check phy result
355 07:14:24.332704 INFO : End of initialization
356 07:14:24.353635 INFO : End of 2D read delay Voltage center optimization
357 07:14:24.374234 INFO : End of 2D read delay Voltage center optimization
358 07:14:24.426266 INFO : End of 2D write delay Voltage center optimization
359 07:14:24.475602 INFO : End of 2D write delay Voltage center optimization
360 07:14:24.481105 INFO : Training has run successfully!
361 07:14:24.481523
362 07:14:24.481916 channel==0
363 07:14:24.486872 RxClkDly_Margin_A0==88 ps 9
364 07:14:24.487279 TxDqDly_Margin_A0==98 ps 10
365 07:14:24.490164 RxClkDly_Margin_A1==88 ps 9
366 07:14:24.490568 TxDqDly_Margin_A1==98 ps 10
367 07:14:24.495705 TrainedVREFDQ_A0==74
368 07:14:24.496141 TrainedVREFDQ_A1==74
369 07:14:24.496535 VrefDac_Margin_A0==25
370 07:14:24.501320 DeviceVref_Margin_A0==40
371 07:14:24.501744 VrefDac_Margin_A1==25
372 07:14:24.506970 DeviceVref_Margin_A1==40
373 07:14:24.507382
374 07:14:24.507775
375 07:14:24.508198 channel==1
376 07:14:24.508583 RxClkDly_Margin_A0==98 ps 10
377 07:14:24.510398 TxDqDly_Margin_A0==98 ps 10
378 07:14:24.515855 RxClkDly_Margin_A1==88 ps 9
379 07:14:24.516290 TxDqDly_Margin_A1==88 ps 9
380 07:14:24.516680 TrainedVREFDQ_A0==77
381 07:14:24.521618 TrainedVREFDQ_A1==77
382 07:14:24.522023 VrefDac_Margin_A0==22
383 07:14:24.527066 DeviceVref_Margin_A0==37
384 07:14:24.527474 VrefDac_Margin_A1==24
385 07:14:24.527859 DeviceVref_Margin_A1==37
386 07:14:24.528266
387 07:14:24.532979 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 07:14:24.533439
389 07:14:24.566275 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 07:14:24.566780 2D training succeed
391 07:14:24.571859 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 07:14:24.577383 auto size-- 65535DDR cs0 size: 2048MB
393 07:14:24.577795 DDR cs1 size: 2048MB
394 07:14:24.582990 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 07:14:24.583397 cs0 DataBus test pass
396 07:14:24.583784 cs1 DataBus test pass
397 07:14:24.588758 cs0 AddrBus test pass
398 07:14:24.589173 cs1 AddrBus test pass
399 07:14:24.589559
400 07:14:24.594201 100bdlr_step_size ps== 420
401 07:14:24.594659 result report
402 07:14:24.595050 boot times 0Enable ddr reg access
403 07:14:24.604016 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 07:14:24.617561 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 07:14:25.191231 0.0;M3 CHK:0;cm4_sp_mode 0
406 07:14:25.191868 MVN_1=0x00000000
407 07:14:25.196824 MVN_2=0x00000000
408 07:14:25.202463 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 07:14:25.202973 OPS=0x10
410 07:14:25.203375 ring efuse init
411 07:14:25.203766 chipver efuse init
412 07:14:25.208120 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 07:14:25.213850 [0.018961 Inits done]
414 07:14:25.214291 secure task start!
415 07:14:25.214680 high task start!
416 07:14:25.218206 low task start!
417 07:14:25.218683 run into bl31
418 07:14:25.224829 NOTICE: BL31: v1.3(release):4fc40b1
419 07:14:25.232640 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 07:14:25.233097 NOTICE: BL31: G12A normal boot!
421 07:14:25.258000 NOTICE: BL31: BL33 decompress pass
422 07:14:25.263668 ERROR: Error initializing runtime service opteed_fast
423 07:14:26.496579
424 07:14:26.497141
425 07:14:26.505022 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 07:14:26.505458
427 07:14:26.505868 Model: Libre Computer AML-A311D-CC Alta
428 07:14:26.713343 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 07:14:26.736815 DRAM: 2 GiB (effective 3.8 GiB)
430 07:14:26.879761 Core: 408 devices, 31 uclasses, devicetree: separate
431 07:14:26.884730 WDT: Not starting watchdog@f0d0
432 07:14:26.917889 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 07:14:26.930358 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 07:14:26.935341 ** Bad device specification mmc 0 **
435 07:14:26.945626 Card did not respond to voltage select! : -110
436 07:14:26.953272 ** Bad device specification mmc 0 **
437 07:14:26.953720 Couldn't find partition mmc 0
438 07:14:26.961622 Card did not respond to voltage select! : -110
439 07:14:26.967119 ** Bad device specification mmc 0 **
440 07:14:26.967542 Couldn't find partition mmc 0
441 07:14:26.972200 Error: could not access storage.
442 07:14:28.235622 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 07:14:28.236213 bl2_stage_init 0x01
444 07:14:28.236634 bl2_stage_init 0x81
445 07:14:28.241176 hw id: 0x0000 - pwm id 0x01
446 07:14:28.241603 bl2_stage_init 0xc1
447 07:14:28.242005 bl2_stage_init 0x02
448 07:14:28.242399
449 07:14:28.246720 L0:00000000
450 07:14:28.247142 L1:20000703
451 07:14:28.247540 L2:00008067
452 07:14:28.247932 L3:14000000
453 07:14:28.249594 B2:00402000
454 07:14:28.250010 B1:e0f83180
455 07:14:28.250405
456 07:14:28.250799 TE: 58124
457 07:14:28.251190
458 07:14:28.260811 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 07:14:28.261240
460 07:14:28.261640 Board ID = 1
461 07:14:28.262032 Set A53 clk to 24M
462 07:14:28.262420 Set A73 clk to 24M
463 07:14:28.266417 Set clk81 to 24M
464 07:14:28.266837 A53 clk: 1200 MHz
465 07:14:28.267232 A73 clk: 1200 MHz
466 07:14:28.269691 CLK81: 166.6M
467 07:14:28.270108 smccc: 00012a92
468 07:14:28.275231 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 07:14:28.280857 board id: 1
470 07:14:28.286250 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 07:14:28.296865 fw parse done
472 07:14:28.302825 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 07:14:28.345206 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 07:14:28.356450 PIEI prepare done
475 07:14:28.356875 fastboot data load
476 07:14:28.357278 fastboot data verify
477 07:14:28.361999 verify result: 266
478 07:14:28.367632 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 07:14:28.368088 LPDDR4 probe
480 07:14:28.368488 ddr clk to 1584MHz
481 07:14:28.375599 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 07:14:28.412846
483 07:14:28.413336 dmc_version 0001
484 07:14:28.419548 Check phy result
485 07:14:28.425568 INFO : End of CA training
486 07:14:28.426163 INFO : End of initialization
487 07:14:28.431051 INFO : Training has run successfully!
488 07:14:28.431539 Check phy result
489 07:14:28.436723 INFO : End of initialization
490 07:14:28.437185 INFO : End of read enable training
491 07:14:28.442359 INFO : End of fine write leveling
492 07:14:28.447869 INFO : End of Write leveling coarse delay
493 07:14:28.448434 INFO : Training has run successfully!
494 07:14:28.448849 Check phy result
495 07:14:28.453377 INFO : End of initialization
496 07:14:28.453835 INFO : End of read dq deskew training
497 07:14:28.459108 INFO : End of MPR read delay center optimization
498 07:14:28.464757 INFO : End of write delay center optimization
499 07:14:28.470411 INFO : End of read delay center optimization
500 07:14:28.470864 INFO : End of max read latency training
501 07:14:28.475856 INFO : Training has run successfully!
502 07:14:28.476388 1D training succeed
503 07:14:28.485000 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 07:14:28.532567 Check phy result
505 07:14:28.533063 INFO : End of initialization
506 07:14:28.554367 INFO : End of 2D read delay Voltage center optimization
507 07:14:28.574510 INFO : End of 2D read delay Voltage center optimization
508 07:14:28.625828 INFO : End of 2D write delay Voltage center optimization
509 07:14:28.675943 INFO : End of 2D write delay Voltage center optimization
510 07:14:28.681564 INFO : Training has run successfully!
511 07:14:28.681993
512 07:14:28.682398 channel==0
513 07:14:28.687095 RxClkDly_Margin_A0==88 ps 9
514 07:14:28.687522 TxDqDly_Margin_A0==98 ps 10
515 07:14:28.690452 RxClkDly_Margin_A1==88 ps 9
516 07:14:28.690874 TxDqDly_Margin_A1==88 ps 9
517 07:14:28.696051 TrainedVREFDQ_A0==74
518 07:14:28.696510 TrainedVREFDQ_A1==74
519 07:14:28.696911 VrefDac_Margin_A0==25
520 07:14:28.701701 DeviceVref_Margin_A0==40
521 07:14:28.702140 VrefDac_Margin_A1==25
522 07:14:28.707336 DeviceVref_Margin_A1==40
523 07:14:28.707755
524 07:14:28.708193
525 07:14:28.708590 channel==1
526 07:14:28.708980 RxClkDly_Margin_A0==98 ps 10
527 07:14:28.712836 TxDqDly_Margin_A0==98 ps 10
528 07:14:28.713259 RxClkDly_Margin_A1==98 ps 10
529 07:14:28.718452 TxDqDly_Margin_A1==88 ps 9
530 07:14:28.718879 TrainedVREFDQ_A0==77
531 07:14:28.719277 TrainedVREFDQ_A1==77
532 07:14:28.724057 VrefDac_Margin_A0==22
533 07:14:28.724476 DeviceVref_Margin_A0==37
534 07:14:28.729661 VrefDac_Margin_A1==24
535 07:14:28.730074 DeviceVref_Margin_A1==37
536 07:14:28.730470
537 07:14:28.735295 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 07:14:28.735711
539 07:14:28.763306 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 07:14:28.768843 2D training succeed
541 07:14:28.774453 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 07:14:28.774883 auto size-- 65535DDR cs0 size: 2048MB
543 07:14:28.780066 DDR cs1 size: 2048MB
544 07:14:28.780487 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 07:14:28.785683 cs0 DataBus test pass
546 07:14:28.786125 cs1 DataBus test pass
547 07:14:28.786524 cs0 AddrBus test pass
548 07:14:28.791313 cs1 AddrBus test pass
549 07:14:28.791756
550 07:14:28.792206 100bdlr_step_size ps== 420
551 07:14:28.792618 result report
552 07:14:28.796854 boot times 0Enable ddr reg access
553 07:14:28.804494 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 07:14:28.817970 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 07:14:29.391643 0.0;M3 CHK:0;cm4_sp_mode 0
556 07:14:29.392194 MVN_1=0x00000000
557 07:14:29.397167 MVN_2=0x00000000
558 07:14:29.402919 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 07:14:29.403399 OPS=0x10
560 07:14:29.403826 ring efuse init
561 07:14:29.404251 chipver efuse init
562 07:14:29.408487 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 07:14:29.414044 [0.018961 Inits done]
564 07:14:29.414456 secure task start!
565 07:14:29.414840 high task start!
566 07:14:29.417697 low task start!
567 07:14:29.418121 run into bl31
568 07:14:29.425397 NOTICE: BL31: v1.3(release):4fc40b1
569 07:14:29.433118 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 07:14:29.433573 NOTICE: BL31: G12A normal boot!
571 07:14:29.458508 NOTICE: BL31: BL33 decompress pass
572 07:14:29.463635 ERROR: Error initializing runtime service opteed_fast
573 07:14:30.697182
574 07:14:30.697750
575 07:14:30.705667 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 07:14:30.706134
577 07:14:30.706545 Model: Libre Computer AML-A311D-CC Alta
578 07:14:30.914224 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 07:14:30.937483 DRAM: 2 GiB (effective 3.8 GiB)
580 07:14:31.080446 Core: 408 devices, 31 uclasses, devicetree: separate
581 07:14:31.086277 WDT: Not starting watchdog@f0d0
582 07:14:31.118473 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 07:14:31.130831 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 07:14:31.138510 ** Bad device specification mmc 0 **
585 07:14:31.146341 Card did not respond to voltage select! : -110
586 07:14:31.153997 ** Bad device specification mmc 0 **
587 07:14:31.154423 Couldn't find partition mmc 0
588 07:14:31.162207 Card did not respond to voltage select! : -110
589 07:14:31.167725 ** Bad device specification mmc 0 **
590 07:14:31.168199 Couldn't find partition mmc 0
591 07:14:31.172849 Error: could not access storage.
592 07:14:31.516505 Net: eth0: ethernet@ff3f0000
593 07:14:31.517067 starting USB...
594 07:14:31.768314 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 07:14:31.768834 Starting the controller
596 07:14:31.775155 USB XHCI 1.10
597 07:14:33.485720 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 07:14:33.486315 bl2_stage_init 0x01
599 07:14:33.486739 bl2_stage_init 0x81
600 07:14:33.491238 hw id: 0x0000 - pwm id 0x01
601 07:14:33.491679 bl2_stage_init 0xc1
602 07:14:33.492136 bl2_stage_init 0x02
603 07:14:33.492545
604 07:14:33.496826 L0:00000000
605 07:14:33.497260 L1:20000703
606 07:14:33.497665 L2:00008067
607 07:14:33.498063 L3:14000000
608 07:14:33.502403 B2:00402000
609 07:14:33.502832 B1:e0f83180
610 07:14:33.503231
611 07:14:33.503624 TE: 58124
612 07:14:33.504050
613 07:14:33.508096 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 07:14:33.508529
615 07:14:33.508928 Board ID = 1
616 07:14:33.513652 Set A53 clk to 24M
617 07:14:33.514093 Set A73 clk to 24M
618 07:14:33.514490 Set clk81 to 24M
619 07:14:33.519179 A53 clk: 1200 MHz
620 07:14:33.519609 A73 clk: 1200 MHz
621 07:14:33.520038 CLK81: 166.6M
622 07:14:33.520435 smccc: 00012a92
623 07:14:33.524756 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 07:14:33.530381 board id: 1
625 07:14:33.536242 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 07:14:33.547005 fw parse done
627 07:14:33.552898 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 07:14:33.595526 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 07:14:33.606401 PIEI prepare done
630 07:14:33.606830 fastboot data load
631 07:14:33.607233 fastboot data verify
632 07:14:33.612040 verify result: 266
633 07:14:33.617628 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 07:14:33.618052 LPDDR4 probe
635 07:14:33.618452 ddr clk to 1584MHz
636 07:14:33.625671 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 07:14:33.662970
638 07:14:33.663408 dmc_version 0001
639 07:14:33.669558 Check phy result
640 07:14:33.675387 INFO : End of CA training
641 07:14:33.675804 INFO : End of initialization
642 07:14:33.681025 INFO : Training has run successfully!
643 07:14:33.681448 Check phy result
644 07:14:33.686593 INFO : End of initialization
645 07:14:33.687017 INFO : End of read enable training
646 07:14:33.692256 INFO : End of fine write leveling
647 07:14:33.697775 INFO : End of Write leveling coarse delay
648 07:14:33.698197 INFO : Training has run successfully!
649 07:14:33.698598 Check phy result
650 07:14:33.703422 INFO : End of initialization
651 07:14:33.703844 INFO : End of read dq deskew training
652 07:14:33.709069 INFO : End of MPR read delay center optimization
653 07:14:33.714610 INFO : End of write delay center optimization
654 07:14:33.720195 INFO : End of read delay center optimization
655 07:14:33.720617 INFO : End of max read latency training
656 07:14:33.725793 INFO : Training has run successfully!
657 07:14:33.726214 1D training succeed
658 07:14:33.735003 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 07:14:33.782701 Check phy result
660 07:14:33.783141 INFO : End of initialization
661 07:14:33.804389 INFO : End of 2D read delay Voltage center optimization
662 07:14:33.823777 INFO : End of 2D read delay Voltage center optimization
663 07:14:33.876763 INFO : End of 2D write delay Voltage center optimization
664 07:14:33.926126 INFO : End of 2D write delay Voltage center optimization
665 07:14:33.931639 INFO : Training has run successfully!
666 07:14:33.932104
667 07:14:33.932512 channel==0
668 07:14:33.937119 RxClkDly_Margin_A0==88 ps 9
669 07:14:33.937540 TxDqDly_Margin_A0==98 ps 10
670 07:14:33.940591 RxClkDly_Margin_A1==88 ps 9
671 07:14:33.941008 TxDqDly_Margin_A1==98 ps 10
672 07:14:33.946121 TrainedVREFDQ_A0==74
673 07:14:33.946555 TrainedVREFDQ_A1==74
674 07:14:33.946961 VrefDac_Margin_A0==25
675 07:14:33.951735 DeviceVref_Margin_A0==40
676 07:14:33.952193 VrefDac_Margin_A1==25
677 07:14:33.957255 DeviceVref_Margin_A1==40
678 07:14:33.957671
679 07:14:33.958074
680 07:14:33.958474 channel==1
681 07:14:33.958864 RxClkDly_Margin_A0==98 ps 10
682 07:14:33.960847 TxDqDly_Margin_A0==98 ps 10
683 07:14:33.966364 RxClkDly_Margin_A1==88 ps 9
684 07:14:33.966778 TxDqDly_Margin_A1==98 ps 10
685 07:14:33.967176 TrainedVREFDQ_A0==77
686 07:14:33.971972 TrainedVREFDQ_A1==78
687 07:14:33.972419 VrefDac_Margin_A0==22
688 07:14:33.977623 DeviceVref_Margin_A0==37
689 07:14:33.978041 VrefDac_Margin_A1==24
690 07:14:33.978439 DeviceVref_Margin_A1==36
691 07:14:33.978829
692 07:14:33.983127 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 07:14:33.983548
694 07:14:34.016789 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 07:14:34.017252 2D training succeed
696 07:14:34.022358 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 07:14:34.027800 auto size-- 65535DDR cs0 size: 2048MB
698 07:14:34.028256 DDR cs1 size: 2048MB
699 07:14:34.033402 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 07:14:34.033824 cs0 DataBus test pass
701 07:14:34.034220 cs1 DataBus test pass
702 07:14:34.038990 cs0 AddrBus test pass
703 07:14:34.039416 cs1 AddrBus test pass
704 07:14:34.039814
705 07:14:34.044597 100bdlr_step_size ps== 420
706 07:14:34.045033 result report
707 07:14:34.045431 boot times 0Enable ddr reg access
708 07:14:34.054495 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 07:14:34.068121 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 07:14:34.641631 0.0;M3 CHK:0;cm4_sp_mode 0
711 07:14:34.642167 MVN_1=0x00000000
712 07:14:34.647139 MVN_2=0x00000000
713 07:14:34.652887 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 07:14:34.653370 OPS=0x10
715 07:14:34.653762 ring efuse init
716 07:14:34.654147 chipver efuse init
717 07:14:34.658460 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 07:14:34.664073 [0.018961 Inits done]
719 07:14:34.664489 secure task start!
720 07:14:34.664872 high task start!
721 07:14:34.668658 low task start!
722 07:14:34.669066 run into bl31
723 07:14:34.675309 NOTICE: BL31: v1.3(release):4fc40b1
724 07:14:34.683141 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 07:14:34.683569 NOTICE: BL31: G12A normal boot!
726 07:14:34.708479 NOTICE: BL31: BL33 decompress pass
727 07:14:34.714142 ERROR: Error initializing runtime service opteed_fast
728 07:14:35.947160
729 07:14:35.947723
730 07:14:35.955433 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 07:14:35.955871
732 07:14:35.956320 Model: Libre Computer AML-A311D-CC Alta
733 07:14:36.163846 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 07:14:36.187356 DRAM: 2 GiB (effective 3.8 GiB)
735 07:14:36.330356 Core: 408 devices, 31 uclasses, devicetree: separate
736 07:14:36.336167 WDT: Not starting watchdog@f0d0
737 07:14:36.368377 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 07:14:36.380827 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 07:14:36.385776 ** Bad device specification mmc 0 **
740 07:14:36.396145 Card did not respond to voltage select! : -110
741 07:14:36.403769 ** Bad device specification mmc 0 **
742 07:14:36.404258 Couldn't find partition mmc 0
743 07:14:36.412125 Card did not respond to voltage select! : -110
744 07:14:36.417636 ** Bad device specification mmc 0 **
745 07:14:36.418066 Couldn't find partition mmc 0
746 07:14:36.422692 Error: could not access storage.
747 07:14:36.764328 Net: eth0: ethernet@ff3f0000
748 07:14:36.764836 starting USB...
749 07:14:37.016979 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 07:14:37.017483 Starting the controller
751 07:14:37.023946 USB XHCI 1.10
752 07:14:39.186035 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 07:14:39.186640 bl2_stage_init 0x01
754 07:14:39.187060 bl2_stage_init 0x81
755 07:14:39.191558 hw id: 0x0000 - pwm id 0x01
756 07:14:39.192029 bl2_stage_init 0xc1
757 07:14:39.192445 bl2_stage_init 0x02
758 07:14:39.192846
759 07:14:39.197152 L0:00000000
760 07:14:39.197581 L1:20000703
761 07:14:39.197984 L2:00008067
762 07:14:39.198378 L3:14000000
763 07:14:39.200022 B2:00402000
764 07:14:39.200458 B1:e0f83180
765 07:14:39.200857
766 07:14:39.201252 TE: 58167
767 07:14:39.201644
768 07:14:39.211160 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 07:14:39.211590
770 07:14:39.212017 Board ID = 1
771 07:14:39.212418 Set A53 clk to 24M
772 07:14:39.212809 Set A73 clk to 24M
773 07:14:39.216758 Set clk81 to 24M
774 07:14:39.217185 A53 clk: 1200 MHz
775 07:14:39.217583 A73 clk: 1200 MHz
776 07:14:39.220243 CLK81: 166.6M
777 07:14:39.220666 smccc: 00012abd
778 07:14:39.225830 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 07:14:39.231357 board id: 1
780 07:14:39.236766 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 07:14:39.247111 fw parse done
782 07:14:39.253142 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 07:14:39.295769 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 07:14:39.306713 PIEI prepare done
785 07:14:39.307166 fastboot data load
786 07:14:39.307575 fastboot data verify
787 07:14:39.312246 verify result: 266
788 07:14:39.317868 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 07:14:39.318298 LPDDR4 probe
790 07:14:39.318721 ddr clk to 1584MHz
791 07:14:39.325819 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 07:14:39.362226
793 07:14:39.362667 dmc_version 0001
794 07:14:39.369885 Check phy result
795 07:14:39.375742 INFO : End of CA training
796 07:14:39.376200 INFO : End of initialization
797 07:14:39.381283 INFO : Training has run successfully!
798 07:14:39.381707 Check phy result
799 07:14:39.386891 INFO : End of initialization
800 07:14:39.387309 INFO : End of read enable training
801 07:14:39.390169 INFO : End of fine write leveling
802 07:14:39.395759 INFO : End of Write leveling coarse delay
803 07:14:39.401290 INFO : Training has run successfully!
804 07:14:39.401714 Check phy result
805 07:14:39.402112 INFO : End of initialization
806 07:14:39.406922 INFO : End of read dq deskew training
807 07:14:39.412535 INFO : End of MPR read delay center optimization
808 07:14:39.412989 INFO : End of write delay center optimization
809 07:14:39.418111 INFO : End of read delay center optimization
810 07:14:39.423772 INFO : End of max read latency training
811 07:14:39.424249 INFO : Training has run successfully!
812 07:14:39.429318 1D training succeed
813 07:14:39.435303 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 07:14:39.482989 Check phy result
815 07:14:39.483457 INFO : End of initialization
816 07:14:39.504621 INFO : End of 2D read delay Voltage center optimization
817 07:14:39.524845 INFO : End of 2D read delay Voltage center optimization
818 07:14:39.577009 INFO : End of 2D write delay Voltage center optimization
819 07:14:39.626265 INFO : End of 2D write delay Voltage center optimization
820 07:14:39.631911 INFO : Training has run successfully!
821 07:14:39.632382
822 07:14:39.632787 channel==0
823 07:14:39.637435 RxClkDly_Margin_A0==88 ps 9
824 07:14:39.637857 TxDqDly_Margin_A0==98 ps 10
825 07:14:39.640933 RxClkDly_Margin_A1==88 ps 9
826 07:14:39.641352 TxDqDly_Margin_A1==88 ps 9
827 07:14:39.646381 TrainedVREFDQ_A0==74
828 07:14:39.646803 TrainedVREFDQ_A1==74
829 07:14:39.647217 VrefDac_Margin_A0==25
830 07:14:39.651975 DeviceVref_Margin_A0==40
831 07:14:39.652462 VrefDac_Margin_A1==25
832 07:14:39.657632 DeviceVref_Margin_A1==40
833 07:14:39.658080
834 07:14:39.658468
835 07:14:39.658849 channel==1
836 07:14:39.659231 RxClkDly_Margin_A0==98 ps 10
837 07:14:39.663275 TxDqDly_Margin_A0==98 ps 10
838 07:14:39.663701 RxClkDly_Margin_A1==88 ps 9
839 07:14:39.668843 TxDqDly_Margin_A1==88 ps 9
840 07:14:39.669278 TrainedVREFDQ_A0==77
841 07:14:39.669668 TrainedVREFDQ_A1==77
842 07:14:39.674422 VrefDac_Margin_A0==22
843 07:14:39.674857 DeviceVref_Margin_A0==37
844 07:14:39.679951 VrefDac_Margin_A1==24
845 07:14:39.680392 DeviceVref_Margin_A1==37
846 07:14:39.680776
847 07:14:39.685585 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 07:14:39.685999
849 07:14:39.713570 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 0000005f
850 07:14:39.719164 2D training succeed
851 07:14:39.724796 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 07:14:39.725223 auto size-- 65535DDR cs0 size: 2048MB
853 07:14:39.730408 DDR cs1 size: 2048MB
854 07:14:39.730820 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 07:14:39.735971 cs0 DataBus test pass
856 07:14:39.736414 cs1 DataBus test pass
857 07:14:39.736797 cs0 AddrBus test pass
858 07:14:39.741600 cs1 AddrBus test pass
859 07:14:39.742008
860 07:14:39.742392 100bdlr_step_size ps== 420
861 07:14:39.742781 result report
862 07:14:39.747198 boot times 0Enable ddr reg access
863 07:14:39.754634 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 07:14:39.768150 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 07:14:40.341090 0.0;M3 CHK:0;cm4_sp_mode 0
866 07:14:40.341665 MVN_1=0x00000000
867 07:14:40.346583 MVN_2=0x00000000
868 07:14:40.352360 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 07:14:40.352793 OPS=0x10
870 07:14:40.353199 ring efuse init
871 07:14:40.353596 chipver efuse init
872 07:14:40.357959 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 07:14:40.363533 [0.018961 Inits done]
874 07:14:40.363950 secure task start!
875 07:14:40.364395 high task start!
876 07:14:40.368149 low task start!
877 07:14:40.368569 run into bl31
878 07:14:40.374809 NOTICE: BL31: v1.3(release):4fc40b1
879 07:14:40.382634 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 07:14:40.383063 NOTICE: BL31: G12A normal boot!
881 07:14:40.408005 NOTICE: BL31: BL33 decompress pass
882 07:14:40.413683 ERROR: Error initializing runtime service opteed_fast
883 07:14:41.646622
884 07:14:41.647204
885 07:14:41.655008 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 07:14:41.655450
887 07:14:41.655862 Model: Libre Computer AML-A311D-CC Alta
888 07:14:41.863485 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 07:14:41.886852 DRAM: 2 GiB (effective 3.8 GiB)
890 07:14:42.029795 Core: 408 devices, 31 uclasses, devicetree: separate
891 07:14:42.035688 WDT: Not starting watchdog@f0d0
892 07:14:42.067945 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 07:14:42.080395 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 07:14:42.085388 ** Bad device specification mmc 0 **
895 07:14:42.095774 Card did not respond to voltage select! : -110
896 07:14:42.103383 ** Bad device specification mmc 0 **
897 07:14:42.103812 Couldn't find partition mmc 0
898 07:14:42.111734 Card did not respond to voltage select! : -110
899 07:14:42.117230 ** Bad device specification mmc 0 **
900 07:14:42.117657 Couldn't find partition mmc 0
901 07:14:42.122308 Error: could not access storage.
902 07:14:42.464430 Net: eth0: ethernet@ff3f0000
903 07:14:42.464960 starting USB...
904 07:14:42.716634 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 07:14:42.717183 Starting the controller
906 07:14:42.723520 USB XHCI 1.10
907 07:14:44.277576 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 07:14:44.285982 scanning usb for storage devices... 0 Storage Device(s) found
910 07:14:44.337516 Hit any key to stop autoboot: 1
911 07:14:44.338362 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
912 07:14:44.338975 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
913 07:14:44.339504 Setting prompt string to ['=>']
914 07:14:44.340082 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
915 07:14:44.353336 0
916 07:14:44.354222 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 07:14:44.354755 Sending with 10 millisecond of delay
919 07:14:45.489304 => setenv autoload no
920 07:14:45.500091 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 07:14:45.505004 setenv autoload no
922 07:14:45.505727 Sending with 10 millisecond of delay
924 07:14:47.302089 => setenv initrd_high 0xffffffff
925 07:14:47.312835 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
926 07:14:47.313640 setenv initrd_high 0xffffffff
927 07:14:47.314343 Sending with 10 millisecond of delay
929 07:14:48.930463 => setenv fdt_high 0xffffffff
930 07:14:48.941225 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 07:14:48.942007 setenv fdt_high 0xffffffff
932 07:14:48.942706 Sending with 10 millisecond of delay
934 07:14:49.234455 => dhcp
935 07:14:49.245163 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
936 07:14:49.245952 dhcp
937 07:14:49.246380 Speed: 1000, full duplex
938 07:14:49.246787 BOOTP broadcast 1
939 07:14:49.492455 BOOTP broadcast 2
940 07:14:49.994390 BOOTP broadcast 3
941 07:14:50.011528 DHCP client bound to address 192.168.6.33 (766 ms)
942 07:14:50.012305 Sending with 10 millisecond of delay
944 07:14:51.688309 => setenv serverip 192.168.6.2
945 07:14:51.699076 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
946 07:14:51.699931 setenv serverip 192.168.6.2
947 07:14:51.700660 Sending with 10 millisecond of delay
949 07:14:55.425009 => tftpboot 0x01080000 714890/tftp-deploy-26yve1ks/kernel/uImage
950 07:14:55.436005 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
951 07:14:55.437042 tftpboot 0x01080000 714890/tftp-deploy-26yve1ks/kernel/uImage
952 07:14:55.437597 Speed: 1000, full duplex
953 07:14:55.438111 Using ethernet@ff3f0000 device
954 07:14:55.438762 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
955 07:14:55.444178 Filename '714890/tftp-deploy-26yve1ks/kernel/uImage'.
956 07:14:55.447956 Load address: 0x1080000
957 07:14:58.365447 Loading: *################################################## 43.2 MiB
958 07:14:58.366075 14.8 MiB/s
959 07:14:58.366482 done
960 07:14:58.369916 Bytes transferred = 45308480 (2b35a40 hex)
961 07:14:58.370708 Sending with 10 millisecond of delay
963 07:15:03.056970 => tftpboot 0x08000000 714890/tftp-deploy-26yve1ks/ramdisk/ramdisk.cpio.gz.uboot
964 07:15:03.067713 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
965 07:15:03.068580 tftpboot 0x08000000 714890/tftp-deploy-26yve1ks/ramdisk/ramdisk.cpio.gz.uboot
966 07:15:03.069024 Speed: 1000, full duplex
967 07:15:03.069432 Using ethernet@ff3f0000 device
968 07:15:03.070360 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
969 07:15:03.082052 Filename '714890/tftp-deploy-26yve1ks/ramdisk/ramdisk.cpio.gz.uboot'.
970 07:15:03.082553 Load address: 0x8000000
971 07:15:12.902891 Loading: *#######T ########################################## UDP wrong checksum 0000000f 00007a09
972 07:15:17.903797 T UDP wrong checksum 0000000f 00007a09
973 07:15:27.905668 T T UDP wrong checksum 0000000f 00007a09
974 07:15:38.528470 T T UDP wrong checksum 000000ff 00002707
975 07:15:38.538694 UDP wrong checksum 000000ff 0000abf9
976 07:15:47.908941 T T UDP wrong checksum 0000000f 00007a09
977 07:16:02.914010 T T
978 07:16:02.914438 Retry count exceeded; starting again
980 07:16:02.915313 end: 2.4.3 bootloader-commands (duration 00:01:19) [common]
983 07:16:02.916311 end: 2.4 uboot-commands (duration 00:01:50) [common]
985 07:16:02.917039 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
987 07:16:02.917604 end: 2 uboot-action (duration 00:01:50) [common]
989 07:16:02.918433 Cleaning after the job
990 07:16:02.918744 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/ramdisk
991 07:16:02.919512 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/kernel
992 07:16:02.945851 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/dtb
993 07:16:02.946648 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714890/tftp-deploy-26yve1ks/modules
994 07:16:02.967278 start: 4.1 power-off (timeout 00:00:30) [common]
995 07:16:02.967932 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
996 07:16:03.001042 >> OK - accepted request
997 07:16:03.003045 Returned 0 in 0 seconds
998 07:16:03.103741 end: 4.1 power-off (duration 00:00:00) [common]
1000 07:16:03.104666 start: 4.2 read-feedback (timeout 00:10:00) [common]
1001 07:16:03.105333 Listened to connection for namespace 'common' for up to 1s
1002 07:16:04.106178 Finalising connection for namespace 'common'
1003 07:16:04.106892 Disconnecting from shell: Finalise
1004 07:16:04.107407 =>
1005 07:16:04.208453 end: 4.2 read-feedback (duration 00:00:01) [common]
1006 07:16:04.209118 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714890
1007 07:16:04.888344 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714890
1008 07:16:04.889067 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.