Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:52:10.993690 lava-dispatcher, installed at version: 2024.01
2 06:52:10.994497 start: 0 validate
3 06:52:10.994963 Start time: 2024-09-06 06:52:10.994933+00:00 (UTC)
4 06:52:10.995508 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:52:10.996084 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:52:11.031139 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:52:11.031673 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:52:11.062984 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:52:11.063635 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:52:11.097760 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:52:11.098273 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:52:11.131047 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:52:11.131536 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 06:52:11.172111 validate duration: 0.18
16 06:52:11.172949 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:52:11.173280 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:52:11.173607 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:52:11.174198 Not decompressing ramdisk as can be used compressed.
20 06:52:11.174649 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 06:52:11.174938 saving as /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/ramdisk/initrd.cpio.gz
22 06:52:11.175227 total size: 5628169 (5 MB)
23 06:52:11.209961 progress 0 % (0 MB)
24 06:52:11.216322 progress 5 % (0 MB)
25 06:52:11.224230 progress 10 % (0 MB)
26 06:52:11.231033 progress 15 % (0 MB)
27 06:52:11.235536 progress 20 % (1 MB)
28 06:52:11.239137 progress 25 % (1 MB)
29 06:52:11.243265 progress 30 % (1 MB)
30 06:52:11.247276 progress 35 % (1 MB)
31 06:52:11.250911 progress 40 % (2 MB)
32 06:52:11.254949 progress 45 % (2 MB)
33 06:52:11.258645 progress 50 % (2 MB)
34 06:52:11.262698 progress 55 % (2 MB)
35 06:52:11.266797 progress 60 % (3 MB)
36 06:52:11.270662 progress 65 % (3 MB)
37 06:52:11.274707 progress 70 % (3 MB)
38 06:52:11.278266 progress 75 % (4 MB)
39 06:52:11.282202 progress 80 % (4 MB)
40 06:52:11.285804 progress 85 % (4 MB)
41 06:52:11.289760 progress 90 % (4 MB)
42 06:52:11.293613 progress 95 % (5 MB)
43 06:52:11.296895 progress 100 % (5 MB)
44 06:52:11.297566 5 MB downloaded in 0.12 s (43.88 MB/s)
45 06:52:11.298107 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:52:11.299016 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:52:11.299322 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:52:11.299603 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:52:11.300110 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
51 06:52:11.300370 saving as /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/kernel/Image
52 06:52:11.300588 total size: 45308416 (43 MB)
53 06:52:11.300804 No compression specified
54 06:52:11.334644 progress 0 % (0 MB)
55 06:52:11.364345 progress 5 % (2 MB)
56 06:52:11.393264 progress 10 % (4 MB)
57 06:52:11.421800 progress 15 % (6 MB)
58 06:52:11.450049 progress 20 % (8 MB)
59 06:52:11.478607 progress 25 % (10 MB)
60 06:52:11.508136 progress 30 % (12 MB)
61 06:52:11.536621 progress 35 % (15 MB)
62 06:52:11.565384 progress 40 % (17 MB)
63 06:52:11.594721 progress 45 % (19 MB)
64 06:52:11.623849 progress 50 % (21 MB)
65 06:52:11.652788 progress 55 % (23 MB)
66 06:52:11.682513 progress 60 % (25 MB)
67 06:52:11.711961 progress 65 % (28 MB)
68 06:52:11.741413 progress 70 % (30 MB)
69 06:52:11.770583 progress 75 % (32 MB)
70 06:52:11.800054 progress 80 % (34 MB)
71 06:52:11.829367 progress 85 % (36 MB)
72 06:52:11.858710 progress 90 % (38 MB)
73 06:52:11.888200 progress 95 % (41 MB)
74 06:52:11.917108 progress 100 % (43 MB)
75 06:52:11.917891 43 MB downloaded in 0.62 s (70.00 MB/s)
76 06:52:11.918421 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:52:11.919288 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:52:11.919582 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:52:11.919864 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:52:11.920414 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 06:52:11.920722 saving as /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/dtb/meson-g12b-a311d-libretech-cc.dtb
83 06:52:11.920944 total size: 54667 (0 MB)
84 06:52:11.921164 No compression specified
85 06:52:11.964651 progress 59 % (0 MB)
86 06:52:11.965854 progress 100 % (0 MB)
87 06:52:11.966577 0 MB downloaded in 0.05 s (1.14 MB/s)
88 06:52:11.967198 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:52:11.968341 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:52:11.968803 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:52:11.969187 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:52:11.969808 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 06:52:11.970130 saving as /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/nfsrootfs/full.rootfs.tar
95 06:52:11.970409 total size: 120894716 (115 MB)
96 06:52:11.970682 Using unxz to decompress xz
97 06:52:12.014169 progress 0 % (0 MB)
98 06:52:12.971679 progress 5 % (5 MB)
99 06:52:13.952440 progress 10 % (11 MB)
100 06:52:14.748813 progress 15 % (17 MB)
101 06:52:15.495828 progress 20 % (23 MB)
102 06:52:16.092539 progress 25 % (28 MB)
103 06:52:16.914509 progress 30 % (34 MB)
104 06:52:17.708841 progress 35 % (40 MB)
105 06:52:18.054252 progress 40 % (46 MB)
106 06:52:18.425539 progress 45 % (51 MB)
107 06:52:19.155493 progress 50 % (57 MB)
108 06:52:20.044769 progress 55 % (63 MB)
109 06:52:20.839548 progress 60 % (69 MB)
110 06:52:21.602542 progress 65 % (74 MB)
111 06:52:22.379411 progress 70 % (80 MB)
112 06:52:23.202357 progress 75 % (86 MB)
113 06:52:23.993752 progress 80 % (92 MB)
114 06:52:24.886395 progress 85 % (98 MB)
115 06:52:25.782995 progress 90 % (103 MB)
116 06:52:26.609195 progress 95 % (109 MB)
117 06:52:27.466458 progress 100 % (115 MB)
118 06:52:27.479478 115 MB downloaded in 15.51 s (7.43 MB/s)
119 06:52:27.480481 end: 1.4.1 http-download (duration 00:00:16) [common]
121 06:52:27.482278 end: 1.4 download-retry (duration 00:00:16) [common]
122 06:52:27.482868 start: 1.5 download-retry (timeout 00:09:44) [common]
123 06:52:27.483454 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 06:52:27.484577 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
125 06:52:27.485121 saving as /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/modules/modules.tar
126 06:52:27.485581 total size: 11502724 (10 MB)
127 06:52:27.486051 Using unxz to decompress xz
128 06:52:27.533359 progress 0 % (0 MB)
129 06:52:27.602670 progress 5 % (0 MB)
130 06:52:27.680356 progress 10 % (1 MB)
131 06:52:27.763740 progress 15 % (1 MB)
132 06:52:27.844802 progress 20 % (2 MB)
133 06:52:27.921911 progress 25 % (2 MB)
134 06:52:28.003923 progress 30 % (3 MB)
135 06:52:28.079314 progress 35 % (3 MB)
136 06:52:28.157826 progress 40 % (4 MB)
137 06:52:28.230107 progress 45 % (4 MB)
138 06:52:28.308970 progress 50 % (5 MB)
139 06:52:28.385802 progress 55 % (6 MB)
140 06:52:28.466303 progress 60 % (6 MB)
141 06:52:28.552978 progress 65 % (7 MB)
142 06:52:28.630761 progress 70 % (7 MB)
143 06:52:28.728878 progress 75 % (8 MB)
144 06:52:28.819226 progress 80 % (8 MB)
145 06:52:28.900641 progress 85 % (9 MB)
146 06:52:28.972110 progress 90 % (9 MB)
147 06:52:29.049035 progress 95 % (10 MB)
148 06:52:29.125783 progress 100 % (10 MB)
149 06:52:29.135653 10 MB downloaded in 1.65 s (6.65 MB/s)
150 06:52:29.136439 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:52:29.138341 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:52:29.138935 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 06:52:29.139517 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 06:52:46.743131 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/714812/extract-nfsrootfs-3bsbcc_n
156 06:52:46.743740 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 06:52:46.744086 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 06:52:46.744839 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_
159 06:52:46.745341 makedir: /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin
160 06:52:46.745759 makedir: /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/tests
161 06:52:46.746160 makedir: /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/results
162 06:52:46.746538 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-add-keys
163 06:52:46.747078 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-add-sources
164 06:52:46.747594 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-background-process-start
165 06:52:46.748211 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-background-process-stop
166 06:52:46.748767 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-common-functions
167 06:52:46.749258 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-echo-ipv4
168 06:52:46.749744 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-install-packages
169 06:52:46.750257 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-installed-packages
170 06:52:46.750784 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-os-build
171 06:52:46.751271 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-probe-channel
172 06:52:46.751749 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-probe-ip
173 06:52:46.752273 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-target-ip
174 06:52:46.752765 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-target-mac
175 06:52:46.753241 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-target-storage
176 06:52:46.753750 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-test-case
177 06:52:46.754268 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-test-event
178 06:52:46.754753 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-test-feedback
179 06:52:46.755233 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-test-raise
180 06:52:46.755713 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-test-reference
181 06:52:46.756249 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-test-runner
182 06:52:46.756747 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-test-set
183 06:52:46.757240 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-test-shell
184 06:52:46.757748 Updating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-add-keys (debian)
185 06:52:46.758293 Updating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-add-sources (debian)
186 06:52:46.758801 Updating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-install-packages (debian)
187 06:52:46.759303 Updating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-installed-packages (debian)
188 06:52:46.759801 Updating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/bin/lava-os-build (debian)
189 06:52:46.760295 Creating /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/environment
190 06:52:46.760677 LAVA metadata
191 06:52:46.760938 - LAVA_JOB_ID=714812
192 06:52:46.761154 - LAVA_DISPATCHER_IP=192.168.6.2
193 06:52:46.761528 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 06:52:46.762518 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 06:52:46.762835 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 06:52:46.763041 skipped lava-vland-overlay
197 06:52:46.763279 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 06:52:46.763531 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 06:52:46.763748 skipped lava-multinode-overlay
200 06:52:46.764014 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 06:52:46.764274 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 06:52:46.764527 Loading test definitions
203 06:52:46.764805 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 06:52:46.765025 Using /lava-714812 at stage 0
205 06:52:46.766165 uuid=714812_1.6.2.4.1 testdef=None
206 06:52:46.766479 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 06:52:46.766741 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 06:52:46.768362 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 06:52:46.769159 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 06:52:46.771120 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 06:52:46.771953 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 06:52:46.773859 runner path: /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/0/tests/0_timesync-off test_uuid 714812_1.6.2.4.1
215 06:52:46.774435 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 06:52:46.775247 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 06:52:46.775471 Using /lava-714812 at stage 0
219 06:52:46.775830 Fetching tests from https://github.com/kernelci/test-definitions.git
220 06:52:46.776152 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/0/tests/1_kselftest-alsa'
221 06:52:50.107441 Running '/usr/bin/git checkout kernelci.org
222 06:52:50.272545 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 06:52:50.274921 uuid=714812_1.6.2.4.5 testdef=None
224 06:52:50.275584 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 06:52:50.277129 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 06:52:50.282788 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 06:52:50.284506 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 06:52:50.292051 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 06:52:50.293831 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 06:52:50.301193 runner path: /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/0/tests/1_kselftest-alsa test_uuid 714812_1.6.2.4.5
234 06:52:50.301788 BOARD='meson-g12b-a311d-libretech-cc'
235 06:52:50.302207 BRANCH='mainline'
236 06:52:50.302605 SKIPFILE='/dev/null'
237 06:52:50.303005 SKIP_INSTALL='True'
238 06:52:50.303399 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 06:52:50.303800 TST_CASENAME=''
240 06:52:50.304235 TST_CMDFILES='alsa'
241 06:52:50.305381 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 06:52:50.306996 Creating lava-test-runner.conf files
244 06:52:50.307411 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714812/lava-overlay-ipcnala_/lava-714812/0 for stage 0
245 06:52:50.308137 - 0_timesync-off
246 06:52:50.308649 - 1_kselftest-alsa
247 06:52:50.309334 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 06:52:50.309899 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 06:53:13.554372 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 06:53:13.554836 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 06:53:13.555136 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 06:53:13.555451 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 06:53:13.555748 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 06:53:14.173972 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 06:53:14.174450 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 06:53:14.174717 extracting modules file /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714812/extract-nfsrootfs-3bsbcc_n
257 06:53:15.522873 extracting modules file /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714812/extract-overlay-ramdisk-fxljqmux/ramdisk
258 06:53:16.903857 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 06:53:16.904369 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 06:53:16.904650 [common] Applying overlay to NFS
261 06:53:16.904866 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714812/compress-overlay-57gpdme0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714812/extract-nfsrootfs-3bsbcc_n
262 06:53:19.652090 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 06:53:19.652559 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 06:53:19.652833 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 06:53:19.653060 Converting downloaded kernel to a uImage
266 06:53:19.653369 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/kernel/Image /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/kernel/uImage
267 06:53:20.128927 output: Image Name:
268 06:53:20.129353 output: Created: Fri Sep 6 06:53:19 2024
269 06:53:20.129559 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 06:53:20.129761 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
271 06:53:20.129962 output: Load Address: 01080000
272 06:53:20.130162 output: Entry Point: 01080000
273 06:53:20.130358 output:
274 06:53:20.130689 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 06:53:20.130956 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 06:53:20.131223 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 06:53:20.131475 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 06:53:20.131730 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 06:53:20.132018 Building ramdisk /var/lib/lava/dispatcher/tmp/714812/extract-overlay-ramdisk-fxljqmux/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714812/extract-overlay-ramdisk-fxljqmux/ramdisk
280 06:53:22.274642 >> 165160 blocks
281 06:53:29.873102 Adding RAMdisk u-boot header.
282 06:53:29.873759 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714812/extract-overlay-ramdisk-fxljqmux/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714812/extract-overlay-ramdisk-fxljqmux/ramdisk.cpio.gz.uboot
283 06:53:30.130677 output: Image Name:
284 06:53:30.131092 output: Created: Fri Sep 6 06:53:29 2024
285 06:53:30.131297 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 06:53:30.131499 output: Data Size: 23258129 Bytes = 22713.02 KiB = 22.18 MiB
287 06:53:30.131699 output: Load Address: 00000000
288 06:53:30.131896 output: Entry Point: 00000000
289 06:53:30.132336 output:
290 06:53:30.133499 rename /var/lib/lava/dispatcher/tmp/714812/extract-overlay-ramdisk-fxljqmux/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/ramdisk/ramdisk.cpio.gz.uboot
291 06:53:30.134271 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 06:53:30.134859 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 06:53:30.135468 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 06:53:30.135951 No LXC device requested
295 06:53:30.136534 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 06:53:30.137087 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 06:53:30.137622 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 06:53:30.138070 Checking files for TFTP limit of 4294967296 bytes.
299 06:53:30.141031 end: 1 tftp-deploy (duration 00:01:19) [common]
300 06:53:30.141657 start: 2 uboot-action (timeout 00:05:00) [common]
301 06:53:30.142230 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 06:53:30.142773 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 06:53:30.143321 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 06:53:30.143896 Using kernel file from prepare-kernel: 714812/tftp-deploy-5blp6lma/kernel/uImage
305 06:53:30.144626 substitutions:
306 06:53:30.145075 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 06:53:30.145520 - {DTB_ADDR}: 0x01070000
308 06:53:30.145960 - {DTB}: 714812/tftp-deploy-5blp6lma/dtb/meson-g12b-a311d-libretech-cc.dtb
309 06:53:30.146407 - {INITRD}: 714812/tftp-deploy-5blp6lma/ramdisk/ramdisk.cpio.gz.uboot
310 06:53:30.146843 - {KERNEL_ADDR}: 0x01080000
311 06:53:30.147279 - {KERNEL}: 714812/tftp-deploy-5blp6lma/kernel/uImage
312 06:53:30.147712 - {LAVA_MAC}: None
313 06:53:30.148212 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/714812/extract-nfsrootfs-3bsbcc_n
314 06:53:30.148653 - {NFS_SERVER_IP}: 192.168.6.2
315 06:53:30.149084 - {PRESEED_CONFIG}: None
316 06:53:30.149517 - {PRESEED_LOCAL}: None
317 06:53:30.149948 - {RAMDISK_ADDR}: 0x08000000
318 06:53:30.150377 - {RAMDISK}: 714812/tftp-deploy-5blp6lma/ramdisk/ramdisk.cpio.gz.uboot
319 06:53:30.150808 - {ROOT_PART}: None
320 06:53:30.151237 - {ROOT}: None
321 06:53:30.151662 - {SERVER_IP}: 192.168.6.2
322 06:53:30.152146 - {TEE_ADDR}: 0x83000000
323 06:53:30.152590 - {TEE}: None
324 06:53:30.153021 Parsed boot commands:
325 06:53:30.153440 - setenv autoload no
326 06:53:30.153866 - setenv initrd_high 0xffffffff
327 06:53:30.154289 - setenv fdt_high 0xffffffff
328 06:53:30.154709 - dhcp
329 06:53:30.155133 - setenv serverip 192.168.6.2
330 06:53:30.155558 - tftpboot 0x01080000 714812/tftp-deploy-5blp6lma/kernel/uImage
331 06:53:30.156023 - tftpboot 0x08000000 714812/tftp-deploy-5blp6lma/ramdisk/ramdisk.cpio.gz.uboot
332 06:53:30.156462 - tftpboot 0x01070000 714812/tftp-deploy-5blp6lma/dtb/meson-g12b-a311d-libretech-cc.dtb
333 06:53:30.156894 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/714812/extract-nfsrootfs-3bsbcc_n,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 06:53:30.157338 - bootm 0x01080000 0x08000000 0x01070000
335 06:53:30.157889 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 06:53:30.159526 start: 2.3 connect-device (timeout 00:05:00) [common]
338 06:53:30.160006 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 06:53:30.176754 Setting prompt string to ['lava-test: # ']
340 06:53:30.178400 end: 2.3 connect-device (duration 00:00:00) [common]
341 06:53:30.179067 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 06:53:30.179672 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 06:53:30.180335 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 06:53:30.181560 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 06:53:30.219024 >> OK - accepted request
346 06:53:30.221194 Returned 0 in 0 seconds
347 06:53:30.322348 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 06:53:30.324126 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 06:53:30.324721 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 06:53:30.325275 Setting prompt string to ['Hit any key to stop autoboot']
352 06:53:30.325771 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 06:53:30.327455 Trying 192.168.56.21...
354 06:53:30.327969 Connected to conserv1.
355 06:53:30.328440 Escape character is '^]'.
356 06:53:30.328893
357 06:53:30.329349 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 06:53:30.329805
359 06:53:42.467343 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 06:53:42.467768 bl2_stage_init 0x01
361 06:53:42.468028 bl2_stage_init 0x81
362 06:53:42.472659 hw id: 0x0000 - pwm id 0x01
363 06:53:42.472987 bl2_stage_init 0xc1
364 06:53:42.473209 bl2_stage_init 0x02
365 06:53:42.473417
366 06:53:42.478405 L0:00000000
367 06:53:42.478751 L1:20000703
368 06:53:42.478999 L2:00008067
369 06:53:42.479233 L3:14000000
370 06:53:42.481296 B2:00402000
371 06:53:42.481700 B1:e0f83180
372 06:53:42.482064
373 06:53:42.482413 TE: 58124
374 06:53:42.482734
375 06:53:42.492365 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 06:53:42.492847
377 06:53:42.493216 Board ID = 1
378 06:53:42.493569 Set A53 clk to 24M
379 06:53:42.493897 Set A73 clk to 24M
380 06:53:42.498011 Set clk81 to 24M
381 06:53:42.498461 A53 clk: 1200 MHz
382 06:53:42.498831 A73 clk: 1200 MHz
383 06:53:42.501498 CLK81: 166.6M
384 06:53:42.501822 smccc: 00012a92
385 06:53:42.507280 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 06:53:42.512589 board id: 1
387 06:53:42.517944 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 06:53:42.528633 fw parse done
389 06:53:42.534412 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 06:53:42.577178 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 06:53:42.588094 PIEI prepare done
392 06:53:42.588492 fastboot data load
393 06:53:42.588707 fastboot data verify
394 06:53:42.593547 verify result: 266
395 06:53:42.599484 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 06:53:42.599862 LPDDR4 probe
397 06:53:42.600116 ddr clk to 1584MHz
398 06:53:42.607220 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 06:53:42.644404
400 06:53:42.644783 dmc_version 0001
401 06:53:42.651070 Check phy result
402 06:53:42.656960 INFO : End of CA training
403 06:53:42.657295 INFO : End of initialization
404 06:53:42.662488 INFO : Training has run successfully!
405 06:53:42.662818 Check phy result
406 06:53:42.668128 INFO : End of initialization
407 06:53:42.668455 INFO : End of read enable training
408 06:53:42.671351 INFO : End of fine write leveling
409 06:53:42.676947 INFO : End of Write leveling coarse delay
410 06:53:42.682529 INFO : Training has run successfully!
411 06:53:42.682853 Check phy result
412 06:53:42.683079 INFO : End of initialization
413 06:53:42.688214 INFO : End of read dq deskew training
414 06:53:42.691517 INFO : End of MPR read delay center optimization
415 06:53:42.697104 INFO : End of write delay center optimization
416 06:53:42.702665 INFO : End of read delay center optimization
417 06:53:42.702985 INFO : End of max read latency training
418 06:53:42.708394 INFO : Training has run successfully!
419 06:53:42.708745 1D training succeed
420 06:53:42.716465 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 06:53:42.764123 Check phy result
422 06:53:42.764511 INFO : End of initialization
423 06:53:42.785818 INFO : End of 2D read delay Voltage center optimization
424 06:53:42.806116 INFO : End of 2D read delay Voltage center optimization
425 06:53:42.858268 INFO : End of 2D write delay Voltage center optimization
426 06:53:42.907609 INFO : End of 2D write delay Voltage center optimization
427 06:53:42.913104 INFO : Training has run successfully!
428 06:53:42.913446
429 06:53:42.913674 channel==0
430 06:53:42.918803 RxClkDly_Margin_A0==88 ps 9
431 06:53:42.919312 TxDqDly_Margin_A0==98 ps 10
432 06:53:42.924333 RxClkDly_Margin_A1==88 ps 9
433 06:53:42.924803 TxDqDly_Margin_A1==98 ps 10
434 06:53:42.925182 TrainedVREFDQ_A0==74
435 06:53:42.929854 TrainedVREFDQ_A1==74
436 06:53:42.930354 VrefDac_Margin_A0==25
437 06:53:42.930733 DeviceVref_Margin_A0==40
438 06:53:42.935528 VrefDac_Margin_A1==24
439 06:53:42.935879 DeviceVref_Margin_A1==40
440 06:53:42.936167
441 06:53:42.936419
442 06:53:42.941084 channel==1
443 06:53:42.941419 RxClkDly_Margin_A0==88 ps 9
444 06:53:42.941673 TxDqDly_Margin_A0==88 ps 9
445 06:53:42.947037 RxClkDly_Margin_A1==98 ps 10
446 06:53:42.947441 TxDqDly_Margin_A1==98 ps 10
447 06:53:42.952328 TrainedVREFDQ_A0==76
448 06:53:42.952706 TrainedVREFDQ_A1==77
449 06:53:42.952975 VrefDac_Margin_A0==22
450 06:53:42.957801 DeviceVref_Margin_A0==38
451 06:53:42.958152 VrefDac_Margin_A1==22
452 06:53:42.963403 DeviceVref_Margin_A1==37
453 06:53:42.963767
454 06:53:42.964056 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 06:53:42.964316
456 06:53:42.997087 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 06:53:42.997733 2D training succeed
458 06:53:43.002738 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 06:53:43.008338 auto size-- 65535DDR cs0 size: 2048MB
460 06:53:43.008864 DDR cs1 size: 2048MB
461 06:53:43.013924 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 06:53:43.014435 cs0 DataBus test pass
463 06:53:43.019494 cs1 DataBus test pass
464 06:53:43.020021 cs0 AddrBus test pass
465 06:53:43.020464 cs1 AddrBus test pass
466 06:53:43.020862
467 06:53:43.025066 100bdlr_step_size ps== 420
468 06:53:43.025573 result report
469 06:53:43.030664 boot times 0Enable ddr reg access
470 06:53:43.036127 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 06:53:43.049574 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 06:53:43.623042 0.0;M3 CHK:0;cm4_sp_mode 0
473 06:53:43.623643 MVN_1=0x00000000
474 06:53:43.628549 MVN_2=0x00000000
475 06:53:43.634352 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 06:53:43.634861 OPS=0x10
477 06:53:43.635238 ring efuse init
478 06:53:43.635493 chipver efuse init
479 06:53:43.639925 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 06:53:43.645539 [0.018961 Inits done]
481 06:53:43.645993 secure task start!
482 06:53:43.646379 high task start!
483 06:53:43.650110 low task start!
484 06:53:43.650440 run into bl31
485 06:53:43.656841 NOTICE: BL31: v1.3(release):4fc40b1
486 06:53:43.664651 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 06:53:43.665181 NOTICE: BL31: G12A normal boot!
488 06:53:43.690052 NOTICE: BL31: BL33 decompress pass
489 06:53:43.695726 ERROR: Error initializing runtime service opteed_fast
490 06:53:44.928685
491 06:53:44.929266
492 06:53:44.937026 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 06:53:44.937501
494 06:53:44.937900 Model: Libre Computer AML-A311D-CC Alta
495 06:53:45.145546 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 06:53:45.168886 DRAM: 2 GiB (effective 3.8 GiB)
497 06:53:45.311969 Core: 408 devices, 31 uclasses, devicetree: separate
498 06:53:45.317687 WDT: Not starting watchdog@f0d0
499 06:53:45.349981 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 06:53:45.362439 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 06:53:45.367369 ** Bad device specification mmc 0 **
502 06:53:45.377662 Card did not respond to voltage select! : -110
503 06:53:45.385381 ** Bad device specification mmc 0 **
504 06:53:45.385662 Couldn't find partition mmc 0
505 06:53:45.393797 Card did not respond to voltage select! : -110
506 06:53:45.399312 ** Bad device specification mmc 0 **
507 06:53:45.399782 Couldn't find partition mmc 0
508 06:53:45.404373 Error: could not access storage.
509 06:53:46.667376 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 06:53:46.667962 bl2_stage_init 0x01
511 06:53:46.668411 bl2_stage_init 0x81
512 06:53:46.672992 hw id: 0x0000 - pwm id 0x01
513 06:53:46.673459 bl2_stage_init 0xc1
514 06:53:46.673857 bl2_stage_init 0x02
515 06:53:46.674247
516 06:53:46.678659 L0:00000000
517 06:53:46.679115 L1:20000703
518 06:53:46.679505 L2:00008067
519 06:53:46.679889 L3:14000000
520 06:53:46.684180 B2:00402000
521 06:53:46.684645 B1:e0f83180
522 06:53:46.685037
523 06:53:46.685427 TE: 58124
524 06:53:46.685813
525 06:53:46.689775 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 06:53:46.690239
527 06:53:46.690632 Board ID = 1
528 06:53:46.695354 Set A53 clk to 24M
529 06:53:46.695819 Set A73 clk to 24M
530 06:53:46.696248 Set clk81 to 24M
531 06:53:46.700992 A53 clk: 1200 MHz
532 06:53:46.701481 A73 clk: 1200 MHz
533 06:53:46.701873 CLK81: 166.6M
534 06:53:46.702259 smccc: 00012a92
535 06:53:46.706692 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 06:53:46.712183 board id: 1
537 06:53:46.718050 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 06:53:46.728749 fw parse done
539 06:53:46.734789 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 06:53:46.777282 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 06:53:46.788237 PIEI prepare done
542 06:53:46.788720 fastboot data load
543 06:53:46.789125 fastboot data verify
544 06:53:46.793951 verify result: 266
545 06:53:46.799501 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 06:53:46.800021 LPDDR4 probe
547 06:53:46.800422 ddr clk to 1584MHz
548 06:53:46.807430 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 06:53:46.844797
550 06:53:46.845312 dmc_version 0001
551 06:53:46.851403 Check phy result
552 06:53:46.857282 INFO : End of CA training
553 06:53:46.857752 INFO : End of initialization
554 06:53:46.862901 INFO : Training has run successfully!
555 06:53:46.863365 Check phy result
556 06:53:46.868475 INFO : End of initialization
557 06:53:46.868943 INFO : End of read enable training
558 06:53:46.871813 INFO : End of fine write leveling
559 06:53:46.877299 INFO : End of Write leveling coarse delay
560 06:53:46.882938 INFO : Training has run successfully!
561 06:53:46.883436 Check phy result
562 06:53:46.883867 INFO : End of initialization
563 06:53:46.888527 INFO : End of read dq deskew training
564 06:53:46.894118 INFO : End of MPR read delay center optimization
565 06:53:46.894588 INFO : End of write delay center optimization
566 06:53:46.899782 INFO : End of read delay center optimization
567 06:53:46.905324 INFO : End of max read latency training
568 06:53:46.905794 INFO : Training has run successfully!
569 06:53:46.910923 1D training succeed
570 06:53:46.916872 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 06:53:46.964446 Check phy result
572 06:53:46.964972 INFO : End of initialization
573 06:53:46.987054 INFO : End of 2D read delay Voltage center optimization
574 06:53:47.007300 INFO : End of 2D read delay Voltage center optimization
575 06:53:47.059328 INFO : End of 2D write delay Voltage center optimization
576 06:53:47.108746 INFO : End of 2D write delay Voltage center optimization
577 06:53:47.114269 INFO : Training has run successfully!
578 06:53:47.114737
579 06:53:47.115137 channel==0
580 06:53:47.119883 RxClkDly_Margin_A0==88 ps 9
581 06:53:47.120393 TxDqDly_Margin_A0==98 ps 10
582 06:53:47.125490 RxClkDly_Margin_A1==88 ps 9
583 06:53:47.125974 TxDqDly_Margin_A1==98 ps 10
584 06:53:47.126370 TrainedVREFDQ_A0==74
585 06:53:47.131020 TrainedVREFDQ_A1==75
586 06:53:47.131492 VrefDac_Margin_A0==25
587 06:53:47.131886 DeviceVref_Margin_A0==40
588 06:53:47.136685 VrefDac_Margin_A1==24
589 06:53:47.137150 DeviceVref_Margin_A1==39
590 06:53:47.137541
591 06:53:47.137927
592 06:53:47.142249 channel==1
593 06:53:47.142714 RxClkDly_Margin_A0==98 ps 10
594 06:53:47.143104 TxDqDly_Margin_A0==98 ps 10
595 06:53:47.147871 RxClkDly_Margin_A1==88 ps 9
596 06:53:47.148371 TxDqDly_Margin_A1==98 ps 10
597 06:53:47.153454 TrainedVREFDQ_A0==77
598 06:53:47.153925 TrainedVREFDQ_A1==78
599 06:53:47.154317 VrefDac_Margin_A0==22
600 06:53:47.159047 DeviceVref_Margin_A0==37
601 06:53:47.159506 VrefDac_Margin_A1==24
602 06:53:47.164689 DeviceVref_Margin_A1==36
603 06:53:47.165154
604 06:53:47.165547 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 06:53:47.170240
606 06:53:47.198195 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000017 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 06:53:47.198759 2D training succeed
608 06:53:47.203920 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 06:53:47.209448 auto size-- 65535DDR cs0 size: 2048MB
610 06:53:47.209928 DDR cs1 size: 2048MB
611 06:53:47.215006 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 06:53:47.215473 cs0 DataBus test pass
613 06:53:47.220680 cs1 DataBus test pass
614 06:53:47.221174 cs0 AddrBus test pass
615 06:53:47.221567 cs1 AddrBus test pass
616 06:53:47.221956
617 06:53:47.226227 100bdlr_step_size ps== 420
618 06:53:47.226708 result report
619 06:53:47.231876 boot times 0Enable ddr reg access
620 06:53:47.237245 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 06:53:47.250716 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 06:53:47.824539 0.0;M3 CHK:0;cm4_sp_mode 0
623 06:53:47.825037 MVN_1=0x00000000
624 06:53:47.829918 MVN_2=0x00000000
625 06:53:47.836101 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 06:53:47.836524 OPS=0x10
627 06:53:47.836747 ring efuse init
628 06:53:47.836950 chipver efuse init
629 06:53:47.841232 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 06:53:47.846787 [0.018960 Inits done]
631 06:53:47.847098 secure task start!
632 06:53:47.847305 high task start!
633 06:53:47.851470 low task start!
634 06:53:47.851752 run into bl31
635 06:53:47.858020 NOTICE: BL31: v1.3(release):4fc40b1
636 06:53:47.865846 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 06:53:47.866169 NOTICE: BL31: G12A normal boot!
638 06:53:47.891805 NOTICE: BL31: BL33 decompress pass
639 06:53:47.897447 ERROR: Error initializing runtime service opteed_fast
640 06:53:49.130509
641 06:53:49.130913
642 06:53:49.138833 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 06:53:49.139289
644 06:53:49.139611 Model: Libre Computer AML-A311D-CC Alta
645 06:53:49.347372 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 06:53:49.370778 DRAM: 2 GiB (effective 3.8 GiB)
647 06:53:49.513720 Core: 408 devices, 31 uclasses, devicetree: separate
648 06:53:49.519088 WDT: Not starting watchdog@f0d0
649 06:53:49.551938 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 06:53:49.564324 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 06:53:49.568738 ** Bad device specification mmc 0 **
652 06:53:49.579655 Card did not respond to voltage select! : -110
653 06:53:49.587312 ** Bad device specification mmc 0 **
654 06:53:49.587949 Couldn't find partition mmc 0
655 06:53:49.595629 Card did not respond to voltage select! : -110
656 06:53:49.601126 ** Bad device specification mmc 0 **
657 06:53:49.601679 Couldn't find partition mmc 0
658 06:53:49.606230 Error: could not access storage.
659 06:53:49.948720 Net: eth0: ethernet@ff3f0000
660 06:53:49.949156 starting USB...
661 06:53:50.201550 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 06:53:50.201979 Starting the controller
663 06:53:50.208124 USB XHCI 1.10
664 06:53:51.917656 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 06:53:51.918080 bl2_stage_init 0x01
666 06:53:51.918304 bl2_stage_init 0x81
667 06:53:51.923291 hw id: 0x0000 - pwm id 0x01
668 06:53:51.923676 bl2_stage_init 0xc1
669 06:53:51.924026 bl2_stage_init 0x02
670 06:53:51.924367
671 06:53:51.928868 L0:00000000
672 06:53:51.929147 L1:20000703
673 06:53:51.929371 L2:00008067
674 06:53:51.929576 L3:14000000
675 06:53:51.931679 B2:00402000
676 06:53:51.932072 B1:e0f83180
677 06:53:51.932407
678 06:53:51.932733 TE: 58124
679 06:53:51.933052
680 06:53:51.942845 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 06:53:51.943138
682 06:53:51.943351 Board ID = 1
683 06:53:51.943552 Set A53 clk to 24M
684 06:53:51.943753 Set A73 clk to 24M
685 06:53:51.948469 Set clk81 to 24M
686 06:53:51.948858 A53 clk: 1200 MHz
687 06:53:51.949192 A73 clk: 1200 MHz
688 06:53:51.954066 CLK81: 166.6M
689 06:53:51.954469 smccc: 00012a92
690 06:53:51.959579 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 06:53:51.959968 board id: 1
692 06:53:51.965342 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 06:53:51.979187 fw parse done
694 06:53:51.984460 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 06:53:52.026892 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 06:53:52.038358 PIEI prepare done
697 06:53:52.038646 fastboot data load
698 06:53:52.038862 fastboot data verify
699 06:53:52.044082 verify result: 266
700 06:53:52.049637 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 06:53:52.050033 LPDDR4 probe
702 06:53:52.050372 ddr clk to 1584MHz
703 06:53:52.056730 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 06:53:52.094081
705 06:53:52.094445 dmc_version 0001
706 06:53:52.100810 Check phy result
707 06:53:52.107371 INFO : End of CA training
708 06:53:52.107754 INFO : End of initialization
709 06:53:52.112988 INFO : Training has run successfully!
710 06:53:52.113246 Check phy result
711 06:53:52.118546 INFO : End of initialization
712 06:53:52.118925 INFO : End of read enable training
713 06:53:52.124217 INFO : End of fine write leveling
714 06:53:52.129779 INFO : End of Write leveling coarse delay
715 06:53:52.130036 INFO : Training has run successfully!
716 06:53:52.130245 Check phy result
717 06:53:52.135398 INFO : End of initialization
718 06:53:52.135653 INFO : End of read dq deskew training
719 06:53:52.141000 INFO : End of MPR read delay center optimization
720 06:53:52.146580 INFO : End of write delay center optimization
721 06:53:52.152171 INFO : End of read delay center optimization
722 06:53:52.152430 INFO : End of max read latency training
723 06:53:52.157767 INFO : Training has run successfully!
724 06:53:52.158157 1D training succeed
725 06:53:52.166541 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 06:53:52.213549 Check phy result
727 06:53:52.213828 INFO : End of initialization
728 06:53:52.236155 INFO : End of 2D read delay Voltage center optimization
729 06:53:52.256428 INFO : End of 2D read delay Voltage center optimization
730 06:53:52.307556 INFO : End of 2D write delay Voltage center optimization
731 06:53:52.357501 INFO : End of 2D write delay Voltage center optimization
732 06:53:52.363027 INFO : Training has run successfully!
733 06:53:52.363301
734 06:53:52.363516 channel==0
735 06:53:52.368615 RxClkDly_Margin_A0==88 ps 9
736 06:53:52.368995 TxDqDly_Margin_A0==98 ps 10
737 06:53:52.374273 RxClkDly_Margin_A1==88 ps 9
738 06:53:52.374650 TxDqDly_Margin_A1==98 ps 10
739 06:53:52.374990 TrainedVREFDQ_A0==74
740 06:53:52.379793 TrainedVREFDQ_A1==74
741 06:53:52.380064 VrefDac_Margin_A0==25
742 06:53:52.380276 DeviceVref_Margin_A0==40
743 06:53:52.385427 VrefDac_Margin_A1==25
744 06:53:52.385802 DeviceVref_Margin_A1==40
745 06:53:52.386135
746 06:53:52.386463
747 06:53:52.390998 channel==1
748 06:53:52.391261 RxClkDly_Margin_A0==98 ps 10
749 06:53:52.391470 TxDqDly_Margin_A0==88 ps 9
750 06:53:52.396594 RxClkDly_Margin_A1==88 ps 9
751 06:53:52.396968 TxDqDly_Margin_A1==88 ps 9
752 06:53:52.402200 TrainedVREFDQ_A0==77
753 06:53:52.402579 TrainedVREFDQ_A1==77
754 06:53:52.402910 VrefDac_Margin_A0==22
755 06:53:52.407806 DeviceVref_Margin_A0==37
756 06:53:52.408080 VrefDac_Margin_A1==24
757 06:53:52.413402 DeviceVref_Margin_A1==37
758 06:53:52.413659
759 06:53:52.413870 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 06:53:52.414073
761 06:53:52.446984 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 06:53:52.447472 2D training succeed
763 06:53:52.452599 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 06:53:52.458269 auto size-- 65535DDR cs0 size: 2048MB
765 06:53:52.458652 DDR cs1 size: 2048MB
766 06:53:52.463807 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 06:53:52.464115 cs0 DataBus test pass
768 06:53:52.469466 cs1 DataBus test pass
769 06:53:52.469927 cs0 AddrBus test pass
770 06:53:52.470340 cs1 AddrBus test pass
771 06:53:52.470744
772 06:53:52.475053 100bdlr_step_size ps== 420
773 06:53:52.475493 result report
774 06:53:52.480632 boot times 0Enable ddr reg access
775 06:53:52.485293 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 06:53:52.499296 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 06:53:53.071358 0.0;M3 CHK:0;cm4_sp_mode 0
778 06:53:53.071910 MVN_1=0x00000000
779 06:53:53.076868 MVN_2=0x00000000
780 06:53:53.082697 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 06:53:53.083178 OPS=0x10
782 06:53:53.083574 ring efuse init
783 06:53:53.083959 chipver efuse init
784 06:53:53.088262 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 06:53:53.093860 [0.018961 Inits done]
786 06:53:53.094271 secure task start!
787 06:53:53.094659 high task start!
788 06:53:53.098338 low task start!
789 06:53:53.098752 run into bl31
790 06:53:53.105034 NOTICE: BL31: v1.3(release):4fc40b1
791 06:53:53.112811 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 06:53:53.113228 NOTICE: BL31: G12A normal boot!
793 06:53:53.138221 NOTICE: BL31: BL33 decompress pass
794 06:53:53.143114 ERROR: Error initializing runtime service opteed_fast
795 06:53:54.376922
796 06:53:54.377492
797 06:53:54.384404 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 06:53:54.384877
799 06:53:54.385287 Model: Libre Computer AML-A311D-CC Alta
800 06:53:54.593560 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 06:53:54.616964 DRAM: 2 GiB (effective 3.8 GiB)
802 06:53:54.759886 Core: 408 devices, 31 uclasses, devicetree: separate
803 06:53:54.765798 WDT: Not starting watchdog@f0d0
804 06:53:54.798012 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 06:53:54.810499 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 06:53:54.815462 ** Bad device specification mmc 0 **
807 06:53:54.825859 Card did not respond to voltage select! : -110
808 06:53:54.832654 ** Bad device specification mmc 0 **
809 06:53:54.833084 Couldn't find partition mmc 0
810 06:53:54.841801 Card did not respond to voltage select! : -110
811 06:53:54.847308 ** Bad device specification mmc 0 **
812 06:53:54.847733 Couldn't find partition mmc 0
813 06:53:54.852360 Error: could not access storage.
814 06:53:55.195952 Net: eth0: ethernet@ff3f0000
815 06:53:55.196548 starting USB...
816 06:53:55.447677 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 06:53:55.448195 Starting the controller
818 06:53:55.454642 USB XHCI 1.10
819 06:53:57.617759 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 06:53:57.618353 bl2_stage_init 0x01
821 06:53:57.618769 bl2_stage_init 0x81
822 06:53:57.623488 hw id: 0x0000 - pwm id 0x01
823 06:53:57.623929 bl2_stage_init 0xc1
824 06:53:57.624384 bl2_stage_init 0x02
825 06:53:57.624782
826 06:53:57.628973 L0:00000000
827 06:53:57.629400 L1:20000703
828 06:53:57.629793 L2:00008067
829 06:53:57.630186 L3:14000000
830 06:53:57.634667 B2:00402000
831 06:53:57.635094 B1:e0f83180
832 06:53:57.635492
833 06:53:57.635889 TE: 58167
834 06:53:57.636326
835 06:53:57.640336 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 06:53:57.640767
837 06:53:57.641163 Board ID = 1
838 06:53:57.645668 Set A53 clk to 24M
839 06:53:57.646092 Set A73 clk to 24M
840 06:53:57.646489 Set clk81 to 24M
841 06:53:57.651332 A53 clk: 1200 MHz
842 06:53:57.651753 A73 clk: 1200 MHz
843 06:53:57.652181 CLK81: 166.6M
844 06:53:57.652577 smccc: 00012abe
845 06:53:57.656962 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 06:53:57.662546 board id: 1
847 06:53:57.668513 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 06:53:57.678975 fw parse done
849 06:53:57.684892 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 06:53:57.727540 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 06:53:57.738461 PIEI prepare done
852 06:53:57.738921 fastboot data load
853 06:53:57.739327 fastboot data verify
854 06:53:57.744214 verify result: 266
855 06:53:57.749731 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 06:53:57.750181 LPDDR4 probe
857 06:53:57.750585 ddr clk to 1584MHz
858 06:53:57.757645 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 06:53:57.794955
860 06:53:57.795435 dmc_version 0001
861 06:53:57.801593 Check phy result
862 06:53:57.807486 INFO : End of CA training
863 06:53:57.807925 INFO : End of initialization
864 06:53:57.813194 INFO : Training has run successfully!
865 06:53:57.813630 Check phy result
866 06:53:57.818707 INFO : End of initialization
867 06:53:57.819151 INFO : End of read enable training
868 06:53:57.824294 INFO : End of fine write leveling
869 06:53:57.829911 INFO : End of Write leveling coarse delay
870 06:53:57.830352 INFO : Training has run successfully!
871 06:53:57.830756 Check phy result
872 06:53:57.835485 INFO : End of initialization
873 06:53:57.835929 INFO : End of read dq deskew training
874 06:53:57.841232 INFO : End of MPR read delay center optimization
875 06:53:57.846678 INFO : End of write delay center optimization
876 06:53:57.852285 INFO : End of read delay center optimization
877 06:53:57.852725 INFO : End of max read latency training
878 06:53:57.857899 INFO : Training has run successfully!
879 06:53:57.858344 1D training succeed
880 06:53:57.866221 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 06:53:57.914675 Check phy result
882 06:53:57.915142 INFO : End of initialization
883 06:53:57.936274 INFO : End of 2D read delay Voltage center optimization
884 06:53:57.957325 INFO : End of 2D read delay Voltage center optimization
885 06:53:58.009101 INFO : End of 2D write delay Voltage center optimization
886 06:53:58.058458 INFO : End of 2D write delay Voltage center optimization
887 06:53:58.063930 INFO : Training has run successfully!
888 06:53:58.064401
889 06:53:58.064807 channel==0
890 06:53:58.069538 RxClkDly_Margin_A0==88 ps 9
891 06:53:58.069970 TxDqDly_Margin_A0==98 ps 10
892 06:53:58.075265 RxClkDly_Margin_A1==88 ps 9
893 06:53:58.075693 TxDqDly_Margin_A1==98 ps 10
894 06:53:58.076155 TrainedVREFDQ_A0==74
895 06:53:58.080788 TrainedVREFDQ_A1==75
896 06:53:58.081262 VrefDac_Margin_A0==24
897 06:53:58.081665 DeviceVref_Margin_A0==40
898 06:53:58.086365 VrefDac_Margin_A1==25
899 06:53:58.086829 DeviceVref_Margin_A1==39
900 06:53:58.087216
901 06:53:58.087598
902 06:53:58.091925 channel==1
903 06:53:58.092369 RxClkDly_Margin_A0==98 ps 10
904 06:53:58.092756 TxDqDly_Margin_A0==98 ps 10
905 06:53:58.097545 RxClkDly_Margin_A1==98 ps 10
906 06:53:58.097958 TxDqDly_Margin_A1==88 ps 9
907 06:53:58.103237 TrainedVREFDQ_A0==77
908 06:53:58.103669 TrainedVREFDQ_A1==77
909 06:53:58.104085 VrefDac_Margin_A0==22
910 06:53:58.108774 DeviceVref_Margin_A0==37
911 06:53:58.109191 VrefDac_Margin_A1==22
912 06:53:58.114317 DeviceVref_Margin_A1==37
913 06:53:58.114732
914 06:53:58.115117 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 06:53:58.119904
916 06:53:58.147934 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 06:53:58.148450 2D training succeed
918 06:53:58.153529 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 06:53:58.159261 auto size-- 65535DDR cs0 size: 2048MB
920 06:53:58.159674 DDR cs1 size: 2048MB
921 06:53:58.164751 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 06:53:58.165174 cs0 DataBus test pass
923 06:53:58.170318 cs1 DataBus test pass
924 06:53:58.170743 cs0 AddrBus test pass
925 06:53:58.171130 cs1 AddrBus test pass
926 06:53:58.171507
927 06:53:58.175936 100bdlr_step_size ps== 420
928 06:53:58.176410 result report
929 06:53:58.181557 boot times 0Enable ddr reg access
930 06:53:58.186960 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 06:53:58.200550 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 06:53:58.772510 0.0;M3 CHK:0;cm4_sp_mode 0
933 06:53:58.773117 MVN_1=0x00000000
934 06:53:58.777905 MVN_2=0x00000000
935 06:53:58.783666 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 06:53:58.784143 OPS=0x10
937 06:53:58.784553 ring efuse init
938 06:53:58.784945 chipver efuse init
939 06:53:58.789296 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 06:53:58.794885 [0.018961 Inits done]
941 06:53:58.795310 secure task start!
942 06:53:58.795709 high task start!
943 06:53:58.799459 low task start!
944 06:53:58.799880 run into bl31
945 06:53:58.806140 NOTICE: BL31: v1.3(release):4fc40b1
946 06:53:58.813879 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 06:53:58.814311 NOTICE: BL31: G12A normal boot!
948 06:53:58.839349 NOTICE: BL31: BL33 decompress pass
949 06:53:58.844894 ERROR: Error initializing runtime service opteed_fast
950 06:54:00.077855
951 06:54:00.078461
952 06:54:00.086210 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 06:54:00.086730
954 06:54:00.087166 Model: Libre Computer AML-A311D-CC Alta
955 06:54:00.293891 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 06:54:00.317988 DRAM: 2 GiB (effective 3.8 GiB)
957 06:54:00.461004 Core: 408 devices, 31 uclasses, devicetree: separate
958 06:54:00.466901 WDT: Not starting watchdog@f0d0
959 06:54:00.499112 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 06:54:00.511531 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 06:54:00.516602 ** Bad device specification mmc 0 **
962 06:54:00.526855 Card did not respond to voltage select! : -110
963 06:54:00.534597 ** Bad device specification mmc 0 **
964 06:54:00.535094 Couldn't find partition mmc 0
965 06:54:00.542837 Card did not respond to voltage select! : -110
966 06:54:00.548409 ** Bad device specification mmc 0 **
967 06:54:00.548873 Couldn't find partition mmc 0
968 06:54:00.553482 Error: could not access storage.
969 06:54:00.896954 Net: eth0: ethernet@ff3f0000
970 06:54:00.897525 starting USB...
971 06:54:01.148806 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 06:54:01.149384 Starting the controller
973 06:54:01.155668 USB XHCI 1.10
974 06:54:03.017873 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
975 06:54:03.018337 bl2_stage_init 0x81
976 06:54:03.023336 hw id: 0x0000 - pwm id 0x01
977 06:54:03.023649 bl2_stage_init 0xc1
978 06:54:03.023885 bl2_stage_init 0x02
979 06:54:03.024164
980 06:54:03.029049 L0:00000000
981 06:54:03.029346 L1:20000703
982 06:54:03.029579 L2:00008067
983 06:54:03.029804 L3:14000000
984 06:54:03.030046 B2:00402000
985 06:54:03.034549 B1:e0f83180
986 06:54:03.034960
987 06:54:03.035232 TE: 58150
988 06:54:03.035468
989 06:54:03.040102 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 06:54:03.040515
991 06:54:03.040889 Board ID = 1
992 06:54:03.045648 Set A53 clk to 24M
993 06:54:03.046063 Set A73 clk to 24M
994 06:54:03.046326 Set clk81 to 24M
995 06:54:03.051268 A53 clk: 1200 MHz
996 06:54:03.051688 A73 clk: 1200 MHz
997 06:54:03.052101 CLK81: 166.6M
998 06:54:03.052365 smccc: 00012aac
999 06:54:03.056899 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 06:54:03.062510 board id: 1
1001 06:54:03.068282 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 06:54:03.078941 fw parse done
1003 06:54:03.085736 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 06:54:03.127673 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 06:54:03.138495 PIEI prepare done
1006 06:54:03.138993 fastboot data load
1007 06:54:03.139391 fastboot data verify
1008 06:54:03.144203 verify result: 266
1009 06:54:03.149714 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 06:54:03.150223 LPDDR4 probe
1011 06:54:03.150620 ddr clk to 1584MHz
1012 06:54:03.157689 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 06:54:03.195038
1014 06:54:03.195599 dmc_version 0001
1015 06:54:03.201744 Check phy result
1016 06:54:03.207581 INFO : End of CA training
1017 06:54:03.208129 INFO : End of initialization
1018 06:54:03.213185 INFO : Training has run successfully!
1019 06:54:03.213715 Check phy result
1020 06:54:03.218735 INFO : End of initialization
1021 06:54:03.219251 INFO : End of read enable training
1022 06:54:03.222124 INFO : End of fine write leveling
1023 06:54:03.227741 INFO : End of Write leveling coarse delay
1024 06:54:03.233316 INFO : Training has run successfully!
1025 06:54:03.233884 Check phy result
1026 06:54:03.234303 INFO : End of initialization
1027 06:54:03.238886 INFO : End of read dq deskew training
1028 06:54:03.244497 INFO : End of MPR read delay center optimization
1029 06:54:03.245049 INFO : End of write delay center optimization
1030 06:54:03.250139 INFO : End of read delay center optimization
1031 06:54:03.255767 INFO : End of max read latency training
1032 06:54:03.256358 INFO : Training has run successfully!
1033 06:54:03.261302 1D training succeed
1034 06:54:03.267241 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 06:54:03.314820 Check phy result
1036 06:54:03.315410 INFO : End of initialization
1037 06:54:03.336567 INFO : End of 2D read delay Voltage center optimization
1038 06:54:03.356791 INFO : End of 2D read delay Voltage center optimization
1039 06:54:03.408818 INFO : End of 2D write delay Voltage center optimization
1040 06:54:03.458348 INFO : End of 2D write delay Voltage center optimization
1041 06:54:03.463718 INFO : Training has run successfully!
1042 06:54:03.464267
1043 06:54:03.464689 channel==0
1044 06:54:03.469378 RxClkDly_Margin_A0==88 ps 9
1045 06:54:03.469878 TxDqDly_Margin_A0==98 ps 10
1046 06:54:03.474859 RxClkDly_Margin_A1==88 ps 9
1047 06:54:03.475343 TxDqDly_Margin_A1==98 ps 10
1048 06:54:03.475757 TrainedVREFDQ_A0==74
1049 06:54:03.480586 TrainedVREFDQ_A1==74
1050 06:54:03.481087 VrefDac_Margin_A0==25
1051 06:54:03.481501 DeviceVref_Margin_A0==40
1052 06:54:03.486290 VrefDac_Margin_A1==25
1053 06:54:03.486779 DeviceVref_Margin_A1==40
1054 06:54:03.487184
1055 06:54:03.487582
1056 06:54:03.491701 channel==1
1057 06:54:03.492227 RxClkDly_Margin_A0==88 ps 9
1058 06:54:03.492641 TxDqDly_Margin_A0==88 ps 9
1059 06:54:03.497374 RxClkDly_Margin_A1==98 ps 10
1060 06:54:03.497857 TxDqDly_Margin_A1==88 ps 9
1061 06:54:03.502873 TrainedVREFDQ_A0==76
1062 06:54:03.503356 TrainedVREFDQ_A1==77
1063 06:54:03.503766 VrefDac_Margin_A0==22
1064 06:54:03.508508 DeviceVref_Margin_A0==38
1065 06:54:03.508994 VrefDac_Margin_A1==24
1066 06:54:03.514282 DeviceVref_Margin_A1==37
1067 06:54:03.514769
1068 06:54:03.515177 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 06:54:03.515574
1070 06:54:03.547694 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1071 06:54:03.548254 2D training succeed
1072 06:54:03.553395 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 06:54:03.558784 auto size-- 65535DDR cs0 size: 2048MB
1074 06:54:03.559259 DDR cs1 size: 2048MB
1075 06:54:03.564434 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 06:54:03.564957 cs0 DataBus test pass
1077 06:54:03.570101 cs1 DataBus test pass
1078 06:54:03.570621 cs0 AddrBus test pass
1079 06:54:03.571029 cs1 AddrBus test pass
1080 06:54:03.571422
1081 06:54:03.575653 100bdlr_step_size ps== 420
1082 06:54:03.576230 result report
1083 06:54:03.581200 boot times 0Enable ddr reg access
1084 06:54:03.586430 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 06:54:03.599960 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 06:54:04.172956 0.0;M3 CHK:0;cm4_sp_mode 0
1087 06:54:04.173583 MVN_1=0x00000000
1088 06:54:04.178416 MVN_2=0x00000000
1089 06:54:04.184204 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 06:54:04.184713 OPS=0x10
1091 06:54:04.185132 ring efuse init
1092 06:54:04.185534 chipver efuse init
1093 06:54:04.189781 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 06:54:04.195363 [0.018961 Inits done]
1095 06:54:04.195860 secure task start!
1096 06:54:04.196327 high task start!
1097 06:54:04.199919 low task start!
1098 06:54:04.200422 run into bl31
1099 06:54:04.206625 NOTICE: BL31: v1.3(release):4fc40b1
1100 06:54:04.214426 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 06:54:04.214939 NOTICE: BL31: G12A normal boot!
1102 06:54:04.239832 NOTICE: BL31: BL33 decompress pass
1103 06:54:04.245481 ERROR: Error initializing runtime service opteed_fast
1104 06:54:05.478425
1105 06:54:05.479024
1106 06:54:05.486763 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 06:54:05.487342
1108 06:54:05.487779 Model: Libre Computer AML-A311D-CC Alta
1109 06:54:05.695158 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 06:54:05.718620 DRAM: 2 GiB (effective 3.8 GiB)
1111 06:54:05.861641 Core: 408 devices, 31 uclasses, devicetree: separate
1112 06:54:05.867432 WDT: Not starting watchdog@f0d0
1113 06:54:05.899736 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 06:54:05.912211 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 06:54:05.917131 ** Bad device specification mmc 0 **
1116 06:54:05.927372 Card did not respond to voltage select! : -110
1117 06:54:05.935058 ** Bad device specification mmc 0 **
1118 06:54:05.935648 Couldn't find partition mmc 0
1119 06:54:05.943366 Card did not respond to voltage select! : -110
1120 06:54:05.948896 ** Bad device specification mmc 0 **
1121 06:54:05.949522 Couldn't find partition mmc 0
1122 06:54:05.953989 Error: could not access storage.
1123 06:54:06.296489 Net: eth0: ethernet@ff3f0000
1124 06:54:06.297063 starting USB...
1125 06:54:06.548265 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 06:54:06.548691 Starting the controller
1127 06:54:06.555183 USB XHCI 1.10
1128 06:54:08.111594 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 06:54:08.120012 scanning usb for storage devices... 0 Storage Device(s) found
1131 06:54:08.172385 Hit any key to stop autoboot: 1
1132 06:54:08.173396 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1133 06:54:08.174056 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1134 06:54:08.174571 Setting prompt string to ['=>']
1135 06:54:08.175086 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1136 06:54:08.187234 0
1137 06:54:08.188435 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 06:54:08.188991 Sending with 10 millisecond of delay
1140 06:54:09.324328 => setenv autoload no
1141 06:54:09.335152 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1142 06:54:09.340548 setenv autoload no
1143 06:54:09.341339 Sending with 10 millisecond of delay
1145 06:54:11.139170 => setenv initrd_high 0xffffffff
1146 06:54:11.149987 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1147 06:54:11.150947 setenv initrd_high 0xffffffff
1148 06:54:11.151701 Sending with 10 millisecond of delay
1150 06:54:12.769119 => setenv fdt_high 0xffffffff
1151 06:54:12.780037 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1152 06:54:12.780966 setenv fdt_high 0xffffffff
1153 06:54:12.781721 Sending with 10 millisecond of delay
1155 06:54:13.073900 => dhcp
1156 06:54:13.084799 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1157 06:54:13.085833 dhcp
1158 06:54:13.086331 Speed: 1000, full duplex
1159 06:54:13.086785 BOOTP broadcast 1
1160 06:54:13.333162 BOOTP broadcast 2
1161 06:54:13.423482 DHCP client bound to address 192.168.6.33 (338 ms)
1162 06:54:13.424441 Sending with 10 millisecond of delay
1164 06:54:15.103313 => setenv serverip 192.168.6.2
1165 06:54:15.114096 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1166 06:54:15.114955 setenv serverip 192.168.6.2
1167 06:54:15.115652 Sending with 10 millisecond of delay
1169 06:54:18.843617 => tftpboot 0x01080000 714812/tftp-deploy-5blp6lma/kernel/uImage
1170 06:54:18.855031 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1171 06:54:18.856652 tftpboot 0x01080000 714812/tftp-deploy-5blp6lma/kernel/uImage
1172 06:54:18.857395 Speed: 1000, full duplex
1173 06:54:18.858086 Using ethernet@ff3f0000 device
1174 06:54:18.858959 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1175 06:54:18.863419 Filename '714812/tftp-deploy-5blp6lma/kernel/uImage'.
1176 06:54:18.867398 Load address: 0x1080000
1177 06:54:21.802966 Loading: *################################################## 43.2 MiB
1178 06:54:21.803593 14.7 MiB/s
1179 06:54:21.804045 done
1180 06:54:21.806900 Bytes transferred = 45308480 (2b35a40 hex)
1181 06:54:21.807608 Sending with 10 millisecond of delay
1183 06:54:26.493623 => tftpboot 0x08000000 714812/tftp-deploy-5blp6lma/ramdisk/ramdisk.cpio.gz.uboot
1184 06:54:26.504538 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 06:54:26.505408 tftpboot 0x08000000 714812/tftp-deploy-5blp6lma/ramdisk/ramdisk.cpio.gz.uboot
1186 06:54:26.505833 Speed: 1000, full duplex
1187 06:54:26.506228 Using ethernet@ff3f0000 device
1188 06:54:26.507869 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1189 06:54:26.519229 Filename '714812/tftp-deploy-5blp6lma/ramdisk/ramdisk.cpio.gz.uboot'.
1190 06:54:26.519703 Load address: 0x8000000
1191 06:54:33.571373 Loading: *################T ################################# UDP wrong checksum 00000005 00005dda
1192 06:54:38.573576 T UDP wrong checksum 00000005 00005dda
1193 06:54:45.954806 T UDP wrong checksum 000000ff 00001c3d
1194 06:54:45.972528 UDP wrong checksum 000000ff 0000b42f
1195 06:54:48.575560 T UDP wrong checksum 00000005 00005dda
1196 06:54:49.224657 UDP wrong checksum 000000ff 00008116
1197 06:54:49.252378 UDP wrong checksum 000000ff 00001b09
1198 06:55:06.181902 T T T UDP wrong checksum 000000ff 000062c0
1199 06:55:06.199925 UDP wrong checksum 000000ff 0000f2b2
1200 06:55:08.578836 T UDP wrong checksum 00000005 00005dda
1201 06:55:23.583320 T T
1202 06:55:23.583951 Retry count exceeded; starting again
1204 06:55:23.585440 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1207 06:55:23.587312 end: 2.4 uboot-commands (duration 00:01:53) [common]
1209 06:55:23.588781 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1211 06:55:23.589856 end: 2 uboot-action (duration 00:01:53) [common]
1213 06:55:23.591348 Cleaning after the job
1214 06:55:23.591890 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/ramdisk
1215 06:55:23.593127 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/kernel
1216 06:55:23.619329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/dtb
1217 06:55:23.620620 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/nfsrootfs
1218 06:55:23.758606 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714812/tftp-deploy-5blp6lma/modules
1219 06:55:23.777516 start: 4.1 power-off (timeout 00:00:30) [common]
1220 06:55:23.778211 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1221 06:55:23.809890 >> OK - accepted request
1222 06:55:23.811975 Returned 0 in 0 seconds
1223 06:55:23.912894 end: 4.1 power-off (duration 00:00:00) [common]
1225 06:55:23.914127 start: 4.2 read-feedback (timeout 00:10:00) [common]
1226 06:55:23.914812 Listened to connection for namespace 'common' for up to 1s
1227 06:55:24.914809 Finalising connection for namespace 'common'
1228 06:55:24.915554 Disconnecting from shell: Finalise
1229 06:55:24.916145 =>
1230 06:55:25.017190 end: 4.2 read-feedback (duration 00:00:01) [common]
1231 06:55:25.017909 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714812
1232 06:55:28.191313 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714812
1233 06:55:28.191943 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.