Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:09:51.687549 lava-dispatcher, installed at version: 2024.01
2 07:09:51.688428 start: 0 validate
3 07:09:51.688929 Start time: 2024-09-06 07:09:51.688899+00:00 (UTC)
4 07:09:51.689539 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:09:51.690091 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:09:51.731229 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:09:51.731753 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:09:51.767792 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:09:51.768580 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:09:51.802515 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:09:51.803051 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:09:51.841266 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:09:51.841823 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 07:09:51.880301 validate duration: 0.19
16 07:09:51.881825 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:09:51.882414 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:09:51.882984 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:09:51.883937 Not decompressing ramdisk as can be used compressed.
20 07:09:51.884744 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 07:09:51.885254 saving as /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/ramdisk/initrd.cpio.gz
22 07:09:51.885767 total size: 5628169 (5 MB)
23 07:09:51.930131 progress 0 % (0 MB)
24 07:09:51.937686 progress 5 % (0 MB)
25 07:09:51.945675 progress 10 % (0 MB)
26 07:09:51.952707 progress 15 % (0 MB)
27 07:09:51.960421 progress 20 % (1 MB)
28 07:09:51.965496 progress 25 % (1 MB)
29 07:09:51.969580 progress 30 % (1 MB)
30 07:09:51.973719 progress 35 % (1 MB)
31 07:09:51.977340 progress 40 % (2 MB)
32 07:09:51.981407 progress 45 % (2 MB)
33 07:09:51.985018 progress 50 % (2 MB)
34 07:09:51.988982 progress 55 % (2 MB)
35 07:09:51.992953 progress 60 % (3 MB)
36 07:09:51.996647 progress 65 % (3 MB)
37 07:09:52.000770 progress 70 % (3 MB)
38 07:09:52.004388 progress 75 % (4 MB)
39 07:09:52.008391 progress 80 % (4 MB)
40 07:09:52.012029 progress 85 % (4 MB)
41 07:09:52.016017 progress 90 % (4 MB)
42 07:09:52.019807 progress 95 % (5 MB)
43 07:09:52.023112 progress 100 % (5 MB)
44 07:09:52.023759 5 MB downloaded in 0.14 s (38.90 MB/s)
45 07:09:52.024306 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:09:52.025193 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:09:52.025482 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:09:52.025750 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:09:52.026212 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
51 07:09:52.026455 saving as /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/kernel/Image
52 07:09:52.026663 total size: 45308416 (43 MB)
53 07:09:52.026873 No compression specified
54 07:09:52.073752 progress 0 % (0 MB)
55 07:09:52.102778 progress 5 % (2 MB)
56 07:09:52.131419 progress 10 % (4 MB)
57 07:09:52.159419 progress 15 % (6 MB)
58 07:09:52.186921 progress 20 % (8 MB)
59 07:09:52.215079 progress 25 % (10 MB)
60 07:09:52.242465 progress 30 % (12 MB)
61 07:09:52.270663 progress 35 % (15 MB)
62 07:09:52.299025 progress 40 % (17 MB)
63 07:09:52.326393 progress 45 % (19 MB)
64 07:09:52.354505 progress 50 % (21 MB)
65 07:09:52.382176 progress 55 % (23 MB)
66 07:09:52.410455 progress 60 % (25 MB)
67 07:09:52.438621 progress 65 % (28 MB)
68 07:09:52.466462 progress 70 % (30 MB)
69 07:09:52.494738 progress 75 % (32 MB)
70 07:09:52.522629 progress 80 % (34 MB)
71 07:09:52.550641 progress 85 % (36 MB)
72 07:09:52.578726 progress 90 % (38 MB)
73 07:09:52.606852 progress 95 % (41 MB)
74 07:09:52.634386 progress 100 % (43 MB)
75 07:09:52.635088 43 MB downloaded in 0.61 s (71.02 MB/s)
76 07:09:52.635559 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:09:52.636408 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:09:52.636685 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:09:52.636950 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:09:52.637436 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:09:52.637702 saving as /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:09:52.637909 total size: 54667 (0 MB)
84 07:09:52.638117 No compression specified
85 07:09:52.687178 progress 59 % (0 MB)
86 07:09:52.688068 progress 100 % (0 MB)
87 07:09:52.688640 0 MB downloaded in 0.05 s (1.03 MB/s)
88 07:09:52.689130 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:09:52.689969 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:09:52.690253 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:09:52.690532 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:09:52.690994 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 07:09:52.691237 saving as /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/nfsrootfs/full.rootfs.tar
95 07:09:52.691462 total size: 120894716 (115 MB)
96 07:09:52.691679 Using unxz to decompress xz
97 07:09:52.731201 progress 0 % (0 MB)
98 07:09:53.523203 progress 5 % (5 MB)
99 07:09:54.358715 progress 10 % (11 MB)
100 07:09:55.146274 progress 15 % (17 MB)
101 07:09:55.875878 progress 20 % (23 MB)
102 07:09:56.466410 progress 25 % (28 MB)
103 07:09:57.288919 progress 30 % (34 MB)
104 07:09:58.092706 progress 35 % (40 MB)
105 07:09:58.463945 progress 40 % (46 MB)
106 07:09:58.853153 progress 45 % (51 MB)
107 07:09:59.572033 progress 50 % (57 MB)
108 07:10:00.456912 progress 55 % (63 MB)
109 07:10:01.236268 progress 60 % (69 MB)
110 07:10:01.989845 progress 65 % (74 MB)
111 07:10:02.762243 progress 70 % (80 MB)
112 07:10:03.585754 progress 75 % (86 MB)
113 07:10:04.379914 progress 80 % (92 MB)
114 07:10:05.141471 progress 85 % (98 MB)
115 07:10:06.000532 progress 90 % (103 MB)
116 07:10:06.779273 progress 95 % (109 MB)
117 07:10:07.608661 progress 100 % (115 MB)
118 07:10:07.621041 115 MB downloaded in 14.93 s (7.72 MB/s)
119 07:10:07.621912 end: 1.4.1 http-download (duration 00:00:15) [common]
121 07:10:07.623475 end: 1.4 download-retry (duration 00:00:15) [common]
122 07:10:07.624022 start: 1.5 download-retry (timeout 00:09:44) [common]
123 07:10:07.624540 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 07:10:07.625364 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
125 07:10:07.625821 saving as /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/modules/modules.tar
126 07:10:07.626225 total size: 11502724 (10 MB)
127 07:10:07.626634 Using unxz to decompress xz
128 07:10:07.672607 progress 0 % (0 MB)
129 07:10:07.741725 progress 5 % (0 MB)
130 07:10:07.818491 progress 10 % (1 MB)
131 07:10:07.901007 progress 15 % (1 MB)
132 07:10:07.981073 progress 20 % (2 MB)
133 07:10:08.057154 progress 25 % (2 MB)
134 07:10:08.138256 progress 30 % (3 MB)
135 07:10:08.212442 progress 35 % (3 MB)
136 07:10:08.290240 progress 40 % (4 MB)
137 07:10:08.361757 progress 45 % (4 MB)
138 07:10:08.439091 progress 50 % (5 MB)
139 07:10:08.514866 progress 55 % (6 MB)
140 07:10:08.595419 progress 60 % (6 MB)
141 07:10:08.684792 progress 65 % (7 MB)
142 07:10:08.763036 progress 70 % (7 MB)
143 07:10:08.859021 progress 75 % (8 MB)
144 07:10:08.948827 progress 80 % (8 MB)
145 07:10:09.029795 progress 85 % (9 MB)
146 07:10:09.100026 progress 90 % (9 MB)
147 07:10:09.174524 progress 95 % (10 MB)
148 07:10:09.249188 progress 100 % (10 MB)
149 07:10:09.259003 10 MB downloaded in 1.63 s (6.72 MB/s)
150 07:10:09.259864 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:10:09.261518 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:10:09.262029 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 07:10:09.262538 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 07:10:25.825766 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/714886/extract-nfsrootfs-8eo5uhke
156 07:10:25.826376 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 07:10:25.826664 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 07:10:25.827274 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx
159 07:10:25.827696 makedir: /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin
160 07:10:25.828046 makedir: /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/tests
161 07:10:25.828368 makedir: /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/results
162 07:10:25.828698 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-add-keys
163 07:10:25.829223 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-add-sources
164 07:10:25.829729 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-background-process-start
165 07:10:25.830224 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-background-process-stop
166 07:10:25.830744 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-common-functions
167 07:10:25.831241 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-echo-ipv4
168 07:10:25.831745 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-install-packages
169 07:10:25.832302 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-installed-packages
170 07:10:25.832789 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-os-build
171 07:10:25.833257 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-probe-channel
172 07:10:25.833725 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-probe-ip
173 07:10:25.834191 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-target-ip
174 07:10:25.834654 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-target-mac
175 07:10:25.835120 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-target-storage
176 07:10:25.835612 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-test-case
177 07:10:25.836223 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-test-event
178 07:10:25.836719 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-test-feedback
179 07:10:25.837191 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-test-raise
180 07:10:25.837658 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-test-reference
181 07:10:25.838127 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-test-runner
182 07:10:25.838600 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-test-set
183 07:10:25.839066 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-test-shell
184 07:10:25.839560 Updating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-add-keys (debian)
185 07:10:25.840121 Updating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-add-sources (debian)
186 07:10:25.840622 Updating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-install-packages (debian)
187 07:10:25.841112 Updating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-installed-packages (debian)
188 07:10:25.841589 Updating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/bin/lava-os-build (debian)
189 07:10:25.842011 Creating /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/environment
190 07:10:25.842369 LAVA metadata
191 07:10:25.842625 - LAVA_JOB_ID=714886
192 07:10:25.842839 - LAVA_DISPATCHER_IP=192.168.6.2
193 07:10:25.843191 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 07:10:25.844160 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 07:10:25.844471 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 07:10:25.844678 skipped lava-vland-overlay
197 07:10:25.844917 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 07:10:25.845171 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 07:10:25.845386 skipped lava-multinode-overlay
200 07:10:25.845627 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 07:10:25.845873 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 07:10:25.846113 Loading test definitions
203 07:10:25.846385 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 07:10:25.846602 Using /lava-714886 at stage 0
205 07:10:25.847643 uuid=714886_1.6.2.4.1 testdef=None
206 07:10:25.847938 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 07:10:25.848232 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 07:10:25.849792 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 07:10:25.850575 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 07:10:25.852522 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 07:10:25.853335 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 07:10:25.855137 runner path: /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/0/tests/0_timesync-off test_uuid 714886_1.6.2.4.1
215 07:10:25.855672 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 07:10:25.856504 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 07:10:25.856725 Using /lava-714886 at stage 0
219 07:10:25.857072 Fetching tests from https://github.com/kernelci/test-definitions.git
220 07:10:25.857358 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/0/tests/1_kselftest-dt'
221 07:10:29.267621 Running '/usr/bin/git checkout kernelci.org
222 07:10:29.527645 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 07:10:29.530200 uuid=714886_1.6.2.4.5 testdef=None
224 07:10:29.530864 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 07:10:29.532512 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 07:10:29.538384 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 07:10:29.540140 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 07:10:29.547948 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 07:10:29.549784 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 07:10:29.557392 runner path: /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/0/tests/1_kselftest-dt test_uuid 714886_1.6.2.4.5
234 07:10:29.557966 BOARD='meson-g12b-a311d-libretech-cc'
235 07:10:29.558411 BRANCH='mainline'
236 07:10:29.558841 SKIPFILE='/dev/null'
237 07:10:29.559270 SKIP_INSTALL='True'
238 07:10:29.559696 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 07:10:29.560173 TST_CASENAME=''
240 07:10:29.560611 TST_CMDFILES='dt'
241 07:10:29.561714 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 07:10:29.563395 Creating lava-test-runner.conf files
244 07:10:29.563836 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714886/lava-overlay-ul50y9yx/lava-714886/0 for stage 0
245 07:10:29.564616 - 0_timesync-off
246 07:10:29.565157 - 1_kselftest-dt
247 07:10:29.565868 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 07:10:29.566459 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 07:10:52.754339 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 07:10:52.754787 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 07:10:52.755054 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 07:10:52.755326 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 07:10:52.755587 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 07:10:53.406701 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 07:10:53.407208 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 07:10:53.407485 extracting modules file /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714886/extract-nfsrootfs-8eo5uhke
257 07:10:54.774100 extracting modules file /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714886/extract-overlay-ramdisk-y2ifvwy8/ramdisk
258 07:10:56.417457 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 07:10:56.418054 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 07:10:56.418443 [common] Applying overlay to NFS
261 07:10:56.418725 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714886/compress-overlay-7g2n_sgy/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714886/extract-nfsrootfs-8eo5uhke
262 07:10:59.614506 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 07:10:59.615081 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 07:10:59.615427 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 07:10:59.615718 Converting downloaded kernel to a uImage
266 07:10:59.616134 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/kernel/Image /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/kernel/uImage
267 07:11:00.055963 output: Image Name:
268 07:11:00.056389 output: Created: Fri Sep 6 07:10:59 2024
269 07:11:00.056601 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 07:11:00.056806 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
271 07:11:00.057006 output: Load Address: 01080000
272 07:11:00.057208 output: Entry Point: 01080000
273 07:11:00.057405 output:
274 07:11:00.057737 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 07:11:00.058003 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 07:11:00.058272 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 07:11:00.058524 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 07:11:00.058782 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 07:11:00.059036 Building ramdisk /var/lib/lava/dispatcher/tmp/714886/extract-overlay-ramdisk-y2ifvwy8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714886/extract-overlay-ramdisk-y2ifvwy8/ramdisk
280 07:11:02.233578 >> 165160 blocks
281 07:11:09.904042 Adding RAMdisk u-boot header.
282 07:11:09.904719 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714886/extract-overlay-ramdisk-y2ifvwy8/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714886/extract-overlay-ramdisk-y2ifvwy8/ramdisk.cpio.gz.uboot
283 07:11:10.160689 output: Image Name:
284 07:11:10.161353 output: Created: Fri Sep 6 07:11:09 2024
285 07:11:10.161805 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 07:11:10.162254 output: Data Size: 23258341 Bytes = 22713.22 KiB = 22.18 MiB
287 07:11:10.162699 output: Load Address: 00000000
288 07:11:10.163132 output: Entry Point: 00000000
289 07:11:10.163568 output:
290 07:11:10.164796 rename /var/lib/lava/dispatcher/tmp/714886/extract-overlay-ramdisk-y2ifvwy8/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/ramdisk/ramdisk.cpio.gz.uboot
291 07:11:10.165590 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 07:11:10.166181 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 07:11:10.166756 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 07:11:10.167259 No LXC device requested
295 07:11:10.167801 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 07:11:10.168402 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 07:11:10.168952 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 07:11:10.169406 Checking files for TFTP limit of 4294967296 bytes.
299 07:11:10.172373 end: 1 tftp-deploy (duration 00:01:18) [common]
300 07:11:10.173012 start: 2 uboot-action (timeout 00:05:00) [common]
301 07:11:10.173588 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 07:11:10.174131 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 07:11:10.174685 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 07:11:10.175267 Using kernel file from prepare-kernel: 714886/tftp-deploy-s2nor1jz/kernel/uImage
305 07:11:10.175966 substitutions:
306 07:11:10.176454 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 07:11:10.176902 - {DTB_ADDR}: 0x01070000
308 07:11:10.177345 - {DTB}: 714886/tftp-deploy-s2nor1jz/dtb/meson-g12b-a311d-libretech-cc.dtb
309 07:11:10.177789 - {INITRD}: 714886/tftp-deploy-s2nor1jz/ramdisk/ramdisk.cpio.gz.uboot
310 07:11:10.178229 - {KERNEL_ADDR}: 0x01080000
311 07:11:10.178664 - {KERNEL}: 714886/tftp-deploy-s2nor1jz/kernel/uImage
312 07:11:10.179100 - {LAVA_MAC}: None
313 07:11:10.179580 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/714886/extract-nfsrootfs-8eo5uhke
314 07:11:10.180057 - {NFS_SERVER_IP}: 192.168.6.2
315 07:11:10.180501 - {PRESEED_CONFIG}: None
316 07:11:10.180940 - {PRESEED_LOCAL}: None
317 07:11:10.181379 - {RAMDISK_ADDR}: 0x08000000
318 07:11:10.181811 - {RAMDISK}: 714886/tftp-deploy-s2nor1jz/ramdisk/ramdisk.cpio.gz.uboot
319 07:11:10.182244 - {ROOT_PART}: None
320 07:11:10.182671 - {ROOT}: None
321 07:11:10.183097 - {SERVER_IP}: 192.168.6.2
322 07:11:10.183524 - {TEE_ADDR}: 0x83000000
323 07:11:10.183949 - {TEE}: None
324 07:11:10.184406 Parsed boot commands:
325 07:11:10.184824 - setenv autoload no
326 07:11:10.185252 - setenv initrd_high 0xffffffff
327 07:11:10.185679 - setenv fdt_high 0xffffffff
328 07:11:10.186102 - dhcp
329 07:11:10.186525 - setenv serverip 192.168.6.2
330 07:11:10.186956 - tftpboot 0x01080000 714886/tftp-deploy-s2nor1jz/kernel/uImage
331 07:11:10.187388 - tftpboot 0x08000000 714886/tftp-deploy-s2nor1jz/ramdisk/ramdisk.cpio.gz.uboot
332 07:11:10.187820 - tftpboot 0x01070000 714886/tftp-deploy-s2nor1jz/dtb/meson-g12b-a311d-libretech-cc.dtb
333 07:11:10.188278 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/714886/extract-nfsrootfs-8eo5uhke,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 07:11:10.188725 - bootm 0x01080000 0x08000000 0x01070000
335 07:11:10.189267 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 07:11:10.190899 start: 2.3 connect-device (timeout 00:05:00) [common]
338 07:11:10.191366 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 07:11:10.206197 Setting prompt string to ['lava-test: # ']
340 07:11:10.207856 end: 2.3 connect-device (duration 00:00:00) [common]
341 07:11:10.208586 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 07:11:10.209234 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 07:11:10.209826 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 07:11:10.211093 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 07:11:10.245636 >> OK - accepted request
346 07:11:10.247764 Returned 0 in 0 seconds
347 07:11:10.348968 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 07:11:10.350727 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 07:11:10.351350 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 07:11:10.351905 Setting prompt string to ['Hit any key to stop autoboot']
352 07:11:10.352504 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 07:11:10.354200 Trying 192.168.56.21...
354 07:11:10.354734 Connected to conserv1.
355 07:11:10.355186 Escape character is '^]'.
356 07:11:10.355650
357 07:11:10.356153 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 07:11:10.356636
359 07:11:22.003782 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 07:11:22.004481 bl2_stage_init 0x01
361 07:11:22.004953 bl2_stage_init 0x81
362 07:11:22.009482 hw id: 0x0000 - pwm id 0x01
363 07:11:22.010004 bl2_stage_init 0xc1
364 07:11:22.010459 bl2_stage_init 0x02
365 07:11:22.010901
366 07:11:22.015007 L0:00000000
367 07:11:22.015523 L1:20000703
368 07:11:22.016009 L2:00008067
369 07:11:22.016481 L3:14000000
370 07:11:22.020706 B2:00402000
371 07:11:22.021195 B1:e0f83180
372 07:11:22.021649
373 07:11:22.022081 TE: 58124
374 07:11:22.022515
375 07:11:22.026077 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 07:11:22.026581
377 07:11:22.027015 Board ID = 1
378 07:11:22.031708 Set A53 clk to 24M
379 07:11:22.032262 Set A73 clk to 24M
380 07:11:22.032712 Set clk81 to 24M
381 07:11:22.038141 A53 clk: 1200 MHz
382 07:11:22.038631 A73 clk: 1200 MHz
383 07:11:22.039062 CLK81: 166.6M
384 07:11:22.039489 smccc: 00012a92
385 07:11:22.042990 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 07:11:22.048574 board id: 1
387 07:11:22.054451 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 07:11:22.065242 fw parse done
389 07:11:22.070165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 07:11:22.113629 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 07:11:22.124556 PIEI prepare done
392 07:11:22.125096 fastboot data load
393 07:11:22.125546 fastboot data verify
394 07:11:22.130382 verify result: 266
395 07:11:22.135827 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 07:11:22.136602 LPDDR4 probe
397 07:11:22.137204 ddr clk to 1584MHz
398 07:11:22.143736 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 07:11:22.180237
400 07:11:22.180997 dmc_version 0001
401 07:11:22.186884 Check phy result
402 07:11:22.193631 INFO : End of CA training
403 07:11:22.194226 INFO : End of initialization
404 07:11:22.199107 INFO : Training has run successfully!
405 07:11:22.199715 Check phy result
406 07:11:22.204670 INFO : End of initialization
407 07:11:22.205252 INFO : End of read enable training
408 07:11:22.210420 INFO : End of fine write leveling
409 07:11:22.215923 INFO : End of Write leveling coarse delay
410 07:11:22.216476 INFO : Training has run successfully!
411 07:11:22.217009 Check phy result
412 07:11:22.221654 INFO : End of initialization
413 07:11:22.222225 INFO : End of read dq deskew training
414 07:11:22.227124 INFO : End of MPR read delay center optimization
415 07:11:22.232734 INFO : End of write delay center optimization
416 07:11:22.238341 INFO : End of read delay center optimization
417 07:11:22.238865 INFO : End of max read latency training
418 07:11:22.243930 INFO : Training has run successfully!
419 07:11:22.244554 1D training succeed
420 07:11:22.253075 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 07:11:22.299888 Check phy result
422 07:11:22.300558 INFO : End of initialization
423 07:11:22.322373 INFO : End of 2D read delay Voltage center optimization
424 07:11:22.342416 INFO : End of 2D read delay Voltage center optimization
425 07:11:22.394369 INFO : End of 2D write delay Voltage center optimization
426 07:11:22.443670 INFO : End of 2D write delay Voltage center optimization
427 07:11:22.449134 INFO : Training has run successfully!
428 07:11:22.449667
429 07:11:22.450104 channel==0
430 07:11:22.454718 RxClkDly_Margin_A0==88 ps 9
431 07:11:22.455236 TxDqDly_Margin_A0==98 ps 10
432 07:11:22.460409 RxClkDly_Margin_A1==88 ps 9
433 07:11:22.460935 TxDqDly_Margin_A1==88 ps 9
434 07:11:22.461370 TrainedVREFDQ_A0==74
435 07:11:22.465997 TrainedVREFDQ_A1==74
436 07:11:22.466516 VrefDac_Margin_A0==25
437 07:11:22.466940 DeviceVref_Margin_A0==40
438 07:11:22.471620 VrefDac_Margin_A1==25
439 07:11:22.472218 DeviceVref_Margin_A1==40
440 07:11:22.472665
441 07:11:22.473084
442 07:11:22.473492 channel==1
443 07:11:22.477194 RxClkDly_Margin_A0==98 ps 10
444 07:11:22.477700 TxDqDly_Margin_A0==98 ps 10
445 07:11:22.482737 RxClkDly_Margin_A1==98 ps 10
446 07:11:22.483239 TxDqDly_Margin_A1==88 ps 9
447 07:11:22.488313 TrainedVREFDQ_A0==77
448 07:11:22.488821 TrainedVREFDQ_A1==77
449 07:11:22.489243 VrefDac_Margin_A0==22
450 07:11:22.493928 DeviceVref_Margin_A0==37
451 07:11:22.494445 VrefDac_Margin_A1==22
452 07:11:22.499527 DeviceVref_Margin_A1==37
453 07:11:22.500057
454 07:11:22.500492 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 07:11:22.500902
456 07:11:22.533103 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 07:11:22.533546 2D training succeed
458 07:11:22.538759 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 07:11:22.544309 auto size-- 65535DDR cs0 size: 2048MB
460 07:11:22.544666 DDR cs1 size: 2048MB
461 07:11:22.549888 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 07:11:22.550224 cs0 DataBus test pass
463 07:11:22.555539 cs1 DataBus test pass
464 07:11:22.555901 cs0 AddrBus test pass
465 07:11:22.556237 cs1 AddrBus test pass
466 07:11:22.556515
467 07:11:22.561159 100bdlr_step_size ps== 420
468 07:11:22.561553 result report
469 07:11:22.566864 boot times 0Enable ddr reg access
470 07:11:22.572211 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 07:11:22.584749 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 07:11:23.157576 0.0;M3 CHK:0;cm4_sp_mode 0
473 07:11:23.158189 MVN_1=0x00000000
474 07:11:23.162936 MVN_2=0x00000000
475 07:11:23.168770 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 07:11:23.169242 OPS=0x10
477 07:11:23.169665 ring efuse init
478 07:11:23.170076 chipver efuse init
479 07:11:23.176843 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 07:11:23.177321 [0.018961 Inits done]
481 07:11:23.184580 secure task start!
482 07:11:23.185037 high task start!
483 07:11:23.185452 low task start!
484 07:11:23.185859 run into bl31
485 07:11:23.191186 NOTICE: BL31: v1.3(release):4fc40b1
486 07:11:23.198970 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 07:11:23.199427 NOTICE: BL31: G12A normal boot!
488 07:11:23.224341 NOTICE: BL31: BL33 decompress pass
489 07:11:23.229074 ERROR: Error initializing runtime service opteed_fast
490 07:11:24.462862
491 07:11:24.463262
492 07:11:24.471255 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 07:11:24.471736
494 07:11:24.472115 Model: Libre Computer AML-A311D-CC Alta
495 07:11:24.679732 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 07:11:24.703134 DRAM: 2 GiB (effective 3.8 GiB)
497 07:11:24.846029 Core: 408 devices, 31 uclasses, devicetree: separate
498 07:11:24.851906 WDT: Not starting watchdog@f0d0
499 07:11:24.884352 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 07:11:24.896632 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 07:11:24.901648 ** Bad device specification mmc 0 **
502 07:11:24.911965 Card did not respond to voltage select! : -110
503 07:11:24.919598 ** Bad device specification mmc 0 **
504 07:11:24.919905 Couldn't find partition mmc 0
505 07:11:24.927925 Card did not respond to voltage select! : -110
506 07:11:24.933442 ** Bad device specification mmc 0 **
507 07:11:24.933755 Couldn't find partition mmc 0
508 07:11:24.937589 Error: could not access storage.
509 07:11:26.205423 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
510 07:11:26.205881 bl2_stage_init 0x81
511 07:11:26.211032 hw id: 0x0000 - pwm id 0x01
512 07:11:26.211475 bl2_stage_init 0xc1
513 07:11:26.211821 bl2_stage_init 0x02
514 07:11:26.212106
515 07:11:26.216516 L0:00000000
516 07:11:26.216816 L1:20000703
517 07:11:26.217036 L2:00008067
518 07:11:26.217261 L3:14000000
519 07:11:26.217468 B2:00402000
520 07:11:26.222209 B1:e0f83180
521 07:11:26.222625
522 07:11:26.222981 TE: 58150
523 07:11:26.223329
524 07:11:26.227825 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 07:11:26.228152
526 07:11:26.228570 Board ID = 1
527 07:11:26.233479 Set A53 clk to 24M
528 07:11:26.233939 Set A73 clk to 24M
529 07:11:26.234349 Set clk81 to 24M
530 07:11:26.239131 A53 clk: 1200 MHz
531 07:11:26.239577 A73 clk: 1200 MHz
532 07:11:26.240008 CLK81: 166.6M
533 07:11:26.240419 smccc: 00012aac
534 07:11:26.244571 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 07:11:26.250150 board id: 1
536 07:11:26.255946 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 07:11:26.266626 fw parse done
538 07:11:26.272583 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 07:11:26.315225 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 07:11:26.326129 PIEI prepare done
541 07:11:26.326590 fastboot data load
542 07:11:26.327008 fastboot data verify
543 07:11:26.331808 verify result: 266
544 07:11:26.337395 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 07:11:26.337842 LPDDR4 probe
546 07:11:26.338250 ddr clk to 1584MHz
547 07:11:26.344460 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 07:11:26.382726
549 07:11:26.383193 dmc_version 0001
550 07:11:26.389296 Check phy result
551 07:11:26.395167 INFO : End of CA training
552 07:11:26.395621 INFO : End of initialization
553 07:11:26.400809 INFO : Training has run successfully!
554 07:11:26.401246 Check phy result
555 07:11:26.406476 INFO : End of initialization
556 07:11:26.406906 INFO : End of read enable training
557 07:11:26.412075 INFO : End of fine write leveling
558 07:11:26.417556 INFO : End of Write leveling coarse delay
559 07:11:26.417987 INFO : Training has run successfully!
560 07:11:26.418391 Check phy result
561 07:11:26.423166 INFO : End of initialization
562 07:11:26.423599 INFO : End of read dq deskew training
563 07:11:26.428780 INFO : End of MPR read delay center optimization
564 07:11:26.434356 INFO : End of write delay center optimization
565 07:11:26.439955 INFO : End of read delay center optimization
566 07:11:26.440418 INFO : End of max read latency training
567 07:11:26.445567 INFO : Training has run successfully!
568 07:11:26.446020 1D training succeed
569 07:11:26.453807 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 07:11:26.502437 Check phy result
571 07:11:26.502921 INFO : End of initialization
572 07:11:26.524233 INFO : End of 2D read delay Voltage center optimization
573 07:11:26.544354 INFO : End of 2D read delay Voltage center optimization
574 07:11:26.596552 INFO : End of 2D write delay Voltage center optimization
575 07:11:26.645846 INFO : End of 2D write delay Voltage center optimization
576 07:11:26.651344 INFO : Training has run successfully!
577 07:11:26.651829
578 07:11:26.652305 channel==0
579 07:11:26.656862 RxClkDly_Margin_A0==88 ps 9
580 07:11:26.657318 TxDqDly_Margin_A0==98 ps 10
581 07:11:26.660218 RxClkDly_Margin_A1==88 ps 9
582 07:11:26.660669 TxDqDly_Margin_A1==88 ps 9
583 07:11:26.665783 TrainedVREFDQ_A0==74
584 07:11:26.666251 TrainedVREFDQ_A1==74
585 07:11:26.666667 VrefDac_Margin_A0==25
586 07:11:26.671510 DeviceVref_Margin_A0==40
587 07:11:26.672262 VrefDac_Margin_A1==25
588 07:11:26.677012 DeviceVref_Margin_A1==40
589 07:11:26.677477
590 07:11:26.677895
591 07:11:26.678302 channel==1
592 07:11:26.678707 RxClkDly_Margin_A0==98 ps 10
593 07:11:26.682572 TxDqDly_Margin_A0==98 ps 10
594 07:11:26.683038 RxClkDly_Margin_A1==88 ps 9
595 07:11:26.688202 TxDqDly_Margin_A1==88 ps 9
596 07:11:26.688669 TrainedVREFDQ_A0==77
597 07:11:26.689085 TrainedVREFDQ_A1==77
598 07:11:26.693909 VrefDac_Margin_A0==22
599 07:11:26.694342 DeviceVref_Margin_A0==37
600 07:11:26.699451 VrefDac_Margin_A1==24
601 07:11:26.699885 DeviceVref_Margin_A1==37
602 07:11:26.700324
603 07:11:26.704954 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 07:11:26.705380
605 07:11:26.733019 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
606 07:11:26.738746 2D training succeed
607 07:11:26.744357 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 07:11:26.744881 auto size-- 65535DDR cs0 size: 2048MB
609 07:11:26.749847 DDR cs1 size: 2048MB
610 07:11:26.750325 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 07:11:26.755426 cs0 DataBus test pass
612 07:11:26.755892 cs1 DataBus test pass
613 07:11:26.756351 cs0 AddrBus test pass
614 07:11:26.760977 cs1 AddrBus test pass
615 07:11:26.761422
616 07:11:26.761829 100bdlr_step_size ps== 420
617 07:11:26.762237 result report
618 07:11:26.766568 boot times 0Enable ddr reg access
619 07:11:26.774108 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 07:11:26.787598 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 07:11:27.361546 0.0;M3 CHK:0;cm4_sp_mode 0
622 07:11:27.362162 MVN_1=0x00000000
623 07:11:27.366845 MVN_2=0x00000000
624 07:11:27.372658 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 07:11:27.373163 OPS=0x10
626 07:11:27.373585 ring efuse init
627 07:11:27.373999 chipver efuse init
628 07:11:27.378428 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 07:11:27.384189 [0.018961 Inits done]
630 07:11:27.384677 secure task start!
631 07:11:27.385093 high task start!
632 07:11:27.387709 low task start!
633 07:11:27.388195 run into bl31
634 07:11:27.395164 NOTICE: BL31: v1.3(release):4fc40b1
635 07:11:27.402922 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 07:11:27.403376 NOTICE: BL31: G12A normal boot!
637 07:11:27.428267 NOTICE: BL31: BL33 decompress pass
638 07:11:27.433809 ERROR: Error initializing runtime service opteed_fast
639 07:11:28.667637
640 07:11:28.668130
641 07:11:28.680528 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 07:11:28.683222
643 07:11:28.697333 Model: Libre Computer AML-A311D-CC Alta
644 07:11:28.882772 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 07:11:28.907057 DRAM: 2 GiB (effective 3.8 GiB)
646 07:11:29.049950 Core: 408 devices, 31 uclasses, devicetree: separate
647 07:11:29.055727 WDT: Not starting watchdog@f0d0
648 07:11:29.088032 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 07:11:29.100461 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 07:11:29.105369 ** Bad device specification mmc 0 **
651 07:11:29.115802 Card did not respond to voltage select! : -110
652 07:11:29.122351 ** Bad device specification mmc 0 **
653 07:11:29.122828 Couldn't find partition mmc 0
654 07:11:29.131721 Card did not respond to voltage select! : -110
655 07:11:29.137301 ** Bad device specification mmc 0 **
656 07:11:29.137839 Couldn't find partition mmc 0
657 07:11:29.142265 Error: could not access storage.
658 07:11:29.484789 Net: eth0: ethernet@ff3f0000
659 07:11:29.485300 starting USB...
660 07:11:29.736638 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 07:11:29.737162 Starting the controller
662 07:11:29.743585 USB XHCI 1.10
663 07:11:31.456098 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 07:11:31.456732 bl2_stage_init 0x01
665 07:11:31.457170 bl2_stage_init 0x81
666 07:11:31.461567 hw id: 0x0000 - pwm id 0x01
667 07:11:31.462072 bl2_stage_init 0xc1
668 07:11:31.462484 bl2_stage_init 0x02
669 07:11:31.462874
670 07:11:31.467146 L0:00000000
671 07:11:31.467631 L1:20000703
672 07:11:31.468074 L2:00008067
673 07:11:31.468488 L3:14000000
674 07:11:31.472834 B2:00402000
675 07:11:31.473322 B1:e0f83180
676 07:11:31.473721
677 07:11:31.474111 TE: 58167
678 07:11:31.474499
679 07:11:31.478369 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 07:11:31.478849
681 07:11:31.479270 Board ID = 1
682 07:11:31.483966 Set A53 clk to 24M
683 07:11:31.484483 Set A73 clk to 24M
684 07:11:31.484898 Set clk81 to 24M
685 07:11:31.489543 A53 clk: 1200 MHz
686 07:11:31.490025 A73 clk: 1200 MHz
687 07:11:31.490440 CLK81: 166.6M
688 07:11:31.490845 smccc: 00012abd
689 07:11:31.495159 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 07:11:31.500843 board id: 1
691 07:11:31.505692 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 07:11:31.518308 fw parse done
693 07:11:31.523336 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 07:11:31.564942 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 07:11:31.576934 PIEI prepare done
696 07:11:31.577459 fastboot data load
697 07:11:31.577889 fastboot data verify
698 07:11:31.582478 verify result: 266
699 07:11:31.588044 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 07:11:31.588554 LPDDR4 probe
701 07:11:31.588975 ddr clk to 1584MHz
702 07:11:31.596019 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 07:11:31.633405
704 07:11:31.633951 dmc_version 0001
705 07:11:31.640002 Check phy result
706 07:11:31.645891 INFO : End of CA training
707 07:11:31.646377 INFO : End of initialization
708 07:11:31.651387 INFO : Training has run successfully!
709 07:11:31.651866 Check phy result
710 07:11:31.657014 INFO : End of initialization
711 07:11:31.657528 INFO : End of read enable training
712 07:11:31.663033 INFO : End of fine write leveling
713 07:11:31.668372 INFO : End of Write leveling coarse delay
714 07:11:31.668868 INFO : Training has run successfully!
715 07:11:31.669284 Check phy result
716 07:11:31.673927 INFO : End of initialization
717 07:11:31.674410 INFO : End of read dq deskew training
718 07:11:31.679479 INFO : End of MPR read delay center optimization
719 07:11:31.685108 INFO : End of write delay center optimization
720 07:11:31.690660 INFO : End of read delay center optimization
721 07:11:31.691154 INFO : End of max read latency training
722 07:11:31.696242 INFO : Training has run successfully!
723 07:11:31.696764 1D training succeed
724 07:11:31.705400 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 07:11:31.753168 Check phy result
726 07:11:31.753772 INFO : End of initialization
727 07:11:31.774823 INFO : End of 2D read delay Voltage center optimization
728 07:11:31.794301 INFO : End of 2D read delay Voltage center optimization
729 07:11:31.846299 INFO : End of 2D write delay Voltage center optimization
730 07:11:31.896473 INFO : End of 2D write delay Voltage center optimization
731 07:11:31.901950 INFO : Training has run successfully!
732 07:11:31.902503
733 07:11:31.902941 channel==0
734 07:11:31.907567 RxClkDly_Margin_A0==88 ps 9
735 07:11:31.908150 TxDqDly_Margin_A0==98 ps 10
736 07:11:31.911026 RxClkDly_Margin_A1==88 ps 9
737 07:11:31.911514 TxDqDly_Margin_A1==98 ps 10
738 07:11:31.916715 TrainedVREFDQ_A0==74
739 07:11:31.917332 TrainedVREFDQ_A1==75
740 07:11:31.917762 VrefDac_Margin_A0==25
741 07:11:31.922133 DeviceVref_Margin_A0==40
742 07:11:31.922736 VrefDac_Margin_A1==23
743 07:11:31.927750 DeviceVref_Margin_A1==39
744 07:11:31.928386
745 07:11:31.928856
746 07:11:31.929315 channel==1
747 07:11:31.929758 RxClkDly_Margin_A0==98 ps 10
748 07:11:31.933281 TxDqDly_Margin_A0==88 ps 9
749 07:11:31.933830 RxClkDly_Margin_A1==88 ps 9
750 07:11:31.938884 TxDqDly_Margin_A1==88 ps 9
751 07:11:31.939490 TrainedVREFDQ_A0==77
752 07:11:31.940011 TrainedVREFDQ_A1==77
753 07:11:31.944508 VrefDac_Margin_A0==22
754 07:11:31.945126 DeviceVref_Margin_A0==37
755 07:11:31.950045 VrefDac_Margin_A1==24
756 07:11:31.950576 DeviceVref_Margin_A1==37
757 07:11:31.951003
758 07:11:31.955819 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 07:11:31.956452
760 07:11:31.983693 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
761 07:11:31.989257 2D training succeed
762 07:11:31.994903 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 07:11:31.995383 auto size-- 65535DDR cs0 size: 2048MB
764 07:11:32.000469 DDR cs1 size: 2048MB
765 07:11:32.001017 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 07:11:32.006072 cs0 DataBus test pass
767 07:11:32.006629 cs1 DataBus test pass
768 07:11:32.007053 cs0 AddrBus test pass
769 07:11:32.011722 cs1 AddrBus test pass
770 07:11:32.012380
771 07:11:32.012810 100bdlr_step_size ps== 420
772 07:11:32.013242 result report
773 07:11:32.017297 boot times 0Enable ddr reg access
774 07:11:32.023909 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 07:11:32.038330 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 07:11:32.612167 0.0;M3 CHK:0;cm4_sp_mode 0
777 07:11:32.612740 MVN_1=0x00000000
778 07:11:32.617628 MVN_2=0x00000000
779 07:11:32.623354 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 07:11:32.623789 OPS=0x10
781 07:11:32.624230 ring efuse init
782 07:11:32.624626 chipver efuse init
783 07:11:32.628899 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 07:11:32.634610 [0.018961 Inits done]
785 07:11:32.635030 secure task start!
786 07:11:32.635418 high task start!
787 07:11:32.639358 low task start!
788 07:11:32.639779 run into bl31
789 07:11:32.645741 NOTICE: BL31: v1.3(release):4fc40b1
790 07:11:32.652877 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 07:11:32.653309 NOTICE: BL31: G12A normal boot!
792 07:11:32.678943 NOTICE: BL31: BL33 decompress pass
793 07:11:32.684567 ERROR: Error initializing runtime service opteed_fast
794 07:11:33.917557
795 07:11:33.918161
796 07:11:33.925868 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 07:11:33.926331
798 07:11:33.926750 Model: Libre Computer AML-A311D-CC Alta
799 07:11:34.134382 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 07:11:34.157696 DRAM: 2 GiB (effective 3.8 GiB)
801 07:11:34.300701 Core: 408 devices, 31 uclasses, devicetree: separate
802 07:11:34.306599 WDT: Not starting watchdog@f0d0
803 07:11:34.338687 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 07:11:34.351391 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 07:11:34.355340 ** Bad device specification mmc 0 **
806 07:11:34.366560 Card did not respond to voltage select! : -110
807 07:11:34.374112 ** Bad device specification mmc 0 **
808 07:11:34.374552 Couldn't find partition mmc 0
809 07:11:34.382496 Card did not respond to voltage select! : -110
810 07:11:34.388019 ** Bad device specification mmc 0 **
811 07:11:34.388462 Couldn't find partition mmc 0
812 07:11:34.393091 Error: could not access storage.
813 07:11:34.735704 Net: eth0: ethernet@ff3f0000
814 07:11:34.736365 starting USB...
815 07:11:34.987513 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 07:11:34.988203 Starting the controller
817 07:11:34.994405 USB XHCI 1.10
818 07:11:37.279726 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 07:11:37.280376 bl2_stage_init 0x01
820 07:11:37.280810 bl2_stage_init 0x81
821 07:11:37.281225 hw id: 0x0000 - pwm id 0x01
822 07:11:37.281633 bl2_stage_init 0xc1
823 07:11:37.282035 bl2_stage_init 0x02
824 07:11:37.282434
825 07:11:37.282832 L0:00000000
826 07:11:37.283227 L1:20000703
827 07:11:37.283621 L2:00008067
828 07:11:37.284047 L3:14000000
829 07:11:37.284455 B2:00402000
830 07:11:37.285264 B1:e0f83180
831 07:11:37.285694
832 07:11:37.286096 TE: 58167
833 07:11:37.286495
834 07:11:37.286894 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 07:11:37.287290
836 07:11:37.287681 Board ID = 1
837 07:11:37.288105 Set A53 clk to 24M
838 07:11:37.288502 Set A73 clk to 24M
839 07:11:37.288890 Set clk81 to 24M
840 07:11:37.289270 A53 clk: 1200 MHz
841 07:11:37.289655 A73 clk: 1200 MHz
842 07:11:37.290040 CLK81: 166.6M
843 07:11:37.290429 smccc: 00012abd
844 07:11:37.290817 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 07:11:37.291207 board id: 1
846 07:11:37.291594 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 07:11:37.292004 fw parse done
848 07:11:37.292403 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 07:11:37.292796 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 07:11:37.293186 PIEI prepare done
851 07:11:37.293571 fastboot data load
852 07:11:37.293960 fastboot data verify
853 07:11:37.294346 verify result: 266
854 07:11:37.294823 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 07:11:37.295228 LPDDR4 probe
856 07:11:37.295617 ddr clk to 1584MHz
857 07:11:37.296040 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 07:11:37.331849
859 07:11:37.332450 dmc_version 0001
860 07:11:37.338520 Check phy result
861 07:11:37.344325 INFO : End of CA training
862 07:11:37.344776 INFO : End of initialization
863 07:11:37.349951 INFO : Training has run successfully!
864 07:11:37.350387 Check phy result
865 07:11:37.355583 INFO : End of initialization
866 07:11:37.356052 INFO : End of read enable training
867 07:11:37.361107 INFO : End of fine write leveling
868 07:11:37.366677 INFO : End of Write leveling coarse delay
869 07:11:37.367108 INFO : Training has run successfully!
870 07:11:37.367514 Check phy result
871 07:11:37.372292 INFO : End of initialization
872 07:11:37.372727 INFO : End of read dq deskew training
873 07:11:37.377887 INFO : End of MPR read delay center optimization
874 07:11:37.383561 INFO : End of write delay center optimization
875 07:11:37.389197 INFO : End of read delay center optimization
876 07:11:37.389633 INFO : End of max read latency training
877 07:11:37.394669 INFO : Training has run successfully!
878 07:11:37.395153 1D training succeed
879 07:11:37.403867 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 07:11:37.451539 Check phy result
881 07:11:37.452163 INFO : End of initialization
882 07:11:37.473054 INFO : End of 2D read delay Voltage center optimization
883 07:11:37.493211 INFO : End of 2D read delay Voltage center optimization
884 07:11:37.545185 INFO : End of 2D write delay Voltage center optimization
885 07:11:37.594417 INFO : End of 2D write delay Voltage center optimization
886 07:11:37.599940 INFO : Training has run successfully!
887 07:11:37.600464
888 07:11:37.600894 channel==0
889 07:11:37.605537 RxClkDly_Margin_A0==88 ps 9
890 07:11:37.606062 TxDqDly_Margin_A0==98 ps 10
891 07:11:37.608864 RxClkDly_Margin_A1==88 ps 9
892 07:11:37.609513 TxDqDly_Margin_A1==88 ps 9
893 07:11:37.614399 TrainedVREFDQ_A0==74
894 07:11:37.614924 TrainedVREFDQ_A1==75
895 07:11:37.615351 VrefDac_Margin_A0==25
896 07:11:37.620066 DeviceVref_Margin_A0==40
897 07:11:37.620530 VrefDac_Margin_A1==25
898 07:11:37.625617 DeviceVref_Margin_A1==39
899 07:11:37.626083
900 07:11:37.626474
901 07:11:37.626860 channel==1
902 07:11:37.627240 RxClkDly_Margin_A0==98 ps 10
903 07:11:37.631185 TxDqDly_Margin_A0==98 ps 10
904 07:11:37.631604 RxClkDly_Margin_A1==98 ps 10
905 07:11:37.636844 TxDqDly_Margin_A1==88 ps 9
906 07:11:37.637271 TrainedVREFDQ_A0==77
907 07:11:37.637660 TrainedVREFDQ_A1==77
908 07:11:37.642409 VrefDac_Margin_A0==22
909 07:11:37.642888 DeviceVref_Margin_A0==37
910 07:11:37.648046 VrefDac_Margin_A1==22
911 07:11:37.648466 DeviceVref_Margin_A1==37
912 07:11:37.648859
913 07:11:37.653607 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 07:11:37.654025
915 07:11:37.681648 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
916 07:11:37.687226 2D training succeed
917 07:11:37.692780 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 07:11:37.693216 auto size-- 65535DDR cs0 size: 2048MB
919 07:11:37.698313 DDR cs1 size: 2048MB
920 07:11:37.698730 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 07:11:37.703914 cs0 DataBus test pass
922 07:11:37.704367 cs1 DataBus test pass
923 07:11:37.704753 cs0 AddrBus test pass
924 07:11:37.709526 cs1 AddrBus test pass
925 07:11:37.709962
926 07:11:37.710354 100bdlr_step_size ps== 420
927 07:11:37.710751 result report
928 07:11:37.715108 boot times 0Enable ddr reg access
929 07:11:37.722713 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 07:11:37.736211 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 07:11:38.308280 0.0;M3 CHK:0;cm4_sp_mode 0
932 07:11:38.308916 MVN_1=0x00000000
933 07:11:38.313714 MVN_2=0x00000000
934 07:11:38.319498 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 07:11:38.319948 OPS=0x10
936 07:11:38.320411 ring efuse init
937 07:11:38.320817 chipver efuse init
938 07:11:38.325096 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 07:11:38.330678 [0.018961 Inits done]
940 07:11:38.331111 secure task start!
941 07:11:38.331518 high task start!
942 07:11:38.335242 low task start!
943 07:11:38.335674 run into bl31
944 07:11:38.341882 NOTICE: BL31: v1.3(release):4fc40b1
945 07:11:38.349677 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 07:11:38.350121 NOTICE: BL31: G12A normal boot!
947 07:11:38.375104 NOTICE: BL31: BL33 decompress pass
948 07:11:38.380797 ERROR: Error initializing runtime service opteed_fast
949 07:11:39.613628
950 07:11:39.614043
951 07:11:39.622025 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 07:11:39.622465
953 07:11:39.622838 Model: Libre Computer AML-A311D-CC Alta
954 07:11:39.830678 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 07:11:39.854038 DRAM: 2 GiB (effective 3.8 GiB)
956 07:11:39.996968 Core: 408 devices, 31 uclasses, devicetree: separate
957 07:11:40.002919 WDT: Not starting watchdog@f0d0
958 07:11:40.035063 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 07:11:40.047501 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 07:11:40.052519 ** Bad device specification mmc 0 **
961 07:11:40.062938 Card did not respond to voltage select! : -110
962 07:11:40.070493 ** Bad device specification mmc 0 **
963 07:11:40.071008 Couldn't find partition mmc 0
964 07:11:40.078932 Card did not respond to voltage select! : -110
965 07:11:40.084350 ** Bad device specification mmc 0 **
966 07:11:40.084861 Couldn't find partition mmc 0
967 07:11:40.089407 Error: could not access storage.
968 07:11:40.432938 Net: eth0: ethernet@ff3f0000
969 07:11:40.433605 starting USB...
970 07:11:40.684753 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 07:11:40.685376 Starting the controller
972 07:11:40.691685 USB XHCI 1.10
973 07:11:42.554302 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 07:11:42.554960 bl2_stage_init 0x01
975 07:11:42.555432 bl2_stage_init 0x81
976 07:11:42.559927 hw id: 0x0000 - pwm id 0x01
977 07:11:42.560488 bl2_stage_init 0xc1
978 07:11:42.560952 bl2_stage_init 0x02
979 07:11:42.561403
980 07:11:42.565501 L0:00000000
981 07:11:42.566012 L1:20000703
982 07:11:42.566467 L2:00008067
983 07:11:42.566913 L3:14000000
984 07:11:42.571151 B2:00402000
985 07:11:42.571649 B1:e0f83180
986 07:11:42.572136
987 07:11:42.572591 TE: 58159
988 07:11:42.573039
989 07:11:42.576685 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 07:11:42.577193
991 07:11:42.577648 Board ID = 1
992 07:11:42.582319 Set A53 clk to 24M
993 07:11:42.582818 Set A73 clk to 24M
994 07:11:42.583268 Set clk81 to 24M
995 07:11:42.587902 A53 clk: 1200 MHz
996 07:11:42.588460 A73 clk: 1200 MHz
997 07:11:42.588916 CLK81: 166.6M
998 07:11:42.589360 smccc: 00012ab5
999 07:11:42.593481 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 07:11:42.599151 board id: 1
1001 07:11:42.604994 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 07:11:42.615641 fw parse done
1003 07:11:42.621662 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 07:11:42.664212 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 07:11:42.675138 PIEI prepare done
1006 07:11:42.675628 fastboot data load
1007 07:11:42.676128 fastboot data verify
1008 07:11:42.680777 verify result: 266
1009 07:11:42.686410 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 07:11:42.686902 LPDDR4 probe
1011 07:11:42.687335 ddr clk to 1584MHz
1012 07:11:42.694658 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 07:11:42.731815
1014 07:11:42.732351 dmc_version 0001
1015 07:11:42.738477 Check phy result
1016 07:11:42.744391 INFO : End of CA training
1017 07:11:42.744885 INFO : End of initialization
1018 07:11:42.749977 INFO : Training has run successfully!
1019 07:11:42.750463 Check phy result
1020 07:11:42.755535 INFO : End of initialization
1021 07:11:42.756062 INFO : End of read enable training
1022 07:11:42.758940 INFO : End of fine write leveling
1023 07:11:42.764543 INFO : End of Write leveling coarse delay
1024 07:11:42.770052 INFO : Training has run successfully!
1025 07:11:42.770555 Check phy result
1026 07:11:42.771009 INFO : End of initialization
1027 07:11:42.775696 INFO : End of read dq deskew training
1028 07:11:42.779143 INFO : End of MPR read delay center optimization
1029 07:11:42.784710 INFO : End of write delay center optimization
1030 07:11:42.790228 INFO : End of read delay center optimization
1031 07:11:42.790723 INFO : End of max read latency training
1032 07:11:42.795765 INFO : Training has run successfully!
1033 07:11:42.796295 1D training succeed
1034 07:11:42.803850 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 07:11:42.851410 Check phy result
1036 07:11:42.851917 INFO : End of initialization
1037 07:11:42.873143 INFO : End of 2D read delay Voltage center optimization
1038 07:11:42.893451 INFO : End of 2D read delay Voltage center optimization
1039 07:11:42.945524 INFO : End of 2D write delay Voltage center optimization
1040 07:11:42.994845 INFO : End of 2D write delay Voltage center optimization
1041 07:11:43.000419 INFO : Training has run successfully!
1042 07:11:43.000918
1043 07:11:43.001373 channel==0
1044 07:11:43.006027 RxClkDly_Margin_A0==88 ps 9
1045 07:11:43.006526 TxDqDly_Margin_A0==98 ps 10
1046 07:11:43.011659 RxClkDly_Margin_A1==88 ps 9
1047 07:11:43.012193 TxDqDly_Margin_A1==98 ps 10
1048 07:11:43.012657 TrainedVREFDQ_A0==74
1049 07:11:43.017235 TrainedVREFDQ_A1==74
1050 07:11:43.017739 VrefDac_Margin_A0==25
1051 07:11:43.018191 DeviceVref_Margin_A0==40
1052 07:11:43.022920 VrefDac_Margin_A1==25
1053 07:11:43.023424 DeviceVref_Margin_A1==40
1054 07:11:43.023880
1055 07:11:43.024368
1056 07:11:43.024812 channel==1
1057 07:11:43.028534 RxClkDly_Margin_A0==98 ps 10
1058 07:11:43.029036 TxDqDly_Margin_A0==98 ps 10
1059 07:11:43.034090 RxClkDly_Margin_A1==98 ps 10
1060 07:11:43.034587 TxDqDly_Margin_A1==88 ps 9
1061 07:11:43.035584 TrainedVREFDQ_A0==77
1062 07:11:43.041005 TrainedVREFDQ_A1==77
1063 07:11:43.041501 VrefDac_Margin_A0==22
1064 07:11:43.046543 DeviceVref_Margin_A0==37
1065 07:11:43.047036 VrefDac_Margin_A1==22
1066 07:11:43.047486 DeviceVref_Margin_A1==37
1067 07:11:43.047928
1068 07:11:43.052159 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 07:11:43.052659
1070 07:11:43.083694 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1071 07:11:43.084261 2D training succeed
1072 07:11:43.089362 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 07:11:43.094849 auto size-- 65535DDR cs0 size: 2048MB
1074 07:11:43.095346 DDR cs1 size: 2048MB
1075 07:11:43.100430 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 07:11:43.100928 cs0 DataBus test pass
1077 07:11:43.106000 cs1 DataBus test pass
1078 07:11:43.106493 cs0 AddrBus test pass
1079 07:11:43.106938 cs1 AddrBus test pass
1080 07:11:43.111605
1081 07:11:43.112140 100bdlr_step_size ps== 420
1082 07:11:43.112608 result report
1083 07:11:43.117210 boot times 0Enable ddr reg access
1084 07:11:43.123377 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 07:11:43.136790 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 07:11:43.710527 0.0;M3 CHK:0;cm4_sp_mode 0
1087 07:11:43.711134 MVN_1=0x00000000
1088 07:11:43.716018 MVN_2=0x00000000
1089 07:11:43.721734 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 07:11:43.722242 OPS=0x10
1091 07:11:43.722695 ring efuse init
1092 07:11:43.723135 chipver efuse init
1093 07:11:43.730003 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 07:11:43.730514 [0.018960 Inits done]
1095 07:11:43.730969 secure task start!
1096 07:11:43.737504 high task start!
1097 07:11:43.738000 low task start!
1098 07:11:43.738453 run into bl31
1099 07:11:43.744165 NOTICE: BL31: v1.3(release):4fc40b1
1100 07:11:43.751956 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 07:11:43.752494 NOTICE: BL31: G12A normal boot!
1102 07:11:43.777245 NOTICE: BL31: BL33 decompress pass
1103 07:11:43.782943 ERROR: Error initializing runtime service opteed_fast
1104 07:11:45.015794
1105 07:11:45.016450
1106 07:11:45.024268 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 07:11:45.024782
1108 07:11:45.025238 Model: Libre Computer AML-A311D-CC Alta
1109 07:11:45.232659 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 07:11:45.256099 DRAM: 2 GiB (effective 3.8 GiB)
1111 07:11:45.398995 Core: 408 devices, 31 uclasses, devicetree: separate
1112 07:11:45.404873 WDT: Not starting watchdog@f0d0
1113 07:11:45.437129 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 07:11:45.449615 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 07:11:45.454609 ** Bad device specification mmc 0 **
1116 07:11:45.464926 Card did not respond to voltage select! : -110
1117 07:11:45.472613 ** Bad device specification mmc 0 **
1118 07:11:45.473118 Couldn't find partition mmc 0
1119 07:11:45.480913 Card did not respond to voltage select! : -110
1120 07:11:45.486420 ** Bad device specification mmc 0 **
1121 07:11:45.486915 Couldn't find partition mmc 0
1122 07:11:45.491507 Error: could not access storage.
1123 07:11:45.834011 Net: eth0: ethernet@ff3f0000
1124 07:11:45.834634 starting USB...
1125 07:11:46.085908 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 07:11:46.086528 Starting the controller
1127 07:11:46.092850 USB XHCI 1.10
1128 07:11:47.646802 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 07:11:47.655277 scanning usb for storage devices... 0 Storage Device(s) found
1131 07:11:47.706936 Hit any key to stop autoboot: 1
1132 07:11:47.707754 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 07:11:47.708912 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1134 07:11:47.709461 Setting prompt string to ['=>']
1135 07:11:47.709991 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1136 07:11:47.722613 0
1137 07:11:47.723532 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 07:11:47.724093 Sending with 10 millisecond of delay
1140 07:11:48.858833 => setenv autoload no
1141 07:11:48.869677 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1142 07:11:48.875026 setenv autoload no
1143 07:11:48.875814 Sending with 10 millisecond of delay
1145 07:11:50.672636 => setenv initrd_high 0xffffffff
1146 07:11:50.683426 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1147 07:11:50.684386 setenv initrd_high 0xffffffff
1148 07:11:50.685150 Sending with 10 millisecond of delay
1150 07:11:52.301754 => setenv fdt_high 0xffffffff
1151 07:11:52.312666 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1152 07:11:52.313607 setenv fdt_high 0xffffffff
1153 07:11:52.314376 Sending with 10 millisecond of delay
1155 07:11:52.606286 => dhcp
1156 07:11:52.617199 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 07:11:52.617746 dhcp
1158 07:11:52.617978 Speed: 1000, full duplex
1159 07:11:52.618189 BOOTP broadcast 1
1160 07:11:52.866248 BOOTP broadcast 2
1161 07:11:52.877899 DHCP client bound to address 192.168.6.33 (261 ms)
1162 07:11:52.878450 Sending with 10 millisecond of delay
1164 07:11:54.554695 => setenv serverip 192.168.6.2
1165 07:11:54.565621 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 07:11:54.566730 setenv serverip 192.168.6.2
1167 07:11:54.567523 Sending with 10 millisecond of delay
1169 07:11:58.292435 => tftpboot 0x01080000 714886/tftp-deploy-s2nor1jz/kernel/uImage
1170 07:11:58.303407 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 07:11:58.304484 tftpboot 0x01080000 714886/tftp-deploy-s2nor1jz/kernel/uImage
1172 07:11:58.305077 Speed: 1000, full duplex
1173 07:11:58.305524 Using ethernet@ff3f0000 device
1174 07:11:58.306297 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1175 07:11:58.311875 Filename '714886/tftp-deploy-s2nor1jz/kernel/uImage'.
1176 07:11:58.315807 Load address: 0x1080000
1177 07:12:01.173521 Loading: *################################################## 43.2 MiB
1178 07:12:01.174163 15.1 MiB/s
1179 07:12:01.174642 done
1180 07:12:01.177746 Bytes transferred = 45308480 (2b35a40 hex)
1181 07:12:01.178530 Sending with 10 millisecond of delay
1183 07:12:05.867238 => tftpboot 0x08000000 714886/tftp-deploy-s2nor1jz/ramdisk/ramdisk.cpio.gz.uboot
1184 07:12:05.878188 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 07:12:05.879234 tftpboot 0x08000000 714886/tftp-deploy-s2nor1jz/ramdisk/ramdisk.cpio.gz.uboot
1186 07:12:05.879722 Speed: 1000, full duplex
1187 07:12:05.880218 Using ethernet@ff3f0000 device
1188 07:12:05.881001 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1189 07:12:05.889651 Filename '714886/tftp-deploy-s2nor1jz/ramdisk/ramdisk.cpio.gz.uboot'.
1190 07:12:05.890281 Load address: 0x8000000
1191 07:12:12.492404 Loading: *######################T ########################### UDP wrong checksum 00000005 00003023
1192 07:12:17.494799 T UDP wrong checksum 00000005 00003023
1193 07:12:27.496291 T T UDP wrong checksum 00000005 00003023
1194 07:12:46.287827 T T T UDP wrong checksum 000000ff 000056b1
1195 07:12:46.305105 UDP wrong checksum 000000ff 0000daa3
1196 07:12:47.500608 T UDP wrong checksum 00000005 00003023
1197 07:12:58.248780 T T UDP wrong checksum 000000ff 000040aa
1198 07:12:58.269933 UDP wrong checksum 000000ff 0000d89c
1199 07:13:02.432404 UDP wrong checksum 000000ff 0000c2c8
1200 07:13:02.454467 UDP wrong checksum 000000ff 00004bbb
1201 07:13:02.504873
1202 07:13:02.505449 Retry count exceeded; starting again
1204 07:13:02.506992 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1207 07:13:02.509093 end: 2.4 uboot-commands (duration 00:01:52) [common]
1209 07:13:02.510607 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1211 07:13:02.511749 end: 2 uboot-action (duration 00:01:52) [common]
1213 07:13:02.513490 Cleaning after the job
1214 07:13:02.514121 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/ramdisk
1215 07:13:02.515507 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/kernel
1216 07:13:02.564747 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/dtb
1217 07:13:02.565622 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/nfsrootfs
1218 07:13:02.740640 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714886/tftp-deploy-s2nor1jz/modules
1219 07:13:02.762262 start: 4.1 power-off (timeout 00:00:30) [common]
1220 07:13:02.762954 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1221 07:13:02.796458 >> OK - accepted request
1222 07:13:02.798821 Returned 0 in 0 seconds
1223 07:13:02.899604 end: 4.1 power-off (duration 00:00:00) [common]
1225 07:13:02.900627 start: 4.2 read-feedback (timeout 00:10:00) [common]
1226 07:13:02.901296 Listened to connection for namespace 'common' for up to 1s
1227 07:13:03.901925 Finalising connection for namespace 'common'
1228 07:13:03.902427 Disconnecting from shell: Finalise
1229 07:13:03.902725 =>
1230 07:13:04.003402 end: 4.2 read-feedback (duration 00:00:01) [common]
1231 07:13:04.003858 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714886
1232 07:13:06.953740 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714886
1233 07:13:06.954372 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.