Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:53:31.146385 lava-dispatcher, installed at version: 2024.01
2 06:53:31.147160 start: 0 validate
3 06:53:31.147616 Start time: 2024-09-06 06:53:31.147586+00:00 (UTC)
4 06:53:31.148172 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:53:31.148708 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:53:31.186184 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:53:31.186732 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:53:31.216531 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:53:31.217130 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 06:53:31.249869 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:53:31.250463 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:53:31.280832 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:53:31.281335 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 06:53:31.319341 validate duration: 0.17
16 06:53:31.320459 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:53:31.320877 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:53:31.321256 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:53:31.321949 Not decompressing ramdisk as can be used compressed.
20 06:53:31.322479 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 06:53:31.322816 saving as /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/ramdisk/initrd.cpio.gz
22 06:53:31.323171 total size: 5628169 (5 MB)
23 06:53:31.359689 progress 0 % (0 MB)
24 06:53:31.364750 progress 5 % (0 MB)
25 06:53:31.369924 progress 10 % (0 MB)
26 06:53:31.374548 progress 15 % (0 MB)
27 06:53:31.379641 progress 20 % (1 MB)
28 06:53:31.384071 progress 25 % (1 MB)
29 06:53:31.389088 progress 30 % (1 MB)
30 06:53:31.394043 progress 35 % (1 MB)
31 06:53:31.398516 progress 40 % (2 MB)
32 06:53:31.403478 progress 45 % (2 MB)
33 06:53:31.407882 progress 50 % (2 MB)
34 06:53:31.412894 progress 55 % (2 MB)
35 06:53:31.417871 progress 60 % (3 MB)
36 06:53:31.422281 progress 65 % (3 MB)
37 06:53:31.427121 progress 70 % (3 MB)
38 06:53:31.431562 progress 75 % (4 MB)
39 06:53:31.436456 progress 80 % (4 MB)
40 06:53:31.440841 progress 85 % (4 MB)
41 06:53:31.445721 progress 90 % (4 MB)
42 06:53:31.450551 progress 95 % (5 MB)
43 06:53:31.454491 progress 100 % (5 MB)
44 06:53:31.455278 5 MB downloaded in 0.13 s (40.64 MB/s)
45 06:53:31.455919 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:53:31.457049 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:53:31.457411 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:53:31.457744 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:53:31.458316 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
51 06:53:31.458620 saving as /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/kernel/Image
52 06:53:31.458876 total size: 45308416 (43 MB)
53 06:53:31.459130 No compression specified
54 06:53:31.498009 progress 0 % (0 MB)
55 06:53:31.530809 progress 5 % (2 MB)
56 06:53:31.564017 progress 10 % (4 MB)
57 06:53:31.596250 progress 15 % (6 MB)
58 06:53:31.628382 progress 20 % (8 MB)
59 06:53:31.660742 progress 25 % (10 MB)
60 06:53:31.687351 progress 30 % (12 MB)
61 06:53:31.714426 progress 35 % (15 MB)
62 06:53:31.741974 progress 40 % (17 MB)
63 06:53:31.769199 progress 45 % (19 MB)
64 06:53:31.796930 progress 50 % (21 MB)
65 06:53:31.824009 progress 55 % (23 MB)
66 06:53:31.851886 progress 60 % (25 MB)
67 06:53:31.880464 progress 65 % (28 MB)
68 06:53:31.908561 progress 70 % (30 MB)
69 06:53:31.936134 progress 75 % (32 MB)
70 06:53:31.963768 progress 80 % (34 MB)
71 06:53:31.991198 progress 85 % (36 MB)
72 06:53:32.019059 progress 90 % (38 MB)
73 06:53:32.046674 progress 95 % (41 MB)
74 06:53:32.073632 progress 100 % (43 MB)
75 06:53:32.074305 43 MB downloaded in 0.62 s (70.21 MB/s)
76 06:53:32.074788 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:53:32.075616 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:53:32.075896 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:53:32.076198 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:53:32.076677 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 06:53:32.076984 saving as /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 06:53:32.077200 total size: 53173 (0 MB)
84 06:53:32.077411 No compression specified
85 06:53:32.116654 progress 61 % (0 MB)
86 06:53:32.117643 progress 100 % (0 MB)
87 06:53:32.118296 0 MB downloaded in 0.04 s (1.23 MB/s)
88 06:53:32.118887 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:53:32.119884 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:53:32.120250 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:53:32.120575 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:53:32.121129 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 06:53:32.121435 saving as /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/nfsrootfs/full.rootfs.tar
95 06:53:32.121687 total size: 120894716 (115 MB)
96 06:53:32.121944 Using unxz to decompress xz
97 06:53:32.156081 progress 0 % (0 MB)
98 06:53:32.939665 progress 5 % (5 MB)
99 06:53:33.771912 progress 10 % (11 MB)
100 06:53:34.584080 progress 15 % (17 MB)
101 06:53:35.453826 progress 20 % (23 MB)
102 06:53:36.101881 progress 25 % (28 MB)
103 06:53:36.918373 progress 30 % (34 MB)
104 06:53:37.708377 progress 35 % (40 MB)
105 06:53:38.078959 progress 40 % (46 MB)
106 06:53:38.468162 progress 45 % (51 MB)
107 06:53:39.190961 progress 50 % (57 MB)
108 06:53:40.081348 progress 55 % (63 MB)
109 06:53:40.869365 progress 60 % (69 MB)
110 06:53:41.628034 progress 65 % (74 MB)
111 06:53:42.413401 progress 70 % (80 MB)
112 06:53:43.245713 progress 75 % (86 MB)
113 06:53:44.048240 progress 80 % (92 MB)
114 06:53:44.821909 progress 85 % (98 MB)
115 06:53:45.677696 progress 90 % (103 MB)
116 06:53:46.462762 progress 95 % (109 MB)
117 06:53:47.302364 progress 100 % (115 MB)
118 06:53:47.315178 115 MB downloaded in 15.19 s (7.59 MB/s)
119 06:53:47.316202 end: 1.4.1 http-download (duration 00:00:15) [common]
121 06:53:47.317861 end: 1.4 download-retry (duration 00:00:15) [common]
122 06:53:47.318382 start: 1.5 download-retry (timeout 00:09:44) [common]
123 06:53:47.318882 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 06:53:47.319685 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
125 06:53:47.320168 saving as /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/modules/modules.tar
126 06:53:47.320566 total size: 11502724 (10 MB)
127 06:53:47.320971 Using unxz to decompress xz
128 06:53:47.366088 progress 0 % (0 MB)
129 06:53:47.435559 progress 5 % (0 MB)
130 06:53:47.513387 progress 10 % (1 MB)
131 06:53:47.599499 progress 15 % (1 MB)
132 06:53:47.680689 progress 20 % (2 MB)
133 06:53:47.758067 progress 25 % (2 MB)
134 06:53:47.841061 progress 30 % (3 MB)
135 06:53:47.916700 progress 35 % (3 MB)
136 06:53:47.997736 progress 40 % (4 MB)
137 06:53:48.071250 progress 45 % (4 MB)
138 06:53:48.149369 progress 50 % (5 MB)
139 06:53:48.226249 progress 55 % (6 MB)
140 06:53:48.306462 progress 60 % (6 MB)
141 06:53:48.393007 progress 65 % (7 MB)
142 06:53:48.471526 progress 70 % (7 MB)
143 06:53:48.571462 progress 75 % (8 MB)
144 06:53:48.661155 progress 80 % (8 MB)
145 06:53:48.749485 progress 85 % (9 MB)
146 06:53:48.820633 progress 90 % (9 MB)
147 06:53:48.897140 progress 95 % (10 MB)
148 06:53:48.973428 progress 100 % (10 MB)
149 06:53:48.983558 10 MB downloaded in 1.66 s (6.60 MB/s)
150 06:53:48.984326 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:53:48.986294 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:53:48.986915 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 06:53:48.987443 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 06:54:05.498537 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/714807/extract-nfsrootfs-5fk5qvuz
156 06:54:05.499140 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 06:54:05.499462 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 06:54:05.500159 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd
159 06:54:05.500648 makedir: /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin
160 06:54:05.501046 makedir: /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/tests
161 06:54:05.501425 makedir: /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/results
162 06:54:05.501813 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-add-keys
163 06:54:05.502368 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-add-sources
164 06:54:05.502971 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-background-process-start
165 06:54:05.503519 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-background-process-stop
166 06:54:05.504113 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-common-functions
167 06:54:05.504631 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-echo-ipv4
168 06:54:05.505113 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-install-packages
169 06:54:05.505579 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-installed-packages
170 06:54:05.506046 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-os-build
171 06:54:05.506509 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-probe-channel
172 06:54:05.506970 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-probe-ip
173 06:54:05.507455 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-target-ip
174 06:54:05.507942 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-target-mac
175 06:54:05.508461 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-target-storage
176 06:54:05.508944 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-test-case
177 06:54:05.509417 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-test-event
178 06:54:05.509880 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-test-feedback
179 06:54:05.510346 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-test-raise
180 06:54:05.510929 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-test-reference
181 06:54:05.511444 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-test-runner
182 06:54:05.511960 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-test-set
183 06:54:05.512504 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-test-shell
184 06:54:05.513005 Updating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-add-keys (debian)
185 06:54:05.513538 Updating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-add-sources (debian)
186 06:54:05.514035 Updating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-install-packages (debian)
187 06:54:05.514527 Updating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-installed-packages (debian)
188 06:54:05.515015 Updating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/bin/lava-os-build (debian)
189 06:54:05.515439 Creating /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/environment
190 06:54:05.515806 LAVA metadata
191 06:54:05.516097 - LAVA_JOB_ID=714807
192 06:54:05.516317 - LAVA_DISPATCHER_IP=192.168.6.2
193 06:54:05.516689 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 06:54:05.517657 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 06:54:05.517967 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 06:54:05.518171 skipped lava-vland-overlay
197 06:54:05.518412 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 06:54:05.518664 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 06:54:05.518879 skipped lava-multinode-overlay
200 06:54:05.519121 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 06:54:05.519371 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 06:54:05.519616 Loading test definitions
203 06:54:05.519892 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 06:54:05.520139 Using /lava-714807 at stage 0
205 06:54:05.521264 uuid=714807_1.6.2.4.1 testdef=None
206 06:54:05.521590 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 06:54:05.521859 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 06:54:05.523409 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 06:54:05.524261 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 06:54:05.526181 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 06:54:05.526999 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 06:54:05.528870 runner path: /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/0/tests/0_timesync-off test_uuid 714807_1.6.2.4.1
215 06:54:05.529455 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 06:54:05.530279 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 06:54:05.530505 Using /lava-714807 at stage 0
219 06:54:05.530865 Fetching tests from https://github.com/kernelci/test-definitions.git
220 06:54:05.531158 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/0/tests/1_kselftest-kvm'
221 06:54:09.069185 Running '/usr/bin/git checkout kernelci.org
222 06:54:09.182443 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/0/tests/1_kselftest-kvm/automated/linux/kselftest/kselftest.yaml
223 06:54:09.183881 uuid=714807_1.6.2.4.5 testdef=None
224 06:54:09.184253 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 06:54:09.184998 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 06:54:09.188006 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 06:54:09.188827 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 06:54:09.192531 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 06:54:09.193504 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 06:54:09.197129 runner path: /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/0/tests/1_kselftest-kvm test_uuid 714807_1.6.2.4.5
234 06:54:09.197415 BOARD='meson-sm1-s905d3-libretech-cc'
235 06:54:09.197621 BRANCH='mainline'
236 06:54:09.197819 SKIPFILE='/dev/null'
237 06:54:09.198016 SKIP_INSTALL='True'
238 06:54:09.198211 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 06:54:09.198409 TST_CASENAME=''
240 06:54:09.198605 TST_CMDFILES='kvm'
241 06:54:09.199149 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 06:54:09.199934 Creating lava-test-runner.conf files
244 06:54:09.200164 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714807/lava-overlay-zil9wssd/lava-714807/0 for stage 0
245 06:54:09.200558 - 0_timesync-off
246 06:54:09.200804 - 1_kselftest-kvm
247 06:54:09.201135 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 06:54:09.201415 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 06:54:32.587106 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 06:54:32.587521 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 06:54:32.587781 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 06:54:32.588075 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 06:54:32.588346 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 06:54:33.205240 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 06:54:33.205724 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 06:54:33.205997 extracting modules file /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714807/extract-nfsrootfs-5fk5qvuz
257 06:54:34.588177 extracting modules file /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714807/extract-overlay-ramdisk-ndx0gjv5/ramdisk
258 06:54:35.965105 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 06:54:35.965550 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 06:54:35.965840 [common] Applying overlay to NFS
261 06:54:35.966065 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714807/compress-overlay-3o0ypeg7/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714807/extract-nfsrootfs-5fk5qvuz
262 06:54:38.698909 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 06:54:38.699400 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 06:54:38.699707 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 06:54:38.699973 Converting downloaded kernel to a uImage
266 06:54:38.700357 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/kernel/Image /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/kernel/uImage
267 06:54:39.154356 output: Image Name:
268 06:54:39.154785 output: Created: Fri Sep 6 06:54:38 2024
269 06:54:39.154994 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 06:54:39.155200 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
271 06:54:39.155403 output: Load Address: 01080000
272 06:54:39.155605 output: Entry Point: 01080000
273 06:54:39.155804 output:
274 06:54:39.156178 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 06:54:39.156459 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 06:54:39.156733 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 06:54:39.156995 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 06:54:39.157257 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 06:54:39.157518 Building ramdisk /var/lib/lava/dispatcher/tmp/714807/extract-overlay-ramdisk-ndx0gjv5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714807/extract-overlay-ramdisk-ndx0gjv5/ramdisk
280 06:54:41.298516 >> 165160 blocks
281 06:54:48.947891 Adding RAMdisk u-boot header.
282 06:54:48.948615 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714807/extract-overlay-ramdisk-ndx0gjv5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714807/extract-overlay-ramdisk-ndx0gjv5/ramdisk.cpio.gz.uboot
283 06:54:49.187416 output: Image Name:
284 06:54:49.187849 output: Created: Fri Sep 6 06:54:48 2024
285 06:54:49.188369 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 06:54:49.188837 output: Data Size: 23258319 Bytes = 22713.20 KiB = 22.18 MiB
287 06:54:49.189292 output: Load Address: 00000000
288 06:54:49.189738 output: Entry Point: 00000000
289 06:54:49.190187 output:
290 06:54:49.191263 rename /var/lib/lava/dispatcher/tmp/714807/extract-overlay-ramdisk-ndx0gjv5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/ramdisk/ramdisk.cpio.gz.uboot
291 06:54:49.192088 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 06:54:49.192716 end: 1.6 prepare-tftp-overlay (duration 00:01:00) [common]
293 06:54:49.193313 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 06:54:49.193832 No LXC device requested
295 06:54:49.194402 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 06:54:49.194975 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 06:54:49.195531 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 06:54:49.196130 Checking files for TFTP limit of 4294967296 bytes.
299 06:54:49.199074 end: 1 tftp-deploy (duration 00:01:18) [common]
300 06:54:49.199712 start: 2 uboot-action (timeout 00:05:00) [common]
301 06:54:49.200343 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 06:54:49.200913 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 06:54:49.201483 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 06:54:49.202071 Using kernel file from prepare-kernel: 714807/tftp-deploy-0gj4i42x/kernel/uImage
305 06:54:49.202769 substitutions:
306 06:54:49.203232 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 06:54:49.203685 - {DTB_ADDR}: 0x01070000
308 06:54:49.204171 - {DTB}: 714807/tftp-deploy-0gj4i42x/dtb/meson-sm1-s905d3-libretech-cc.dtb
309 06:54:49.204634 - {INITRD}: 714807/tftp-deploy-0gj4i42x/ramdisk/ramdisk.cpio.gz.uboot
310 06:54:49.205079 - {KERNEL_ADDR}: 0x01080000
311 06:54:49.205520 - {KERNEL}: 714807/tftp-deploy-0gj4i42x/kernel/uImage
312 06:54:49.205961 - {LAVA_MAC}: None
313 06:54:49.206461 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/714807/extract-nfsrootfs-5fk5qvuz
314 06:54:49.206911 - {NFS_SERVER_IP}: 192.168.6.2
315 06:54:49.207346 - {PRESEED_CONFIG}: None
316 06:54:49.207783 - {PRESEED_LOCAL}: None
317 06:54:49.208256 - {RAMDISK_ADDR}: 0x08000000
318 06:54:49.208697 - {RAMDISK}: 714807/tftp-deploy-0gj4i42x/ramdisk/ramdisk.cpio.gz.uboot
319 06:54:49.209133 - {ROOT_PART}: None
320 06:54:49.209569 - {ROOT}: None
321 06:54:49.210005 - {SERVER_IP}: 192.168.6.2
322 06:54:49.210441 - {TEE_ADDR}: 0x83000000
323 06:54:49.210874 - {TEE}: None
324 06:54:49.211306 Parsed boot commands:
325 06:54:49.211726 - setenv autoload no
326 06:54:49.212191 - setenv initrd_high 0xffffffff
327 06:54:49.212626 - setenv fdt_high 0xffffffff
328 06:54:49.213056 - dhcp
329 06:54:49.213483 - setenv serverip 192.168.6.2
330 06:54:49.213915 - tftpboot 0x01080000 714807/tftp-deploy-0gj4i42x/kernel/uImage
331 06:54:49.214351 - tftpboot 0x08000000 714807/tftp-deploy-0gj4i42x/ramdisk/ramdisk.cpio.gz.uboot
332 06:54:49.214782 - tftpboot 0x01070000 714807/tftp-deploy-0gj4i42x/dtb/meson-sm1-s905d3-libretech-cc.dtb
333 06:54:49.215216 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/714807/extract-nfsrootfs-5fk5qvuz,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 06:54:49.215662 - bootm 0x01080000 0x08000000 0x01070000
335 06:54:49.216286 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 06:54:49.217962 start: 2.3 connect-device (timeout 00:05:00) [common]
338 06:54:49.218438 [common] connect-device Connecting to device using 'telnet conserv1 3008'
339 06:54:49.235326 Setting prompt string to ['lava-test: # ']
340 06:54:49.237037 end: 2.3 connect-device (duration 00:00:00) [common]
341 06:54:49.237740 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 06:54:49.238394 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 06:54:49.239003 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 06:54:49.240530 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
345 06:54:49.278147 >> OK - accepted request
346 06:54:49.281625 Returned 0 in 0 seconds
347 06:54:49.383029 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 06:54:49.388628 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 06:54:49.389360 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 06:54:49.389976 Setting prompt string to ['Hit any key to stop autoboot']
352 06:54:49.390509 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 06:54:49.392358 Trying 192.168.56.21...
354 06:54:49.392918 Connected to conserv1.
355 06:54:49.393384 Escape character is '^]'.
356 06:54:49.393852
357 06:54:49.394334 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 06:54:49.394852
359 06:54:57.033670 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
360 06:54:57.034315 bl2_stage_init 0x01
361 06:54:57.034766 bl2_stage_init 0x81
362 06:54:57.039207 hw id: 0x0000 - pwm id 0x01
363 06:54:57.039738 bl2_stage_init 0xc1
364 06:54:57.043529 bl2_stage_init 0x02
365 06:54:57.044007
366 06:54:57.044454 L0:00000000
367 06:54:57.044878 L1:00000703
368 06:54:57.045290 L2:00008067
369 06:54:57.048985 L3:15000000
370 06:54:57.049452 S1:00000000
371 06:54:57.049868 B2:20282000
372 06:54:57.050277 B1:a0f83180
373 06:54:57.050671
374 06:54:57.051064 TE: 69618
375 06:54:57.054626
376 06:54:57.060167 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
377 06:54:57.060621
378 06:54:57.061025 Board ID = 1
379 06:54:57.061415 Set cpu clk to 24M
380 06:54:57.061802 Set clk81 to 24M
381 06:54:57.064146 Use GP1_pll as DSU clk.
382 06:54:57.069502 DSU clk: 1200 Mhz
383 06:54:57.069952 CPU clk: 1200 MHz
384 06:54:57.070354 Set clk81 to 166.6M
385 06:54:57.074964 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
386 06:54:57.080571 board id: 1
387 06:54:57.084754 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 06:54:57.096183 fw parse done
389 06:54:57.101498 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 06:54:57.144161 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 06:54:57.155601 PIEI prepare done
392 06:54:57.156120 fastboot data load
393 06:54:57.156547 fastboot data verify
394 06:54:57.161219 verify result: 266
395 06:54:57.166834 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
396 06:54:57.167304 LPDDR4 probe
397 06:54:57.167705 ddr clk to 1584MHz
398 06:54:57.173928 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 06:54:57.212135
400 06:54:57.212696 dmc_version 0001
401 06:54:57.218282 Check phy result
402 06:54:57.224714 INFO : End of CA training
403 06:54:57.225178 INFO : End of initialization
404 06:54:57.230241 INFO : Training has run successfully!
405 06:54:57.230708 Check phy result
406 06:54:57.235874 INFO : End of initialization
407 06:54:57.236340 INFO : End of read enable training
408 06:54:57.241463 INFO : End of fine write leveling
409 06:54:57.247071 INFO : End of Write leveling coarse delay
410 06:54:57.247578 INFO : Training has run successfully!
411 06:54:57.248017 Check phy result
412 06:54:57.252630 INFO : End of initialization
413 06:54:57.253085 INFO : End of read dq deskew training
414 06:54:57.258278 INFO : End of MPR read delay center optimization
415 06:54:57.263876 INFO : End of write delay center optimization
416 06:54:57.269456 INFO : End of read delay center optimization
417 06:54:57.269925 INFO : End of max read latency training
418 06:54:57.275057 INFO : Training has run successfully!
419 06:54:57.275507 1D training succeed
420 06:54:57.284062 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 06:54:57.331561 Check phy result
422 06:54:57.332195 INFO : End of initialization
423 06:54:57.354216 INFO : End of 2D read delay Voltage center optimization
424 06:54:57.373418 INFO : End of 2D read delay Voltage center optimization
425 06:54:57.425106 INFO : End of 2D write delay Voltage center optimization
426 06:54:57.474518 INFO : End of 2D write delay Voltage center optimization
427 06:54:57.479936 INFO : Training has run successfully!
428 06:54:57.480438
429 06:54:57.480847 channel==0
430 06:54:57.485506 RxClkDly_Margin_A0==88 ps 9
431 06:54:57.485945 TxDqDly_Margin_A0==98 ps 10
432 06:54:57.491362 RxClkDly_Margin_A1==88 ps 9
433 06:54:57.491804 TxDqDly_Margin_A1==88 ps 9
434 06:54:57.492237 TrainedVREFDQ_A0==74
435 06:54:57.496777 TrainedVREFDQ_A1==75
436 06:54:57.497240 VrefDac_Margin_A0==24
437 06:54:57.497638 DeviceVref_Margin_A0==40
438 06:54:57.502430 VrefDac_Margin_A1==23
439 06:54:57.502885 DeviceVref_Margin_A1==39
440 06:54:57.503294
441 06:54:57.503701
442 06:54:57.504135 channel==1
443 06:54:57.507964 RxClkDly_Margin_A0==78 ps 8
444 06:54:57.508475 TxDqDly_Margin_A0==98 ps 10
445 06:54:57.513573 RxClkDly_Margin_A1==88 ps 9
446 06:54:57.514065 TxDqDly_Margin_A1==78 ps 8
447 06:54:57.519247 TrainedVREFDQ_A0==78
448 06:54:57.519704 TrainedVREFDQ_A1==75
449 06:54:57.520149 VrefDac_Margin_A0==23
450 06:54:57.524707 DeviceVref_Margin_A0==36
451 06:54:57.525159 VrefDac_Margin_A1==22
452 06:54:57.530385 DeviceVref_Margin_A1==38
453 06:54:57.530823
454 06:54:57.531225 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 06:54:57.531618
456 06:54:57.563913 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000017 00000019 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
457 06:54:57.564552 2D training succeed
458 06:54:57.569553 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 06:54:57.575210 auto size-- 65535DDR cs0 size: 2048MB
460 06:54:57.575658 DDR cs1 size: 2048MB
461 06:54:57.580756 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 06:54:57.581200 cs0 DataBus test pass
463 06:54:57.586407 cs1 DataBus test pass
464 06:54:57.586890 cs0 AddrBus test pass
465 06:54:57.587296 cs1 AddrBus test pass
466 06:54:57.587694
467 06:54:57.591966 100bdlr_step_size ps== 478
468 06:54:57.592482 result report
469 06:54:57.597586 boot times 0Enable ddr reg access
470 06:54:57.602516 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 06:54:57.615717 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
472 06:54:58.270996 bl2z: ptr: 05129330, size: 00001e40
473 06:54:58.277856 0.0;M3 CHK:0;cm4_sp_mode 0
474 06:54:58.278390 MVN_1=0x00000000
475 06:54:58.278798 MVN_2=0x00000000
476 06:54:58.289318 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
477 06:54:58.289831 OPS=0x04
478 06:54:58.290241 ring efuse init
479 06:54:58.295023 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
480 06:54:58.295526 [0.017319 Inits done]
481 06:54:58.295932 secure task start!
482 06:54:58.301414 high task start!
483 06:54:58.301918 low task start!
484 06:54:58.302321 run into bl31
485 06:54:58.310938 NOTICE: BL31: v1.3(release):4fc40b1
486 06:54:58.317777 NOTICE: BL31: Built : 15:57:33, May 22 2019
487 06:54:58.318275 NOTICE: BL31: G12A normal boot!
488 06:54:58.334526 NOTICE: BL31: BL33 decompress pass
489 06:54:58.339146 ERROR: Error initializing runtime service opteed_fast
490 06:54:59.583995 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
491 06:54:59.584425 bl2_stage_init 0x01
492 06:54:59.584644 bl2_stage_init 0x81
493 06:54:59.589311 hw id: 0x0000 - pwm id 0x01
494 06:54:59.589692 bl2_stage_init 0xc1
495 06:54:59.594736 bl2_stage_init 0x02
496 06:54:59.595166
497 06:54:59.595529 L0:00000000
498 06:54:59.595934 L1:00000703
499 06:54:59.596315 L2:00008067
500 06:54:59.596569 L3:15000000
501 06:54:59.600204 S1:00000000
502 06:54:59.600541 B2:20282000
503 06:54:59.600840 B1:a0f83180
504 06:54:59.601097
505 06:54:59.601350 TE: 68338
506 06:54:59.601693
507 06:54:59.605707 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
508 06:54:59.611375
509 06:54:59.611756 Board ID = 1
510 06:54:59.612264 Set cpu clk to 24M
511 06:54:59.612589 Set clk81 to 24M
512 06:54:59.617233 Use GP1_pll as DSU clk.
513 06:54:59.617593 DSU clk: 1200 Mhz
514 06:54:59.617891 CPU clk: 1200 MHz
515 06:54:59.622863 Set clk81 to 166.6M
516 06:54:59.628262 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
517 06:54:59.628632 board id: 1
518 06:54:59.635354 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
519 06:54:59.646625 fw parse done
520 06:54:59.652127 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
521 06:54:59.694751 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
522 06:54:59.706884 PIEI prepare done
523 06:54:59.707264 fastboot data load
524 06:54:59.707497 fastboot data verify
525 06:54:59.712461 verify result: 266
526 06:54:59.718245 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
527 06:54:59.718595 LPDDR4 probe
528 06:54:59.718909 ddr clk to 1584MHz
529 06:55:01.084358 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x000� SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
530 06:55:01.085076 bl2_stage_init 0x01
531 06:55:01.085535 bl2_stage_init 0x81
532 06:55:01.089868 hw id: 0x0000 - pwm id 0x01
533 06:55:01.090398 bl2_stage_init 0xc1
534 06:55:01.095458 bl2_stage_init 0x02
535 06:55:01.095967
536 06:55:01.096473 L0:00000000
537 06:55:01.096909 L1:00000703
538 06:55:01.097344 L2:00008067
539 06:55:01.097776 L3:15000000
540 06:55:01.101110 S1:00000000
541 06:55:01.101617 B2:20282000
542 06:55:01.102057 B1:a0f83180
543 06:55:01.102491
544 06:55:01.102924 TE: 70498
545 06:55:01.103357
546 06:55:01.106660 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
547 06:55:01.107190
548 06:55:01.112400 Board ID = 1
549 06:55:01.112939 Set cpu clk to 24M
550 06:55:01.113407 Set clk81 to 24M
551 06:55:01.117856 Use GP1_pll as DSU clk.
552 06:55:01.118366 DSU clk: 1200 Mhz
553 06:55:01.118802 CPU clk: 1200 MHz
554 06:55:01.123463 Set clk81 to 166.6M
555 06:55:01.129075 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
556 06:55:01.129624 board id: 1
557 06:55:01.136338 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
558 06:55:01.147141 fw parse done
559 06:55:01.153121 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
560 06:55:01.196225 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
561 06:55:01.207453 PIEI prepare done
562 06:55:01.207977 fastboot data load
563 06:55:01.208482 fastboot data verify
564 06:55:01.213003 verify result: 266
565 06:55:01.218634 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
566 06:55:01.219144 LPDDR4 probe
567 06:55:01.219583 ddr clk to 1584MHz
568 06:55:01.226584 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
569 06:55:01.264376
570 06:55:01.264913 dmc_version 0001
571 06:55:01.271381 Check phy result
572 06:55:01.277421 INFO : End of CA training
573 06:55:01.277921 INFO : End of initialization
574 06:55:01.282975 INFO : Training has run successfully!
575 06:55:01.283477 Check phy result
576 06:55:01.288594 INFO : End of initialization
577 06:55:01.289105 INFO : End of read enable training
578 06:55:01.294139 INFO : End of fine write leveling
579 06:55:01.299774 INFO : End of Write leveling coarse delay
580 06:55:01.300310 INFO : Training has run successfully!
581 06:55:01.300750 Check phy result
582 06:55:01.305448 INFO : End of initialization
583 06:55:01.305954 INFO : End of read dq deskew training
584 06:55:01.310968 INFO : End of MPR read delay center optimization
585 06:55:01.316620 INFO : End of write delay center optimization
586 06:55:01.322220 INFO : End of read delay center optimization
587 06:55:01.322730 INFO : End of max read latency training
588 06:55:01.327766 INFO : Training has run successfully!
589 06:55:01.328326 1D training succeed
590 06:55:01.337032 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
591 06:55:01.385278 Check phy result
592 06:55:01.385893 INFO : End of initialization
593 06:55:01.412707 INFO : End of 2D read delay Voltage center optimization
594 06:55:01.436856 INFO : End of 2D read delay Voltage center optimization
595 06:55:01.493614 INFO : End of 2D write delay Voltage center optimization
596 06:55:01.547595 INFO : End of 2D write delay Voltage center optimization
597 06:55:01.553111 INFO : Training has run successfully!
598 06:55:01.553648
599 06:55:01.554117 channel==0
600 06:55:01.558704 RxClkDly_Margin_A0==78 ps 8
601 06:55:01.559216 TxDqDly_Margin_A0==98 ps 10
602 06:55:01.562022 RxClkDly_Margin_A1==69 ps 7
603 06:55:01.562536 TxDqDly_Margin_A1==98 ps 10
604 06:55:01.567549 TrainedVREFDQ_A0==74
605 06:55:01.568110 TrainedVREFDQ_A1==75
606 06:55:01.573182 VrefDac_Margin_A0==24
607 06:55:01.573696 DeviceVref_Margin_A0==40
608 06:55:01.574149 VrefDac_Margin_A1==23
609 06:55:01.578720 DeviceVref_Margin_A1==39
610 06:55:01.579229
611 06:55:01.579683
612 06:55:01.580169 channel==1
613 06:55:01.580619 RxClkDly_Margin_A0==78 ps 8
614 06:55:01.584357 TxDqDly_Margin_A0==98 ps 10
615 06:55:01.584867 RxClkDly_Margin_A1==88 ps 9
616 06:55:01.590002 TxDqDly_Margin_A1==88 ps 9
617 06:55:01.590514 TrainedVREFDQ_A0==78
618 06:55:01.590972 TrainedVREFDQ_A1==75
619 06:55:01.595593 VrefDac_Margin_A0==23
620 06:55:01.596159 DeviceVref_Margin_A0==36
621 06:55:01.601165 VrefDac_Margin_A1==22
622 06:55:01.601709 DeviceVref_Margin_A1==39
623 06:55:01.602199
624 06:55:01.606700 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
625 06:55:01.607226
626 06:55:01.634660 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
627 06:55:01.640362 2D training succeed
628 06:55:01.645935 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
629 06:55:01.646458 auto size-- 65535DDR cs0 size: 2048MB
630 06:55:01.651523 DDR cs1 size: 2048MB
631 06:55:01.652074 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
632 06:55:01.657137 cs0 DataBus test pass
633 06:55:01.657650 cs1 DataBus test pass
634 06:55:01.658109 cs0 AddrBus test pass
635 06:55:01.662703 cs1 AddrBus test pass
636 06:55:01.663206
637 06:55:01.663660 100bdlr_step_size ps== 471
638 06:55:01.664148 result report
639 06:55:01.668329 boot times 0Enable ddr reg access
640 06:55:01.676014 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
641 06:55:01.689793 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
642 06:55:02.349440 bl2z: ptr: 05129330, size: 00001e40
643 06:55:02.358469 0.0;M3 CHK:0;cm4_sp_mode 0
644 06:55:02.359014 MVN_1=0x00000000
645 06:55:02.359476 MVN_2=0x00000000
646 06:55:02.369911 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
647 06:55:02.370463 OPS=0x04
648 06:55:02.370925 ring efuse init
649 06:55:02.375472 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
650 06:55:02.376028 [0.017355 Inits done]
651 06:55:02.376486 secure task start!
652 06:55:02.383605 high task start!
653 06:55:02.384162 low task start!
654 06:55:02.384618 run into bl31
655 06:55:02.392218 NOTICE: BL31: v1.3(release):4fc40b1
656 06:55:02.400056 NOTICE: BL31: Built : 15:57:33, May 22 2019
657 06:55:02.400577 NOTICE: BL31: G12A normal boot!
658 06:55:02.415485 NOTICE: BL31: BL33 decompress pass
659 06:55:02.421157 ERROR: Error initializing runtime service opteed_fast
660 06:55:03.635629 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
661 06:55:03.636312 bl2_stage_init 0x01
662 06:55:03.636737 bl2_stage_init 0x81
663 06:55:03.641026 hw id: 0x0000 - pwm id 0x01
664 06:55:03.641506 bl2_stage_init 0xc1
665 06:55:03.646540 bl2_stage_init 0x02
666 06:55:03.647060
667 06:55:03.647512 L0:00000000
668 06:55:03.647922 L1:00000703
669 06:55:03.648426 L2:00008067
670 06:55:03.648857 L3:15000000
671 06:55:03.652541 S1:00000000
672 06:55:03.653022 B2:20282000
673 06:55:03.653463 B1:a0f83180
674 06:55:03.653916
675 06:55:03.654389 TE: 71158
676 06:55:03.654845
677 06:55:03.658110 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
678 06:55:03.658596
679 06:55:03.663667 Board ID = 1
680 06:55:03.664207 Set cpu clk to 24M
681 06:55:03.664663 Set clk81 to 24M
682 06:55:03.667385 Use GP1_pll as DSU clk.
683 06:55:03.668350 DSU clk: 1200 Mhz
684 06:55:03.673025 CPU clk: 1200 MHz
685 06:55:03.673881 Set clk81 to 166.6M
686 06:55:03.678476 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
687 06:55:03.679553 board id: 1
688 06:55:03.687281 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
689 06:55:03.698242 fw parse done
690 06:55:03.704239 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
691 06:55:03.747193 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
692 06:55:03.758337 PIEI prepare done
693 06:55:03.758886 fastboot data load
694 06:55:03.759332 fastboot data verify
695 06:55:03.763940 verify result: 266
696 06:55:03.769489 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
697 06:55:03.770013 LPDDR4 probe
698 06:55:03.770430 ddr clk to 1584MHz
699 06:55:03.777686 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
700 06:55:03.815355
701 06:55:03.815903 dmc_version 0001
702 06:55:03.821430 Check phy result
703 06:55:03.828316 INFO : End of CA training
704 06:55:03.828809 INFO : End of initialization
705 06:55:03.833873 INFO : Training has run successfully!
706 06:55:03.834353 Check phy result
707 06:55:03.839466 INFO : End of initialization
708 06:55:03.839939 INFO : End of read enable training
709 06:55:03.845028 INFO : End of fine write leveling
710 06:55:03.850782 INFO : End of Write leveling coarse delay
711 06:55:03.851254 INFO : Training has run successfully!
712 06:55:03.851685 Check phy result
713 06:55:03.856368 INFO : End of initialization
714 06:55:03.856874 INFO : End of read dq deskew training
715 06:55:03.861886 INFO : End of MPR read delay center optimization
716 06:55:03.867428 INFO : End of write delay center optimization
717 06:55:03.873106 INFO : End of read delay center optimization
718 06:55:03.873587 INFO : End of max read latency training
719 06:55:03.878803 INFO : Training has run successfully!
720 06:55:03.879271 1D training succeed
721 06:55:03.887856 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
722 06:55:03.936301 Check phy result
723 06:55:03.936869 INFO : End of initialization
724 06:55:03.963603 INFO : End of 2D read delay Voltage center optimization
725 06:55:03.987814 INFO : End of 2D read delay Voltage center optimization
726 06:55:04.044553 INFO : End of 2D write delay Voltage center optimization
727 06:55:04.098572 INFO : End of 2D write delay Voltage center optimization
728 06:55:04.103920 INFO : Training has run successfully!
729 06:55:04.104459
730 06:55:04.104900 channel==0
731 06:55:04.109560 RxClkDly_Margin_A0==78 ps 8
732 06:55:04.110045 TxDqDly_Margin_A0==98 ps 10
733 06:55:04.115166 RxClkDly_Margin_A1==88 ps 9
734 06:55:04.115642 TxDqDly_Margin_A1==98 ps 10
735 06:55:04.116107 TrainedVREFDQ_A0==75
736 06:55:04.120940 TrainedVREFDQ_A1==74
737 06:55:04.121447 VrefDac_Margin_A0==23
738 06:55:04.121874 DeviceVref_Margin_A0==39
739 06:55:04.126506 VrefDac_Margin_A1==23
740 06:55:04.127388 DeviceVref_Margin_A1==40
741 06:55:04.128140
742 06:55:04.129164
743 06:55:04.132237 channel==1
744 06:55:04.133109 RxClkDly_Margin_A0==88 ps 9
745 06:55:04.134049 TxDqDly_Margin_A0==88 ps 9
746 06:55:04.137749 RxClkDly_Margin_A1==78 ps 8
747 06:55:04.138298 TxDqDly_Margin_A1==78 ps 8
748 06:55:04.143350 TrainedVREFDQ_A0==75
749 06:55:04.144034 TrainedVREFDQ_A1==75
750 06:55:04.144570 VrefDac_Margin_A0==22
751 06:55:04.149072 DeviceVref_Margin_A0==39
752 06:55:04.149655 VrefDac_Margin_A1==22
753 06:55:04.154471 DeviceVref_Margin_A1==39
754 06:55:04.155033
755 06:55:04.155546 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
756 06:55:04.156115
757 06:55:04.189318 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
758 06:55:04.189939 2D training succeed
759 06:55:04.193700 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
760 06:55:04.199054 auto size-- 65535DDR cs0 size: 2048MB
761 06:55:04.199646 DDR cs1 size: 2048MB
762 06:55:04.204781 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
763 06:55:04.205310 cs0 DataBus test pass
764 06:55:04.210307 cs1 DataBus test pass
765 06:55:04.210907 cs0 AddrBus test pass
766 06:55:04.211323 cs1 AddrBus test pass
767 06:55:04.211725
768 06:55:04.215807 100bdlr_step_size ps== 471
769 06:55:04.216324 result report
770 06:55:04.221436 boot times 0Enable ddr reg access
771 06:55:04.226604 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
772 06:55:04.240803 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
773 06:55:04.901157 bl2z: ptr: 05129330, size: 00001e40
774 06:55:04.908874 0.0;M3 CHK:0;cm4_sp_mode 0
775 06:55:04.909400 MVN_1=0x00000000
776 06:55:04.909807 MVN_2=0x00000000
777 06:55:04.920277 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
778 06:55:04.920825 OPS=0x04
779 06:55:04.921225 ring efuse init
780 06:55:04.925841 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
781 06:55:04.926341 [0.017354 Inits done]
782 06:55:04.926771 secure task start!
783 06:55:04.933063 high task start!
784 06:55:04.933516 low task start!
785 06:55:04.933905 run into bl31
786 06:55:04.941814 NOTICE: BL31: v1.3(release):4fc40b1
787 06:55:04.948775 NOTICE: BL31: Built : 15:57:33, May 22 2019
788 06:55:04.949244 NOTICE: BL31: G12A normal boot!
789 06:55:04.965083 NOTICE: BL31: BL33 decompress pass
790 06:55:04.970884 ERROR: Error initializing runtime service opteed_fast
791 06:55:05.766200
792 06:55:05.766861
793 06:55:05.771547 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
794 06:55:05.772083
795 06:55:05.774111 Model: Libre Computer AML-S905D3-CC Solitude
796 06:55:05.921137 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
797 06:55:05.937376 DRAM: 2 GiB (effective 3.8 GiB)
798 06:55:06.038618 Core: 406 devices, 33 uclasses, devicetree: separate
799 06:55:06.043535 WDT: Not starting watchdog@f0d0
800 06:55:06.069352 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
801 06:55:06.081595 Loading Environment from FAT... Card did not respond to voltage select! : -110
802 06:55:06.085755 ** Bad device specification mmc 0 **
803 06:55:06.096728 Card did not respond to voltage select! : -110
804 06:55:06.103777 ** Bad device specification mmc 0 **
805 06:55:06.104298 Couldn't find partition mmc 0
806 06:55:06.112564 Card did not respond to voltage select! : -110
807 06:55:06.118085 ** Bad device specification mmc 0 **
808 06:55:06.118592 Couldn't find partition mmc 0
809 06:55:06.122135 Error: could not access storage.
810 06:55:06.418689 Net: eth0: ethernet@ff3f0000
811 06:55:06.419299 starting USB...
812 06:55:06.664330 Bus usb@ff500000: Register 3000140 NbrPorts 3
813 06:55:06.664953 Starting the controller
814 06:55:06.671261 USB XHCI 1.10
815 06:55:08.225361 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
816 06:55:08.233288 scanning usb for storage devices... 0 Storage Device(s) found
818 06:55:08.285089 Hit any key to stop autoboot: 1
819 06:55:08.286071 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
820 06:55:08.286679 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
821 06:55:08.287163 Setting prompt string to ['=>']
822 06:55:08.287651 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
823 06:55:08.299712 0
824 06:55:08.300706 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
826 06:55:08.402004 => setenv autoload no
827 06:55:08.402855 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
828 06:55:08.407924 setenv autoload no
830 06:55:08.509674 => setenv initrd_high 0xffffffff
831 06:55:08.510461 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
832 06:55:08.513893 setenv initrd_high 0xffffffff
834 06:55:08.615474 => setenv fdt_high 0xffffffff
835 06:55:08.616367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
836 06:55:08.620059 setenv fdt_high 0xffffffff
838 06:55:08.721711 => dhcp
839 06:55:08.722521 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
840 06:55:08.725987 dhcp
841 06:55:09.782748 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
842 06:55:09.783504 Speed: 1000, full duplex
843 06:55:09.784119 BOOTP broadcast 1
844 06:55:10.030181 BOOTP broadcast 2
845 06:55:10.531098 BOOTP broadcast 3
846 06:55:11.532919 BOOTP broadcast 4
847 06:55:13.533389 BOOTP broadcast 5
848 06:55:13.546835 DHCP client bound to address 192.168.6.12 (3763 ms)
850 06:55:13.648515 => setenv serverip 192.168.6.2
851 06:55:13.649198 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
852 06:55:13.652733 setenv serverip 192.168.6.2
854 06:55:13.754241 => tftpboot 0x01080000 714807/tftp-deploy-0gj4i42x/kernel/uImage
855 06:55:13.755169 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
856 06:55:13.761814 tftpboot 0x01080000 714807/tftp-deploy-0gj4i42x/kernel/uImage
857 06:55:13.762302 Speed: 1000, full duplex
858 06:55:13.762707 Using ethernet@ff3f0000 device
859 06:55:13.767604 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
860 06:55:13.772791 Filename '714807/tftp-deploy-0gj4i42x/kernel/uImage'.
861 06:55:13.776864 Load address: 0x1080000
862 06:55:16.658642 Loading: *################################################## 43.2 MiB
863 06:55:16.659245 15 MiB/s
864 06:55:16.659649 done
865 06:55:16.662001 Bytes transferred = 45308480 (2b35a40 hex)
867 06:55:16.763420 => tftpboot 0x08000000 714807/tftp-deploy-0gj4i42x/ramdisk/ramdisk.cpio.gz.uboot
868 06:55:16.764074 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
869 06:55:16.770524 tftpboot 0x08000000 714807/tftp-deploy-0gj4i42x/ramdisk/ramdisk.cpio.gz.uboot
870 06:55:16.770844 Speed: 1000, full duplex
871 06:55:16.771060 Using ethernet@ff3f0000 device
872 06:55:16.776105 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
873 06:55:16.785791 Filename '714807/tftp-deploy-0gj4i42x/ramdisk/ramdisk.cpio.gz.uboot'.
874 06:55:16.786240 Load address: 0x8000000
875 06:55:18.230473 Loading: *################################################# UDP wrong checksum 00000005 000005ff
876 06:55:23.231819 T UDP wrong checksum 00000005 000005ff
877 06:55:33.233745 T T UDP wrong checksum 00000005 000005ff
878 06:55:46.520018 T T UDP wrong checksum 000000ff 000000a8
879 06:55:46.524202 UDP wrong checksum 000000ff 00008a9a
880 06:55:53.238061 T T UDP wrong checksum 00000005 000005ff
881 06:56:13.242815 T T T
882 06:56:13.243242 Retry count exceeded; starting again
884 06:56:13.244179 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
887 06:56:13.245851 end: 2.4 uboot-commands (duration 00:01:24) [common]
889 06:56:13.246582 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
891 06:56:13.247380 end: 2 uboot-action (duration 00:01:24) [common]
893 06:56:13.248264 Cleaning after the job
894 06:56:13.248615 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/ramdisk
895 06:56:13.249579 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/kernel
896 06:56:13.273951 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/dtb
897 06:56:13.274958 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/nfsrootfs
898 06:56:13.464271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714807/tftp-deploy-0gj4i42x/modules
899 06:56:13.492891 start: 4.1 power-off (timeout 00:00:30) [common]
900 06:56:13.494009 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
901 06:56:13.531694 >> OK - accepted request
902 06:56:13.533956 Returned 0 in 0 seconds
903 06:56:13.634806 end: 4.1 power-off (duration 00:00:00) [common]
905 06:56:13.635879 start: 4.2 read-feedback (timeout 00:10:00) [common]
906 06:56:13.636649 Listened to connection for namespace 'common' for up to 1s
907 06:56:14.637550 Finalising connection for namespace 'common'
908 06:56:14.638062 Disconnecting from shell: Finalise
909 06:56:14.638338 =>
910 06:56:14.739020 end: 4.2 read-feedback (duration 00:00:01) [common]
911 06:56:14.739454 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714807
912 06:56:17.703827 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714807
913 06:56:17.704471 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.