Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:02:51.415904 lava-dispatcher, installed at version: 2024.01
2 07:02:51.416725 start: 0 validate
3 07:02:51.417210 Start time: 2024-09-06 07:02:51.417180+00:00 (UTC)
4 07:02:51.417749 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:02:51.418271 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:02:51.456958 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:02:51.457483 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:02:51.488408 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:02:51.489015 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:02:51.520051 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:02:51.520541 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:02:51.554846 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:02:51.555357 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 07:02:51.595958 validate duration: 0.18
16 07:02:51.596866 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:02:51.597208 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:02:51.597539 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:02:51.598157 Not decompressing ramdisk as can be used compressed.
20 07:02:51.598637 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 07:02:51.598931 saving as /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/ramdisk/initrd.cpio.gz
22 07:02:51.599200 total size: 5628140 (5 MB)
23 07:02:51.639677 progress 0 % (0 MB)
24 07:02:51.647664 progress 5 % (0 MB)
25 07:02:51.655413 progress 10 % (0 MB)
26 07:02:51.661265 progress 15 % (0 MB)
27 07:02:51.665330 progress 20 % (1 MB)
28 07:02:51.668906 progress 25 % (1 MB)
29 07:02:51.672859 progress 30 % (1 MB)
30 07:02:51.676831 progress 35 % (1 MB)
31 07:02:51.680419 progress 40 % (2 MB)
32 07:02:51.684361 progress 45 % (2 MB)
33 07:02:51.687903 progress 50 % (2 MB)
34 07:02:51.691779 progress 55 % (2 MB)
35 07:02:51.695720 progress 60 % (3 MB)
36 07:02:51.699286 progress 65 % (3 MB)
37 07:02:51.703186 progress 70 % (3 MB)
38 07:02:51.706850 progress 75 % (4 MB)
39 07:02:51.710650 progress 80 % (4 MB)
40 07:02:51.713968 progress 85 % (4 MB)
41 07:02:51.717582 progress 90 % (4 MB)
42 07:02:51.721202 progress 95 % (5 MB)
43 07:02:51.724497 progress 100 % (5 MB)
44 07:02:51.725144 5 MB downloaded in 0.13 s (42.62 MB/s)
45 07:02:51.725703 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:02:51.726573 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:02:51.726865 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:02:51.727134 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:02:51.727609 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
51 07:02:51.727860 saving as /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/kernel/Image
52 07:02:51.728097 total size: 45308416 (43 MB)
53 07:02:51.728307 No compression specified
54 07:02:51.768341 progress 0 % (0 MB)
55 07:02:51.795268 progress 5 % (2 MB)
56 07:02:51.822070 progress 10 % (4 MB)
57 07:02:51.848243 progress 15 % (6 MB)
58 07:02:51.874401 progress 20 % (8 MB)
59 07:02:51.900512 progress 25 % (10 MB)
60 07:02:51.926389 progress 30 % (12 MB)
61 07:02:51.952369 progress 35 % (15 MB)
62 07:02:51.978720 progress 40 % (17 MB)
63 07:02:52.004927 progress 45 % (19 MB)
64 07:02:52.031241 progress 50 % (21 MB)
65 07:02:52.057323 progress 55 % (23 MB)
66 07:02:52.084301 progress 60 % (25 MB)
67 07:02:52.110999 progress 65 % (28 MB)
68 07:02:52.137669 progress 70 % (30 MB)
69 07:02:52.164218 progress 75 % (32 MB)
70 07:02:52.190570 progress 80 % (34 MB)
71 07:02:52.216851 progress 85 % (36 MB)
72 07:02:52.243292 progress 90 % (38 MB)
73 07:02:52.269720 progress 95 % (41 MB)
74 07:02:52.295271 progress 100 % (43 MB)
75 07:02:52.296039 43 MB downloaded in 0.57 s (76.08 MB/s)
76 07:02:52.296535 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:02:52.297352 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:02:52.297627 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:02:52.297891 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:02:52.298383 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:02:52.298672 saving as /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:02:52.298880 total size: 54667 (0 MB)
84 07:02:52.299090 No compression specified
85 07:02:52.334166 progress 59 % (0 MB)
86 07:02:52.335052 progress 100 % (0 MB)
87 07:02:52.335613 0 MB downloaded in 0.04 s (1.42 MB/s)
88 07:02:52.336135 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:02:52.336969 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:02:52.337233 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:02:52.337498 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:02:52.337972 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 07:02:52.338220 saving as /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/nfsrootfs/full.rootfs.tar
95 07:02:52.338422 total size: 474398908 (452 MB)
96 07:02:52.338632 Using unxz to decompress xz
97 07:02:52.377676 progress 0 % (0 MB)
98 07:02:53.475204 progress 5 % (22 MB)
99 07:02:54.905518 progress 10 % (45 MB)
100 07:02:55.331095 progress 15 % (67 MB)
101 07:02:56.187592 progress 20 % (90 MB)
102 07:02:56.723927 progress 25 % (113 MB)
103 07:02:57.078515 progress 30 % (135 MB)
104 07:02:57.683705 progress 35 % (158 MB)
105 07:02:58.615826 progress 40 % (181 MB)
106 07:02:59.472951 progress 45 % (203 MB)
107 07:03:00.217662 progress 50 % (226 MB)
108 07:03:00.977010 progress 55 % (248 MB)
109 07:03:02.200436 progress 60 % (271 MB)
110 07:03:03.699595 progress 65 % (294 MB)
111 07:03:05.285973 progress 70 % (316 MB)
112 07:03:08.366458 progress 75 % (339 MB)
113 07:03:10.822702 progress 80 % (361 MB)
114 07:03:13.696661 progress 85 % (384 MB)
115 07:03:16.847165 progress 90 % (407 MB)
116 07:03:20.102891 progress 95 % (429 MB)
117 07:03:23.258133 progress 100 % (452 MB)
118 07:03:23.270899 452 MB downloaded in 30.93 s (14.63 MB/s)
119 07:03:23.271767 end: 1.4.1 http-download (duration 00:00:31) [common]
121 07:03:23.273412 end: 1.4 download-retry (duration 00:00:31) [common]
122 07:03:23.273937 start: 1.5 download-retry (timeout 00:09:28) [common]
123 07:03:23.274440 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 07:03:23.275972 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
125 07:03:23.276517 saving as /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/modules/modules.tar
126 07:03:23.276944 total size: 11502724 (10 MB)
127 07:03:23.277392 Using unxz to decompress xz
128 07:03:23.320285 progress 0 % (0 MB)
129 07:03:23.389012 progress 5 % (0 MB)
130 07:03:23.470819 progress 10 % (1 MB)
131 07:03:23.555256 progress 15 % (1 MB)
132 07:03:23.635141 progress 20 % (2 MB)
133 07:03:23.712133 progress 25 % (2 MB)
134 07:03:23.796826 progress 30 % (3 MB)
135 07:03:23.873221 progress 35 % (3 MB)
136 07:03:23.953226 progress 40 % (4 MB)
137 07:03:24.025661 progress 45 % (4 MB)
138 07:03:24.103184 progress 50 % (5 MB)
139 07:03:24.178825 progress 55 % (6 MB)
140 07:03:24.258283 progress 60 % (6 MB)
141 07:03:24.344520 progress 65 % (7 MB)
142 07:03:24.421400 progress 70 % (7 MB)
143 07:03:24.516532 progress 75 % (8 MB)
144 07:03:24.605935 progress 80 % (8 MB)
145 07:03:24.686177 progress 85 % (9 MB)
146 07:03:24.756660 progress 90 % (9 MB)
147 07:03:24.832197 progress 95 % (10 MB)
148 07:03:24.908465 progress 100 % (10 MB)
149 07:03:24.918991 10 MB downloaded in 1.64 s (6.68 MB/s)
150 07:03:24.919594 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:03:24.920945 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:03:24.921476 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 07:03:24.921989 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 07:03:40.384608 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/714863/extract-nfsrootfs-uj8lrrpr
156 07:03:40.385213 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 07:03:40.385502 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 07:03:40.386190 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3
159 07:03:40.386644 makedir: /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin
160 07:03:40.386974 makedir: /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/tests
161 07:03:40.387290 makedir: /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/results
162 07:03:40.387617 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-add-keys
163 07:03:40.388172 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-add-sources
164 07:03:40.388693 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-background-process-start
165 07:03:40.389192 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-background-process-stop
166 07:03:40.389719 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-common-functions
167 07:03:40.390225 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-echo-ipv4
168 07:03:40.390738 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-install-packages
169 07:03:40.391272 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-installed-packages
170 07:03:40.391757 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-os-build
171 07:03:40.392273 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-probe-channel
172 07:03:40.392765 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-probe-ip
173 07:03:40.393318 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-target-ip
174 07:03:40.393812 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-target-mac
175 07:03:40.394290 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-target-storage
176 07:03:40.394800 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-test-case
177 07:03:40.395332 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-test-event
178 07:03:40.395814 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-test-feedback
179 07:03:40.396318 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-test-raise
180 07:03:40.396793 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-test-reference
181 07:03:40.397264 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-test-runner
182 07:03:40.397745 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-test-set
183 07:03:40.398216 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-test-shell
184 07:03:40.398724 Updating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-install-packages (oe)
185 07:03:40.399279 Updating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/bin/lava-installed-packages (oe)
186 07:03:40.399721 Creating /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/environment
187 07:03:40.400133 LAVA metadata
188 07:03:40.400403 - LAVA_JOB_ID=714863
189 07:03:40.400619 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:03:40.400973 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 07:03:40.401917 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:03:40.402232 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 07:03:40.402440 skipped lava-vland-overlay
194 07:03:40.402677 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:03:40.402927 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 07:03:40.403143 skipped lava-multinode-overlay
197 07:03:40.403384 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:03:40.403634 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 07:03:40.403883 Loading test definitions
200 07:03:40.404188 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 07:03:40.404410 Using /lava-714863 at stage 0
202 07:03:40.405537 uuid=714863_1.6.2.4.1 testdef=None
203 07:03:40.405842 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:03:40.406104 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 07:03:40.407782 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:03:40.408626 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 07:03:40.410818 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:03:40.411646 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 07:03:40.413711 runner path: /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 714863_1.6.2.4.1
212 07:03:40.414274 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:03:40.415030 Creating lava-test-runner.conf files
215 07:03:40.415229 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714863/lava-overlay-k5748mc3/lava-714863/0 for stage 0
216 07:03:40.415554 - 0_v4l2-decoder-conformance-h264
217 07:03:40.415890 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:03:40.416187 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 07:03:40.437602 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:03:40.437955 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 07:03:40.438211 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:03:40.438474 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:03:40.438733 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 07:03:41.047358 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:03:41.047930 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 07:03:41.048283 extracting modules file /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714863/extract-nfsrootfs-uj8lrrpr
227 07:03:42.689194 extracting modules file /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714863/extract-overlay-ramdisk-gtmdpakg/ramdisk
228 07:03:44.103849 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:03:44.104363 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 07:03:44.104643 [common] Applying overlay to NFS
231 07:03:44.104856 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714863/compress-overlay-hm6dv0a5/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714863/extract-nfsrootfs-uj8lrrpr
232 07:03:44.134228 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:03:44.134593 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 07:03:44.134865 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 07:03:44.135095 Converting downloaded kernel to a uImage
236 07:03:44.135403 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/kernel/Image /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/kernel/uImage
237 07:03:44.630086 output: Image Name:
238 07:03:44.630479 output: Created: Fri Sep 6 07:03:44 2024
239 07:03:44.630688 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:03:44.630891 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
241 07:03:44.631089 output: Load Address: 01080000
242 07:03:44.631286 output: Entry Point: 01080000
243 07:03:44.631481 output:
244 07:03:44.631814 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 07:03:44.632123 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 07:03:44.632401 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 07:03:44.632656 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:03:44.632913 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 07:03:44.633175 Building ramdisk /var/lib/lava/dispatcher/tmp/714863/extract-overlay-ramdisk-gtmdpakg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714863/extract-overlay-ramdisk-gtmdpakg/ramdisk
250 07:03:46.744310 >> 165160 blocks
251 07:03:54.396158 Adding RAMdisk u-boot header.
252 07:03:54.396878 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714863/extract-overlay-ramdisk-gtmdpakg/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714863/extract-overlay-ramdisk-gtmdpakg/ramdisk.cpio.gz.uboot
253 07:03:54.641698 output: Image Name:
254 07:03:54.642118 output: Created: Fri Sep 6 07:03:54 2024
255 07:03:54.642586 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:03:54.643051 output: Data Size: 23258047 Bytes = 22712.94 KiB = 22.18 MiB
257 07:03:54.643503 output: Load Address: 00000000
258 07:03:54.643942 output: Entry Point: 00000000
259 07:03:54.644641 output:
260 07:03:54.645726 rename /var/lib/lava/dispatcher/tmp/714863/extract-overlay-ramdisk-gtmdpakg/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/ramdisk/ramdisk.cpio.gz.uboot
261 07:03:54.646461 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 07:03:54.647033 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 07:03:54.647614 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 07:03:54.648169 No LXC device requested
265 07:03:54.648709 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:03:54.649240 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 07:03:54.649751 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:03:54.650174 Checking files for TFTP limit of 4294967296 bytes.
269 07:03:54.652903 end: 1 tftp-deploy (duration 00:01:03) [common]
270 07:03:54.653501 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:03:54.654044 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:03:54.654557 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:03:54.655070 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:03:54.655606 Using kernel file from prepare-kernel: 714863/tftp-deploy-4qwjekvt/kernel/uImage
275 07:03:54.656277 substitutions:
276 07:03:54.656699 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:03:54.657106 - {DTB_ADDR}: 0x01070000
278 07:03:54.657508 - {DTB}: 714863/tftp-deploy-4qwjekvt/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:03:54.657909 - {INITRD}: 714863/tftp-deploy-4qwjekvt/ramdisk/ramdisk.cpio.gz.uboot
280 07:03:54.658309 - {KERNEL_ADDR}: 0x01080000
281 07:03:54.658704 - {KERNEL}: 714863/tftp-deploy-4qwjekvt/kernel/uImage
282 07:03:54.659098 - {LAVA_MAC}: None
283 07:03:54.659534 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/714863/extract-nfsrootfs-uj8lrrpr
284 07:03:54.659939 - {NFS_SERVER_IP}: 192.168.6.2
285 07:03:54.660371 - {PRESEED_CONFIG}: None
286 07:03:54.660778 - {PRESEED_LOCAL}: None
287 07:03:54.661177 - {RAMDISK_ADDR}: 0x08000000
288 07:03:54.661574 - {RAMDISK}: 714863/tftp-deploy-4qwjekvt/ramdisk/ramdisk.cpio.gz.uboot
289 07:03:54.661969 - {ROOT_PART}: None
290 07:03:54.662365 - {ROOT}: None
291 07:03:54.662756 - {SERVER_IP}: 192.168.6.2
292 07:03:54.663151 - {TEE_ADDR}: 0x83000000
293 07:03:54.663541 - {TEE}: None
294 07:03:54.663932 Parsed boot commands:
295 07:03:54.664348 - setenv autoload no
296 07:03:54.664741 - setenv initrd_high 0xffffffff
297 07:03:54.665133 - setenv fdt_high 0xffffffff
298 07:03:54.665522 - dhcp
299 07:03:54.665914 - setenv serverip 192.168.6.2
300 07:03:54.666305 - tftpboot 0x01080000 714863/tftp-deploy-4qwjekvt/kernel/uImage
301 07:03:54.666693 - tftpboot 0x08000000 714863/tftp-deploy-4qwjekvt/ramdisk/ramdisk.cpio.gz.uboot
302 07:03:54.667087 - tftpboot 0x01070000 714863/tftp-deploy-4qwjekvt/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:03:54.667478 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/714863/extract-nfsrootfs-uj8lrrpr,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:03:54.667884 - bootm 0x01080000 0x08000000 0x01070000
305 07:03:54.668431 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:03:54.669941 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:03:54.670374 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:03:54.685393 Setting prompt string to ['lava-test: # ']
310 07:03:54.686917 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:03:54.687555 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:03:54.688162 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:03:54.688750 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:03:54.689905 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:03:54.726934 >> OK - accepted request
316 07:03:54.729106 Returned 0 in 0 seconds
317 07:03:54.830243 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:03:54.831893 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:03:54.832542 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:03:54.833099 Setting prompt string to ['Hit any key to stop autoboot']
322 07:03:54.833577 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:03:54.835149 Trying 192.168.56.21...
324 07:03:54.835643 Connected to conserv1.
325 07:03:54.836106 Escape character is '^]'.
326 07:03:54.836541
327 07:03:54.836973 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 07:03:54.837389
329 07:04:05.882191 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:04:05.882607 bl2_stage_init 0x01
331 07:04:05.882893 bl2_stage_init 0x81
332 07:04:05.887800 hw id: 0x0000 - pwm id 0x01
333 07:04:05.888130 bl2_stage_init 0xc1
334 07:04:05.888426 bl2_stage_init 0x02
335 07:04:05.888691
336 07:04:05.893401 L0:00000000
337 07:04:05.893710 L1:20000703
338 07:04:05.893919 L2:00008067
339 07:04:05.894123 L3:14000000
340 07:04:05.898879 B2:00402000
341 07:04:05.899227 B1:e0f83180
342 07:04:05.899440
343 07:04:05.899644 TE: 58159
344 07:04:05.899847
345 07:04:05.904493 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:04:05.904786
347 07:04:05.904997 Board ID = 1
348 07:04:05.910163 Set A53 clk to 24M
349 07:04:05.910459 Set A73 clk to 24M
350 07:04:05.910731 Set clk81 to 24M
351 07:04:05.915742 A53 clk: 1200 MHz
352 07:04:05.916113 A73 clk: 1200 MHz
353 07:04:05.916330 CLK81: 166.6M
354 07:04:05.916533 smccc: 00012ab5
355 07:04:05.921343 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:04:05.926955 board id: 1
357 07:04:05.932926 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:04:05.943486 fw parse done
359 07:04:05.949423 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:04:05.992067 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:04:06.002978 PIEI prepare done
362 07:04:06.003312 fastboot data load
363 07:04:06.003527 fastboot data verify
364 07:04:06.008674 verify result: 266
365 07:04:06.014810 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:04:06.015120 LPDDR4 probe
367 07:04:06.015331 ddr clk to 1584MHz
368 07:04:06.022263 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:04:06.059620
370 07:04:06.060115 dmc_version 0001
371 07:04:06.066671 Check phy result
372 07:04:06.072215 INFO : End of CA training
373 07:04:06.072532 INFO : End of initialization
374 07:04:06.078067 INFO : Training has run successfully!
375 07:04:06.078372 Check phy result
376 07:04:06.083311 INFO : End of initialization
377 07:04:06.083613 INFO : End of read enable training
378 07:04:06.086539 INFO : End of fine write leveling
379 07:04:06.092079 INFO : End of Write leveling coarse delay
380 07:04:06.097672 INFO : Training has run successfully!
381 07:04:06.097996 Check phy result
382 07:04:06.098280 INFO : End of initialization
383 07:04:06.103221 INFO : End of read dq deskew training
384 07:04:06.108838 INFO : End of MPR read delay center optimization
385 07:04:06.109137 INFO : End of write delay center optimization
386 07:04:06.114515 INFO : End of read delay center optimization
387 07:04:06.120076 INFO : End of max read latency training
388 07:04:06.120374 INFO : Training has run successfully!
389 07:04:06.125705 1D training succeed
390 07:04:06.131689 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:04:06.179240 Check phy result
392 07:04:06.179644 INFO : End of initialization
393 07:04:06.201696 INFO : End of 2D read delay Voltage center optimization
394 07:04:06.221799 INFO : End of 2D read delay Voltage center optimization
395 07:04:06.273766 INFO : End of 2D write delay Voltage center optimization
396 07:04:06.323011 INFO : End of 2D write delay Voltage center optimization
397 07:04:06.328509 INFO : Training has run successfully!
398 07:04:06.328845
399 07:04:06.329061 channel==0
400 07:04:06.334112 RxClkDly_Margin_A0==88 ps 9
401 07:04:06.334458 TxDqDly_Margin_A0==98 ps 10
402 07:04:06.339734 RxClkDly_Margin_A1==88 ps 9
403 07:04:06.340044 TxDqDly_Margin_A1==98 ps 10
404 07:04:06.340264 TrainedVREFDQ_A0==74
405 07:04:06.345325 TrainedVREFDQ_A1==74
406 07:04:06.345660 VrefDac_Margin_A0==25
407 07:04:06.345883 DeviceVref_Margin_A0==40
408 07:04:06.350977 VrefDac_Margin_A1==25
409 07:04:06.351304 DeviceVref_Margin_A1==40
410 07:04:06.351513
411 07:04:06.351719
412 07:04:06.356651 channel==1
413 07:04:06.356940 RxClkDly_Margin_A0==88 ps 9
414 07:04:06.357148 TxDqDly_Margin_A0==98 ps 10
415 07:04:06.362047 RxClkDly_Margin_A1==98 ps 10
416 07:04:06.362379 TxDqDly_Margin_A1==88 ps 9
417 07:04:06.367575 TrainedVREFDQ_A0==77
418 07:04:06.367866 TrainedVREFDQ_A1==77
419 07:04:06.368104 VrefDac_Margin_A0==22
420 07:04:06.373228 DeviceVref_Margin_A0==37
421 07:04:06.373515 VrefDac_Margin_A1==22
422 07:04:06.378923 DeviceVref_Margin_A1==37
423 07:04:06.379205
424 07:04:06.379417 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:04:06.379620
426 07:04:06.412526 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 07:04:06.412983 2D training succeed
428 07:04:06.418004 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:04:06.423661 auto size-- 65535DDR cs0 size: 2048MB
430 07:04:06.423957 DDR cs1 size: 2048MB
431 07:04:06.429207 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:04:06.429500 cs0 DataBus test pass
433 07:04:06.434785 cs1 DataBus test pass
434 07:04:06.435093 cs0 AddrBus test pass
435 07:04:06.435307 cs1 AddrBus test pass
436 07:04:06.435574
437 07:04:06.440527 100bdlr_step_size ps== 420
438 07:04:06.440850 result report
439 07:04:06.445980 boot times 0Enable ddr reg access
440 07:04:06.451389 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:04:06.464800 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:04:07.037193 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:04:07.037609 MVN_1=0x00000000
444 07:04:07.042392 MVN_2=0x00000000
445 07:04:07.048169 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:04:07.048467 OPS=0x10
447 07:04:07.048683 ring efuse init
448 07:04:07.048889 chipver efuse init
449 07:04:07.056351 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:04:07.056672 [0.018960 Inits done]
451 07:04:07.064024 secure task start!
452 07:04:07.064322 high task start!
453 07:04:07.064531 low task start!
454 07:04:07.064731 run into bl31
455 07:04:07.070677 NOTICE: BL31: v1.3(release):4fc40b1
456 07:04:07.078369 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:04:07.078679 NOTICE: BL31: G12A normal boot!
458 07:04:07.103638 NOTICE: BL31: BL33 decompress pass
459 07:04:07.109317 ERROR: Error initializing runtime service opteed_fast
460 07:04:08.342368
461 07:04:08.343018
462 07:04:08.350550 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:04:08.351062
464 07:04:08.351508 Model: Libre Computer AML-A311D-CC Alta
465 07:04:08.559255 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:04:08.582558 DRAM: 2 GiB (effective 3.8 GiB)
467 07:04:08.725454 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:04:08.731310 WDT: Not starting watchdog@f0d0
469 07:04:08.763670 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:04:08.776046 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:04:08.780961 ** Bad device specification mmc 0 **
472 07:04:08.791341 Card did not respond to voltage select! : -110
473 07:04:08.798921 ** Bad device specification mmc 0 **
474 07:04:08.799418 Couldn't find partition mmc 0
475 07:04:08.807250 Card did not respond to voltage select! : -110
476 07:04:08.812769 ** Bad device specification mmc 0 **
477 07:04:08.813272 Couldn't find partition mmc 0
478 07:04:08.817847 Error: could not access storage.
479 07:04:10.081825 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:04:10.082474 bl2_stage_init 0x01
481 07:04:10.082950 bl2_stage_init 0x81
482 07:04:10.087362 hw id: 0x0000 - pwm id 0x01
483 07:04:10.087905 bl2_stage_init 0xc1
484 07:04:10.088435 bl2_stage_init 0x02
485 07:04:10.088894
486 07:04:10.093020 L0:00000000
487 07:04:10.093540 L1:20000703
488 07:04:10.093998 L2:00008067
489 07:04:10.094437 L3:14000000
490 07:04:10.098538 B2:00402000
491 07:04:10.099032 B1:e0f83180
492 07:04:10.099477
493 07:04:10.099914 TE: 58159
494 07:04:10.100413
495 07:04:10.104136 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:04:10.104631
497 07:04:10.105095 Board ID = 1
498 07:04:10.110028 Set A53 clk to 24M
499 07:04:10.110517 Set A73 clk to 24M
500 07:04:10.110965 Set clk81 to 24M
501 07:04:10.115347 A53 clk: 1200 MHz
502 07:04:10.115843 A73 clk: 1200 MHz
503 07:04:10.116334 CLK81: 166.6M
504 07:04:10.116783 smccc: 00012ab5
505 07:04:10.121023 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:04:10.126459 board id: 1
507 07:04:10.132451 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:04:10.143093 fw parse done
509 07:04:10.149174 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:04:10.191593 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:04:10.202439 PIEI prepare done
512 07:04:10.202955 fastboot data load
513 07:04:10.203420 fastboot data verify
514 07:04:10.208088 verify result: 266
515 07:04:10.213702 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:04:10.214198 LPDDR4 probe
517 07:04:10.214645 ddr clk to 1584MHz
518 07:04:10.221626 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:04:10.258972
520 07:04:10.259518 dmc_version 0001
521 07:04:10.265677 Check phy result
522 07:04:10.271522 INFO : End of CA training
523 07:04:10.272047 INFO : End of initialization
524 07:04:10.277104 INFO : Training has run successfully!
525 07:04:10.277600 Check phy result
526 07:04:10.282655 INFO : End of initialization
527 07:04:10.283153 INFO : End of read enable training
528 07:04:10.288292 INFO : End of fine write leveling
529 07:04:10.293961 INFO : End of Write leveling coarse delay
530 07:04:10.294447 INFO : Training has run successfully!
531 07:04:10.294894 Check phy result
532 07:04:10.299572 INFO : End of initialization
533 07:04:10.300147 INFO : End of read dq deskew training
534 07:04:10.305085 INFO : End of MPR read delay center optimization
535 07:04:10.310729 INFO : End of write delay center optimization
536 07:04:10.316403 INFO : End of read delay center optimization
537 07:04:10.316874 INFO : End of max read latency training
538 07:04:10.322017 INFO : Training has run successfully!
539 07:04:10.322492 1D training succeed
540 07:04:10.331152 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:04:10.378780 Check phy result
542 07:04:10.379386 INFO : End of initialization
543 07:04:10.400463 INFO : End of 2D read delay Voltage center optimization
544 07:04:10.420535 INFO : End of 2D read delay Voltage center optimization
545 07:04:10.472463 INFO : End of 2D write delay Voltage center optimization
546 07:04:10.521736 INFO : End of 2D write delay Voltage center optimization
547 07:04:10.527101 INFO : Training has run successfully!
548 07:04:10.527586
549 07:04:10.528093 channel==0
550 07:04:10.532833 RxClkDly_Margin_A0==88 ps 9
551 07:04:10.533340 TxDqDly_Margin_A0==98 ps 10
552 07:04:10.538393 RxClkDly_Margin_A1==88 ps 9
553 07:04:10.538947 TxDqDly_Margin_A1==88 ps 9
554 07:04:10.539414 TrainedVREFDQ_A0==74
555 07:04:10.544108 TrainedVREFDQ_A1==74
556 07:04:10.544683 VrefDac_Margin_A0==25
557 07:04:10.545139 DeviceVref_Margin_A0==40
558 07:04:10.550392 VrefDac_Margin_A1==25
559 07:04:10.550936 DeviceVref_Margin_A1==40
560 07:04:10.551394
561 07:04:10.551843
562 07:04:10.552329 channel==1
563 07:04:10.555233 RxClkDly_Margin_A0==88 ps 9
564 07:04:10.555717 TxDqDly_Margin_A0==98 ps 10
565 07:04:10.560867 RxClkDly_Margin_A1==98 ps 10
566 07:04:10.561355 TxDqDly_Margin_A1==88 ps 9
567 07:04:10.566413 TrainedVREFDQ_A0==77
568 07:04:10.566971 TrainedVREFDQ_A1==77
569 07:04:10.567420 VrefDac_Margin_A0==22
570 07:04:10.571887 DeviceVref_Margin_A0==37
571 07:04:10.572392 VrefDac_Margin_A1==24
572 07:04:10.577645 DeviceVref_Margin_A1==37
573 07:04:10.578195
574 07:04:10.578657 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:04:10.579108
576 07:04:10.611123 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 07:04:10.611788 2D training succeed
578 07:04:10.616659 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:04:10.622342 auto size-- 65535DDR cs0 size: 2048MB
580 07:04:10.622886 DDR cs1 size: 2048MB
581 07:04:10.627866 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:04:10.628418 cs0 DataBus test pass
583 07:04:10.633418 cs1 DataBus test pass
584 07:04:10.633905 cs0 AddrBus test pass
585 07:04:10.634353 cs1 AddrBus test pass
586 07:04:10.634788
587 07:04:10.639016 100bdlr_step_size ps== 420
588 07:04:10.639510 result report
589 07:04:10.644650 boot times 0Enable ddr reg access
590 07:04:10.649921 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:04:10.663571 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:04:11.235497 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:04:11.236222 MVN_1=0x00000000
594 07:04:11.240941 MVN_2=0x00000000
595 07:04:11.246624 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:04:11.247145 OPS=0x10
597 07:04:11.247624 ring efuse init
598 07:04:11.248115 chipver efuse init
599 07:04:11.252256 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:04:11.257843 [0.018961 Inits done]
601 07:04:11.258352 secure task start!
602 07:04:11.258788 high task start!
603 07:04:11.262386 low task start!
604 07:04:11.262868 run into bl31
605 07:04:11.269051 NOTICE: BL31: v1.3(release):4fc40b1
606 07:04:11.276822 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:04:11.277316 NOTICE: BL31: G12A normal boot!
608 07:04:11.302210 NOTICE: BL31: BL33 decompress pass
609 07:04:11.307891 ERROR: Error initializing runtime service opteed_fast
610 07:04:12.540793
611 07:04:12.541477
612 07:04:12.549449 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:04:12.549959
614 07:04:12.550419 Model: Libre Computer AML-A311D-CC Alta
615 07:04:12.757637 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:04:12.780997 DRAM: 2 GiB (effective 3.8 GiB)
617 07:04:12.924013 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:04:12.929886 WDT: Not starting watchdog@f0d0
619 07:04:12.962139 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:04:12.974594 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:04:12.979583 ** Bad device specification mmc 0 **
622 07:04:12.989907 Card did not respond to voltage select! : -110
623 07:04:12.997525 ** Bad device specification mmc 0 **
624 07:04:12.998066 Couldn't find partition mmc 0
625 07:04:13.005872 Card did not respond to voltage select! : -110
626 07:04:13.011372 ** Bad device specification mmc 0 **
627 07:04:13.011886 Couldn't find partition mmc 0
628 07:04:13.016443 Error: could not access storage.
629 07:04:13.358958 Net: eth0: ethernet@ff3f0000
630 07:04:13.359599 starting USB...
631 07:04:13.610743 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:04:13.611387 Starting the controller
633 07:04:13.617639 USB XHCI 1.10
634 07:04:15.333521 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
635 07:04:15.334179 bl2_stage_init 0x81
636 07:04:15.339044 hw id: 0x0000 - pwm id 0x01
637 07:04:15.339569 bl2_stage_init 0xc1
638 07:04:15.340078 bl2_stage_init 0x02
639 07:04:15.340531
640 07:04:15.344728 L0:00000000
641 07:04:15.345242 L1:20000703
642 07:04:15.345695 L2:00008067
643 07:04:15.346140 L3:14000000
644 07:04:15.346580 B2:00402000
645 07:04:15.350239 B1:e0f83180
646 07:04:15.350745
647 07:04:15.351196 TE: 58150
648 07:04:15.351642
649 07:04:15.355811 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 07:04:15.356360
651 07:04:15.356819 Board ID = 1
652 07:04:15.361504 Set A53 clk to 24M
653 07:04:15.362034 Set A73 clk to 24M
654 07:04:15.362487 Set clk81 to 24M
655 07:04:15.367016 A53 clk: 1200 MHz
656 07:04:15.367527 A73 clk: 1200 MHz
657 07:04:15.368010 CLK81: 166.6M
658 07:04:15.368468 smccc: 00012aac
659 07:04:15.372763 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 07:04:15.378244 board id: 1
661 07:04:15.384031 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 07:04:15.394779 fw parse done
663 07:04:15.400607 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 07:04:15.443226 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 07:04:15.454200 PIEI prepare done
666 07:04:15.454757 fastboot data load
667 07:04:15.455216 fastboot data verify
668 07:04:15.459816 verify result: 266
669 07:04:15.465395 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 07:04:15.465923 LPDDR4 probe
671 07:04:15.466379 ddr clk to 1584MHz
672 07:04:15.473276 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 07:04:15.510594
674 07:04:15.511156 dmc_version 0001
675 07:04:15.517274 Check phy result
676 07:04:15.523125 INFO : End of CA training
677 07:04:15.523654 INFO : End of initialization
678 07:04:15.528759 INFO : Training has run successfully!
679 07:04:15.529277 Check phy result
680 07:04:15.534328 INFO : End of initialization
681 07:04:15.534868 INFO : End of read enable training
682 07:04:15.540021 INFO : End of fine write leveling
683 07:04:15.545640 INFO : End of Write leveling coarse delay
684 07:04:15.546221 INFO : Training has run successfully!
685 07:04:15.546705 Check phy result
686 07:04:15.551172 INFO : End of initialization
687 07:04:15.551735 INFO : End of read dq deskew training
688 07:04:15.556769 INFO : End of MPR read delay center optimization
689 07:04:15.562355 INFO : End of write delay center optimization
690 07:04:15.567923 INFO : End of read delay center optimization
691 07:04:15.568503 INFO : End of max read latency training
692 07:04:15.573624 INFO : Training has run successfully!
693 07:04:15.574208 1D training succeed
694 07:04:15.582784 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 07:04:15.630515 Check phy result
696 07:04:15.631115 INFO : End of initialization
697 07:04:15.653116 INFO : End of 2D read delay Voltage center optimization
698 07:04:15.673419 INFO : End of 2D read delay Voltage center optimization
699 07:04:15.725412 INFO : End of 2D write delay Voltage center optimization
700 07:04:15.774928 INFO : End of 2D write delay Voltage center optimization
701 07:04:15.780316 INFO : Training has run successfully!
702 07:04:15.780849
703 07:04:15.781302 channel==0
704 07:04:15.786010 RxClkDly_Margin_A0==88 ps 9
705 07:04:15.786531 TxDqDly_Margin_A0==98 ps 10
706 07:04:15.789274 RxClkDly_Margin_A1==88 ps 9
707 07:04:15.789794 TxDqDly_Margin_A1==98 ps 10
708 07:04:15.794970 TrainedVREFDQ_A0==74
709 07:04:15.795495 TrainedVREFDQ_A1==74
710 07:04:15.795951 VrefDac_Margin_A0==25
711 07:04:15.800369 DeviceVref_Margin_A0==40
712 07:04:15.800884 VrefDac_Margin_A1==24
713 07:04:15.806018 DeviceVref_Margin_A1==40
714 07:04:15.806561
715 07:04:15.807024
716 07:04:15.807474 channel==1
717 07:04:15.807911 RxClkDly_Margin_A0==98 ps 10
718 07:04:15.809538 TxDqDly_Margin_A0==98 ps 10
719 07:04:15.815112 RxClkDly_Margin_A1==88 ps 9
720 07:04:15.815648 TxDqDly_Margin_A1==88 ps 9
721 07:04:15.816148 TrainedVREFDQ_A0==77
722 07:04:15.820624 TrainedVREFDQ_A1==77
723 07:04:15.821175 VrefDac_Margin_A0==22
724 07:04:15.826258 DeviceVref_Margin_A0==37
725 07:04:15.826804 VrefDac_Margin_A1==24
726 07:04:15.827251 DeviceVref_Margin_A1==37
727 07:04:15.827688
728 07:04:15.831888 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 07:04:15.832499
730 07:04:15.865426 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
731 07:04:15.866091 2D training succeed
732 07:04:15.871104 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 07:04:15.876644 auto size-- 65535DDR cs0 size: 2048MB
734 07:04:15.877192 DDR cs1 size: 2048MB
735 07:04:15.882294 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 07:04:15.882837 cs0 DataBus test pass
737 07:04:15.883290 cs1 DataBus test pass
738 07:04:15.887870 cs0 AddrBus test pass
739 07:04:15.888455 cs1 AddrBus test pass
740 07:04:15.888939
741 07:04:15.893444 100bdlr_step_size ps== 420
742 07:04:15.894003 result report
743 07:04:15.894454 boot times 0Enable ddr reg access
744 07:04:15.903124 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 07:04:15.916756 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 07:04:16.489787 0.0;M3 CHK:0;cm4_sp_mode 0
747 07:04:16.490455 MVN_1=0x00000000
748 07:04:16.495271 MVN_2=0x00000000
749 07:04:16.500971 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 07:04:16.501565 OPS=0x10
751 07:04:16.502023 ring efuse init
752 07:04:16.502451 chipver efuse init
753 07:04:16.506659 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 07:04:16.512204 [0.018960 Inits done]
755 07:04:16.512722 secure task start!
756 07:04:16.513155 high task start!
757 07:04:16.516744 low task start!
758 07:04:16.517237 run into bl31
759 07:04:16.523335 NOTICE: BL31: v1.3(release):4fc40b1
760 07:04:16.531160 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 07:04:16.531679 NOTICE: BL31: G12A normal boot!
762 07:04:16.556579 NOTICE: BL31: BL33 decompress pass
763 07:04:16.562244 ERROR: Error initializing runtime service opteed_fast
764 07:04:17.795248
765 07:04:17.795921
766 07:04:17.803545 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 07:04:17.804124
768 07:04:17.804594 Model: Libre Computer AML-A311D-CC Alta
769 07:04:18.011960 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 07:04:18.035410 DRAM: 2 GiB (effective 3.8 GiB)
771 07:04:18.178345 Core: 408 devices, 31 uclasses, devicetree: separate
772 07:04:18.184231 WDT: Not starting watchdog@f0d0
773 07:04:18.216467 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 07:04:18.228909 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 07:04:18.233954 ** Bad device specification mmc 0 **
776 07:04:18.244271 Card did not respond to voltage select! : -110
777 07:04:18.252142 ** Bad device specification mmc 0 **
778 07:04:18.252745 Couldn't find partition mmc 0
779 07:04:18.260240 Card did not respond to voltage select! : -110
780 07:04:18.265701 ** Bad device specification mmc 0 **
781 07:04:18.266424 Couldn't find partition mmc 0
782 07:04:18.270729 Error: could not access storage.
783 07:04:18.613230 Net: eth0: ethernet@ff3f0000
784 07:04:18.614029 starting USB...
785 07:04:18.865010 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 07:04:18.865742 Starting the controller
787 07:04:18.871936 USB XHCI 1.10
788 07:04:21.032283 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
789 07:04:21.033073 bl2_stage_init 0x81
790 07:04:21.037786 hw id: 0x0000 - pwm id 0x01
791 07:04:21.038378 bl2_stage_init 0xc1
792 07:04:21.038920 bl2_stage_init 0x02
793 07:04:21.039441
794 07:04:21.043343 L0:00000000
795 07:04:21.043919 L1:20000703
796 07:04:21.044506 L2:00008067
797 07:04:21.045039 L3:14000000
798 07:04:21.045552 B2:00402000
799 07:04:21.046452 B1:e0f83180
800 07:04:21.046997
801 07:04:21.047529 TE: 58150
802 07:04:21.048077
803 07:04:21.057360 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
804 07:04:21.057946
805 07:04:21.058489 Board ID = 1
806 07:04:21.059002 Set A53 clk to 24M
807 07:04:21.059511 Set A73 clk to 24M
808 07:04:21.063068 Set clk81 to 24M
809 07:04:21.063631 A53 clk: 1200 MHz
810 07:04:21.064198 A73 clk: 1200 MHz
811 07:04:21.068618 CLK81: 166.6M
812 07:04:21.069177 smccc: 00012aab
813 07:04:21.074112 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
814 07:04:21.074691 board id: 1
815 07:04:21.082803 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
816 07:04:21.093260 fw parse done
817 07:04:21.099190 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
818 07:04:21.141903 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
819 07:04:21.152768 PIEI prepare done
820 07:04:21.153357 fastboot data load
821 07:04:21.153896 fastboot data verify
822 07:04:21.158328 verify result: 266
823 07:04:21.163965 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
824 07:04:21.164576 LPDDR4 probe
825 07:04:21.165109 ddr clk to 1584MHz
826 07:04:21.171905 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
827 07:04:21.209211
828 07:04:21.209840 dmc_version 0001
829 07:04:21.215890 Check phy result
830 07:04:21.221787 INFO : End of CA training
831 07:04:21.222354 INFO : End of initialization
832 07:04:21.227352 INFO : Training has run successfully!
833 07:04:21.227915 Check phy result
834 07:04:21.232970 INFO : End of initialization
835 07:04:21.233526 INFO : End of read enable training
836 07:04:21.238507 INFO : End of fine write leveling
837 07:04:21.244203 INFO : End of Write leveling coarse delay
838 07:04:21.244763 INFO : Training has run successfully!
839 07:04:21.245283 Check phy result
840 07:04:21.249785 INFO : End of initialization
841 07:04:21.250358 INFO : End of read dq deskew training
842 07:04:21.255333 INFO : End of MPR read delay center optimization
843 07:04:21.260988 INFO : End of write delay center optimization
844 07:04:21.266564 INFO : End of read delay center optimization
845 07:04:21.267133 INFO : End of max read latency training
846 07:04:21.272264 INFO : Training has run successfully!
847 07:04:21.272824 1D training succeed
848 07:04:21.281484 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 07:04:21.328902 Check phy result
850 07:04:21.329536 INFO : End of initialization
851 07:04:21.350565 INFO : End of 2D read delay Voltage center optimization
852 07:04:21.370884 INFO : End of 2D read delay Voltage center optimization
853 07:04:21.422878 INFO : End of 2D write delay Voltage center optimization
854 07:04:21.472262 INFO : End of 2D write delay Voltage center optimization
855 07:04:21.477768 INFO : Training has run successfully!
856 07:04:21.478355
857 07:04:21.478905 channel==0
858 07:04:21.483477 RxClkDly_Margin_A0==88 ps 9
859 07:04:21.484128 TxDqDly_Margin_A0==98 ps 10
860 07:04:21.488986 RxClkDly_Margin_A1==88 ps 9
861 07:04:21.489544 TxDqDly_Margin_A1==98 ps 10
862 07:04:21.490075 TrainedVREFDQ_A0==74
863 07:04:21.494609 TrainedVREFDQ_A1==74
864 07:04:21.495245 VrefDac_Margin_A0==25
865 07:04:21.495760 DeviceVref_Margin_A0==40
866 07:04:21.500247 VrefDac_Margin_A1==23
867 07:04:21.500861 DeviceVref_Margin_A1==40
868 07:04:21.501376
869 07:04:21.501880
870 07:04:21.505758 channel==1
871 07:04:21.506307 RxClkDly_Margin_A0==98 ps 10
872 07:04:21.506812 TxDqDly_Margin_A0==98 ps 10
873 07:04:21.511500 RxClkDly_Margin_A1==88 ps 9
874 07:04:21.512068 TxDqDly_Margin_A1==88 ps 9
875 07:04:21.516990 TrainedVREFDQ_A0==77
876 07:04:21.517547 TrainedVREFDQ_A1==77
877 07:04:21.518050 VrefDac_Margin_A0==22
878 07:04:21.522580 DeviceVref_Margin_A0==37
879 07:04:21.523125 VrefDac_Margin_A1==24
880 07:04:21.528226 DeviceVref_Margin_A1==37
881 07:04:21.528770
882 07:04:21.529264 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
883 07:04:21.529763
884 07:04:21.561791 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
885 07:04:21.562480 2D training succeed
886 07:04:21.567491 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
887 07:04:21.572995 auto size-- 65535DDR cs0 size: 2048MB
888 07:04:21.573556 DDR cs1 size: 2048MB
889 07:04:21.578581 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
890 07:04:21.579153 cs0 DataBus test pass
891 07:04:21.584240 cs1 DataBus test pass
892 07:04:21.584815 cs0 AddrBus test pass
893 07:04:21.585318 cs1 AddrBus test pass
894 07:04:21.585805
895 07:04:21.589762 100bdlr_step_size ps== 420
896 07:04:21.590343 result report
897 07:04:21.595450 boot times 0Enable ddr reg access
898 07:04:21.600727 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
899 07:04:21.614172 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
900 07:04:22.188131 0.0;M3 CHK:0;cm4_sp_mode 0
901 07:04:22.188931 MVN_1=0x00000000
902 07:04:22.193584 MVN_2=0x00000000
903 07:04:22.199206 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
904 07:04:22.199800 OPS=0x10
905 07:04:22.200374 ring efuse init
906 07:04:22.200905 chipver efuse init
907 07:04:22.204782 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
908 07:04:22.210392 [0.018961 Inits done]
909 07:04:22.210954 secure task start!
910 07:04:22.211486 high task start!
911 07:04:22.214970 low task start!
912 07:04:22.215531 run into bl31
913 07:04:22.221627 NOTICE: BL31: v1.3(release):4fc40b1
914 07:04:22.229395 NOTICE: BL31: Built : 15:58:17, May 22 2019
915 07:04:22.230006 NOTICE: BL31: G12A normal boot!
916 07:04:22.254767 NOTICE: BL31: BL33 decompress pass
917 07:04:22.260457 ERROR: Error initializing runtime service opteed_fast
918 07:04:23.493479
919 07:04:23.494288
920 07:04:23.501861 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
921 07:04:23.502466
922 07:04:23.503011 Model: Libre Computer AML-A311D-CC Alta
923 07:04:23.710314 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
924 07:04:23.733563 DRAM: 2 GiB (effective 3.8 GiB)
925 07:04:23.876621 Core: 408 devices, 31 uclasses, devicetree: separate
926 07:04:23.882405 WDT: Not starting watchdog@f0d0
927 07:04:23.914695 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
928 07:04:23.927120 Loading Environment from FAT... Card did not respond to voltage select! : -110
929 07:04:23.932118 ** Bad device specification mmc 0 **
930 07:04:23.942463 Card did not respond to voltage select! : -110
931 07:04:23.950095 ** Bad device specification mmc 0 **
932 07:04:23.950703 Couldn't find partition mmc 0
933 07:04:23.958442 Card did not respond to voltage select! : -110
934 07:04:23.963939 ** Bad device specification mmc 0 **
935 07:04:23.964566 Couldn't find partition mmc 0
936 07:04:23.969017 Error: could not access storage.
937 07:04:24.311493 Net: eth0: ethernet@ff3f0000
938 07:04:24.312297 starting USB...
939 07:04:24.563389 Bus usb@ff500000: Register 3000140 NbrPorts 3
940 07:04:24.564194 Starting the controller
941 07:04:24.570253 USB XHCI 1.10
942 07:04:26.124337 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
943 07:04:26.132625 scanning usb for storage devices... 0 Storage Device(s) found
945 07:04:26.184612 Hit any key to stop autoboot: 1
946 07:04:26.185667 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
947 07:04:26.186422 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
948 07:04:26.187047 Setting prompt string to ['=>']
949 07:04:26.187662 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
950 07:04:26.200088 0
951 07:04:26.201150 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
952 07:04:26.201801 Sending with 10 millisecond of delay
954 07:04:27.338168 => setenv autoload no
955 07:04:27.349032 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
956 07:04:27.354489 setenv autoload no
957 07:04:27.355266 Sending with 10 millisecond of delay
959 07:04:29.152725 => setenv initrd_high 0xffffffff
960 07:04:29.163540 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
961 07:04:29.164520 setenv initrd_high 0xffffffff
962 07:04:29.165249 Sending with 10 millisecond of delay
964 07:04:30.781220 => setenv fdt_high 0xffffffff
965 07:04:30.791969 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
966 07:04:30.792816 setenv fdt_high 0xffffffff
967 07:04:30.793516 Sending with 10 millisecond of delay
969 07:04:31.085280 => dhcp
970 07:04:31.096083 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
971 07:04:31.096954 dhcp
972 07:04:31.097378 Speed: 1000, full duplex
973 07:04:31.097785 BOOTP broadcast 1
974 07:04:31.343955 BOOTP broadcast 2
975 07:04:31.356837 DHCP client bound to address 192.168.6.33 (260 ms)
976 07:04:31.357554 Sending with 10 millisecond of delay
978 07:04:33.033879 => setenv serverip 192.168.6.2
979 07:04:33.044659 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
980 07:04:33.045557 setenv serverip 192.168.6.2
981 07:04:33.046262 Sending with 10 millisecond of delay
983 07:04:36.769214 => tftpboot 0x01080000 714863/tftp-deploy-4qwjekvt/kernel/uImage
984 07:04:36.780030 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
985 07:04:36.780878 tftpboot 0x01080000 714863/tftp-deploy-4qwjekvt/kernel/uImage
986 07:04:36.781334 Speed: 1000, full duplex
987 07:04:36.781771 Using ethernet@ff3f0000 device
988 07:04:36.782793 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
989 07:04:36.788158 Filename '714863/tftp-deploy-4qwjekvt/kernel/uImage'.
990 07:04:36.792184 Load address: 0x1080000
991 07:04:39.667897 Loading: *################################################## 43.2 MiB
992 07:04:39.668566 15 MiB/s
993 07:04:39.669000 done
994 07:04:39.672155 Bytes transferred = 45308480 (2b35a40 hex)
995 07:04:39.673031 Sending with 10 millisecond of delay
997 07:04:44.359431 => tftpboot 0x08000000 714863/tftp-deploy-4qwjekvt/ramdisk/ramdisk.cpio.gz.uboot
998 07:04:44.370194 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
999 07:04:44.370990 tftpboot 0x08000000 714863/tftp-deploy-4qwjekvt/ramdisk/ramdisk.cpio.gz.uboot
1000 07:04:44.371424 Speed: 1000, full duplex
1001 07:04:44.371830 Using ethernet@ff3f0000 device
1002 07:04:44.373001 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1003 07:04:44.384926 Filename '714863/tftp-deploy-4qwjekvt/ramdisk/ramdisk.cpio.gz.uboot'.
1004 07:04:44.385394 Load address: 0x8000000
1005 07:04:50.932438 Loading: *#####################T ############################ UDP wrong checksum 00000005 00009dc3
1006 07:04:55.934433 T UDP wrong checksum 00000005 00009dc3
1007 07:05:05.936336 T T UDP wrong checksum 00000005 00009dc3
1008 07:05:25.940401 T T T T UDP wrong checksum 00000005 00009dc3
1009 07:05:40.944122 T T
1010 07:05:40.944798 Retry count exceeded; starting again
1012 07:05:40.946336 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1015 07:05:40.948433 end: 2.4 uboot-commands (duration 00:01:46) [common]
1017 07:05:40.949938 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1019 07:05:40.951049 end: 2 uboot-action (duration 00:01:46) [common]
1021 07:05:40.952726 Cleaning after the job
1022 07:05:40.953312 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/ramdisk
1023 07:05:40.954752 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/kernel
1024 07:05:41.003252 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/dtb
1025 07:05:41.004141 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/nfsrootfs
1026 07:05:41.316769 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714863/tftp-deploy-4qwjekvt/modules
1027 07:05:41.337452 start: 4.1 power-off (timeout 00:00:30) [common]
1028 07:05:41.338138 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1029 07:05:41.371201 >> OK - accepted request
1030 07:05:41.373236 Returned 0 in 0 seconds
1031 07:05:41.474031 end: 4.1 power-off (duration 00:00:00) [common]
1033 07:05:41.475052 start: 4.2 read-feedback (timeout 00:10:00) [common]
1034 07:05:41.475716 Listened to connection for namespace 'common' for up to 1s
1035 07:05:42.476698 Finalising connection for namespace 'common'
1036 07:05:42.477183 Disconnecting from shell: Finalise
1037 07:05:42.477475 =>
1038 07:05:42.578170 end: 4.2 read-feedback (duration 00:00:01) [common]
1039 07:05:42.578628 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714863
1040 07:05:45.264745 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714863
1041 07:05:45.265396 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.