Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:45:51.193070 lava-dispatcher, installed at version: 2024.01
2 06:45:51.193838 start: 0 validate
3 06:45:51.194301 Start time: 2024-09-06 06:45:51.194272+00:00 (UTC)
4 06:45:51.194838 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:45:51.195373 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:45:51.231244 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:45:51.231791 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:45:51.262825 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:45:51.263451 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 06:45:56.328820 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:45:56.329299 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:45:56.361633 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:45:56.362089 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 06:45:58.426090 validate duration: 7.23
16 06:45:58.427571 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:45:58.428229 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:45:58.428828 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:45:58.429820 Not decompressing ramdisk as can be used compressed.
20 06:45:58.430596 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 06:45:58.431099 saving as /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/ramdisk/initrd.cpio.gz
22 06:45:58.431623 total size: 5628140 (5 MB)
23 06:45:58.477254 progress 0 % (0 MB)
24 06:45:58.483535 progress 5 % (0 MB)
25 06:45:58.492426 progress 10 % (0 MB)
26 06:45:58.500443 progress 15 % (0 MB)
27 06:45:58.509094 progress 20 % (1 MB)
28 06:45:58.516178 progress 25 % (1 MB)
29 06:45:58.520550 progress 30 % (1 MB)
30 06:45:58.524852 progress 35 % (1 MB)
31 06:45:58.528555 progress 40 % (2 MB)
32 06:45:58.532737 progress 45 % (2 MB)
33 06:45:58.536543 progress 50 % (2 MB)
34 06:45:58.540647 progress 55 % (2 MB)
35 06:45:58.544753 progress 60 % (3 MB)
36 06:45:58.548439 progress 65 % (3 MB)
37 06:45:58.552612 progress 70 % (3 MB)
38 06:45:58.556387 progress 75 % (4 MB)
39 06:45:58.560512 progress 80 % (4 MB)
40 06:45:58.564194 progress 85 % (4 MB)
41 06:45:58.568251 progress 90 % (4 MB)
42 06:45:58.571949 progress 95 % (5 MB)
43 06:45:58.575261 progress 100 % (5 MB)
44 06:45:58.575939 5 MB downloaded in 0.14 s (37.20 MB/s)
45 06:45:58.576523 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:45:58.577407 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:45:58.577699 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:45:58.577970 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:45:58.578445 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
51 06:45:58.578695 saving as /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/kernel/Image
52 06:45:58.578904 total size: 45308416 (43 MB)
53 06:45:58.579118 No compression specified
54 06:45:58.613315 progress 0 % (0 MB)
55 06:45:58.641527 progress 5 % (2 MB)
56 06:45:58.669737 progress 10 % (4 MB)
57 06:45:58.697734 progress 15 % (6 MB)
58 06:45:58.725663 progress 20 % (8 MB)
59 06:45:58.753269 progress 25 % (10 MB)
60 06:45:58.780754 progress 30 % (12 MB)
61 06:45:58.808038 progress 35 % (15 MB)
62 06:45:58.836315 progress 40 % (17 MB)
63 06:45:58.863593 progress 45 % (19 MB)
64 06:45:58.891100 progress 50 % (21 MB)
65 06:45:58.918509 progress 55 % (23 MB)
66 06:45:58.945510 progress 60 % (25 MB)
67 06:45:58.972798 progress 65 % (28 MB)
68 06:45:59.000516 progress 70 % (30 MB)
69 06:45:59.028462 progress 75 % (32 MB)
70 06:45:59.055933 progress 80 % (34 MB)
71 06:45:59.083376 progress 85 % (36 MB)
72 06:45:59.110719 progress 90 % (38 MB)
73 06:45:59.137912 progress 95 % (41 MB)
74 06:45:59.164656 progress 100 % (43 MB)
75 06:45:59.165408 43 MB downloaded in 0.59 s (73.67 MB/s)
76 06:45:59.165891 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:45:59.166704 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:45:59.166977 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:45:59.167239 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:45:59.167709 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 06:45:59.168003 saving as /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 06:45:59.168216 total size: 53173 (0 MB)
84 06:45:59.168425 No compression specified
85 06:45:59.202224 progress 61 % (0 MB)
86 06:45:59.203068 progress 100 % (0 MB)
87 06:45:59.203601 0 MB downloaded in 0.04 s (1.43 MB/s)
88 06:45:59.204112 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:45:59.204931 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:45:59.205194 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:45:59.205456 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:45:59.205920 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 06:45:59.206160 saving as /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/nfsrootfs/full.rootfs.tar
95 06:45:59.206364 total size: 474398908 (452 MB)
96 06:45:59.206574 Using unxz to decompress xz
97 06:45:59.243558 progress 0 % (0 MB)
98 06:46:00.375768 progress 5 % (22 MB)
99 06:46:01.830327 progress 10 % (45 MB)
100 06:46:02.266708 progress 15 % (67 MB)
101 06:46:03.034383 progress 20 % (90 MB)
102 06:46:03.568113 progress 25 % (113 MB)
103 06:46:03.923527 progress 30 % (135 MB)
104 06:46:04.524424 progress 35 % (158 MB)
105 06:46:05.408727 progress 40 % (181 MB)
106 06:46:06.282703 progress 45 % (203 MB)
107 06:46:07.030404 progress 50 % (226 MB)
108 06:46:07.798003 progress 55 % (248 MB)
109 06:46:09.040072 progress 60 % (271 MB)
110 06:46:10.537152 progress 65 % (294 MB)
111 06:46:12.161012 progress 70 % (316 MB)
112 06:46:15.286156 progress 75 % (339 MB)
113 06:46:17.758943 progress 80 % (361 MB)
114 06:46:20.665859 progress 85 % (384 MB)
115 06:46:23.841856 progress 90 % (407 MB)
116 06:46:27.040914 progress 95 % (429 MB)
117 06:46:30.203079 progress 100 % (452 MB)
118 06:46:30.215923 452 MB downloaded in 31.01 s (14.59 MB/s)
119 06:46:30.216938 end: 1.4.1 http-download (duration 00:00:31) [common]
121 06:46:30.218671 end: 1.4 download-retry (duration 00:00:31) [common]
122 06:46:30.219229 start: 1.5 download-retry (timeout 00:09:28) [common]
123 06:46:30.219782 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 06:46:30.220777 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
125 06:46:30.221272 saving as /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/modules/modules.tar
126 06:46:30.221714 total size: 11502724 (10 MB)
127 06:46:30.222171 Using unxz to decompress xz
128 06:46:30.265609 progress 0 % (0 MB)
129 06:46:30.343404 progress 5 % (0 MB)
130 06:46:30.428323 progress 10 % (1 MB)
131 06:46:30.508357 progress 15 % (1 MB)
132 06:46:30.588185 progress 20 % (2 MB)
133 06:46:30.664233 progress 25 % (2 MB)
134 06:46:30.745205 progress 30 % (3 MB)
135 06:46:30.819285 progress 35 % (3 MB)
136 06:46:30.896803 progress 40 % (4 MB)
137 06:46:30.967880 progress 45 % (4 MB)
138 06:46:31.045078 progress 50 % (5 MB)
139 06:46:31.119705 progress 55 % (6 MB)
140 06:46:31.198297 progress 60 % (6 MB)
141 06:46:31.283232 progress 65 % (7 MB)
142 06:46:31.359543 progress 70 % (7 MB)
143 06:46:31.453669 progress 75 % (8 MB)
144 06:46:31.541751 progress 80 % (8 MB)
145 06:46:31.621799 progress 85 % (9 MB)
146 06:46:31.691628 progress 90 % (9 MB)
147 06:46:31.766842 progress 95 % (10 MB)
148 06:46:31.842196 progress 100 % (10 MB)
149 06:46:31.852107 10 MB downloaded in 1.63 s (6.73 MB/s)
150 06:46:31.853069 end: 1.5.1 http-download (duration 00:00:02) [common]
152 06:46:31.854768 end: 1.5 download-retry (duration 00:00:02) [common]
153 06:46:31.855314 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 06:46:31.855848 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 06:46:47.430390 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/714802/extract-nfsrootfs-33_4kp35
156 06:46:47.431004 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 06:46:47.431291 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 06:46:47.432153 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a
159 06:46:47.432635 makedir: /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin
160 06:46:47.433020 makedir: /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/tests
161 06:46:47.433349 makedir: /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/results
162 06:46:47.433689 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-add-keys
163 06:46:47.434217 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-add-sources
164 06:46:47.434723 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-background-process-start
165 06:46:47.435221 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-background-process-stop
166 06:46:47.435854 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-common-functions
167 06:46:47.436433 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-echo-ipv4
168 06:46:47.436953 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-install-packages
169 06:46:47.437515 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-installed-packages
170 06:46:47.438011 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-os-build
171 06:46:47.438489 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-probe-channel
172 06:46:47.438965 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-probe-ip
173 06:46:47.439435 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-target-ip
174 06:46:47.439911 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-target-mac
175 06:46:47.440425 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-target-storage
176 06:46:47.440940 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-test-case
177 06:46:47.441476 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-test-event
178 06:46:47.441955 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-test-feedback
179 06:46:47.442427 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-test-raise
180 06:46:47.442894 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-test-reference
181 06:46:47.443365 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-test-runner
182 06:46:47.443842 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-test-set
183 06:46:47.444352 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-test-shell
184 06:46:47.444860 Updating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-install-packages (oe)
185 06:46:47.445403 Updating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/bin/lava-installed-packages (oe)
186 06:46:47.445845 Creating /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/environment
187 06:46:47.446214 LAVA metadata
188 06:46:47.446471 - LAVA_JOB_ID=714802
189 06:46:47.446683 - LAVA_DISPATCHER_IP=192.168.6.2
190 06:46:47.447043 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 06:46:47.448025 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 06:46:47.448352 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 06:46:47.448561 skipped lava-vland-overlay
194 06:46:47.448802 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 06:46:47.449057 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 06:46:47.449276 skipped lava-multinode-overlay
197 06:46:47.449517 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 06:46:47.449769 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 06:46:47.450018 Loading test definitions
200 06:46:47.450294 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 06:46:47.450514 Using /lava-714802 at stage 0
202 06:46:47.451682 uuid=714802_1.6.2.4.1 testdef=None
203 06:46:47.452007 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 06:46:47.452279 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 06:46:47.454048 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 06:46:47.454840 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 06:46:47.457047 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 06:46:47.457886 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 06:46:47.459948 runner path: /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 714802_1.6.2.4.1
212 06:46:47.460562 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 06:46:47.461315 Creating lava-test-runner.conf files
215 06:46:47.461517 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714802/lava-overlay-zgdkca6a/lava-714802/0 for stage 0
216 06:46:47.461843 - 0_v4l2-decoder-conformance-h264
217 06:46:47.462179 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 06:46:47.462448 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 06:46:47.484051 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 06:46:47.484416 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 06:46:47.484673 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 06:46:47.484937 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 06:46:47.485196 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 06:46:48.184618 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 06:46:48.185095 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 06:46:48.185345 extracting modules file /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714802/extract-nfsrootfs-33_4kp35
227 06:46:49.533186 extracting modules file /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714802/extract-overlay-ramdisk-9nui4jhc/ramdisk
228 06:46:50.923495 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 06:46:50.924007 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 06:46:50.924293 [common] Applying overlay to NFS
231 06:46:50.924508 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714802/compress-overlay-lfqclo57/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714802/extract-nfsrootfs-33_4kp35
232 06:46:50.953800 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 06:46:50.954200 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 06:46:50.954471 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 06:46:50.954703 Converting downloaded kernel to a uImage
236 06:46:50.955012 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/kernel/Image /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/kernel/uImage
237 06:46:51.411842 output: Image Name:
238 06:46:51.412301 output: Created: Fri Sep 6 06:46:50 2024
239 06:46:51.412515 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 06:46:51.412721 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
241 06:46:51.412923 output: Load Address: 01080000
242 06:46:51.413121 output: Entry Point: 01080000
243 06:46:51.413320 output:
244 06:46:51.413657 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 06:46:51.413925 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 06:46:51.414196 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 06:46:51.414447 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 06:46:51.414704 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 06:46:51.414957 Building ramdisk /var/lib/lava/dispatcher/tmp/714802/extract-overlay-ramdisk-9nui4jhc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714802/extract-overlay-ramdisk-9nui4jhc/ramdisk
250 06:46:53.542762 >> 165160 blocks
251 06:47:01.264945 Adding RAMdisk u-boot header.
252 06:47:01.265595 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714802/extract-overlay-ramdisk-9nui4jhc/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714802/extract-overlay-ramdisk-9nui4jhc/ramdisk.cpio.gz.uboot
253 06:47:01.557661 output: Image Name:
254 06:47:01.558083 output: Created: Fri Sep 6 06:47:01 2024
255 06:47:01.558294 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 06:47:01.558499 output: Data Size: 23257911 Bytes = 22712.80 KiB = 22.18 MiB
257 06:47:01.558701 output: Load Address: 00000000
258 06:47:01.558900 output: Entry Point: 00000000
259 06:47:01.559097 output:
260 06:47:01.559698 rename /var/lib/lava/dispatcher/tmp/714802/extract-overlay-ramdisk-9nui4jhc/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/ramdisk/ramdisk.cpio.gz.uboot
261 06:47:01.560330 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 06:47:01.560998 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 06:47:01.561658 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 06:47:01.562219 No LXC device requested
265 06:47:01.563219 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 06:47:01.563862 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 06:47:01.564471 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 06:47:01.564956 Checking files for TFTP limit of 4294967296 bytes.
269 06:47:01.567907 end: 1 tftp-deploy (duration 00:01:03) [common]
270 06:47:01.568578 start: 2 uboot-action (timeout 00:05:00) [common]
271 06:47:01.569151 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 06:47:01.569698 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 06:47:01.570242 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 06:47:01.570814 Using kernel file from prepare-kernel: 714802/tftp-deploy-6kcla559/kernel/uImage
275 06:47:01.571495 substitutions:
276 06:47:01.571943 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 06:47:01.572420 - {DTB_ADDR}: 0x01070000
278 06:47:01.572863 - {DTB}: 714802/tftp-deploy-6kcla559/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 06:47:01.573302 - {INITRD}: 714802/tftp-deploy-6kcla559/ramdisk/ramdisk.cpio.gz.uboot
280 06:47:01.573733 - {KERNEL_ADDR}: 0x01080000
281 06:47:01.574163 - {KERNEL}: 714802/tftp-deploy-6kcla559/kernel/uImage
282 06:47:01.574594 - {LAVA_MAC}: None
283 06:47:01.575065 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/714802/extract-nfsrootfs-33_4kp35
284 06:47:01.575502 - {NFS_SERVER_IP}: 192.168.6.2
285 06:47:01.575933 - {PRESEED_CONFIG}: None
286 06:47:01.576394 - {PRESEED_LOCAL}: None
287 06:47:01.576827 - {RAMDISK_ADDR}: 0x08000000
288 06:47:01.577252 - {RAMDISK}: 714802/tftp-deploy-6kcla559/ramdisk/ramdisk.cpio.gz.uboot
289 06:47:01.577678 - {ROOT_PART}: None
290 06:47:01.578104 - {ROOT}: None
291 06:47:01.578532 - {SERVER_IP}: 192.168.6.2
292 06:47:01.578957 - {TEE_ADDR}: 0x83000000
293 06:47:01.579383 - {TEE}: None
294 06:47:01.579808 Parsed boot commands:
295 06:47:01.580251 - setenv autoload no
296 06:47:01.580680 - setenv initrd_high 0xffffffff
297 06:47:01.581104 - setenv fdt_high 0xffffffff
298 06:47:01.581528 - dhcp
299 06:47:01.581949 - setenv serverip 192.168.6.2
300 06:47:01.582372 - tftpboot 0x01080000 714802/tftp-deploy-6kcla559/kernel/uImage
301 06:47:01.582795 - tftpboot 0x08000000 714802/tftp-deploy-6kcla559/ramdisk/ramdisk.cpio.gz.uboot
302 06:47:01.583217 - tftpboot 0x01070000 714802/tftp-deploy-6kcla559/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 06:47:01.583639 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/714802/extract-nfsrootfs-33_4kp35,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 06:47:01.584099 - bootm 0x01080000 0x08000000 0x01070000
305 06:47:01.584636 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 06:47:01.586255 start: 2.3 connect-device (timeout 00:05:00) [common]
308 06:47:01.586708 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 06:47:01.601561 Setting prompt string to ['lava-test: # ']
310 06:47:01.603184 end: 2.3 connect-device (duration 00:00:00) [common]
311 06:47:01.603849 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 06:47:01.604485 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 06:47:01.605063 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 06:47:01.606315 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 06:47:01.640463 >> OK - accepted request
316 06:47:01.642523 Returned 0 in 0 seconds
317 06:47:01.743786 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 06:47:01.745612 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 06:47:01.746240 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 06:47:01.746801 Setting prompt string to ['Hit any key to stop autoboot']
322 06:47:01.747301 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 06:47:01.749022 Trying 192.168.56.21...
324 06:47:01.749536 Connected to conserv1.
325 06:47:01.749996 Escape character is '^]'.
326 06:47:01.750449
327 06:47:01.750898 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 06:47:01.751353
329 06:47:09.171926 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 06:47:09.172559 bl2_stage_init 0x01
331 06:47:09.172962 bl2_stage_init 0x81
332 06:47:09.177482 hw id: 0x0000 - pwm id 0x01
333 06:47:09.177947 bl2_stage_init 0xc1
334 06:47:09.178356 bl2_stage_init 0x02
335 06:47:09.178745
336 06:47:09.183095 L0:00000000
337 06:47:09.183550 L1:00000703
338 06:47:09.184163 L2:00008067
339 06:47:09.184573 L3:15000000
340 06:47:09.184975 S1:00000000
341 06:47:09.189698 B2:20282000
342 06:47:09.190177 B1:a0f83180
343 06:47:09.190582
344 06:47:09.190985 TE: 70600
345 06:47:09.191383
346 06:47:09.195272 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 06:47:09.195728
348 06:47:09.196159 Board ID = 1
349 06:47:09.200854 Set cpu clk to 24M
350 06:47:09.201304 Set clk81 to 24M
351 06:47:09.201701 Use GP1_pll as DSU clk.
352 06:47:09.206450 DSU clk: 1200 Mhz
353 06:47:09.206901 CPU clk: 1200 MHz
354 06:47:09.207294 Set clk81 to 166.6M
355 06:47:09.212066 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 06:47:09.217676 board id: 1
357 06:47:09.222538 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 06:47:09.233699 fw parse done
359 06:47:09.238915 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 06:47:09.281881 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 06:47:09.293299 PIEI prepare done
362 06:47:09.293769 fastboot data load
363 06:47:09.294167 fastboot data verify
364 06:47:09.298878 verify result: 266
365 06:47:09.304494 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 06:47:09.304957 LPDDR4 probe
367 06:47:09.305349 ddr clk to 1584MHz
368 06:47:09.311534 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 06:47:09.348827
370 06:47:09.349291 dmc_version 0001
371 06:47:09.355430 Check phy result
372 06:47:09.362279 INFO : End of CA training
373 06:47:09.362733 INFO : End of initialization
374 06:47:09.367867 INFO : Training has run successfully!
375 06:47:09.368345 Check phy result
376 06:47:09.373462 INFO : End of initialization
377 06:47:09.373909 INFO : End of read enable training
378 06:47:09.379099 INFO : End of fine write leveling
379 06:47:09.384731 INFO : End of Write leveling coarse delay
380 06:47:09.385182 INFO : Training has run successfully!
381 06:47:09.385575 Check phy result
382 06:47:09.390268 INFO : End of initialization
383 06:47:09.390714 INFO : End of read dq deskew training
384 06:47:09.395885 INFO : End of MPR read delay center optimization
385 06:47:09.401513 INFO : End of write delay center optimization
386 06:47:09.407113 INFO : End of read delay center optimization
387 06:47:09.407563 INFO : End of max read latency training
388 06:47:09.412728 INFO : Training has run successfully!
389 06:47:09.413175 1D training succeed
390 06:47:09.421388 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 06:47:09.469486 Check phy result
392 06:47:09.469966 INFO : End of initialization
393 06:47:09.491550 INFO : End of 2D read delay Voltage center optimization
394 06:47:09.510158 INFO : End of 2D read delay Voltage center optimization
395 06:47:09.562607 INFO : End of 2D write delay Voltage center optimization
396 06:47:09.612088 INFO : End of 2D write delay Voltage center optimization
397 06:47:09.617616 INFO : Training has run successfully!
398 06:47:09.618069
399 06:47:09.618469 channel==0
400 06:47:09.623201 RxClkDly_Margin_A0==88 ps 9
401 06:47:09.623653 TxDqDly_Margin_A0==98 ps 10
402 06:47:09.626464 RxClkDly_Margin_A1==88 ps 9
403 06:47:09.626916 TxDqDly_Margin_A1==98 ps 10
404 06:47:09.632229 TrainedVREFDQ_A0==74
405 06:47:09.632687 TrainedVREFDQ_A1==75
406 06:47:09.637635 VrefDac_Margin_A0==25
407 06:47:09.638084 DeviceVref_Margin_A0==40
408 06:47:09.638472 VrefDac_Margin_A1==23
409 06:47:09.643250 DeviceVref_Margin_A1==39
410 06:47:09.643698
411 06:47:09.644120
412 06:47:09.644511 channel==1
413 06:47:09.644897 RxClkDly_Margin_A0==88 ps 9
414 06:47:09.646567 TxDqDly_Margin_A0==98 ps 10
415 06:47:09.652192 RxClkDly_Margin_A1==88 ps 9
416 06:47:09.652638 TxDqDly_Margin_A1==88 ps 9
417 06:47:09.653034 TrainedVREFDQ_A0==77
418 06:47:09.657795 TrainedVREFDQ_A1==77
419 06:47:09.658250 VrefDac_Margin_A0==22
420 06:47:09.663359 DeviceVref_Margin_A0==37
421 06:47:09.663806 VrefDac_Margin_A1==22
422 06:47:09.664230 DeviceVref_Margin_A1==37
423 06:47:09.664617
424 06:47:09.668928 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 06:47:09.669378
426 06:47:09.702490 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
427 06:47:09.703031 2D training succeed
428 06:47:09.708212 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 06:47:09.713787 auto size-- 65535DDR cs0 size: 2048MB
430 06:47:09.714245 DDR cs1 size: 2048MB
431 06:47:09.719345 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 06:47:09.719801 cs0 DataBus test pass
433 06:47:09.720243 cs1 DataBus test pass
434 06:47:09.724943 cs0 AddrBus test pass
435 06:47:09.725396 cs1 AddrBus test pass
436 06:47:09.725787
437 06:47:09.730557 100bdlr_step_size ps== 464
438 06:47:09.731034 result report
439 06:47:09.731423 boot times 0Enable ddr reg access
440 06:47:09.740179 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 06:47:09.753557 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 06:47:10.408800 bl2z: ptr: 05129330, size: 00001e40
443 06:47:10.415297 0.0;M3 CHK:0;cm4_sp_mode 0
444 06:47:10.415768 MVN_1=0x00000000
445 06:47:10.416228 MVN_2=0x00000000
446 06:47:10.426646 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 06:47:10.427128 OPS=0x04
448 06:47:10.427540 ring efuse init
449 06:47:10.432329 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 06:47:10.432796 [0.017319 Inits done]
451 06:47:10.433200 secure task start!
452 06:47:10.440022 high task start!
453 06:47:10.440476 low task start!
454 06:47:10.440877 run into bl31
455 06:47:10.448576 NOTICE: BL31: v1.3(release):4fc40b1
456 06:47:10.456373 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 06:47:10.456834 NOTICE: BL31: G12A normal boot!
458 06:47:10.471922 NOTICE: BL31: BL33 decompress pass
459 06:47:10.477536 ERROR: Error initializing runtime service opteed_fast
460 06:47:11.718439 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 06:47:11.718989 bl2_stage_init 0x01
462 06:47:11.719405 bl2_stage_init 0x81
463 06:47:11.724092 hw id: 0x0000 - pwm id 0x01
464 06:47:11.724569 bl2_stage_init 0xc1
465 06:47:11.729604 bl2_stage_init 0x02
466 06:47:11.730067
467 06:47:11.730482 L0:00000000
468 06:47:11.730882 L1:00000703
469 06:47:11.731281 L2:00008067
470 06:47:11.731673 L3:15000000
471 06:47:11.735221 S1:00000000
472 06:47:11.735677 B2:20282000
473 06:47:11.736118 B1:a0f83180
474 06:47:11.736518
475 06:47:11.736910 TE: 67775
476 06:47:11.737305
477 06:47:11.740835 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 06:47:11.741312
479 06:47:11.746440 Board ID = 1
480 06:47:11.746923 Set cpu clk to 24M
481 06:47:11.747350 Set clk81 to 24M
482 06:47:11.751977 Use GP1_pll as DSU clk.
483 06:47:11.752475 DSU clk: 1200 Mhz
484 06:47:11.752918 CPU clk: 1200 MHz
485 06:47:11.757575 Set clk81 to 166.6M
486 06:47:11.763160 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 06:47:11.763651 board id: 1
488 06:47:11.770344 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 06:47:11.781003 fw parse done
490 06:47:11.786925 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 06:47:11.829559 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 06:47:11.840463 PIEI prepare done
493 06:47:11.840906 fastboot data load
494 06:47:11.841300 fastboot data verify
495 06:47:11.846126 verify result: 266
496 06:47:11.851758 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 06:47:11.852254 LPDDR4 probe
498 06:47:11.852648 ddr clk to 1584MHz
499 06:47:11.861803 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
500 06:47:13.222633 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
501 06:47:13.223215 bl2_stage_init 0x01
502 06:47:13.223640 bl2_stage_init 0x81
503 06:47:13.228290 hw id: 0x0000 - pwm id 0x01
504 06:47:13.228785 bl2_stage_init 0xc1
505 06:47:13.231774 bl2_stage_init 0x02
506 06:47:13.232265
507 06:47:13.232683 L0:00000000
508 06:47:13.233083 L1:00000703
509 06:47:13.237366 L2:00008067
510 06:47:13.237826 L3:15000000
511 06:47:13.238239 S1:00000000
512 06:47:13.238636 B2:20282000
513 06:47:13.239027 B1:a0f83180
514 06:47:13.239420
515 06:47:13.242974 TE: 70747
516 06:47:13.243433
517 06:47:13.248594 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
518 06:47:13.249074
519 06:47:13.249488 Board ID = 1
520 06:47:13.249883 Set cpu clk to 24M
521 06:47:13.254228 Set clk81 to 24M
522 06:47:13.254679 Use GP1_pll as DSU clk.
523 06:47:13.255085 DSU clk: 1200 Mhz
524 06:47:13.259742 CPU clk: 1200 MHz
525 06:47:13.260226 Set clk81 to 166.6M
526 06:47:13.265350 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
527 06:47:13.265801 board id: 1
528 06:47:13.274603 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
529 06:47:13.285268 fw parse done
530 06:47:13.291327 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
531 06:47:13.333890 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
532 06:47:13.344878 PIEI prepare done
533 06:47:13.345330 fastboot data load
534 06:47:13.345736 fastboot data verify
535 06:47:13.350472 verify result: 266
536 06:47:13.356078 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
537 06:47:13.356543 LPDDR4 probe
538 06:47:13.356949 ddr clk to 1584MHz
539 06:47:13.364101 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 06:47:13.401301
541 06:47:13.401753 dmc_version 0001
542 06:47:13.408023 Check phy result
543 06:47:13.413896 INFO : End of CA training
544 06:47:13.414345 INFO : End of initialization
545 06:47:13.419474 INFO : Training has run successfully!
546 06:47:13.419920 Check phy result
547 06:47:13.425101 INFO : End of initialization
548 06:47:13.425543 INFO : End of read enable training
549 06:47:13.430691 INFO : End of fine write leveling
550 06:47:13.436312 INFO : End of Write leveling coarse delay
551 06:47:13.436758 INFO : Training has run successfully!
552 06:47:13.437163 Check phy result
553 06:47:13.441882 INFO : End of initialization
554 06:47:13.442352 INFO : End of read dq deskew training
555 06:47:13.447452 INFO : End of MPR read delay center optimization
556 06:47:13.453054 INFO : End of write delay center optimization
557 06:47:13.458690 INFO : End of read delay center optimization
558 06:47:13.459150 INFO : End of max read latency training
559 06:47:13.464309 INFO : Training has run successfully!
560 06:47:13.464752 1D training succeed
561 06:47:13.473470 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
562 06:47:13.521044 Check phy result
563 06:47:13.521503 INFO : End of initialization
564 06:47:13.542650 INFO : End of 2D read delay Voltage center optimization
565 06:47:13.561630 INFO : End of 2D read delay Voltage center optimization
566 06:47:13.614469 INFO : End of 2D write delay Voltage center optimization
567 06:47:13.663743 INFO : End of 2D write delay Voltage center optimization
568 06:47:13.669315 INFO : Training has run successfully!
569 06:47:13.669783
570 06:47:13.670197 channel==0
571 06:47:13.674825 RxClkDly_Margin_A0==78 ps 8
572 06:47:13.675287 TxDqDly_Margin_A0==98 ps 10
573 06:47:13.680416 RxClkDly_Margin_A1==88 ps 9
574 06:47:13.680868 TxDqDly_Margin_A1==98 ps 10
575 06:47:13.681280 TrainedVREFDQ_A0==77
576 06:47:13.685997 TrainedVREFDQ_A1==74
577 06:47:13.686448 VrefDac_Margin_A0==25
578 06:47:13.686853 DeviceVref_Margin_A0==37
579 06:47:13.691736 VrefDac_Margin_A1==23
580 06:47:13.692211 DeviceVref_Margin_A1==40
581 06:47:13.692620
582 06:47:13.693019
583 06:47:13.697194 channel==1
584 06:47:13.697643 RxClkDly_Margin_A0==78 ps 8
585 06:47:13.698049 TxDqDly_Margin_A0==98 ps 10
586 06:47:13.702808 RxClkDly_Margin_A1==78 ps 8
587 06:47:13.703256 TxDqDly_Margin_A1==88 ps 9
588 06:47:13.708386 TrainedVREFDQ_A0==78
589 06:47:13.708837 TrainedVREFDQ_A1==75
590 06:47:13.709246 VrefDac_Margin_A0==22
591 06:47:13.714057 DeviceVref_Margin_A0==36
592 06:47:13.714518 VrefDac_Margin_A1==22
593 06:47:13.719819 DeviceVref_Margin_A1==39
594 06:47:13.720322
595 06:47:13.720740 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
596 06:47:13.721138
597 06:47:13.753211 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
598 06:47:13.753708 2D training succeed
599 06:47:13.758846 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
600 06:47:13.764427 auto size-- 65535DDR cs0 size: 2048MB
601 06:47:13.764896 DDR cs1 size: 2048MB
602 06:47:13.770016 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
603 06:47:13.770481 cs0 DataBus test pass
604 06:47:13.775809 cs1 DataBus test pass
605 06:47:13.776322 cs0 AddrBus test pass
606 06:47:13.776761 cs1 AddrBus test pass
607 06:47:13.777161
608 06:47:13.781266 100bdlr_step_size ps== 478
609 06:47:13.781744 result report
610 06:47:13.786825 boot times 0Enable ddr reg access
611 06:47:13.792080 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
612 06:47:13.805869 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
613 06:47:14.460519 bl2z: ptr: 05129330, size: 00001e40
614 06:47:14.467043 0.0;M3 CHK:0;cm4_sp_mode 0
615 06:47:14.467512 MVN_1=0x00000000
616 06:47:14.467918 MVN_2=0x00000000
617 06:47:14.478470 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
618 06:47:14.478932 OPS=0x04
619 06:47:14.479342 ring efuse init
620 06:47:14.484140 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
621 06:47:14.484601 [0.017320 Inits done]
622 06:47:14.485005 secure task start!
623 06:47:14.491703 high task start!
624 06:47:14.492189 low task start!
625 06:47:14.492596 run into bl31
626 06:47:14.500344 NOTICE: BL31: v1.3(release):4fc40b1
627 06:47:14.508176 NOTICE: BL31: Built : 15:57:33, May 22 2019
628 06:47:14.508634 NOTICE: BL31: G12A normal boot!
629 06:47:14.523644 NOTICE: BL31: BL33 decompress pass
630 06:47:14.529408 ERROR: Error initializing runtime service opteed_fast
631 06:47:15.771219 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
632 06:47:15.771791 bl2_stage_init 0x01
633 06:47:15.772256 bl2_stage_init 0x81
634 06:47:15.776859 hw id: 0x0000 - pwm id 0x01
635 06:47:15.777334 bl2_stage_init 0xc1
636 06:47:15.777740 bl2_stage_init 0x02
637 06:47:15.778143
638 06:47:15.782449 L0:00000000
639 06:47:15.782904 L1:00000703
640 06:47:15.783306 L2:00008067
641 06:47:15.783697 L3:15000000
642 06:47:15.784120 S1:00000000
643 06:47:15.788118 B2:20282000
644 06:47:15.788594 B1:a0f83180
645 06:47:15.789002
646 06:47:15.789401 TE: 69813
647 06:47:15.789824
648 06:47:15.793783 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
649 06:47:15.794254
650 06:47:15.799242 Board ID = 1
651 06:47:15.799694 Set cpu clk to 24M
652 06:47:15.800115 Set clk81 to 24M
653 06:47:15.804848 Use GP1_pll as DSU clk.
654 06:47:15.805296 DSU clk: 1200 Mhz
655 06:47:15.805689 CPU clk: 1200 MHz
656 06:47:15.806072 Set clk81 to 166.6M
657 06:47:15.816068 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
658 06:47:15.816541 board id: 1
659 06:47:15.821998 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
660 06:47:15.833374 fw parse done
661 06:47:15.839047 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
662 06:47:15.881675 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
663 06:47:15.893611 PIEI prepare done
664 06:47:15.894105 fastboot data load
665 06:47:15.894506 fastboot data verify
666 06:47:15.899169 verify result: 266
667 06:47:15.904740 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
668 06:47:15.905192 LPDDR4 probe
669 06:47:15.905583 ddr clk to 1584MHz
670 06:47:15.911728 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
671 06:47:15.949566
672 06:47:15.950062 dmc_version 0001
673 06:47:15.956526 Check phy result
674 06:47:15.963460 INFO : End of CA training
675 06:47:15.963910 INFO : End of initialization
676 06:47:15.969115 INFO : Training has run successfully!
677 06:47:15.969568 Check phy result
678 06:47:15.974764 INFO : End of initialization
679 06:47:15.975219 INFO : End of read enable training
680 06:47:15.980310 INFO : End of fine write leveling
681 06:47:15.985925 INFO : End of Write leveling coarse delay
682 06:47:15.986375 INFO : Training has run successfully!
683 06:47:15.986769 Check phy result
684 06:47:15.991518 INFO : End of initialization
685 06:47:15.992008 INFO : End of read dq deskew training
686 06:47:15.997368 INFO : End of MPR read delay center optimization
687 06:47:16.002797 INFO : End of write delay center optimization
688 06:47:16.008311 INFO : End of read delay center optimization
689 06:47:16.008802 INFO : End of max read latency training
690 06:47:16.013798 INFO : Training has run successfully!
691 06:47:16.014277 1D training succeed
692 06:47:16.022120 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
693 06:47:16.070342 Check phy result
694 06:47:16.070834 INFO : End of initialization
695 06:47:16.097854 INFO : End of 2D read delay Voltage center optimization
696 06:47:16.121902 INFO : End of 2D read delay Voltage center optimization
697 06:47:16.178728 INFO : End of 2D write delay Voltage center optimization
698 06:47:16.233723 INFO : End of 2D write delay Voltage center optimization
699 06:47:16.239322 INFO : Training has run successfully!
700 06:47:16.239828
701 06:47:16.240307 channel==0
702 06:47:16.244879 RxClkDly_Margin_A0==78 ps 8
703 06:47:16.245382 TxDqDly_Margin_A0==98 ps 10
704 06:47:16.250435 RxClkDly_Margin_A1==69 ps 7
705 06:47:16.250922 TxDqDly_Margin_A1==98 ps 10
706 06:47:16.251347 TrainedVREFDQ_A0==74
707 06:47:16.256212 TrainedVREFDQ_A1==74
708 06:47:16.256709 VrefDac_Margin_A0==25
709 06:47:16.257134 DeviceVref_Margin_A0==40
710 06:47:16.261638 VrefDac_Margin_A1==23
711 06:47:16.262130 DeviceVref_Margin_A1==40
712 06:47:16.262545
713 06:47:16.262955
714 06:47:16.267238 channel==1
715 06:47:16.267725 RxClkDly_Margin_A0==78 ps 8
716 06:47:16.268183 TxDqDly_Margin_A0==98 ps 10
717 06:47:16.272840 RxClkDly_Margin_A1==88 ps 9
718 06:47:16.273328 TxDqDly_Margin_A1==88 ps 9
719 06:47:16.278440 TrainedVREFDQ_A0==78
720 06:47:16.278930 TrainedVREFDQ_A1==77
721 06:47:16.279348 VrefDac_Margin_A0==22
722 06:47:16.284098 DeviceVref_Margin_A0==36
723 06:47:16.284585 VrefDac_Margin_A1==22
724 06:47:16.289633 DeviceVref_Margin_A1==37
725 06:47:16.290114
726 06:47:16.290529 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
727 06:47:16.290931
728 06:47:16.323172 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
729 06:47:16.323703 2D training succeed
730 06:47:16.328875 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
731 06:47:16.334433 auto size-- 65535DDR cs0 size: 2048MB
732 06:47:16.334920 DDR cs1 size: 2048MB
733 06:47:16.340098 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
734 06:47:16.340584 cs0 DataBus test pass
735 06:47:16.345640 cs1 DataBus test pass
736 06:47:16.346124 cs0 AddrBus test pass
737 06:47:16.346534 cs1 AddrBus test pass
738 06:47:16.346941
739 06:47:16.351252 100bdlr_step_size ps== 471
740 06:47:16.351754 result report
741 06:47:16.356862 boot times 0Enable ddr reg access
742 06:47:16.361846 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
743 06:47:16.374944 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
744 06:47:17.034961 bl2z: ptr: 05129330, size: 00001e40
745 06:47:17.044521 0.0;M3 CHK:0;cm4_sp_mode 0
746 06:47:17.045079 MVN_1=0x00000000
747 06:47:17.045507 MVN_2=0x00000000
748 06:47:17.055924 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
749 06:47:17.056500 OPS=0x04
750 06:47:17.056899 ring efuse init
751 06:47:17.061551 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
752 06:47:17.062046 [0.017354 Inits done]
753 06:47:17.062439 secure task start!
754 06:47:17.068576 high task start!
755 06:47:17.069099 low task start!
756 06:47:17.069498 run into bl31
757 06:47:17.078171 NOTICE: BL31: v1.3(release):4fc40b1
758 06:47:17.085172 NOTICE: BL31: Built : 15:57:33, May 22 2019
759 06:47:17.085663 NOTICE: BL31: G12A normal boot!
760 06:47:17.101484 NOTICE: BL31: BL33 decompress pass
761 06:47:17.106859 ERROR: Error initializing runtime service opteed_fast
762 06:47:17.902509
763 06:47:17.903077
764 06:47:17.908031 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
765 06:47:17.908539
766 06:47:17.910679 Model: Libre Computer AML-S905D3-CC Solitude
767 06:47:18.057693 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
768 06:47:18.073192 DRAM: 2 GiB (effective 3.8 GiB)
769 06:47:18.174967 Core: 406 devices, 33 uclasses, devicetree: separate
770 06:47:18.180248 WDT: Not starting watchdog@f0d0
771 06:47:18.205864 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
772 06:47:18.218134 Loading Environment from FAT... Card did not respond to voltage select! : -110
773 06:47:18.222079 ** Bad device specification mmc 0 **
774 06:47:18.233122 Card did not respond to voltage select! : -110
775 06:47:18.240857 ** Bad device specification mmc 0 **
776 06:47:18.241266 Couldn't find partition mmc 0
777 06:47:18.249366 Card did not respond to voltage select! : -110
778 06:47:18.254590 ** Bad device specification mmc 0 **
779 06:47:18.255068 Couldn't find partition mmc 0
780 06:47:18.258684 Error: could not access storage.
781 06:47:18.556930 Net: eth0: ethernet@ff3f0000
782 06:47:18.557557 starting USB...
783 06:47:18.801734 Bus usb@ff500000: Register 3000140 NbrPorts 3
784 06:47:18.802248 Starting the controller
785 06:47:18.808199 USB XHCI 1.10
786 06:47:20.362791 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
787 06:47:20.370587 scanning usb for storage devices... 0 Storage Device(s) found
789 06:47:20.422096 Hit any key to stop autoboot: 1
790 06:47:20.423148 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
791 06:47:20.423782 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
792 06:47:20.424330 Setting prompt string to ['=>']
793 06:47:20.424820 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
794 06:47:20.436349 0
795 06:47:20.437267 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
797 06:47:20.538450 => setenv autoload no
798 06:47:20.539150 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
799 06:47:20.544308 setenv autoload no
801 06:47:20.645738 => setenv initrd_high 0xffffffff
802 06:47:20.646378 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
803 06:47:20.650594 setenv initrd_high 0xffffffff
805 06:47:20.752016 => setenv fdt_high 0xffffffff
806 06:47:20.752627 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
807 06:47:20.756508 setenv fdt_high 0xffffffff
809 06:47:20.857931 => dhcp
810 06:47:20.858552 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
811 06:47:20.862138 dhcp
812 06:47:21.667402 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
813 06:47:21.667947 Speed: 1000, full duplex
814 06:47:21.668404 BOOTP broadcast 1
815 06:47:21.916360 BOOTP broadcast 2
816 06:47:22.416545 BOOTP broadcast 3
817 06:47:23.417483 BOOTP broadcast 4
818 06:47:25.418583 BOOTP broadcast 5
819 06:47:25.431905 DHCP client bound to address 192.168.6.12 (3764 ms)
821 06:47:25.533415 => setenv serverip 192.168.6.2
822 06:47:25.534269 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
823 06:47:25.538056 setenv serverip 192.168.6.2
825 06:47:25.639536 => tftpboot 0x01080000 714802/tftp-deploy-6kcla559/kernel/uImage
826 06:47:25.640228 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
827 06:47:25.647075 tftpboot 0x01080000 714802/tftp-deploy-6kcla559/kernel/uImage
828 06:47:25.647576 Speed: 1000, full duplex
829 06:47:25.648029 Using ethernet@ff3f0000 device
830 06:47:25.652420 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
831 06:47:25.658102 Filename '714802/tftp-deploy-6kcla559/kernel/uImage'.
832 06:47:25.662284 Load address: 0x1080000
833 06:47:28.573852 Loading: *################################################## 43.2 MiB
834 06:47:28.574449 14.8 MiB/s
835 06:47:28.574885 done
836 06:47:28.578398 Bytes transferred = 45308480 (2b35a40 hex)
838 06:47:28.679914 => tftpboot 0x08000000 714802/tftp-deploy-6kcla559/ramdisk/ramdisk.cpio.gz.uboot
839 06:47:28.680616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
840 06:47:28.687232 tftpboot 0x08000000 714802/tftp-deploy-6kcla559/ramdisk/ramdisk.cpio.gz.uboot
841 06:47:28.687701 Speed: 1000, full duplex
842 06:47:28.688127 Using ethernet@ff3f0000 device
843 06:47:28.692810 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
844 06:47:28.701619 Filename '714802/tftp-deploy-6kcla559/ramdisk/ramdisk.cpio.gz.uboot'.
845 06:47:28.702092 Load address: 0x8000000
846 06:47:30.241628 Loading: *################################################# UDP wrong checksum 00000005 00005601
847 06:47:33.042060 UDP wrong checksum 000000ff 00006cdf
848 06:47:33.050254 UDP wrong checksum 000000ff 000000d2
849 06:47:35.243117 T UDP wrong checksum 00000005 00005601
850 06:47:45.245467 T T UDP wrong checksum 00000005 00005601
851 06:47:55.753747 T T UDP wrong checksum 000000ff 00006b36
852 06:47:55.780599 UDP wrong checksum 000000ff 0000fc28
853 06:48:05.249471 T T UDP wrong checksum 00000005 00005601
854 06:48:17.759797 T T UDP wrong checksum 000000ff 0000ace5
855 06:48:17.767078 UDP wrong checksum 000000ff 000045d8
856 06:48:25.254229 T
857 06:48:25.254803 Retry count exceeded; starting again
859 06:48:25.256246 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
862 06:48:25.258083 end: 2.4 uboot-commands (duration 00:01:24) [common]
864 06:48:25.259425 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
866 06:48:25.260462 end: 2 uboot-action (duration 00:01:24) [common]
868 06:48:25.261987 Cleaning after the job
869 06:48:25.262551 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/ramdisk
870 06:48:25.263821 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/kernel
871 06:48:25.307362 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/dtb
872 06:48:25.308206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/nfsrootfs
873 06:48:25.605136 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714802/tftp-deploy-6kcla559/modules
874 06:48:25.625606 start: 4.1 power-off (timeout 00:00:30) [common]
875 06:48:25.626259 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
876 06:48:25.659006 >> OK - accepted request
877 06:48:25.661087 Returned 0 in 0 seconds
878 06:48:25.761854 end: 4.1 power-off (duration 00:00:00) [common]
880 06:48:25.762793 start: 4.2 read-feedback (timeout 00:10:00) [common]
881 06:48:25.763440 Listened to connection for namespace 'common' for up to 1s
882 06:48:26.764334 Finalising connection for namespace 'common'
883 06:48:26.764721 Disconnecting from shell: Finalise
884 06:48:26.764996 =>
885 06:48:26.865592 end: 4.2 read-feedback (duration 00:00:01) [common]
886 06:48:26.865924 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714802
887 06:48:29.334196 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714802
888 06:48:29.334790 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.