Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 06:59:31.465114 lava-dispatcher, installed at version: 2024.01
2 06:59:31.466123 start: 0 validate
3 06:59:31.466845 Start time: 2024-09-06 06:59:31.466813+00:00 (UTC)
4 06:59:31.467563 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 06:59:31.468377 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 06:59:31.517334 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 06:59:31.517879 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 06:59:31.554527 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 06:59:31.555516 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 06:59:31.592642 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 06:59:31.593143 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 06:59:31.622941 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 06:59:31.623445 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 06:59:31.665977 validate duration: 0.20
16 06:59:31.667593 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 06:59:31.668239 start: 1.1 download-retry (timeout 00:10:00) [common]
18 06:59:31.668841 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 06:59:31.669823 Not decompressing ramdisk as can be used compressed.
20 06:59:31.670604 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 06:59:31.671119 saving as /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/ramdisk/initrd.cpio.gz
22 06:59:31.671632 total size: 5628140 (5 MB)
23 06:59:31.715302 progress 0 % (0 MB)
24 06:59:31.723915 progress 5 % (0 MB)
25 06:59:31.734734 progress 10 % (0 MB)
26 06:59:31.742626 progress 15 % (0 MB)
27 06:59:31.750653 progress 20 % (1 MB)
28 06:59:31.754874 progress 25 % (1 MB)
29 06:59:31.758905 progress 30 % (1 MB)
30 06:59:31.762951 progress 35 % (1 MB)
31 06:59:31.766434 progress 40 % (2 MB)
32 06:59:31.770400 progress 45 % (2 MB)
33 06:59:31.773993 progress 50 % (2 MB)
34 06:59:31.778045 progress 55 % (2 MB)
35 06:59:31.782146 progress 60 % (3 MB)
36 06:59:31.785777 progress 65 % (3 MB)
37 06:59:31.789726 progress 70 % (3 MB)
38 06:59:31.793238 progress 75 % (4 MB)
39 06:59:31.797164 progress 80 % (4 MB)
40 06:59:31.800687 progress 85 % (4 MB)
41 06:59:31.804613 progress 90 % (4 MB)
42 06:59:31.808313 progress 95 % (5 MB)
43 06:59:31.811499 progress 100 % (5 MB)
44 06:59:31.812153 5 MB downloaded in 0.14 s (38.20 MB/s)
45 06:59:31.812723 end: 1.1.1 http-download (duration 00:00:00) [common]
47 06:59:31.813702 end: 1.1 download-retry (duration 00:00:00) [common]
48 06:59:31.814043 start: 1.2 download-retry (timeout 00:10:00) [common]
49 06:59:31.814337 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 06:59:31.814936 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
51 06:59:31.815229 saving as /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/kernel/Image
52 06:59:31.815492 total size: 45308416 (43 MB)
53 06:59:31.815759 No compression specified
54 06:59:31.853232 progress 0 % (0 MB)
55 06:59:31.881421 progress 5 % (2 MB)
56 06:59:31.909060 progress 10 % (4 MB)
57 06:59:31.936250 progress 15 % (6 MB)
58 06:59:31.964105 progress 20 % (8 MB)
59 06:59:31.991618 progress 25 % (10 MB)
60 06:59:32.019018 progress 30 % (12 MB)
61 06:59:32.046231 progress 35 % (15 MB)
62 06:59:32.075331 progress 40 % (17 MB)
63 06:59:32.102378 progress 45 % (19 MB)
64 06:59:32.129720 progress 50 % (21 MB)
65 06:59:32.156802 progress 55 % (23 MB)
66 06:59:32.184985 progress 60 % (25 MB)
67 06:59:32.213123 progress 65 % (28 MB)
68 06:59:32.242645 progress 70 % (30 MB)
69 06:59:32.270402 progress 75 % (32 MB)
70 06:59:32.298380 progress 80 % (34 MB)
71 06:59:32.326082 progress 85 % (36 MB)
72 06:59:32.355831 progress 90 % (38 MB)
73 06:59:32.383296 progress 95 % (41 MB)
74 06:59:32.409816 progress 100 % (43 MB)
75 06:59:32.410520 43 MB downloaded in 0.60 s (72.62 MB/s)
76 06:59:32.411010 end: 1.2.1 http-download (duration 00:00:01) [common]
78 06:59:32.411826 end: 1.2 download-retry (duration 00:00:01) [common]
79 06:59:32.412128 start: 1.3 download-retry (timeout 00:09:59) [common]
80 06:59:32.412402 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 06:59:32.412880 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 06:59:32.413154 saving as /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/dtb/meson-g12b-a311d-libretech-cc.dtb
83 06:59:32.413366 total size: 54667 (0 MB)
84 06:59:32.413576 No compression specified
85 06:59:32.454740 progress 59 % (0 MB)
86 06:59:32.455605 progress 100 % (0 MB)
87 06:59:32.456188 0 MB downloaded in 0.04 s (1.22 MB/s)
88 06:59:32.456672 end: 1.3.1 http-download (duration 00:00:00) [common]
90 06:59:32.457500 end: 1.3 download-retry (duration 00:00:00) [common]
91 06:59:32.457765 start: 1.4 download-retry (timeout 00:09:59) [common]
92 06:59:32.458027 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 06:59:32.458487 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 06:59:32.458739 saving as /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/nfsrootfs/full.rootfs.tar
95 06:59:32.458944 total size: 474398908 (452 MB)
96 06:59:32.459155 Using unxz to decompress xz
97 06:59:32.496805 progress 0 % (0 MB)
98 06:59:33.585370 progress 5 % (22 MB)
99 06:59:35.018092 progress 10 % (45 MB)
100 06:59:35.451135 progress 15 % (67 MB)
101 06:59:36.216526 progress 20 % (90 MB)
102 06:59:36.741275 progress 25 % (113 MB)
103 06:59:37.083489 progress 30 % (135 MB)
104 06:59:37.673450 progress 35 % (158 MB)
105 06:59:38.547400 progress 40 % (181 MB)
106 06:59:39.388179 progress 45 % (203 MB)
107 06:59:40.028000 progress 50 % (226 MB)
108 06:59:40.691291 progress 55 % (248 MB)
109 06:59:41.883035 progress 60 % (271 MB)
110 06:59:43.366729 progress 65 % (294 MB)
111 06:59:44.981807 progress 70 % (316 MB)
112 06:59:48.291715 progress 75 % (339 MB)
113 06:59:50.731365 progress 80 % (361 MB)
114 06:59:53.704887 progress 85 % (384 MB)
115 06:59:56.899598 progress 90 % (407 MB)
116 07:00:00.098223 progress 95 % (429 MB)
117 07:00:03.283504 progress 100 % (452 MB)
118 07:00:03.296452 452 MB downloaded in 30.84 s (14.67 MB/s)
119 07:00:03.297399 end: 1.4.1 http-download (duration 00:00:31) [common]
121 07:00:03.299140 end: 1.4 download-retry (duration 00:00:31) [common]
122 07:00:03.299700 start: 1.5 download-retry (timeout 00:09:28) [common]
123 07:00:03.300308 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 07:00:03.301499 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
125 07:00:03.302048 saving as /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/modules/modules.tar
126 07:00:03.302495 total size: 11502724 (10 MB)
127 07:00:03.302953 Using unxz to decompress xz
128 07:00:03.351655 progress 0 % (0 MB)
129 07:00:03.422785 progress 5 % (0 MB)
130 07:00:03.499875 progress 10 % (1 MB)
131 07:00:03.582684 progress 15 % (1 MB)
132 07:00:03.663077 progress 20 % (2 MB)
133 07:00:03.739517 progress 25 % (2 MB)
134 07:00:03.822045 progress 30 % (3 MB)
135 07:00:03.898472 progress 35 % (3 MB)
136 07:00:03.976220 progress 40 % (4 MB)
137 07:00:04.047488 progress 45 % (4 MB)
138 07:00:04.124471 progress 50 % (5 MB)
139 07:00:04.199768 progress 55 % (6 MB)
140 07:00:04.278666 progress 60 % (6 MB)
141 07:00:04.364117 progress 65 % (7 MB)
142 07:00:04.440556 progress 70 % (7 MB)
143 07:00:04.535148 progress 75 % (8 MB)
144 07:00:04.624275 progress 80 % (8 MB)
145 07:00:04.704475 progress 85 % (9 MB)
146 07:00:04.774348 progress 90 % (9 MB)
147 07:00:04.849611 progress 95 % (10 MB)
148 07:00:04.924794 progress 100 % (10 MB)
149 07:00:04.934627 10 MB downloaded in 1.63 s (6.72 MB/s)
150 07:00:04.935460 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:00:04.937083 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:00:04.937598 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 07:00:04.938111 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 07:00:20.268753 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/714861/extract-nfsrootfs-nrcdfx7j
156 07:00:20.269354 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 07:00:20.269641 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 07:00:20.270343 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08
159 07:00:20.270786 makedir: /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin
160 07:00:20.271112 makedir: /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/tests
161 07:00:20.271445 makedir: /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/results
162 07:00:20.271778 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-add-keys
163 07:00:20.272337 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-add-sources
164 07:00:20.272874 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-background-process-start
165 07:00:20.273409 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-background-process-stop
166 07:00:20.273959 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-common-functions
167 07:00:20.274463 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-echo-ipv4
168 07:00:20.274944 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-install-packages
169 07:00:20.275433 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-installed-packages
170 07:00:20.275905 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-os-build
171 07:00:20.283684 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-probe-channel
172 07:00:20.284252 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-probe-ip
173 07:00:20.284759 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-target-ip
174 07:00:20.285232 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-target-mac
175 07:00:20.285703 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-target-storage
176 07:00:20.286192 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-test-case
177 07:00:20.286678 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-test-event
178 07:00:20.287150 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-test-feedback
179 07:00:20.287615 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-test-raise
180 07:00:20.288130 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-test-reference
181 07:00:20.288634 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-test-runner
182 07:00:20.289115 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-test-set
183 07:00:20.289584 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-test-shell
184 07:00:20.290077 Updating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-install-packages (oe)
185 07:00:20.290683 Updating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/bin/lava-installed-packages (oe)
186 07:00:20.291155 Creating /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/environment
187 07:00:20.291552 LAVA metadata
188 07:00:20.291823 - LAVA_JOB_ID=714861
189 07:00:20.292066 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:00:20.292454 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 07:00:20.293454 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:00:20.293792 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 07:00:20.294003 skipped lava-vland-overlay
194 07:00:20.294244 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:00:20.294496 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 07:00:20.294714 skipped lava-multinode-overlay
197 07:00:20.294956 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:00:20.295206 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 07:00:20.295455 Loading test definitions
200 07:00:20.295731 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 07:00:20.295952 Using /lava-714861 at stage 0
202 07:00:20.297163 uuid=714861_1.6.2.4.1 testdef=None
203 07:00:20.297482 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:00:20.297746 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 07:00:20.299496 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:00:20.300320 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 07:00:20.302597 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:00:20.303497 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 07:00:20.305740 runner path: /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 714861_1.6.2.4.1
212 07:00:20.306411 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:00:20.307202 Creating lava-test-runner.conf files
215 07:00:20.307407 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714861/lava-overlay-rba74l08/lava-714861/0 for stage 0
216 07:00:20.307764 - 0_v4l2-decoder-conformance-h265
217 07:00:20.308164 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:00:20.308448 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 07:00:20.330730 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:00:20.331169 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 07:00:20.331434 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:00:20.331703 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:00:20.331964 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 07:00:20.950633 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:00:20.951083 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 07:00:20.951332 extracting modules file /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714861/extract-nfsrootfs-nrcdfx7j
227 07:00:22.318402 extracting modules file /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714861/extract-overlay-ramdisk-udhmuupa/ramdisk
228 07:00:23.732032 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:00:23.732488 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 07:00:23.732784 [common] Applying overlay to NFS
231 07:00:23.733008 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714861/compress-overlay-5bc0osco/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714861/extract-nfsrootfs-nrcdfx7j
232 07:00:23.762715 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:00:23.763108 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 07:00:23.763404 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 07:00:23.763643 Converting downloaded kernel to a uImage
236 07:00:23.763961 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/kernel/Image /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/kernel/uImage
237 07:00:24.226439 output: Image Name:
238 07:00:24.226856 output: Created: Fri Sep 6 07:00:23 2024
239 07:00:24.227067 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:00:24.227274 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
241 07:00:24.227475 output: Load Address: 01080000
242 07:00:24.227675 output: Entry Point: 01080000
243 07:00:24.227870 output:
244 07:00:24.228279 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 07:00:24.228554 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 07:00:24.228825 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 07:00:24.229080 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:00:24.229337 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 07:00:24.229603 Building ramdisk /var/lib/lava/dispatcher/tmp/714861/extract-overlay-ramdisk-udhmuupa/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714861/extract-overlay-ramdisk-udhmuupa/ramdisk
250 07:00:26.606321 >> 165160 blocks
251 07:00:34.440364 Adding RAMdisk u-boot header.
252 07:00:34.441061 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714861/extract-overlay-ramdisk-udhmuupa/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714861/extract-overlay-ramdisk-udhmuupa/ramdisk.cpio.gz.uboot
253 07:00:34.698753 output: Image Name:
254 07:00:34.699168 output: Created: Fri Sep 6 07:00:34 2024
255 07:00:34.699379 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:00:34.699586 output: Data Size: 23257121 Bytes = 22712.03 KiB = 22.18 MiB
257 07:00:34.699787 output: Load Address: 00000000
258 07:00:34.700062 output: Entry Point: 00000000
259 07:00:34.700516 output:
260 07:00:34.701838 rename /var/lib/lava/dispatcher/tmp/714861/extract-overlay-ramdisk-udhmuupa/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/ramdisk/ramdisk.cpio.gz.uboot
261 07:00:34.702647 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 07:00:34.703246 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 07:00:34.703824 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 07:00:34.704368 No LXC device requested
265 07:00:34.704925 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:00:34.705486 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 07:00:34.706034 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:00:34.706487 Checking files for TFTP limit of 4294967296 bytes.
269 07:00:34.709413 end: 1 tftp-deploy (duration 00:01:03) [common]
270 07:00:34.710046 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:00:34.710621 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:00:34.711169 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:00:34.711718 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:00:34.712368 Using kernel file from prepare-kernel: 714861/tftp-deploy-nnapnqbl/kernel/uImage
275 07:00:34.713062 substitutions:
276 07:00:34.713508 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:00:34.713952 - {DTB_ADDR}: 0x01070000
278 07:00:34.714391 - {DTB}: 714861/tftp-deploy-nnapnqbl/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:00:34.714857 - {INITRD}: 714861/tftp-deploy-nnapnqbl/ramdisk/ramdisk.cpio.gz.uboot
280 07:00:34.715297 - {KERNEL_ADDR}: 0x01080000
281 07:00:34.715739 - {KERNEL}: 714861/tftp-deploy-nnapnqbl/kernel/uImage
282 07:00:34.716222 - {LAVA_MAC}: None
283 07:00:34.716703 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/714861/extract-nfsrootfs-nrcdfx7j
284 07:00:34.717143 - {NFS_SERVER_IP}: 192.168.6.2
285 07:00:34.717570 - {PRESEED_CONFIG}: None
286 07:00:34.718001 - {PRESEED_LOCAL}: None
287 07:00:34.718428 - {RAMDISK_ADDR}: 0x08000000
288 07:00:34.718854 - {RAMDISK}: 714861/tftp-deploy-nnapnqbl/ramdisk/ramdisk.cpio.gz.uboot
289 07:00:34.719280 - {ROOT_PART}: None
290 07:00:34.719707 - {ROOT}: None
291 07:00:34.720161 - {SERVER_IP}: 192.168.6.2
292 07:00:34.720591 - {TEE_ADDR}: 0x83000000
293 07:00:34.721018 - {TEE}: None
294 07:00:34.721445 Parsed boot commands:
295 07:00:34.721863 - setenv autoload no
296 07:00:34.722289 - setenv initrd_high 0xffffffff
297 07:00:34.722712 - setenv fdt_high 0xffffffff
298 07:00:34.723136 - dhcp
299 07:00:34.723562 - setenv serverip 192.168.6.2
300 07:00:34.724005 - tftpboot 0x01080000 714861/tftp-deploy-nnapnqbl/kernel/uImage
301 07:00:34.724438 - tftpboot 0x08000000 714861/tftp-deploy-nnapnqbl/ramdisk/ramdisk.cpio.gz.uboot
302 07:00:34.724867 - tftpboot 0x01070000 714861/tftp-deploy-nnapnqbl/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:00:34.725293 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/714861/extract-nfsrootfs-nrcdfx7j,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:00:34.725733 - bootm 0x01080000 0x08000000 0x01070000
305 07:00:34.726279 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:00:34.727903 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:00:34.728388 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:00:34.743823 Setting prompt string to ['lava-test: # ']
310 07:00:34.745440 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:00:34.746087 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:00:34.746739 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:00:34.747396 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:00:34.748666 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:00:34.786472 >> OK - accepted request
316 07:00:34.788832 Returned 0 in 0 seconds
317 07:00:34.889968 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:00:34.891647 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:00:34.892317 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:00:34.892891 Setting prompt string to ['Hit any key to stop autoboot']
322 07:00:34.893407 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:00:34.895094 Trying 192.168.56.21...
324 07:00:34.895617 Connected to conserv1.
325 07:00:34.896115 Escape character is '^]'.
326 07:00:34.896579
327 07:00:34.897043 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 07:00:34.897513
329 07:00:45.819768 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:00:45.820443 bl2_stage_init 0x01
331 07:00:45.820909 bl2_stage_init 0x81
332 07:00:45.825530 hw id: 0x0000 - pwm id 0x01
333 07:00:45.826033 bl2_stage_init 0xc1
334 07:00:45.826472 bl2_stage_init 0x02
335 07:00:45.826920
336 07:00:45.830948 L0:00000000
337 07:00:45.831432 L1:20000703
338 07:00:45.831863 L2:00008067
339 07:00:45.832346 L3:14000000
340 07:00:45.836489 B2:00402000
341 07:00:45.836949 B1:e0f83180
342 07:00:45.837376
343 07:00:45.837808 TE: 58159
344 07:00:45.838238
345 07:00:45.842224 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:00:45.842687
347 07:00:45.843119 Board ID = 1
348 07:00:45.847812 Set A53 clk to 24M
349 07:00:45.848303 Set A73 clk to 24M
350 07:00:45.848733 Set clk81 to 24M
351 07:00:45.853414 A53 clk: 1200 MHz
352 07:00:45.853872 A73 clk: 1200 MHz
353 07:00:45.854297 CLK81: 166.6M
354 07:00:45.854717 smccc: 00012ab5
355 07:00:45.858935 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:00:45.864525 board id: 1
357 07:00:45.870541 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:00:45.880981 fw parse done
359 07:00:45.886972 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:00:45.929596 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:00:45.940652 PIEI prepare done
362 07:00:45.941104 fastboot data load
363 07:00:45.941535 fastboot data verify
364 07:00:45.946133 verify result: 266
365 07:00:45.951804 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:00:45.952304 LPDDR4 probe
367 07:00:45.952734 ddr clk to 1584MHz
368 07:00:45.959850 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:00:45.997062
370 07:00:45.997530 dmc_version 0001
371 07:00:46.003736 Check phy result
372 07:00:46.009559 INFO : End of CA training
373 07:00:46.010012 INFO : End of initialization
374 07:00:46.015235 INFO : Training has run successfully!
375 07:00:46.015689 Check phy result
376 07:00:46.020758 INFO : End of initialization
377 07:00:46.021213 INFO : End of read enable training
378 07:00:46.026409 INFO : End of fine write leveling
379 07:00:46.031965 INFO : End of Write leveling coarse delay
380 07:00:46.032444 INFO : Training has run successfully!
381 07:00:46.032878 Check phy result
382 07:00:46.037654 INFO : End of initialization
383 07:00:46.038109 INFO : End of read dq deskew training
384 07:00:46.043232 INFO : End of MPR read delay center optimization
385 07:00:46.048833 INFO : End of write delay center optimization
386 07:00:46.054442 INFO : End of read delay center optimization
387 07:00:46.054892 INFO : End of max read latency training
388 07:00:46.060023 INFO : Training has run successfully!
389 07:00:46.060481 1D training succeed
390 07:00:46.069266 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:00:46.116761 Check phy result
392 07:00:46.117278 INFO : End of initialization
393 07:00:46.138474 INFO : End of 2D read delay Voltage center optimization
394 07:00:46.158795 INFO : End of 2D read delay Voltage center optimization
395 07:00:46.210886 INFO : End of 2D write delay Voltage center optimization
396 07:00:46.260276 INFO : End of 2D write delay Voltage center optimization
397 07:00:46.265842 INFO : Training has run successfully!
398 07:00:46.266298
399 07:00:46.266735 channel==0
400 07:00:46.271453 RxClkDly_Margin_A0==88 ps 9
401 07:00:46.271907 TxDqDly_Margin_A0==98 ps 10
402 07:00:46.277084 RxClkDly_Margin_A1==88 ps 9
403 07:00:46.277563 TxDqDly_Margin_A1==98 ps 10
404 07:00:46.278002 TrainedVREFDQ_A0==74
405 07:00:46.282599 TrainedVREFDQ_A1==74
406 07:00:46.283059 VrefDac_Margin_A0==25
407 07:00:46.283489 DeviceVref_Margin_A0==40
408 07:00:46.288296 VrefDac_Margin_A1==25
409 07:00:46.288750 DeviceVref_Margin_A1==40
410 07:00:46.289176
411 07:00:46.289604
412 07:00:46.293850 channel==1
413 07:00:46.294304 RxClkDly_Margin_A0==98 ps 10
414 07:00:46.294735 TxDqDly_Margin_A0==98 ps 10
415 07:00:46.299409 RxClkDly_Margin_A1==98 ps 10
416 07:00:46.299860 TxDqDly_Margin_A1==88 ps 9
417 07:00:46.305098 TrainedVREFDQ_A0==77
418 07:00:46.305554 TrainedVREFDQ_A1==77
419 07:00:46.305987 VrefDac_Margin_A0==22
420 07:00:46.310551 DeviceVref_Margin_A0==37
421 07:00:46.311007 VrefDac_Margin_A1==22
422 07:00:46.316164 DeviceVref_Margin_A1==37
423 07:00:46.316614
424 07:00:46.317051 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:00:46.321756
426 07:00:46.349696 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 07:00:46.350229 2D training succeed
428 07:00:46.355354 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:00:46.360987 auto size-- 65535DDR cs0 size: 2048MB
430 07:00:46.361477 DDR cs1 size: 2048MB
431 07:00:46.366494 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:00:46.366953 cs0 DataBus test pass
433 07:00:46.372202 cs1 DataBus test pass
434 07:00:46.372657 cs0 AddrBus test pass
435 07:00:46.373091 cs1 AddrBus test pass
436 07:00:46.373516
437 07:00:46.377778 100bdlr_step_size ps== 420
438 07:00:46.378245 result report
439 07:00:46.383287 boot times 0Enable ddr reg access
440 07:00:46.388743 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:00:46.401372 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:00:46.975888 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:00:46.976421 MVN_1=0x00000000
444 07:00:46.981395 MVN_2=0x00000000
445 07:00:46.987107 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:00:46.987577 OPS=0x10
447 07:00:46.988051 ring efuse init
448 07:00:46.988493 chipver efuse init
449 07:00:46.992835 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:00:46.998266 [0.018961 Inits done]
451 07:00:46.998728 secure task start!
452 07:00:46.999168 high task start!
453 07:00:47.002808 low task start!
454 07:00:47.003268 run into bl31
455 07:00:47.009441 NOTICE: BL31: v1.3(release):4fc40b1
456 07:00:47.017245 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:00:47.017713 NOTICE: BL31: G12A normal boot!
458 07:00:47.043209 NOTICE: BL31: BL33 decompress pass
459 07:00:47.048987 ERROR: Error initializing runtime service opteed_fast
460 07:00:48.281757
461 07:00:48.282385
462 07:00:48.290186 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:00:48.290671
464 07:00:48.291133 Model: Libre Computer AML-A311D-CC Alta
465 07:00:48.498556 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:00:48.521060 DRAM: 2 GiB (effective 3.8 GiB)
467 07:00:48.664911 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:00:48.669978 WDT: Not starting watchdog@f0d0
469 07:00:48.703160 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:00:48.715524 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:00:48.720518 ** Bad device specification mmc 0 **
472 07:00:48.730823 Card did not respond to voltage select! : -110
473 07:00:48.738482 ** Bad device specification mmc 0 **
474 07:00:48.738948 Couldn't find partition mmc 0
475 07:00:48.746838 Card did not respond to voltage select! : -110
476 07:00:48.752365 ** Bad device specification mmc 0 **
477 07:00:48.752831 Couldn't find partition mmc 0
478 07:00:48.757404 Error: could not access storage.
479 07:00:50.020068 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:00:50.020666 bl2_stage_init 0x01
481 07:00:50.021125 bl2_stage_init 0x81
482 07:00:50.025611 hw id: 0x0000 - pwm id 0x01
483 07:00:50.026079 bl2_stage_init 0xc1
484 07:00:50.026535 bl2_stage_init 0x02
485 07:00:50.026972
486 07:00:50.031207 L0:00000000
487 07:00:50.031692 L1:20000703
488 07:00:50.032170 L2:00008067
489 07:00:50.032611 L3:14000000
490 07:00:50.034082 B2:00402000
491 07:00:50.034548 B1:e0f83180
492 07:00:50.034985
493 07:00:50.035422 TE: 58124
494 07:00:50.035854
495 07:00:50.045330 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:00:50.045825
497 07:00:50.046276 Board ID = 1
498 07:00:50.046717 Set A53 clk to 24M
499 07:00:50.047154 Set A73 clk to 24M
500 07:00:50.050873 Set clk81 to 24M
501 07:00:50.051341 A53 clk: 1200 MHz
502 07:00:50.051787 A73 clk: 1200 MHz
503 07:00:50.056461 CLK81: 166.6M
504 07:00:50.056937 smccc: 00012a92
505 07:00:50.062095 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:00:50.062561 board id: 1
507 07:00:50.070687 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:00:50.081341 fw parse done
509 07:00:50.087424 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:00:50.129940 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:00:50.140831 PIEI prepare done
512 07:00:50.141306 fastboot data load
513 07:00:50.141755 fastboot data verify
514 07:00:50.146501 verify result: 266
515 07:00:50.152112 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:00:50.152577 LPDDR4 probe
517 07:00:50.153017 ddr clk to 1584MHz
518 07:00:50.160156 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:00:50.197327
520 07:00:50.197801 dmc_version 0001
521 07:00:50.204035 Check phy result
522 07:00:50.209835 INFO : End of CA training
523 07:00:50.210315 INFO : End of initialization
524 07:00:50.215442 INFO : Training has run successfully!
525 07:00:50.215907 Check phy result
526 07:00:50.221061 INFO : End of initialization
527 07:00:50.221525 INFO : End of read enable training
528 07:00:50.226642 INFO : End of fine write leveling
529 07:00:50.232244 INFO : End of Write leveling coarse delay
530 07:00:50.232728 INFO : Training has run successfully!
531 07:00:50.233173 Check phy result
532 07:00:50.237878 INFO : End of initialization
533 07:00:50.238364 INFO : End of read dq deskew training
534 07:00:50.243467 INFO : End of MPR read delay center optimization
535 07:00:50.249050 INFO : End of write delay center optimization
536 07:00:50.254679 INFO : End of read delay center optimization
537 07:00:50.255140 INFO : End of max read latency training
538 07:00:50.260241 INFO : Training has run successfully!
539 07:00:50.260726 1D training succeed
540 07:00:50.269484 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:00:50.317120 Check phy result
542 07:00:50.317627 INFO : End of initialization
543 07:00:50.338738 INFO : End of 2D read delay Voltage center optimization
544 07:00:50.359066 INFO : End of 2D read delay Voltage center optimization
545 07:00:50.411147 INFO : End of 2D write delay Voltage center optimization
546 07:00:50.460501 INFO : End of 2D write delay Voltage center optimization
547 07:00:50.466080 INFO : Training has run successfully!
548 07:00:50.466555
549 07:00:50.467013 channel==0
550 07:00:50.471648 RxClkDly_Margin_A0==88 ps 9
551 07:00:50.472165 TxDqDly_Margin_A0==98 ps 10
552 07:00:50.477214 RxClkDly_Margin_A1==88 ps 9
553 07:00:50.477685 TxDqDly_Margin_A1==98 ps 10
554 07:00:50.478131 TrainedVREFDQ_A0==74
555 07:00:50.482849 TrainedVREFDQ_A1==74
556 07:00:50.483322 VrefDac_Margin_A0==25
557 07:00:50.483761 DeviceVref_Margin_A0==40
558 07:00:50.488442 VrefDac_Margin_A1==25
559 07:00:50.488937 DeviceVref_Margin_A1==40
560 07:00:50.489387
561 07:00:50.489824
562 07:00:50.494116 channel==1
563 07:00:50.494595 RxClkDly_Margin_A0==98 ps 10
564 07:00:50.495037 TxDqDly_Margin_A0==98 ps 10
565 07:00:50.499634 RxClkDly_Margin_A1==98 ps 10
566 07:00:50.500161 TxDqDly_Margin_A1==98 ps 10
567 07:00:50.505233 TrainedVREFDQ_A0==77
568 07:00:50.505708 TrainedVREFDQ_A1==77
569 07:00:50.506148 VrefDac_Margin_A0==22
570 07:00:50.510867 DeviceVref_Margin_A0==37
571 07:00:50.511331 VrefDac_Margin_A1==24
572 07:00:50.516465 DeviceVref_Margin_A1==37
573 07:00:50.516954
574 07:00:50.517398 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:00:50.522082
576 07:00:50.550065 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 07:00:50.550566 2D training succeed
578 07:00:50.555595 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:00:50.561221 auto size-- 65535DDR cs0 size: 2048MB
580 07:00:50.561693 DDR cs1 size: 2048MB
581 07:00:50.566846 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:00:50.567318 cs0 DataBus test pass
583 07:00:50.572462 cs1 DataBus test pass
584 07:00:50.572928 cs0 AddrBus test pass
585 07:00:50.573366 cs1 AddrBus test pass
586 07:00:50.573800
587 07:00:50.578094 100bdlr_step_size ps== 420
588 07:00:50.578613 result report
589 07:00:50.583597 boot times 0Enable ddr reg access
590 07:00:50.589139 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:00:50.602660 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:00:51.176302 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:00:51.176886 MVN_1=0x00000000
594 07:00:51.181838 MVN_2=0x00000000
595 07:00:51.187616 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:00:51.188307 OPS=0x10
597 07:00:51.188795 ring efuse init
598 07:00:51.189267 chipver efuse init
599 07:00:51.193262 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:00:51.198806 [0.018961 Inits done]
601 07:00:51.199264 secure task start!
602 07:00:51.199690 high task start!
603 07:00:51.203397 low task start!
604 07:00:51.203861 run into bl31
605 07:00:51.210080 NOTICE: BL31: v1.3(release):4fc40b1
606 07:00:51.217841 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:00:51.218304 NOTICE: BL31: G12A normal boot!
608 07:00:51.243187 NOTICE: BL31: BL33 decompress pass
609 07:00:51.248855 ERROR: Error initializing runtime service opteed_fast
610 07:00:52.482002
611 07:00:52.482626
612 07:00:52.490298 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:00:52.490787
614 07:00:52.491245 Model: Libre Computer AML-A311D-CC Alta
615 07:00:52.698619 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:00:52.722126 DRAM: 2 GiB (effective 3.8 GiB)
617 07:00:52.865002 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:00:52.870985 WDT: Not starting watchdog@f0d0
619 07:00:52.903114 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:00:52.915724 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:00:52.919696 ** Bad device specification mmc 0 **
622 07:00:52.930850 Card did not respond to voltage select! : -110
623 07:00:52.938585 ** Bad device specification mmc 0 **
624 07:00:52.939073 Couldn't find partition mmc 0
625 07:00:52.946840 Card did not respond to voltage select! : -110
626 07:00:52.952458 ** Bad device specification mmc 0 **
627 07:00:52.952934 Couldn't find partition mmc 0
628 07:00:52.957589 Error: could not access storage.
629 07:00:53.301095 Net: eth0: ethernet@ff3f0000
630 07:00:53.301758 starting USB...
631 07:00:53.552884 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:00:53.553491 Starting the controller
633 07:00:53.559789 USB XHCI 1.10
634 07:00:55.270431 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 07:00:55.271094 bl2_stage_init 0x01
636 07:00:55.271571 bl2_stage_init 0x81
637 07:00:55.276077 hw id: 0x0000 - pwm id 0x01
638 07:00:55.276622 bl2_stage_init 0xc1
639 07:00:55.277088 bl2_stage_init 0x02
640 07:00:55.277544
641 07:00:55.281577 L0:00000000
642 07:00:55.282110 L1:20000703
643 07:00:55.282572 L2:00008067
644 07:00:55.283023 L3:14000000
645 07:00:55.287331 B2:00402000
646 07:00:55.287861 B1:e0f83180
647 07:00:55.288368
648 07:00:55.288822 TE: 58159
649 07:00:55.289273
650 07:00:55.292744 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 07:00:55.293280
652 07:00:55.293745 Board ID = 1
653 07:00:55.298433 Set A53 clk to 24M
654 07:00:55.298961 Set A73 clk to 24M
655 07:00:55.299419 Set clk81 to 24M
656 07:00:55.304089 A53 clk: 1200 MHz
657 07:00:55.304620 A73 clk: 1200 MHz
658 07:00:55.305072 CLK81: 166.6M
659 07:00:55.305517 smccc: 00012ab5
660 07:00:55.309592 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 07:00:55.315330 board id: 1
662 07:00:55.321288 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 07:00:55.331644 fw parse done
664 07:00:55.337601 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 07:00:55.380210 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 07:00:55.391220 PIEI prepare done
667 07:00:55.391761 fastboot data load
668 07:00:55.392276 fastboot data verify
669 07:00:55.396816 verify result: 266
670 07:00:55.402434 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 07:00:55.402964 LPDDR4 probe
672 07:00:55.403424 ddr clk to 1584MHz
673 07:00:55.410423 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 07:00:55.447679
675 07:00:55.448258 dmc_version 0001
676 07:00:55.454414 Check phy result
677 07:00:55.460317 INFO : End of CA training
678 07:00:55.460847 INFO : End of initialization
679 07:00:55.465806 INFO : Training has run successfully!
680 07:00:55.466333 Check phy result
681 07:00:55.471414 INFO : End of initialization
682 07:00:55.471942 INFO : End of read enable training
683 07:00:55.474727 INFO : End of fine write leveling
684 07:00:55.480306 INFO : End of Write leveling coarse delay
685 07:00:55.485941 INFO : Training has run successfully!
686 07:00:55.486473 Check phy result
687 07:00:55.486933 INFO : End of initialization
688 07:00:55.491504 INFO : End of read dq deskew training
689 07:00:55.497121 INFO : End of MPR read delay center optimization
690 07:00:55.497649 INFO : End of write delay center optimization
691 07:00:55.502656 INFO : End of read delay center optimization
692 07:00:55.508295 INFO : End of max read latency training
693 07:00:55.508823 INFO : Training has run successfully!
694 07:00:55.513943 1D training succeed
695 07:00:55.519868 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 07:00:55.567412 Check phy result
697 07:00:55.567941 INFO : End of initialization
698 07:00:55.588109 INFO : End of 2D read delay Voltage center optimization
699 07:00:55.608127 INFO : End of 2D read delay Voltage center optimization
700 07:00:55.661100 INFO : End of 2D write delay Voltage center optimization
701 07:00:55.710308 INFO : End of 2D write delay Voltage center optimization
702 07:00:55.715791 INFO : Training has run successfully!
703 07:00:55.716365
704 07:00:55.716829 channel==0
705 07:00:55.721395 RxClkDly_Margin_A0==88 ps 9
706 07:00:55.721927 TxDqDly_Margin_A0==98 ps 10
707 07:00:55.726965 RxClkDly_Margin_A1==88 ps 9
708 07:00:55.727492 TxDqDly_Margin_A1==98 ps 10
709 07:00:55.727955 TrainedVREFDQ_A0==74
710 07:00:55.732595 TrainedVREFDQ_A1==74
711 07:00:55.733125 VrefDac_Margin_A0==25
712 07:00:55.733584 DeviceVref_Margin_A0==40
713 07:00:55.738298 VrefDac_Margin_A1==25
714 07:00:55.738833 DeviceVref_Margin_A1==40
715 07:00:55.739290
716 07:00:55.739736
717 07:00:55.743801 channel==1
718 07:00:55.744364 RxClkDly_Margin_A0==98 ps 10
719 07:00:55.744824 TxDqDly_Margin_A0==98 ps 10
720 07:00:55.749362 RxClkDly_Margin_A1==98 ps 10
721 07:00:55.749893 TxDqDly_Margin_A1==88 ps 9
722 07:00:55.754961 TrainedVREFDQ_A0==77
723 07:00:55.755488 TrainedVREFDQ_A1==77
724 07:00:55.755946 VrefDac_Margin_A0==22
725 07:00:55.760554 DeviceVref_Margin_A0==37
726 07:00:55.761031 VrefDac_Margin_A1==22
727 07:00:55.766203 DeviceVref_Margin_A1==37
728 07:00:55.766657
729 07:00:55.767078 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 07:00:55.771671
731 07:00:55.799680 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 07:00:55.800237 2D training succeed
733 07:00:55.805287 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 07:00:55.810864 auto size-- 65535DDR cs0 size: 2048MB
735 07:00:55.811315 DDR cs1 size: 2048MB
736 07:00:55.816457 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 07:00:55.816906 cs0 DataBus test pass
738 07:00:55.822185 cs1 DataBus test pass
739 07:00:55.822625 cs0 AddrBus test pass
740 07:00:55.823033 cs1 AddrBus test pass
741 07:00:55.823435
742 07:00:55.827705 100bdlr_step_size ps== 420
743 07:00:55.828209 result report
744 07:00:55.833273 boot times 0Enable ddr reg access
745 07:00:55.838729 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 07:00:55.852263 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 07:00:56.424122 0.0;M3 CHK:0;cm4_sp_mode 0
748 07:00:56.424680 MVN_1=0x00000000
749 07:00:56.429645 MVN_2=0x00000000
750 07:00:56.435418 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 07:00:56.435957 OPS=0x10
752 07:00:56.436396 ring efuse init
753 07:00:56.436783 chipver efuse init
754 07:00:56.440976 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 07:00:56.446602 [0.018960 Inits done]
756 07:00:56.447046 secure task start!
757 07:00:56.447438 high task start!
758 07:00:56.451270 low task start!
759 07:00:56.451701 run into bl31
760 07:00:56.457834 NOTICE: BL31: v1.3(release):4fc40b1
761 07:00:56.465616 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 07:00:56.466049 NOTICE: BL31: G12A normal boot!
763 07:00:56.491002 NOTICE: BL31: BL33 decompress pass
764 07:00:56.496374 ERROR: Error initializing runtime service opteed_fast
765 07:00:57.729539
766 07:00:57.730140
767 07:00:57.737967 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 07:00:57.738432
769 07:00:57.738851 Model: Libre Computer AML-A311D-CC Alta
770 07:00:57.946372 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 07:00:57.969782 DRAM: 2 GiB (effective 3.8 GiB)
772 07:00:58.112757 Core: 408 devices, 31 uclasses, devicetree: separate
773 07:00:58.118686 WDT: Not starting watchdog@f0d0
774 07:00:58.150907 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 07:00:58.163433 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 07:00:58.168358 ** Bad device specification mmc 0 **
777 07:00:58.178722 Card did not respond to voltage select! : -110
778 07:00:58.185816 ** Bad device specification mmc 0 **
779 07:00:58.186383 Couldn't find partition mmc 0
780 07:00:58.194711 Card did not respond to voltage select! : -110
781 07:00:58.200223 ** Bad device specification mmc 0 **
782 07:00:58.200705 Couldn't find partition mmc 0
783 07:00:58.206192 Error: could not access storage.
784 07:00:58.548796 Net: eth0: ethernet@ff3f0000
785 07:00:58.549369 starting USB...
786 07:00:58.800604 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 07:00:58.801108 Starting the controller
788 07:00:58.807604 USB XHCI 1.10
789 07:01:00.971798 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 07:01:00.972418 bl2_stage_init 0x01
791 07:01:00.972849 bl2_stage_init 0x81
792 07:01:00.977408 hw id: 0x0000 - pwm id 0x01
793 07:01:00.977860 bl2_stage_init 0xc1
794 07:01:00.978273 bl2_stage_init 0x02
795 07:01:00.978671
796 07:01:00.983002 L0:00000000
797 07:01:00.983460 L1:20000703
798 07:01:00.983872 L2:00008067
799 07:01:00.984314 L3:14000000
800 07:01:00.986065 B2:00402000
801 07:01:00.986506 B1:e0f83180
802 07:01:00.986910
803 07:01:00.987309 TE: 58159
804 07:01:00.987707
805 07:01:00.997132 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 07:01:00.997605
807 07:01:00.998017 Board ID = 1
808 07:01:00.998418 Set A53 clk to 24M
809 07:01:00.998811 Set A73 clk to 24M
810 07:01:01.002683 Set clk81 to 24M
811 07:01:01.003126 A53 clk: 1200 MHz
812 07:01:01.003532 A73 clk: 1200 MHz
813 07:01:01.006287 CLK81: 166.6M
814 07:01:01.006736 smccc: 00012ab5
815 07:01:01.012035 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 07:01:01.017516 board id: 1
817 07:01:01.022508 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 07:01:01.033173 fw parse done
819 07:01:01.039068 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 07:01:01.081705 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 07:01:01.092662 PIEI prepare done
822 07:01:01.093124 fastboot data load
823 07:01:01.093535 fastboot data verify
824 07:01:01.098269 verify result: 266
825 07:01:01.103800 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 07:01:01.104296 LPDDR4 probe
827 07:01:01.104706 ddr clk to 1584MHz
828 07:01:01.111815 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 07:01:01.149130
830 07:01:01.149616 dmc_version 0001
831 07:01:01.155749 Check phy result
832 07:01:01.161568 INFO : End of CA training
833 07:01:01.162017 INFO : End of initialization
834 07:01:01.167182 INFO : Training has run successfully!
835 07:01:01.167623 Check phy result
836 07:01:01.172843 INFO : End of initialization
837 07:01:01.173291 INFO : End of read enable training
838 07:01:01.178420 INFO : End of fine write leveling
839 07:01:01.183972 INFO : End of Write leveling coarse delay
840 07:01:01.184440 INFO : Training has run successfully!
841 07:01:01.184848 Check phy result
842 07:01:01.189576 INFO : End of initialization
843 07:01:01.190010 INFO : End of read dq deskew training
844 07:01:01.195163 INFO : End of MPR read delay center optimization
845 07:01:01.200815 INFO : End of write delay center optimization
846 07:01:01.206380 INFO : End of read delay center optimization
847 07:01:01.206827 INFO : End of max read latency training
848 07:01:01.211962 INFO : Training has run successfully!
849 07:01:01.212438 1D training succeed
850 07:01:01.221184 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 07:01:01.268798 Check phy result
852 07:01:01.269277 INFO : End of initialization
853 07:01:01.290379 INFO : End of 2D read delay Voltage center optimization
854 07:01:01.310493 INFO : End of 2D read delay Voltage center optimization
855 07:01:01.362459 INFO : End of 2D write delay Voltage center optimization
856 07:01:01.411830 INFO : End of 2D write delay Voltage center optimization
857 07:01:01.417274 INFO : Training has run successfully!
858 07:01:01.417769
859 07:01:01.418189 channel==0
860 07:01:01.422865 RxClkDly_Margin_A0==88 ps 9
861 07:01:01.423354 TxDqDly_Margin_A0==98 ps 10
862 07:01:01.428455 RxClkDly_Margin_A1==88 ps 9
863 07:01:01.428905 TxDqDly_Margin_A1==98 ps 10
864 07:01:01.429333 TrainedVREFDQ_A0==74
865 07:01:01.434074 TrainedVREFDQ_A1==74
866 07:01:01.434586 VrefDac_Margin_A0==25
867 07:01:01.435002 DeviceVref_Margin_A0==40
868 07:01:01.439579 VrefDac_Margin_A1==25
869 07:01:01.440090 DeviceVref_Margin_A1==40
870 07:01:01.440480
871 07:01:01.440868
872 07:01:01.445254 channel==1
873 07:01:01.445734 RxClkDly_Margin_A0==98 ps 10
874 07:01:01.446123 TxDqDly_Margin_A0==98 ps 10
875 07:01:01.450836 RxClkDly_Margin_A1==98 ps 10
876 07:01:01.451316 TxDqDly_Margin_A1==88 ps 9
877 07:01:01.456372 TrainedVREFDQ_A0==77
878 07:01:01.456865 TrainedVREFDQ_A1==77
879 07:01:01.457259 VrefDac_Margin_A0==22
880 07:01:01.462101 DeviceVref_Margin_A0==37
881 07:01:01.462588 VrefDac_Margin_A1==22
882 07:01:01.467550 DeviceVref_Margin_A1==37
883 07:01:01.467974
884 07:01:01.468400 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 07:01:01.473285
886 07:01:01.501243 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
887 07:01:01.501760 2D training succeed
888 07:01:01.506898 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 07:01:01.512307 auto size-- 65535DDR cs0 size: 2048MB
890 07:01:01.512790 DDR cs1 size: 2048MB
891 07:01:01.517982 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 07:01:01.518470 cs0 DataBus test pass
893 07:01:01.523524 cs1 DataBus test pass
894 07:01:01.524053 cs0 AddrBus test pass
895 07:01:01.524462 cs1 AddrBus test pass
896 07:01:01.524853
897 07:01:01.529115 100bdlr_step_size ps== 420
898 07:01:01.529617 result report
899 07:01:01.534756 boot times 0Enable ddr reg access
900 07:01:01.540161 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 07:01:01.553675 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 07:01:02.125624 0.0;M3 CHK:0;cm4_sp_mode 0
903 07:01:02.126191 MVN_1=0x00000000
904 07:01:02.131100 MVN_2=0x00000000
905 07:01:02.136857 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 07:01:02.137302 OPS=0x10
907 07:01:02.137716 ring efuse init
908 07:01:02.138115 chipver efuse init
909 07:01:02.142490 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 07:01:02.148108 [0.018960 Inits done]
911 07:01:02.148545 secure task start!
912 07:01:02.148953 high task start!
913 07:01:02.152655 low task start!
914 07:01:02.153095 run into bl31
915 07:01:02.159329 NOTICE: BL31: v1.3(release):4fc40b1
916 07:01:02.167143 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 07:01:02.167641 NOTICE: BL31: G12A normal boot!
918 07:01:02.192529 NOTICE: BL31: BL33 decompress pass
919 07:01:02.198197 ERROR: Error initializing runtime service opteed_fast
920 07:01:03.431142
921 07:01:03.431724
922 07:01:03.439528 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 07:01:03.440021
924 07:01:03.440445 Model: Libre Computer AML-A311D-CC Alta
925 07:01:03.647957 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 07:01:03.671357 DRAM: 2 GiB (effective 3.8 GiB)
927 07:01:03.814512 Core: 408 devices, 31 uclasses, devicetree: separate
928 07:01:03.820098 WDT: Not starting watchdog@f0d0
929 07:01:03.852352 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 07:01:03.864904 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 07:01:03.869773 ** Bad device specification mmc 0 **
932 07:01:03.880217 Card did not respond to voltage select! : -110
933 07:01:03.887741 ** Bad device specification mmc 0 **
934 07:01:03.888288 Couldn't find partition mmc 0
935 07:01:03.900428 Card did not respond to voltage select! : -110
936 07:01:03.901633 ** Bad device specification mmc 0 **
937 07:01:03.902101 Couldn't find partition mmc 0
938 07:01:03.906721 Error: could not access storage.
939 07:01:04.250235 Net: eth0: ethernet@ff3f0000
940 07:01:04.250823 starting USB...
941 07:01:04.502130 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 07:01:04.502700 Starting the controller
943 07:01:04.509014 USB XHCI 1.10
944 07:01:06.063184 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 07:01:06.071464 scanning usb for storage devices... 0 Storage Device(s) found
947 07:01:06.123021 Hit any key to stop autoboot: 1
948 07:01:06.124089 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
949 07:01:06.124775 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
950 07:01:06.125335 Setting prompt string to ['=>']
951 07:01:06.125846 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
952 07:01:06.139468 0
953 07:01:06.140570 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 07:01:06.141156 Sending with 10 millisecond of delay
956 07:01:07.275691 => setenv autoload no
957 07:01:07.286559 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 07:01:07.291466 setenv autoload no
959 07:01:07.292187 Sending with 10 millisecond of delay
961 07:01:09.088539 => setenv initrd_high 0xffffffff
962 07:01:09.099286 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
963 07:01:09.100197 setenv initrd_high 0xffffffff
964 07:01:09.100914 Sending with 10 millisecond of delay
966 07:01:10.717150 => setenv fdt_high 0xffffffff
967 07:01:10.727927 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
968 07:01:10.728799 setenv fdt_high 0xffffffff
969 07:01:10.729547 Sending with 10 millisecond of delay
971 07:01:11.021368 => dhcp
972 07:01:11.032123 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
973 07:01:11.032969 dhcp
974 07:01:11.033410 Speed: 1000, full duplex
975 07:01:11.033826 BOOTP broadcast 1
976 07:01:11.278727 BOOTP broadcast 2
977 07:01:11.780021 BOOTP broadcast 3
978 07:01:11.793397 DHCP client bound to address 192.168.6.33 (761 ms)
979 07:01:11.794004 Sending with 10 millisecond of delay
981 07:01:13.472105 => setenv serverip 192.168.6.2
982 07:01:13.482687 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
983 07:01:13.483286 setenv serverip 192.168.6.2
984 07:01:13.483756 Sending with 10 millisecond of delay
986 07:01:17.207919 => tftpboot 0x01080000 714861/tftp-deploy-nnapnqbl/kernel/uImage
987 07:01:17.218768 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
988 07:01:17.219671 tftpboot 0x01080000 714861/tftp-deploy-nnapnqbl/kernel/uImage
989 07:01:17.220161 Speed: 1000, full duplex
990 07:01:17.220587 Using ethernet@ff3f0000 device
991 07:01:17.221627 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
992 07:01:17.227258 Filename '714861/tftp-deploy-nnapnqbl/kernel/uImage'.
993 07:01:17.231042 Load address: 0x1080000
994 07:01:20.146622 Loading: *################################################## 43.2 MiB
995 07:01:20.147090 14.8 MiB/s
996 07:01:20.147329 done
997 07:01:20.151083 Bytes transferred = 45308480 (2b35a40 hex)
998 07:01:20.151703 Sending with 10 millisecond of delay
1000 07:01:24.838950 => tftpboot 0x08000000 714861/tftp-deploy-nnapnqbl/ramdisk/ramdisk.cpio.gz.uboot
1001 07:01:24.849673 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1002 07:01:24.850232 tftpboot 0x08000000 714861/tftp-deploy-nnapnqbl/ramdisk/ramdisk.cpio.gz.uboot
1003 07:01:24.850467 Speed: 1000, full duplex
1004 07:01:24.850695 Using ethernet@ff3f0000 device
1005 07:01:24.852186 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1006 07:01:24.861075 Filename '714861/tftp-deploy-nnapnqbl/ramdisk/ramdisk.cpio.gz.uboot'.
1007 07:01:24.861428 Load address: 0x8000000
1008 07:01:32.227315 Loading: *##############T ################################### UDP wrong checksum 00000005 000008c6
1009 07:01:36.963269 T UDP wrong checksum 00000005 000008c6
1010 07:01:46.965143 T T UDP wrong checksum 00000005 000008c6
1011 07:01:55.618478 T UDP wrong checksum 000000ff 000090e0
1012 07:01:55.645806 UDP wrong checksum 000000ff 000022d3
1013 07:02:06.969188 T T T UDP wrong checksum 00000005 000008c6
1014 07:02:21.973378 T T
1015 07:02:21.973829 Retry count exceeded; starting again
1017 07:02:21.974708 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1020 07:02:21.975681 end: 2.4 uboot-commands (duration 00:01:47) [common]
1022 07:02:21.976486 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1024 07:02:21.977129 end: 2 uboot-action (duration 00:01:47) [common]
1026 07:02:21.978009 Cleaning after the job
1027 07:02:21.978353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/ramdisk
1028 07:02:21.979222 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/kernel
1029 07:02:22.003429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/dtb
1030 07:02:22.004381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/nfsrootfs
1031 07:02:22.309052 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714861/tftp-deploy-nnapnqbl/modules
1032 07:02:22.331378 start: 4.1 power-off (timeout 00:00:30) [common]
1033 07:02:22.332137 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1034 07:02:22.366211 >> OK - accepted request
1035 07:02:22.368408 Returned 0 in 0 seconds
1036 07:02:22.469312 end: 4.1 power-off (duration 00:00:00) [common]
1038 07:02:22.470389 start: 4.2 read-feedback (timeout 00:10:00) [common]
1039 07:02:22.471087 Listened to connection for namespace 'common' for up to 1s
1040 07:02:23.472276 Finalising connection for namespace 'common'
1041 07:02:23.473039 Disconnecting from shell: Finalise
1042 07:02:23.473334 =>
1043 07:02:23.574171 end: 4.2 read-feedback (duration 00:00:01) [common]
1044 07:02:23.574663 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714861
1045 07:02:26.275270 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714861
1046 07:02:26.276114 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.