Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:06:11.550203 lava-dispatcher, installed at version: 2024.01
2 07:06:11.550978 start: 0 validate
3 07:06:11.551459 Start time: 2024-09-06 07:06:11.551427+00:00 (UTC)
4 07:06:11.552013 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:06:11.552565 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:06:11.594455 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:06:11.594988 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:06:11.622893 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:06:11.623489 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 07:06:11.650693 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:06:11.651190 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:06:11.684459 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:06:11.684945 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 07:06:11.720865 validate duration: 0.17
16 07:06:11.721735 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:06:11.722082 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:06:11.722409 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:06:11.723007 Not decompressing ramdisk as can be used compressed.
20 07:06:11.723472 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 07:06:11.723763 saving as /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/ramdisk/initrd.cpio.gz
22 07:06:11.724070 total size: 5628140 (5 MB)
23 07:06:11.760222 progress 0 % (0 MB)
24 07:06:11.765265 progress 5 % (0 MB)
25 07:06:11.773352 progress 10 % (0 MB)
26 07:06:11.780446 progress 15 % (0 MB)
27 07:06:11.786261 progress 20 % (1 MB)
28 07:06:11.789884 progress 25 % (1 MB)
29 07:06:11.793940 progress 30 % (1 MB)
30 07:06:11.798022 progress 35 % (1 MB)
31 07:06:11.801624 progress 40 % (2 MB)
32 07:06:11.805683 progress 45 % (2 MB)
33 07:06:11.809296 progress 50 % (2 MB)
34 07:06:11.813314 progress 55 % (2 MB)
35 07:06:11.817378 progress 60 % (3 MB)
36 07:06:11.821016 progress 65 % (3 MB)
37 07:06:11.824991 progress 70 % (3 MB)
38 07:06:11.828650 progress 75 % (4 MB)
39 07:06:11.832627 progress 80 % (4 MB)
40 07:06:11.836236 progress 85 % (4 MB)
41 07:06:11.840250 progress 90 % (4 MB)
42 07:06:11.844194 progress 95 % (5 MB)
43 07:06:11.847438 progress 100 % (5 MB)
44 07:06:11.848090 5 MB downloaded in 0.12 s (43.29 MB/s)
45 07:06:11.848649 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:06:11.849526 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:06:11.849818 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:06:11.850086 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:06:11.850562 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
51 07:06:11.850805 saving as /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/kernel/Image
52 07:06:11.851013 total size: 45308416 (43 MB)
53 07:06:11.851222 No compression specified
54 07:06:11.887291 progress 0 % (0 MB)
55 07:06:11.915087 progress 5 % (2 MB)
56 07:06:11.942581 progress 10 % (4 MB)
57 07:06:11.969454 progress 15 % (6 MB)
58 07:06:11.996451 progress 20 % (8 MB)
59 07:06:12.023109 progress 25 % (10 MB)
60 07:06:12.049904 progress 30 % (12 MB)
61 07:06:12.076730 progress 35 % (15 MB)
62 07:06:12.103924 progress 40 % (17 MB)
63 07:06:12.130832 progress 45 % (19 MB)
64 07:06:12.158329 progress 50 % (21 MB)
65 07:06:12.185375 progress 55 % (23 MB)
66 07:06:12.212780 progress 60 % (25 MB)
67 07:06:12.240052 progress 65 % (28 MB)
68 07:06:12.267573 progress 70 % (30 MB)
69 07:06:12.294936 progress 75 % (32 MB)
70 07:06:12.322219 progress 80 % (34 MB)
71 07:06:12.350567 progress 85 % (36 MB)
72 07:06:12.380008 progress 90 % (38 MB)
73 07:06:12.409044 progress 95 % (41 MB)
74 07:06:12.437570 progress 100 % (43 MB)
75 07:06:12.438285 43 MB downloaded in 0.59 s (73.58 MB/s)
76 07:06:12.438763 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:06:12.439577 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:06:12.439853 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:06:12.440162 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:06:12.440645 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 07:06:12.440915 saving as /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/dtb/meson-g12b-a311d-libretech-cc.dtb
83 07:06:12.441124 total size: 54667 (0 MB)
84 07:06:12.441336 No compression specified
85 07:06:12.480357 progress 59 % (0 MB)
86 07:06:12.481204 progress 100 % (0 MB)
87 07:06:12.481759 0 MB downloaded in 0.04 s (1.28 MB/s)
88 07:06:12.482256 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:06:12.483073 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:06:12.483333 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:06:12.483596 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:06:12.484080 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 07:06:12.484341 saving as /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/nfsrootfs/full.rootfs.tar
95 07:06:12.484544 total size: 474398908 (452 MB)
96 07:06:12.484752 Using unxz to decompress xz
97 07:06:12.519167 progress 0 % (0 MB)
98 07:06:13.669655 progress 5 % (22 MB)
99 07:06:15.106478 progress 10 % (45 MB)
100 07:06:15.552657 progress 15 % (67 MB)
101 07:06:16.385217 progress 20 % (90 MB)
102 07:06:16.918857 progress 25 % (113 MB)
103 07:06:17.275547 progress 30 % (135 MB)
104 07:06:17.878660 progress 35 % (158 MB)
105 07:06:18.804497 progress 40 % (181 MB)
106 07:06:19.647541 progress 45 % (203 MB)
107 07:06:20.368264 progress 50 % (226 MB)
108 07:06:21.124869 progress 55 % (248 MB)
109 07:06:22.334749 progress 60 % (271 MB)
110 07:06:23.835621 progress 65 % (294 MB)
111 07:06:25.456573 progress 70 % (316 MB)
112 07:06:28.519776 progress 75 % (339 MB)
113 07:06:30.935652 progress 80 % (361 MB)
114 07:06:33.794416 progress 85 % (384 MB)
115 07:06:36.947423 progress 90 % (407 MB)
116 07:06:40.181641 progress 95 % (429 MB)
117 07:06:43.617107 progress 100 % (452 MB)
118 07:06:43.630219 452 MB downloaded in 31.15 s (14.53 MB/s)
119 07:06:43.631082 end: 1.4.1 http-download (duration 00:00:31) [common]
121 07:06:43.632748 end: 1.4 download-retry (duration 00:00:31) [common]
122 07:06:43.633282 start: 1.5 download-retry (timeout 00:09:28) [common]
123 07:06:43.633805 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 07:06:43.634932 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
125 07:06:43.635420 saving as /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/modules/modules.tar
126 07:06:43.635835 total size: 11502724 (10 MB)
127 07:06:43.636298 Using unxz to decompress xz
128 07:06:43.678163 progress 0 % (0 MB)
129 07:06:43.746522 progress 5 % (0 MB)
130 07:06:43.823652 progress 10 % (1 MB)
131 07:06:43.908210 progress 15 % (1 MB)
132 07:06:43.988575 progress 20 % (2 MB)
133 07:06:44.065732 progress 25 % (2 MB)
134 07:06:44.147736 progress 30 % (3 MB)
135 07:06:44.222277 progress 35 % (3 MB)
136 07:06:44.301079 progress 40 % (4 MB)
137 07:06:44.372484 progress 45 % (4 MB)
138 07:06:44.451119 progress 50 % (5 MB)
139 07:06:44.526929 progress 55 % (6 MB)
140 07:06:44.607746 progress 60 % (6 MB)
141 07:06:44.695663 progress 65 % (7 MB)
142 07:06:44.775124 progress 70 % (7 MB)
143 07:06:44.871289 progress 75 % (8 MB)
144 07:06:44.961535 progress 80 % (8 MB)
145 07:06:45.042127 progress 85 % (9 MB)
146 07:06:45.112626 progress 90 % (9 MB)
147 07:06:45.188420 progress 95 % (10 MB)
148 07:06:45.264357 progress 100 % (10 MB)
149 07:06:45.274237 10 MB downloaded in 1.64 s (6.70 MB/s)
150 07:06:45.274835 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:06:45.275698 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:06:45.275972 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 07:06:45.276578 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 07:07:00.445651 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/714873/extract-nfsrootfs-utphco0a
156 07:07:00.446261 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 07:07:00.446548 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 07:07:00.447272 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w
159 07:07:00.447734 makedir: /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin
160 07:07:00.448113 makedir: /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/tests
161 07:07:00.448459 makedir: /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/results
162 07:07:00.448792 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-add-keys
163 07:07:00.449317 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-add-sources
164 07:07:00.449812 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-background-process-start
165 07:07:00.450313 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-background-process-stop
166 07:07:00.450948 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-common-functions
167 07:07:00.451473 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-echo-ipv4
168 07:07:00.451953 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-install-packages
169 07:07:00.452515 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-installed-packages
170 07:07:00.453013 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-os-build
171 07:07:00.453485 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-probe-channel
172 07:07:00.453953 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-probe-ip
173 07:07:00.454419 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-target-ip
174 07:07:00.454877 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-target-mac
175 07:07:00.455341 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-target-storage
176 07:07:00.455814 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-test-case
177 07:07:00.456337 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-test-event
178 07:07:00.456821 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-test-feedback
179 07:07:00.457290 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-test-raise
180 07:07:00.457751 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-test-reference
181 07:07:00.458215 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-test-runner
182 07:07:00.458683 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-test-set
183 07:07:00.459149 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-test-shell
184 07:07:00.459624 Updating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-install-packages (oe)
185 07:07:00.460169 Updating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/bin/lava-installed-packages (oe)
186 07:07:00.460609 Creating /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/environment
187 07:07:00.461044 LAVA metadata
188 07:07:00.461317 - LAVA_JOB_ID=714873
189 07:07:00.461530 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:07:00.461885 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 07:07:00.462820 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:07:00.463122 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 07:07:00.463328 skipped lava-vland-overlay
194 07:07:00.463569 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:07:00.463823 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 07:07:00.464066 skipped lava-multinode-overlay
197 07:07:00.464310 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:07:00.464560 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 07:07:00.464805 Loading test definitions
200 07:07:00.465081 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 07:07:00.465300 Using /lava-714873 at stage 0
202 07:07:00.466458 uuid=714873_1.6.2.4.1 testdef=None
203 07:07:00.466760 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:07:00.467019 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 07:07:00.468731 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:07:00.469512 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 07:07:00.471646 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:07:00.472507 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 07:07:00.474534 runner path: /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 714873_1.6.2.4.1
212 07:07:00.475090 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:07:00.475841 Creating lava-test-runner.conf files
215 07:07:00.476070 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714873/lava-overlay-1un3ll8w/lava-714873/0 for stage 0
216 07:07:00.476402 - 0_v4l2-decoder-conformance-vp9
217 07:07:00.476735 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:07:00.477002 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 07:07:00.498173 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:07:00.498547 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 07:07:00.498807 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:07:00.499072 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:07:00.499331 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 07:07:01.110652 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:07:01.111219 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 07:07:01.111518 extracting modules file /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714873/extract-nfsrootfs-utphco0a
227 07:07:02.630026 extracting modules file /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714873/extract-overlay-ramdisk-x75lyc_y/ramdisk
228 07:07:04.000540 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:07:04.001022 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 07:07:04.001298 [common] Applying overlay to NFS
231 07:07:04.001510 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714873/compress-overlay-6134ac03/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714873/extract-nfsrootfs-utphco0a
232 07:07:04.030775 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:07:04.031153 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 07:07:04.031427 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 07:07:04.031655 Converting downloaded kernel to a uImage
236 07:07:04.031956 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/kernel/Image /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/kernel/uImage
237 07:07:04.484679 output: Image Name:
238 07:07:04.485087 output: Created: Fri Sep 6 07:07:04 2024
239 07:07:04.485300 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:07:04.485506 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
241 07:07:04.485707 output: Load Address: 01080000
242 07:07:04.485905 output: Entry Point: 01080000
243 07:07:04.486099 output:
244 07:07:04.486433 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 07:07:04.486704 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 07:07:04.486973 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 07:07:04.487227 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:07:04.487486 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 07:07:04.487748 Building ramdisk /var/lib/lava/dispatcher/tmp/714873/extract-overlay-ramdisk-x75lyc_y/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714873/extract-overlay-ramdisk-x75lyc_y/ramdisk
250 07:07:06.647806 >> 165160 blocks
251 07:07:14.414800 Adding RAMdisk u-boot header.
252 07:07:14.415641 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714873/extract-overlay-ramdisk-x75lyc_y/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714873/extract-overlay-ramdisk-x75lyc_y/ramdisk.cpio.gz.uboot
253 07:07:14.650011 output: Image Name:
254 07:07:14.650441 output: Created: Fri Sep 6 07:07:14 2024
255 07:07:14.650655 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:07:14.650861 output: Data Size: 23257933 Bytes = 22712.83 KiB = 22.18 MiB
257 07:07:14.651063 output: Load Address: 00000000
258 07:07:14.651263 output: Entry Point: 00000000
259 07:07:14.651460 output:
260 07:07:14.652278 rename /var/lib/lava/dispatcher/tmp/714873/extract-overlay-ramdisk-x75lyc_y/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/ramdisk/ramdisk.cpio.gz.uboot
261 07:07:14.653006 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 07:07:14.653571 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 07:07:14.654099 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 07:07:14.654561 No LXC device requested
265 07:07:14.655057 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:07:14.655566 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 07:07:14.656087 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:07:14.656509 Checking files for TFTP limit of 4294967296 bytes.
269 07:07:14.659158 end: 1 tftp-deploy (duration 00:01:03) [common]
270 07:07:14.659728 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:07:14.660285 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:07:14.660780 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:07:14.661278 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:07:14.661799 Using kernel file from prepare-kernel: 714873/tftp-deploy-wnkbayv_/kernel/uImage
275 07:07:14.662419 substitutions:
276 07:07:14.662820 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:07:14.663216 - {DTB_ADDR}: 0x01070000
278 07:07:14.663609 - {DTB}: 714873/tftp-deploy-wnkbayv_/dtb/meson-g12b-a311d-libretech-cc.dtb
279 07:07:14.664025 - {INITRD}: 714873/tftp-deploy-wnkbayv_/ramdisk/ramdisk.cpio.gz.uboot
280 07:07:14.664422 - {KERNEL_ADDR}: 0x01080000
281 07:07:14.664809 - {KERNEL}: 714873/tftp-deploy-wnkbayv_/kernel/uImage
282 07:07:14.665193 - {LAVA_MAC}: None
283 07:07:14.665617 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/714873/extract-nfsrootfs-utphco0a
284 07:07:14.666007 - {NFS_SERVER_IP}: 192.168.6.2
285 07:07:14.666393 - {PRESEED_CONFIG}: None
286 07:07:14.666779 - {PRESEED_LOCAL}: None
287 07:07:14.667165 - {RAMDISK_ADDR}: 0x08000000
288 07:07:14.667544 - {RAMDISK}: 714873/tftp-deploy-wnkbayv_/ramdisk/ramdisk.cpio.gz.uboot
289 07:07:14.667926 - {ROOT_PART}: None
290 07:07:14.668393 - {ROOT}: None
291 07:07:14.668781 - {SERVER_IP}: 192.168.6.2
292 07:07:14.669165 - {TEE_ADDR}: 0x83000000
293 07:07:14.669561 - {TEE}: None
294 07:07:14.669955 Parsed boot commands:
295 07:07:14.670327 - setenv autoload no
296 07:07:14.670708 - setenv initrd_high 0xffffffff
297 07:07:14.671087 - setenv fdt_high 0xffffffff
298 07:07:14.671467 - dhcp
299 07:07:14.671846 - setenv serverip 192.168.6.2
300 07:07:14.672257 - tftpboot 0x01080000 714873/tftp-deploy-wnkbayv_/kernel/uImage
301 07:07:14.672645 - tftpboot 0x08000000 714873/tftp-deploy-wnkbayv_/ramdisk/ramdisk.cpio.gz.uboot
302 07:07:14.673025 - tftpboot 0x01070000 714873/tftp-deploy-wnkbayv_/dtb/meson-g12b-a311d-libretech-cc.dtb
303 07:07:14.673408 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/714873/extract-nfsrootfs-utphco0a,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:07:14.673803 - bootm 0x01080000 0x08000000 0x01070000
305 07:07:14.674296 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:07:14.675773 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:07:14.676219 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 07:07:14.690083 Setting prompt string to ['lava-test: # ']
310 07:07:14.691543 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:07:14.692205 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:07:14.692766 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:07:14.693285 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:07:14.694391 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 07:07:14.731912 >> OK - accepted request
316 07:07:14.734259 Returned 0 in 0 seconds
317 07:07:14.835405 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:07:14.837135 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:07:14.837712 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:07:14.838234 Setting prompt string to ['Hit any key to stop autoboot']
322 07:07:14.838688 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:07:14.840264 Trying 192.168.56.21...
324 07:07:14.840747 Connected to conserv1.
325 07:07:14.841163 Escape character is '^]'.
326 07:07:14.959726
327 07:07:14.960362 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 07:07:14.960796
329 07:07:25.842245 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 07:07:25.842886 bl2_stage_init 0x01
331 07:07:25.843312 bl2_stage_init 0x81
332 07:07:25.847920 hw id: 0x0000 - pwm id 0x01
333 07:07:25.848477 bl2_stage_init 0xc1
334 07:07:25.848918 bl2_stage_init 0x02
335 07:07:25.849310
336 07:07:25.853359 L0:00000000
337 07:07:25.853793 L1:20000703
338 07:07:25.854183 L2:00008067
339 07:07:25.854567 L3:14000000
340 07:07:25.858942 B2:00402000
341 07:07:25.859404 B1:e0f83180
342 07:07:25.859794
343 07:07:25.860218 TE: 58159
344 07:07:25.860606
345 07:07:25.864610 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 07:07:25.865056
347 07:07:25.865448 Board ID = 1
348 07:07:25.870099 Set A53 clk to 24M
349 07:07:25.870510 Set A73 clk to 24M
350 07:07:25.870900 Set clk81 to 24M
351 07:07:25.875848 A53 clk: 1200 MHz
352 07:07:25.876287 A73 clk: 1200 MHz
353 07:07:25.876673 CLK81: 166.6M
354 07:07:25.877052 smccc: 00012ab5
355 07:07:25.881305 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 07:07:25.886978 board id: 1
357 07:07:25.892906 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:07:25.903542 fw parse done
359 07:07:25.909407 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:07:25.952121 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:07:25.963035 PIEI prepare done
362 07:07:25.963502 fastboot data load
363 07:07:25.963897 fastboot data verify
364 07:07:25.968674 verify result: 266
365 07:07:25.974192 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 07:07:25.974604 LPDDR4 probe
367 07:07:25.974988 ddr clk to 1584MHz
368 07:07:25.982185 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:07:26.019461
370 07:07:26.019900 dmc_version 0001
371 07:07:26.026133 Check phy result
372 07:07:26.032032 INFO : End of CA training
373 07:07:26.032455 INFO : End of initialization
374 07:07:26.037656 INFO : Training has run successfully!
375 07:07:26.038074 Check phy result
376 07:07:26.043217 INFO : End of initialization
377 07:07:26.043640 INFO : End of read enable training
378 07:07:26.048952 INFO : End of fine write leveling
379 07:07:26.054395 INFO : End of Write leveling coarse delay
380 07:07:26.054809 INFO : Training has run successfully!
381 07:07:26.055201 Check phy result
382 07:07:26.060003 INFO : End of initialization
383 07:07:26.060423 INFO : End of read dq deskew training
384 07:07:26.065577 INFO : End of MPR read delay center optimization
385 07:07:26.071226 INFO : End of write delay center optimization
386 07:07:26.076950 INFO : End of read delay center optimization
387 07:07:26.077375 INFO : End of max read latency training
388 07:07:26.082439 INFO : Training has run successfully!
389 07:07:26.082865 1D training succeed
390 07:07:26.091597 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:07:26.138276 Check phy result
392 07:07:26.138720 INFO : End of initialization
393 07:07:26.160784 INFO : End of 2D read delay Voltage center optimization
394 07:07:26.179629 INFO : End of 2D read delay Voltage center optimization
395 07:07:26.232190 INFO : End of 2D write delay Voltage center optimization
396 07:07:26.281315 INFO : End of 2D write delay Voltage center optimization
397 07:07:26.286808 INFO : Training has run successfully!
398 07:07:26.287232
399 07:07:26.287631 channel==0
400 07:07:26.292416 RxClkDly_Margin_A0==88 ps 9
401 07:07:26.292980 TxDqDly_Margin_A0==98 ps 10
402 07:07:26.297992 RxClkDly_Margin_A1==88 ps 9
403 07:07:26.298474 TxDqDly_Margin_A1==88 ps 9
404 07:07:26.298920 TrainedVREFDQ_A0==74
405 07:07:26.303593 TrainedVREFDQ_A1==74
406 07:07:26.304106 VrefDac_Margin_A0==25
407 07:07:26.304550 DeviceVref_Margin_A0==40
408 07:07:26.309177 VrefDac_Margin_A1==25
409 07:07:26.309647 DeviceVref_Margin_A1==40
410 07:07:26.310081
411 07:07:26.310514
412 07:07:26.310944 channel==1
413 07:07:26.314799 RxClkDly_Margin_A0==88 ps 9
414 07:07:26.315268 TxDqDly_Margin_A0==98 ps 10
415 07:07:26.320399 RxClkDly_Margin_A1==88 ps 9
416 07:07:26.320872 TxDqDly_Margin_A1==88 ps 9
417 07:07:26.325975 TrainedVREFDQ_A0==77
418 07:07:26.326449 TrainedVREFDQ_A1==77
419 07:07:26.326886 VrefDac_Margin_A0==23
420 07:07:26.331602 DeviceVref_Margin_A0==37
421 07:07:26.332102 VrefDac_Margin_A1==24
422 07:07:26.337211 DeviceVref_Margin_A1==37
423 07:07:26.337676
424 07:07:26.338111 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:07:26.338540
426 07:07:26.370756 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 07:07:26.371355 2D training succeed
428 07:07:26.376381 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:07:26.381971 auto size-- 65535DDR cs0 size: 2048MB
430 07:07:26.382447 DDR cs1 size: 2048MB
431 07:07:26.388296 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:07:26.388771 cs0 DataBus test pass
433 07:07:26.393173 cs1 DataBus test pass
434 07:07:26.393644 cs0 AddrBus test pass
435 07:07:26.394077 cs1 AddrBus test pass
436 07:07:26.394505
437 07:07:26.398774 100bdlr_step_size ps== 420
438 07:07:26.399256 result report
439 07:07:26.404456 boot times 0Enable ddr reg access
440 07:07:26.409578 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:07:26.423075 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 07:07:26.998067 0.0;M3 CHK:0;cm4_sp_mode 0
443 07:07:26.998749 MVN_1=0x00000000
444 07:07:27.000988 MVN_2=0x00000000
445 07:07:27.006958 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 07:07:27.007479 OPS=0x10
447 07:07:27.007942 ring efuse init
448 07:07:27.008691 chipver efuse init
449 07:07:27.012524 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 07:07:27.018153 [0.018961 Inits done]
451 07:07:27.018790 secure task start!
452 07:07:27.019619 high task start!
453 07:07:27.020465 low task start!
454 07:07:27.022481 run into bl31
455 07:07:27.028918 NOTICE: BL31: v1.3(release):4fc40b1
456 07:07:27.036739 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 07:07:27.037139 NOTICE: BL31: G12A normal boot!
458 07:07:27.062059 NOTICE: BL31: BL33 decompress pass
459 07:07:27.068236 ERROR: Error initializing runtime service opteed_fast
460 07:07:28.300836
461 07:07:28.301511
462 07:07:28.309032 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 07:07:28.309541
464 07:07:28.309988 Model: Libre Computer AML-A311D-CC Alta
465 07:07:28.517631 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 07:07:28.540097 DRAM: 2 GiB (effective 3.8 GiB)
467 07:07:28.683869 Core: 408 devices, 31 uclasses, devicetree: separate
468 07:07:28.689684 WDT: Not starting watchdog@f0d0
469 07:07:28.721945 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 07:07:28.734423 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 07:07:28.739507 ** Bad device specification mmc 0 **
472 07:07:28.749771 Card did not respond to voltage select! : -110
473 07:07:28.757503 ** Bad device specification mmc 0 **
474 07:07:28.757975 Couldn't find partition mmc 0
475 07:07:28.765735 Card did not respond to voltage select! : -110
476 07:07:28.771183 ** Bad device specification mmc 0 **
477 07:07:28.771652 Couldn't find partition mmc 0
478 07:07:28.776304 Error: could not access storage.
479 07:07:30.043641 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 07:07:30.044360 bl2_stage_init 0x01
481 07:07:30.044843 bl2_stage_init 0x81
482 07:07:30.049106 hw id: 0x0000 - pwm id 0x01
483 07:07:30.049590 bl2_stage_init 0xc1
484 07:07:30.050043 bl2_stage_init 0x02
485 07:07:30.050484
486 07:07:30.054756 L0:00000000
487 07:07:30.055255 L1:20000703
488 07:07:30.055703 L2:00008067
489 07:07:30.056184 L3:14000000
490 07:07:30.060332 B2:00402000
491 07:07:30.060836 B1:e0f83180
492 07:07:30.061285
493 07:07:30.061725 TE: 58159
494 07:07:30.062182
495 07:07:30.065972 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 07:07:30.066461
497 07:07:30.066911 Board ID = 1
498 07:07:30.071613 Set A53 clk to 24M
499 07:07:30.072114 Set A73 clk to 24M
500 07:07:30.072560 Set clk81 to 24M
501 07:07:30.077116 A53 clk: 1200 MHz
502 07:07:30.077581 A73 clk: 1200 MHz
503 07:07:30.078024 CLK81: 166.6M
504 07:07:30.078465 smccc: 00012ab5
505 07:07:30.082760 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 07:07:30.088321 board id: 1
507 07:07:30.094284 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 07:07:30.105020 fw parse done
509 07:07:30.110801 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 07:07:30.153540 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 07:07:30.164273 PIEI prepare done
512 07:07:30.164763 fastboot data load
513 07:07:30.165217 fastboot data verify
514 07:07:30.169958 verify result: 266
515 07:07:30.175580 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 07:07:30.176187 LPDDR4 probe
517 07:07:30.176683 ddr clk to 1584MHz
518 07:07:30.183656 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 07:07:30.220798
520 07:07:30.221329 dmc_version 0001
521 07:07:30.227476 Check phy result
522 07:07:30.233343 INFO : End of CA training
523 07:07:30.233825 INFO : End of initialization
524 07:07:30.238946 INFO : Training has run successfully!
525 07:07:30.239424 Check phy result
526 07:07:30.244539 INFO : End of initialization
527 07:07:30.245009 INFO : End of read enable training
528 07:07:30.250135 INFO : End of fine write leveling
529 07:07:30.255727 INFO : End of Write leveling coarse delay
530 07:07:30.256251 INFO : Training has run successfully!
531 07:07:30.256699 Check phy result
532 07:07:30.261313 INFO : End of initialization
533 07:07:30.261786 INFO : End of read dq deskew training
534 07:07:30.266920 INFO : End of MPR read delay center optimization
535 07:07:30.272548 INFO : End of write delay center optimization
536 07:07:30.278140 INFO : End of read delay center optimization
537 07:07:30.278622 INFO : End of max read latency training
538 07:07:30.283868 INFO : Training has run successfully!
539 07:07:30.284435 1D training succeed
540 07:07:30.292921 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 07:07:30.340500 Check phy result
542 07:07:30.341050 INFO : End of initialization
543 07:07:30.362146 INFO : End of 2D read delay Voltage center optimization
544 07:07:30.382270 INFO : End of 2D read delay Voltage center optimization
545 07:07:30.434206 INFO : End of 2D write delay Voltage center optimization
546 07:07:30.483419 INFO : End of 2D write delay Voltage center optimization
547 07:07:30.488945 INFO : Training has run successfully!
548 07:07:30.489446
549 07:07:30.489944 channel==0
550 07:07:30.494554 RxClkDly_Margin_A0==88 ps 9
551 07:07:30.495047 TxDqDly_Margin_A0==98 ps 10
552 07:07:30.500209 RxClkDly_Margin_A1==88 ps 9
553 07:07:30.500713 TxDqDly_Margin_A1==88 ps 9
554 07:07:30.501165 TrainedVREFDQ_A0==74
555 07:07:30.505780 TrainedVREFDQ_A1==74
556 07:07:30.506253 VrefDac_Margin_A0==25
557 07:07:30.506698 DeviceVref_Margin_A0==40
558 07:07:30.511399 VrefDac_Margin_A1==25
559 07:07:30.511906 DeviceVref_Margin_A1==40
560 07:07:30.512405
561 07:07:30.512852
562 07:07:30.513287 channel==1
563 07:07:30.516962 RxClkDly_Margin_A0==88 ps 9
564 07:07:30.517433 TxDqDly_Margin_A0==88 ps 9
565 07:07:30.522595 RxClkDly_Margin_A1==98 ps 10
566 07:07:30.523067 TxDqDly_Margin_A1==88 ps 9
567 07:07:30.528216 TrainedVREFDQ_A0==77
568 07:07:30.528697 TrainedVREFDQ_A1==77
569 07:07:30.529145 VrefDac_Margin_A0==22
570 07:07:30.533759 DeviceVref_Margin_A0==37
571 07:07:30.534237 VrefDac_Margin_A1==22
572 07:07:30.539380 DeviceVref_Margin_A1==37
573 07:07:30.539857
574 07:07:30.540345 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 07:07:30.540791
576 07:07:30.572985 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 07:07:30.573584 2D training succeed
578 07:07:30.578567 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 07:07:30.584229 auto size-- 65535DDR cs0 size: 2048MB
580 07:07:30.584745 DDR cs1 size: 2048MB
581 07:07:30.589863 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 07:07:30.590407 cs0 DataBus test pass
583 07:07:30.595388 cs1 DataBus test pass
584 07:07:30.595877 cs0 AddrBus test pass
585 07:07:30.596383 cs1 AddrBus test pass
586 07:07:30.596827
587 07:07:30.601007 100bdlr_step_size ps== 420
588 07:07:30.601533 result report
589 07:07:30.606604 boot times 0Enable ddr reg access
590 07:07:30.611761 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 07:07:30.625215 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 07:07:31.197224 0.0;M3 CHK:0;cm4_sp_mode 0
593 07:07:31.197911 MVN_1=0x00000000
594 07:07:31.202704 MVN_2=0x00000000
595 07:07:31.208462 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 07:07:31.209020 OPS=0x10
597 07:07:31.209487 ring efuse init
598 07:07:31.209967 chipver efuse init
599 07:07:31.216778 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 07:07:31.217358 [0.018961 Inits done]
601 07:07:31.217796 secure task start!
602 07:07:31.224255 high task start!
603 07:07:31.224769 low task start!
604 07:07:31.225205 run into bl31
605 07:07:31.230922 NOTICE: BL31: v1.3(release):4fc40b1
606 07:07:31.238777 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 07:07:31.239271 NOTICE: BL31: G12A normal boot!
608 07:07:31.264106 NOTICE: BL31: BL33 decompress pass
609 07:07:31.269777 ERROR: Error initializing runtime service opteed_fast
610 07:07:32.502706
611 07:07:32.503380
612 07:07:32.511141 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 07:07:32.511728
614 07:07:32.512226 Model: Libre Computer AML-A311D-CC Alta
615 07:07:32.719469 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 07:07:32.742973 DRAM: 2 GiB (effective 3.8 GiB)
617 07:07:32.886317 Core: 408 devices, 31 uclasses, devicetree: separate
618 07:07:32.891872 WDT: Not starting watchdog@f0d0
619 07:07:32.924062 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 07:07:32.936701 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 07:07:32.941501 ** Bad device specification mmc 0 **
622 07:07:32.951922 Card did not respond to voltage select! : -110
623 07:07:32.959430 ** Bad device specification mmc 0 **
624 07:07:32.959843 Couldn't find partition mmc 0
625 07:07:32.967906 Card did not respond to voltage select! : -110
626 07:07:32.973264 ** Bad device specification mmc 0 **
627 07:07:32.973875 Couldn't find partition mmc 0
628 07:07:32.978301 Error: could not access storage.
629 07:07:33.320872 Net: eth0: ethernet@ff3f0000
630 07:07:33.321469 starting USB...
631 07:07:33.572713 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 07:07:33.573215 Starting the controller
633 07:07:33.579553 USB XHCI 1.10
634 07:07:35.294519 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 07:07:35.295152 bl2_stage_init 0x01
636 07:07:35.295578 bl2_stage_init 0x81
637 07:07:35.300099 hw id: 0x0000 - pwm id 0x01
638 07:07:35.300552 bl2_stage_init 0xc1
639 07:07:35.300960 bl2_stage_init 0x02
640 07:07:35.301360
641 07:07:35.305790 L0:00000000
642 07:07:35.306230 L1:20000703
643 07:07:35.306635 L2:00008067
644 07:07:35.307031 L3:14000000
645 07:07:35.308641 B2:00402000
646 07:07:35.309067 B1:e0f83180
647 07:07:35.309469
648 07:07:35.309866 TE: 58124
649 07:07:35.310263
650 07:07:35.319793 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 07:07:35.320319
652 07:07:35.320766 Board ID = 1
653 07:07:35.321187 Set A53 clk to 24M
654 07:07:35.321578 Set A73 clk to 24M
655 07:07:35.325448 Set clk81 to 24M
656 07:07:35.325877 A53 clk: 1200 MHz
657 07:07:35.326266 A73 clk: 1200 MHz
658 07:07:35.330916 CLK81: 166.6M
659 07:07:35.331350 smccc: 00012a92
660 07:07:35.336595 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 07:07:35.337029 board id: 1
662 07:07:35.345400 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 07:07:35.355796 fw parse done
664 07:07:35.361678 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 07:07:35.404417 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 07:07:35.415279 PIEI prepare done
667 07:07:35.415712 fastboot data load
668 07:07:35.416134 fastboot data verify
669 07:07:35.420850 verify result: 266
670 07:07:35.426465 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 07:07:35.426908 LPDDR4 probe
672 07:07:35.427308 ddr clk to 1584MHz
673 07:07:35.434412 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 07:07:35.471751
675 07:07:35.472245 dmc_version 0001
676 07:07:35.478424 Check phy result
677 07:07:35.484314 INFO : End of CA training
678 07:07:35.484737 INFO : End of initialization
679 07:07:35.489896 INFO : Training has run successfully!
680 07:07:35.490322 Check phy result
681 07:07:35.495468 INFO : End of initialization
682 07:07:35.495893 INFO : End of read enable training
683 07:07:35.501087 INFO : End of fine write leveling
684 07:07:35.506715 INFO : End of Write leveling coarse delay
685 07:07:35.507144 INFO : Training has run successfully!
686 07:07:35.507536 Check phy result
687 07:07:35.512295 INFO : End of initialization
688 07:07:35.512722 INFO : End of read dq deskew training
689 07:07:35.517904 INFO : End of MPR read delay center optimization
690 07:07:35.523500 INFO : End of write delay center optimization
691 07:07:35.529095 INFO : End of read delay center optimization
692 07:07:35.529518 INFO : End of max read latency training
693 07:07:35.534671 INFO : Training has run successfully!
694 07:07:35.535092 1D training succeed
695 07:07:35.543949 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 07:07:35.591450 Check phy result
697 07:07:35.591894 INFO : End of initialization
698 07:07:35.613193 INFO : End of 2D read delay Voltage center optimization
699 07:07:35.633433 INFO : End of 2D read delay Voltage center optimization
700 07:07:35.685509 INFO : End of 2D write delay Voltage center optimization
701 07:07:35.734923 INFO : End of 2D write delay Voltage center optimization
702 07:07:35.740417 INFO : Training has run successfully!
703 07:07:35.740862
704 07:07:35.741272 channel==0
705 07:07:35.746026 RxClkDly_Margin_A0==88 ps 9
706 07:07:35.746465 TxDqDly_Margin_A0==98 ps 10
707 07:07:35.751624 RxClkDly_Margin_A1==88 ps 9
708 07:07:35.752102 TxDqDly_Margin_A1==98 ps 10
709 07:07:35.752521 TrainedVREFDQ_A0==74
710 07:07:35.757212 TrainedVREFDQ_A1==74
711 07:07:35.757645 VrefDac_Margin_A0==25
712 07:07:35.758049 DeviceVref_Margin_A0==40
713 07:07:35.762836 VrefDac_Margin_A1==25
714 07:07:35.763270 DeviceVref_Margin_A1==40
715 07:07:35.763672
716 07:07:35.764104
717 07:07:35.768440 channel==1
718 07:07:35.768870 RxClkDly_Margin_A0==98 ps 10
719 07:07:35.769272 TxDqDly_Margin_A0==88 ps 9
720 07:07:35.774005 RxClkDly_Margin_A1==98 ps 10
721 07:07:35.774447 TxDqDly_Margin_A1==88 ps 9
722 07:07:35.779620 TrainedVREFDQ_A0==77
723 07:07:35.780084 TrainedVREFDQ_A1==77
724 07:07:35.780497 VrefDac_Margin_A0==22
725 07:07:35.785215 DeviceVref_Margin_A0==37
726 07:07:35.785645 VrefDac_Margin_A1==24
727 07:07:35.790782 DeviceVref_Margin_A1==37
728 07:07:35.791217
729 07:07:35.791617 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 07:07:35.792042
731 07:07:35.824402 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000018 dram_vref_reg_value 0x 00000060
732 07:07:35.824907 2D training succeed
733 07:07:35.829959 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 07:07:35.835575 auto size-- 65535DDR cs0 size: 2048MB
735 07:07:35.836044 DDR cs1 size: 2048MB
736 07:07:35.841163 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 07:07:35.841602 cs0 DataBus test pass
738 07:07:35.846732 cs1 DataBus test pass
739 07:07:35.847172 cs0 AddrBus test pass
740 07:07:35.847575 cs1 AddrBus test pass
741 07:07:35.847970
742 07:07:35.852351 100bdlr_step_size ps== 420
743 07:07:35.852795 result report
744 07:07:35.857976 boot times 0Enable ddr reg access
745 07:07:35.863443 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 07:07:35.876846 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 07:07:36.450755 0.0;M3 CHK:0;cm4_sp_mode 0
748 07:07:36.451204 MVN_1=0x00000000
749 07:07:36.456204 MVN_2=0x00000000
750 07:07:36.461932 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 07:07:36.462420 OPS=0x10
752 07:07:36.462823 ring efuse init
753 07:07:36.463213 chipver efuse init
754 07:07:36.470287 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 07:07:36.470747 [0.018961 Inits done]
756 07:07:36.471146 secure task start!
757 07:07:36.477682 high task start!
758 07:07:36.478122 low task start!
759 07:07:36.478514 run into bl31
760 07:07:36.484354 NOTICE: BL31: v1.3(release):4fc40b1
761 07:07:36.492207 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 07:07:36.492648 NOTICE: BL31: G12A normal boot!
763 07:07:36.517999 NOTICE: BL31: BL33 decompress pass
764 07:07:36.523671 ERROR: Error initializing runtime service opteed_fast
765 07:07:37.756784
766 07:07:37.757412
767 07:07:37.765135 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 07:07:37.765604
769 07:07:37.766023 Model: Libre Computer AML-A311D-CC Alta
770 07:07:37.973498 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 07:07:37.998441 DRAM: 2 GiB (effective 3.8 GiB)
772 07:07:38.139838 Core: 408 devices, 31 uclasses, devicetree: separate
773 07:07:38.145881 WDT: Not starting watchdog@f0d0
774 07:07:38.177970 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 07:07:38.190488 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 07:07:38.195497 ** Bad device specification mmc 0 **
777 07:07:38.205778 Card did not respond to voltage select! : -110
778 07:07:38.213470 ** Bad device specification mmc 0 **
779 07:07:38.213946 Couldn't find partition mmc 0
780 07:07:38.221718 Card did not respond to voltage select! : -110
781 07:07:38.227208 ** Bad device specification mmc 0 **
782 07:07:38.227658 Couldn't find partition mmc 0
783 07:07:38.232291 Error: could not access storage.
784 07:07:38.575094 Net: eth0: ethernet@ff3f0000
785 07:07:38.575775 starting USB...
786 07:07:38.826688 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 07:07:38.827274 Starting the controller
788 07:07:38.833763 USB XHCI 1.10
789 07:07:40.993344 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
790 07:07:40.994014 bl2_stage_init 0x81
791 07:07:40.998854 hw id: 0x0000 - pwm id 0x01
792 07:07:40.999386 bl2_stage_init 0xc1
793 07:07:40.999846 bl2_stage_init 0x02
794 07:07:41.000353
795 07:07:41.005245 L0:00000000
796 07:07:41.005765 L1:20000703
797 07:07:41.006223 L2:00008067
798 07:07:41.006675 L3:14000000
799 07:07:41.007117 B2:00402000
800 07:07:41.010082 B1:e0f83180
801 07:07:41.010590
802 07:07:41.011043 TE: 58150
803 07:07:41.011491
804 07:07:41.015622 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 07:07:41.016183
806 07:07:41.016645 Board ID = 1
807 07:07:41.021242 Set A53 clk to 24M
808 07:07:41.021969 Set A73 clk to 24M
809 07:07:41.022434 Set clk81 to 24M
810 07:07:41.026995 A53 clk: 1200 MHz
811 07:07:41.027509 A73 clk: 1200 MHz
812 07:07:41.027962 CLK81: 166.6M
813 07:07:41.028451 smccc: 00012aab
814 07:07:41.032499 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 07:07:41.037996 board id: 1
816 07:07:41.043876 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 07:07:41.054485 fw parse done
818 07:07:41.060427 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 07:07:41.102987 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 07:07:41.113880 PIEI prepare done
821 07:07:41.114421 fastboot data load
822 07:07:41.114890 fastboot data verify
823 07:07:41.119586 verify result: 266
824 07:07:41.125198 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 07:07:41.125719 LPDDR4 probe
826 07:07:41.126176 ddr clk to 1584MHz
827 07:07:41.133311 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 07:07:41.170431
829 07:07:41.170969 dmc_version 0001
830 07:07:41.177104 Check phy result
831 07:07:41.182945 INFO : End of CA training
832 07:07:41.183457 INFO : End of initialization
833 07:07:41.188539 INFO : Training has run successfully!
834 07:07:41.189059 Check phy result
835 07:07:41.194208 INFO : End of initialization
836 07:07:41.194726 INFO : End of read enable training
837 07:07:41.199758 INFO : End of fine write leveling
838 07:07:41.205392 INFO : End of Write leveling coarse delay
839 07:07:41.205907 INFO : Training has run successfully!
840 07:07:41.206367 Check phy result
841 07:07:41.210981 INFO : End of initialization
842 07:07:41.211492 INFO : End of read dq deskew training
843 07:07:41.216582 INFO : End of MPR read delay center optimization
844 07:07:41.222210 INFO : End of write delay center optimization
845 07:07:41.227752 INFO : End of read delay center optimization
846 07:07:41.228305 INFO : End of max read latency training
847 07:07:41.233401 INFO : Training has run successfully!
848 07:07:41.233924 1D training succeed
849 07:07:41.242529 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 07:07:41.290171 Check phy result
851 07:07:41.290729 INFO : End of initialization
852 07:07:41.311943 INFO : End of 2D read delay Voltage center optimization
853 07:07:41.332133 INFO : End of 2D read delay Voltage center optimization
854 07:07:41.384288 INFO : End of 2D write delay Voltage center optimization
855 07:07:41.433579 INFO : End of 2D write delay Voltage center optimization
856 07:07:41.439315 INFO : Training has run successfully!
857 07:07:41.439830
858 07:07:41.440338 channel==0
859 07:07:41.444816 RxClkDly_Margin_A0==88 ps 9
860 07:07:41.445320 TxDqDly_Margin_A0==98 ps 10
861 07:07:41.448124 RxClkDly_Margin_A1==88 ps 9
862 07:07:41.448634 TxDqDly_Margin_A1==88 ps 9
863 07:07:41.453701 TrainedVREFDQ_A0==74
864 07:07:41.454217 TrainedVREFDQ_A1==74
865 07:07:41.454690 VrefDac_Margin_A0==25
866 07:07:41.459397 DeviceVref_Margin_A0==40
867 07:07:41.459939 VrefDac_Margin_A1==25
868 07:07:41.464950 DeviceVref_Margin_A1==40
869 07:07:41.465477
870 07:07:41.465912
871 07:07:41.466336 channel==1
872 07:07:41.466756 RxClkDly_Margin_A0==98 ps 10
873 07:07:41.468384 TxDqDly_Margin_A0==88 ps 9
874 07:07:41.473898 RxClkDly_Margin_A1==98 ps 10
875 07:07:41.474396 TxDqDly_Margin_A1==88 ps 9
876 07:07:41.474831 TrainedVREFDQ_A0==77
877 07:07:41.479568 TrainedVREFDQ_A1==77
878 07:07:41.480110 VrefDac_Margin_A0==22
879 07:07:41.485074 DeviceVref_Margin_A0==37
880 07:07:41.485579 VrefDac_Margin_A1==22
881 07:07:41.486010 DeviceVref_Margin_A1==37
882 07:07:41.486434
883 07:07:41.494242 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 07:07:41.494753
885 07:07:41.522326 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
886 07:07:41.522892 2D training succeed
887 07:07:41.527768 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 07:07:41.533286 auto size-- 65535DDR cs0 size: 2048MB
889 07:07:41.533792 DDR cs1 size: 2048MB
890 07:07:41.538952 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 07:07:41.539456 cs0 DataBus test pass
892 07:07:41.544482 cs1 DataBus test pass
893 07:07:41.544983 cs0 AddrBus test pass
894 07:07:41.545413 cs1 AddrBus test pass
895 07:07:41.550196
896 07:07:41.550697 100bdlr_step_size ps== 420
897 07:07:41.551138 result report
898 07:07:41.555716 boot times 0Enable ddr reg access
899 07:07:41.561924 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 07:07:41.575394 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 07:07:42.148970 0.0;M3 CHK:0;cm4_sp_mode 0
902 07:07:42.149646 MVN_1=0x00000000
903 07:07:42.154472 MVN_2=0x00000000
904 07:07:42.160280 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 07:07:42.160818 OPS=0x10
906 07:07:42.161279 ring efuse init
907 07:07:42.161727 chipver efuse init
908 07:07:42.165823 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 07:07:42.171403 [0.018960 Inits done]
910 07:07:42.171933 secure task start!
911 07:07:42.172439 high task start!
912 07:07:42.176057 low task start!
913 07:07:42.176589 run into bl31
914 07:07:42.182678 NOTICE: BL31: v1.3(release):4fc40b1
915 07:07:42.190466 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 07:07:42.191012 NOTICE: BL31: G12A normal boot!
917 07:07:42.215898 NOTICE: BL31: BL33 decompress pass
918 07:07:42.221567 ERROR: Error initializing runtime service opteed_fast
919 07:07:43.454372
920 07:07:43.454815
921 07:07:43.461773 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 07:07:43.462180
923 07:07:43.462412 Model: Libre Computer AML-A311D-CC Alta
924 07:07:43.671266 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 07:07:43.694617 DRAM: 2 GiB (effective 3.8 GiB)
926 07:07:43.837606 Core: 408 devices, 31 uclasses, devicetree: separate
927 07:07:43.843468 WDT: Not starting watchdog@f0d0
928 07:07:43.875673 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 07:07:43.888265 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 07:07:43.893091 ** Bad device specification mmc 0 **
931 07:07:43.903475 Card did not respond to voltage select! : -110
932 07:07:43.911083 ** Bad device specification mmc 0 **
933 07:07:43.911716 Couldn't find partition mmc 0
934 07:07:43.919412 Card did not respond to voltage select! : -110
935 07:07:43.924877 ** Bad device specification mmc 0 **
936 07:07:43.925482 Couldn't find partition mmc 0
937 07:07:43.929951 Error: could not access storage.
938 07:07:44.273585 Net: eth0: ethernet@ff3f0000
939 07:07:44.274258 starting USB...
940 07:07:44.525334 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 07:07:44.525925 Starting the controller
942 07:07:44.531301 USB XHCI 1.10
943 07:07:46.392843 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
944 07:07:46.393275 bl2_stage_init 0x81
945 07:07:46.398456 hw id: 0x0000 - pwm id 0x01
946 07:07:46.398796 bl2_stage_init 0xc1
947 07:07:46.399047 bl2_stage_init 0x02
948 07:07:46.399274
949 07:07:46.404009 L0:00000000
950 07:07:46.404363 L1:20000703
951 07:07:46.404594 L2:00008067
952 07:07:46.404828 L3:14000000
953 07:07:46.405061 B2:00402000
954 07:07:46.409698 B1:e0f83180
955 07:07:46.410042
956 07:07:46.410273 TE: 58150
957 07:07:46.410506
958 07:07:46.415183 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 07:07:46.415535
960 07:07:46.415776 Board ID = 1
961 07:07:46.420778 Set A53 clk to 24M
962 07:07:46.421125 Set A73 clk to 24M
963 07:07:46.421358 Set clk81 to 24M
964 07:07:46.426456 A53 clk: 1200 MHz
965 07:07:46.426797 A73 clk: 1200 MHz
966 07:07:46.427038 CLK81: 166.6M
967 07:07:46.427260 smccc: 00012aac
968 07:07:46.432001 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 07:07:46.437690 board id: 1
970 07:07:46.443403 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 07:07:46.454048 fw parse done
972 07:07:46.460039 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 07:07:46.501832 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 07:07:46.513559 PIEI prepare done
975 07:07:46.514110 fastboot data load
976 07:07:46.514527 fastboot data verify
977 07:07:46.519147 verify result: 266
978 07:07:46.524818 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 07:07:46.525345 LPDDR4 probe
980 07:07:46.525776 ddr clk to 1584MHz
981 07:07:46.532953 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 07:07:46.569262
983 07:07:46.569823 dmc_version 0001
984 07:07:46.576856 Check phy result
985 07:07:46.582562 INFO : End of CA training
986 07:07:46.583025 INFO : End of initialization
987 07:07:46.588272 INFO : Training has run successfully!
988 07:07:46.588815 Check phy result
989 07:07:46.593942 INFO : End of initialization
990 07:07:46.594469 INFO : End of read enable training
991 07:07:46.597218 INFO : End of fine write leveling
992 07:07:46.602967 INFO : End of Write leveling coarse delay
993 07:07:46.608319 INFO : Training has run successfully!
994 07:07:46.608849 Check phy result
995 07:07:46.609280 INFO : End of initialization
996 07:07:46.614007 INFO : End of read dq deskew training
997 07:07:46.617569 INFO : End of MPR read delay center optimization
998 07:07:46.623133 INFO : End of write delay center optimization
999 07:07:46.628601 INFO : End of read delay center optimization
1000 07:07:46.629097 INFO : End of max read latency training
1001 07:07:46.634085 INFO : Training has run successfully!
1002 07:07:46.634607 1D training succeed
1003 07:07:46.642200 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 07:07:46.689821 Check phy result
1005 07:07:46.690381 INFO : End of initialization
1006 07:07:46.712369 INFO : End of 2D read delay Voltage center optimization
1007 07:07:46.731667 INFO : End of 2D read delay Voltage center optimization
1008 07:07:46.784271 INFO : End of 2D write delay Voltage center optimization
1009 07:07:46.833999 INFO : End of 2D write delay Voltage center optimization
1010 07:07:46.839606 INFO : Training has run successfully!
1011 07:07:46.840146
1012 07:07:46.840580 channel==0
1013 07:07:46.845110 RxClkDly_Margin_A0==88 ps 9
1014 07:07:46.845644 TxDqDly_Margin_A0==108 ps 11
1015 07:07:46.850759 RxClkDly_Margin_A1==88 ps 9
1016 07:07:46.851232 TxDqDly_Margin_A1==98 ps 10
1017 07:07:46.851635 TrainedVREFDQ_A0==74
1018 07:07:46.856296 TrainedVREFDQ_A1==74
1019 07:07:46.856738 VrefDac_Margin_A0==24
1020 07:07:46.861881 DeviceVref_Margin_A0==40
1021 07:07:46.862401 VrefDac_Margin_A1==24
1022 07:07:46.862804 DeviceVref_Margin_A1==40
1023 07:07:46.863196
1024 07:07:46.863585
1025 07:07:46.867503 channel==1
1026 07:07:46.867956 RxClkDly_Margin_A0==98 ps 10
1027 07:07:46.868399 TxDqDly_Margin_A0==88 ps 9
1028 07:07:46.873066 RxClkDly_Margin_A1==88 ps 9
1029 07:07:46.873569 TxDqDly_Margin_A1==88 ps 9
1030 07:07:46.878834 TrainedVREFDQ_A0==76
1031 07:07:46.879377 TrainedVREFDQ_A1==77
1032 07:07:46.879809 VrefDac_Margin_A0==22
1033 07:07:46.884343 DeviceVref_Margin_A0==38
1034 07:07:46.884827 VrefDac_Margin_A1==24
1035 07:07:46.889940 DeviceVref_Margin_A1==37
1036 07:07:46.890452
1037 07:07:46.890905 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 07:07:46.891322
1039 07:07:46.923579 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1040 07:07:46.924191 2D training succeed
1041 07:07:46.929106 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 07:07:46.934662 auto size-- 65535DDR cs0 size: 2048MB
1043 07:07:46.935126 DDR cs1 size: 2048MB
1044 07:07:46.940271 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 07:07:46.940734 cs0 DataBus test pass
1046 07:07:46.945895 cs1 DataBus test pass
1047 07:07:46.946355 cs0 AddrBus test pass
1048 07:07:46.946772 cs1 AddrBus test pass
1049 07:07:46.947180
1050 07:07:46.951451 100bdlr_step_size ps== 420
1051 07:07:46.951921 result report
1052 07:07:46.957042 boot times 0Enable ddr reg access
1053 07:07:46.961465 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 07:07:46.975921 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 07:07:47.549690 0.0;M3 CHK:0;cm4_sp_mode 0
1056 07:07:47.550277 MVN_1=0x00000000
1057 07:07:47.555127 MVN_2=0x00000000
1058 07:07:47.560921 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 07:07:47.561381 OPS=0x10
1060 07:07:47.561801 ring efuse init
1061 07:07:47.562206 chipver efuse init
1062 07:07:47.569191 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 07:07:47.569661 [0.018961 Inits done]
1064 07:07:47.570073 secure task start!
1065 07:07:47.576691 high task start!
1066 07:07:47.577150 low task start!
1067 07:07:47.577563 run into bl31
1068 07:07:47.583320 NOTICE: BL31: v1.3(release):4fc40b1
1069 07:07:47.590197 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 07:07:47.590667 NOTICE: BL31: G12A normal boot!
1071 07:07:47.616495 NOTICE: BL31: BL33 decompress pass
1072 07:07:47.622171 ERROR: Error initializing runtime service opteed_fast
1073 07:07:48.855228
1074 07:07:48.855814
1075 07:07:48.863475 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 07:07:48.863947
1077 07:07:48.864398 Model: Libre Computer AML-A311D-CC Alta
1078 07:07:49.071819 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 07:07:49.095236 DRAM: 2 GiB (effective 3.8 GiB)
1080 07:07:49.238186 Core: 408 devices, 31 uclasses, devicetree: separate
1081 07:07:49.244169 WDT: Not starting watchdog@f0d0
1082 07:07:49.276386 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 07:07:49.288842 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 07:07:49.293839 ** Bad device specification mmc 0 **
1085 07:07:49.304164 Card did not respond to voltage select! : -110
1086 07:07:49.311817 ** Bad device specification mmc 0 **
1087 07:07:49.312297 Couldn't find partition mmc 0
1088 07:07:49.320173 Card did not respond to voltage select! : -110
1089 07:07:49.325652 ** Bad device specification mmc 0 **
1090 07:07:49.326118 Couldn't find partition mmc 0
1091 07:07:49.330702 Error: could not access storage.
1092 07:07:49.673325 Net: eth0: ethernet@ff3f0000
1093 07:07:49.673859 starting USB...
1094 07:07:49.926065 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 07:07:49.926571 Starting the controller
1096 07:07:49.933042 USB XHCI 1.10
1097 07:07:51.487180 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 07:07:51.495401 scanning usb for storage devices... 0 Storage Device(s) found
1100 07:07:51.547016 Hit any key to stop autoboot: 1
1101 07:07:51.547817 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1102 07:07:51.548436 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1103 07:07:51.548900 Setting prompt string to ['=>']
1104 07:07:51.549367 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1105 07:07:51.562837 0
1106 07:07:51.563682 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 07:07:51.564197 Sending with 10 millisecond of delay
1109 07:07:52.699665 => setenv autoload no
1110 07:07:52.710645 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1111 07:07:52.715678 setenv autoload no
1112 07:07:52.716675 Sending with 10 millisecond of delay
1114 07:07:54.513314 => setenv initrd_high 0xffffffff
1115 07:07:54.524111 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1116 07:07:54.524951 setenv initrd_high 0xffffffff
1117 07:07:54.525662 Sending with 10 millisecond of delay
1119 07:07:56.141898 => setenv fdt_high 0xffffffff
1120 07:07:56.152676 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1121 07:07:56.153503 setenv fdt_high 0xffffffff
1122 07:07:56.154210 Sending with 10 millisecond of delay
1124 07:07:56.446030 => dhcp
1125 07:07:56.456779 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1126 07:07:56.457608 dhcp
1127 07:07:56.458042 Speed: 1000, full duplex
1128 07:07:56.458451 BOOTP broadcast 1
1129 07:07:56.704834 BOOTP broadcast 2
1130 07:07:57.205819 BOOTP broadcast 3
1131 07:07:57.219316 DHCP client bound to address 192.168.6.33 (762 ms)
1132 07:07:57.220085 Sending with 10 millisecond of delay
1134 07:07:58.896816 => setenv serverip 192.168.6.2
1135 07:07:58.907598 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 07:07:58.908441 setenv serverip 192.168.6.2
1137 07:07:58.909150 Sending with 10 millisecond of delay
1139 07:08:02.633337 => tftpboot 0x01080000 714873/tftp-deploy-wnkbayv_/kernel/uImage
1140 07:08:02.644819 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 07:08:02.645795 tftpboot 0x01080000 714873/tftp-deploy-wnkbayv_/kernel/uImage
1142 07:08:02.646267 Speed: 1000, full duplex
1143 07:08:02.646738 Using ethernet@ff3f0000 device
1144 07:08:02.647266 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1145 07:08:02.652143 Filename '714873/tftp-deploy-wnkbayv_/kernel/uImage'.
1146 07:08:02.656084 Load address: 0x1080000
1147 07:08:05.467429 Loading: *################################################## 43.2 MiB
1148 07:08:05.468233 15.4 MiB/s
1149 07:08:05.468844 done
1150 07:08:05.471825 Bytes transferred = 45308480 (2b35a40 hex)
1151 07:08:05.472793 Sending with 10 millisecond of delay
1153 07:08:10.163197 => tftpboot 0x08000000 714873/tftp-deploy-wnkbayv_/ramdisk/ramdisk.cpio.gz.uboot
1154 07:08:10.173977 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1155 07:08:10.174856 tftpboot 0x08000000 714873/tftp-deploy-wnkbayv_/ramdisk/ramdisk.cpio.gz.uboot
1156 07:08:10.175298 Speed: 1000, full duplex
1157 07:08:10.175726 Using ethernet@ff3f0000 device
1158 07:08:10.176885 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1159 07:08:10.188535 Filename '714873/tftp-deploy-wnkbayv_/ramdisk/ramdisk.cpio.gz.uboot'.
1160 07:08:10.189073 Load address: 0x8000000
1161 07:08:14.149929 Loading: *##################### UDP wrong checksum 000000ff 0000f9a6
1162 07:08:14.166356 UDP wrong checksum 000000ff 00009399
1163 07:08:16.706858 T ############################ UDP wrong checksum 00000005 0000a318
1164 07:08:21.708257 T UDP wrong checksum 00000005 0000a318
1165 07:08:22.397813 UDP wrong checksum 000000ff 000067d4
1166 07:08:22.413109 UDP wrong checksum 000000ff 0000f7c6
1167 07:08:31.710009 T T UDP wrong checksum 00000005 0000a318
1168 07:08:51.713119 T T T UDP wrong checksum 00000005 0000a318
1169 07:09:06.719195 T T T
1170 07:09:06.719640 Retry count exceeded; starting again
1172 07:09:06.721204 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1175 07:09:06.722522 end: 2.4 uboot-commands (duration 00:01:52) [common]
1177 07:09:06.723336 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 07:09:06.724256 end: 2 uboot-action (duration 00:01:52) [common]
1181 07:09:06.725135 Cleaning after the job
1182 07:09:06.725489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/ramdisk
1183 07:09:06.726320 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/kernel
1184 07:09:06.751184 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/dtb
1185 07:09:06.752426 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/nfsrootfs
1186 07:09:07.007075 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714873/tftp-deploy-wnkbayv_/modules
1187 07:09:07.027103 start: 4.1 power-off (timeout 00:00:30) [common]
1188 07:09:07.028611 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 07:09:07.062338 >> OK - accepted request
1190 07:09:07.064562 Returned 0 in 0 seconds
1191 07:09:07.165526 end: 4.1 power-off (duration 00:00:00) [common]
1193 07:09:07.166581 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 07:09:07.167331 Listened to connection for namespace 'common' for up to 1s
1195 07:09:08.168172 Finalising connection for namespace 'common'
1196 07:09:08.168659 Disconnecting from shell: Finalise
1197 07:09:08.168933 =>
1198 07:09:08.269619 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 07:09:08.270095 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714873
1200 07:09:11.339773 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714873
1201 07:09:11.340896 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.