Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 07:02:11.471690 lava-dispatcher, installed at version: 2024.01
2 07:02:11.472537 start: 0 validate
3 07:02:11.473003 Start time: 2024-09-06 07:02:11.472973+00:00 (UTC)
4 07:02:11.473554 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 07:02:11.474074 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 07:02:11.518381 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 07:02:11.518935 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 07:02:11.547669 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 07:02:11.548320 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 07:02:11.577363 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 07:02:11.577826 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 07:02:11.607134 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 07:02:11.607597 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-183-gb831f83e40a24%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 07:02:11.646137 validate duration: 0.17
16 07:02:11.646956 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 07:02:11.647279 start: 1.1 download-retry (timeout 00:10:00) [common]
18 07:02:11.647567 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 07:02:11.648164 Not decompressing ramdisk as can be used compressed.
20 07:02:11.648618 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 07:02:11.648887 saving as /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/ramdisk/initrd.cpio.gz
22 07:02:11.649158 total size: 5628140 (5 MB)
23 07:02:11.684342 progress 0 % (0 MB)
24 07:02:11.692501 progress 5 % (0 MB)
25 07:02:11.700098 progress 10 % (0 MB)
26 07:02:11.706951 progress 15 % (0 MB)
27 07:02:11.711492 progress 20 % (1 MB)
28 07:02:11.715078 progress 25 % (1 MB)
29 07:02:11.719001 progress 30 % (1 MB)
30 07:02:11.722938 progress 35 % (1 MB)
31 07:02:11.726513 progress 40 % (2 MB)
32 07:02:11.730430 progress 45 % (2 MB)
33 07:02:11.734003 progress 50 % (2 MB)
34 07:02:11.737921 progress 55 % (2 MB)
35 07:02:11.741863 progress 60 % (3 MB)
36 07:02:11.745402 progress 65 % (3 MB)
37 07:02:11.749342 progress 70 % (3 MB)
38 07:02:11.752822 progress 75 % (4 MB)
39 07:02:11.756583 progress 80 % (4 MB)
40 07:02:11.759803 progress 85 % (4 MB)
41 07:02:11.763472 progress 90 % (4 MB)
42 07:02:11.767076 progress 95 % (5 MB)
43 07:02:11.770355 progress 100 % (5 MB)
44 07:02:11.771011 5 MB downloaded in 0.12 s (44.06 MB/s)
45 07:02:11.771582 end: 1.1.1 http-download (duration 00:00:00) [common]
47 07:02:11.772511 end: 1.1 download-retry (duration 00:00:00) [common]
48 07:02:11.772813 start: 1.2 download-retry (timeout 00:10:00) [common]
49 07:02:11.773087 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 07:02:11.773568 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/kernel/Image
51 07:02:11.773826 saving as /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/kernel/Image
52 07:02:11.774039 total size: 45308416 (43 MB)
53 07:02:11.774251 No compression specified
54 07:02:11.812575 progress 0 % (0 MB)
55 07:02:11.840509 progress 5 % (2 MB)
56 07:02:11.867851 progress 10 % (4 MB)
57 07:02:11.894467 progress 15 % (6 MB)
58 07:02:11.921361 progress 20 % (8 MB)
59 07:02:11.948019 progress 25 % (10 MB)
60 07:02:11.974605 progress 30 % (12 MB)
61 07:02:12.003620 progress 35 % (15 MB)
62 07:02:12.030387 progress 40 % (17 MB)
63 07:02:12.056894 progress 45 % (19 MB)
64 07:02:12.083625 progress 50 % (21 MB)
65 07:02:12.110261 progress 55 % (23 MB)
66 07:02:12.137347 progress 60 % (25 MB)
67 07:02:12.164573 progress 65 % (28 MB)
68 07:02:12.191762 progress 70 % (30 MB)
69 07:02:12.218477 progress 75 % (32 MB)
70 07:02:12.245155 progress 80 % (34 MB)
71 07:02:12.271972 progress 85 % (36 MB)
72 07:02:12.299007 progress 90 % (38 MB)
73 07:02:12.325961 progress 95 % (41 MB)
74 07:02:12.351701 progress 100 % (43 MB)
75 07:02:12.352417 43 MB downloaded in 0.58 s (74.71 MB/s)
76 07:02:12.352918 end: 1.2.1 http-download (duration 00:00:01) [common]
78 07:02:12.353741 end: 1.2 download-retry (duration 00:00:01) [common]
79 07:02:12.354017 start: 1.3 download-retry (timeout 00:09:59) [common]
80 07:02:12.354286 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 07:02:12.354759 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 07:02:12.355046 saving as /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 07:02:12.355262 total size: 53173 (0 MB)
84 07:02:12.355471 No compression specified
85 07:02:12.398043 progress 61 % (0 MB)
86 07:02:12.398869 progress 100 % (0 MB)
87 07:02:12.399405 0 MB downloaded in 0.04 s (1.15 MB/s)
88 07:02:12.399891 end: 1.3.1 http-download (duration 00:00:00) [common]
90 07:02:12.400748 end: 1.3 download-retry (duration 00:00:00) [common]
91 07:02:12.401014 start: 1.4 download-retry (timeout 00:09:59) [common]
92 07:02:12.401279 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 07:02:12.401737 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 07:02:12.401990 saving as /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/nfsrootfs/full.rootfs.tar
95 07:02:12.402199 total size: 474398908 (452 MB)
96 07:02:12.402410 Using unxz to decompress xz
97 07:02:12.434820 progress 0 % (0 MB)
98 07:02:13.516127 progress 5 % (22 MB)
99 07:02:14.987760 progress 10 % (45 MB)
100 07:02:15.426831 progress 15 % (67 MB)
101 07:02:16.294774 progress 20 % (90 MB)
102 07:02:16.818061 progress 25 % (113 MB)
103 07:02:17.172408 progress 30 % (135 MB)
104 07:02:17.775068 progress 35 % (158 MB)
105 07:02:18.695078 progress 40 % (181 MB)
106 07:02:19.557991 progress 45 % (203 MB)
107 07:02:20.202304 progress 50 % (226 MB)
108 07:02:20.842191 progress 55 % (248 MB)
109 07:02:22.057703 progress 60 % (271 MB)
110 07:02:23.481124 progress 65 % (294 MB)
111 07:02:25.145768 progress 70 % (316 MB)
112 07:02:28.337113 progress 75 % (339 MB)
113 07:02:30.781647 progress 80 % (361 MB)
114 07:02:33.699698 progress 85 % (384 MB)
115 07:02:36.825992 progress 90 % (407 MB)
116 07:02:40.063416 progress 95 % (429 MB)
117 07:02:43.175245 progress 100 % (452 MB)
118 07:02:43.188073 452 MB downloaded in 30.79 s (14.70 MB/s)
119 07:02:43.188928 end: 1.4.1 http-download (duration 00:00:31) [common]
121 07:02:43.190498 end: 1.4 download-retry (duration 00:00:31) [common]
122 07:02:43.191010 start: 1.5 download-retry (timeout 00:09:28) [common]
123 07:02:43.191516 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 07:02:43.192340 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-183-gb831f83e40a24/arm64/defconfig/gcc-12/modules.tar.xz
125 07:02:43.192805 saving as /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/modules/modules.tar
126 07:02:43.193206 total size: 11502724 (10 MB)
127 07:02:43.193619 Using unxz to decompress xz
128 07:02:43.234150 progress 0 % (0 MB)
129 07:02:43.302781 progress 5 % (0 MB)
130 07:02:43.378932 progress 10 % (1 MB)
131 07:02:43.460849 progress 15 % (1 MB)
132 07:02:43.540223 progress 20 % (2 MB)
133 07:02:43.615466 progress 25 % (2 MB)
134 07:02:43.697333 progress 30 % (3 MB)
135 07:02:43.772768 progress 35 % (3 MB)
136 07:02:43.850070 progress 40 % (4 MB)
137 07:02:43.920829 progress 45 % (4 MB)
138 07:02:43.997628 progress 50 % (5 MB)
139 07:02:44.072362 progress 55 % (6 MB)
140 07:02:44.150892 progress 60 % (6 MB)
141 07:02:44.235589 progress 65 % (7 MB)
142 07:02:44.311772 progress 70 % (7 MB)
143 07:02:44.406001 progress 75 % (8 MB)
144 07:02:44.494220 progress 80 % (8 MB)
145 07:02:44.574052 progress 85 % (9 MB)
146 07:02:44.643889 progress 90 % (9 MB)
147 07:02:44.718726 progress 95 % (10 MB)
148 07:02:44.793588 progress 100 % (10 MB)
149 07:02:44.803391 10 MB downloaded in 1.61 s (6.81 MB/s)
150 07:02:44.804055 end: 1.5.1 http-download (duration 00:00:02) [common]
152 07:02:44.805747 end: 1.5 download-retry (duration 00:00:02) [common]
153 07:02:44.806267 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 07:02:44.806784 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 07:03:00.348410 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/714841/extract-nfsrootfs-89w_7ax1
156 07:03:00.349023 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 07:03:00.349347 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 07:03:00.350005 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y
159 07:03:00.350474 makedir: /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin
160 07:03:00.350862 makedir: /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/tests
161 07:03:00.351227 makedir: /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/results
162 07:03:00.351623 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-add-keys
163 07:03:00.352238 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-add-sources
164 07:03:00.352750 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-background-process-start
165 07:03:00.353255 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-background-process-stop
166 07:03:00.353783 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-common-functions
167 07:03:00.354267 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-echo-ipv4
168 07:03:00.354730 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-install-packages
169 07:03:00.355197 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-installed-packages
170 07:03:00.355654 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-os-build
171 07:03:00.356147 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-probe-channel
172 07:03:00.356625 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-probe-ip
173 07:03:00.357109 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-target-ip
174 07:03:00.357577 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-target-mac
175 07:03:00.358038 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-target-storage
176 07:03:00.358504 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-test-case
177 07:03:00.358962 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-test-event
178 07:03:00.359413 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-test-feedback
179 07:03:00.359890 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-test-raise
180 07:03:00.360455 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-test-reference
181 07:03:00.360968 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-test-runner
182 07:03:00.361458 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-test-set
183 07:03:00.361919 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-test-shell
184 07:03:00.362384 Updating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-install-packages (oe)
185 07:03:00.362904 Updating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/bin/lava-installed-packages (oe)
186 07:03:00.363335 Creating /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/environment
187 07:03:00.363691 LAVA metadata
188 07:03:00.363946 - LAVA_JOB_ID=714841
189 07:03:00.364192 - LAVA_DISPATCHER_IP=192.168.6.2
190 07:03:00.364553 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 07:03:00.365489 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 07:03:00.365799 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 07:03:00.366007 skipped lava-vland-overlay
194 07:03:00.366249 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 07:03:00.366503 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 07:03:00.366721 skipped lava-multinode-overlay
197 07:03:00.366963 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 07:03:00.367213 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 07:03:00.367459 Loading test definitions
200 07:03:00.367731 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 07:03:00.367949 Using /lava-714841 at stage 0
202 07:03:00.369127 uuid=714841_1.6.2.4.1 testdef=None
203 07:03:00.369432 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 07:03:00.369692 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 07:03:00.371375 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 07:03:00.372189 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 07:03:00.374333 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 07:03:00.375160 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 07:03:00.377261 runner path: /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 714841_1.6.2.4.1
212 07:03:00.377815 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 07:03:00.378572 Creating lava-test-runner.conf files
215 07:03:00.378772 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/714841/lava-overlay-d6lvki3y/lava-714841/0 for stage 0
216 07:03:00.379096 - 0_v4l2-decoder-conformance-vp9
217 07:03:00.379427 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 07:03:00.379698 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 07:03:00.400793 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 07:03:00.401183 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 07:03:00.401441 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 07:03:00.401707 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 07:03:00.401970 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 07:03:01.094842 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 07:03:01.095312 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 07:03:01.095561 extracting modules file /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714841/extract-nfsrootfs-89w_7ax1
227 07:03:02.421584 extracting modules file /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/714841/extract-overlay-ramdisk-vzwh8qxs/ramdisk
228 07:03:03.793274 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 07:03:03.793746 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 07:03:03.794025 [common] Applying overlay to NFS
231 07:03:03.794241 [common] Applying overlay /var/lib/lava/dispatcher/tmp/714841/compress-overlay-dxriq_qw/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/714841/extract-nfsrootfs-89w_7ax1
232 07:03:03.823061 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 07:03:03.823451 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 07:03:03.823723 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 07:03:03.823950 Converting downloaded kernel to a uImage
236 07:03:03.824295 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/kernel/Image /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/kernel/uImage
237 07:03:04.328363 output: Image Name:
238 07:03:04.328777 output: Created: Fri Sep 6 07:03:03 2024
239 07:03:04.328987 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 07:03:04.329191 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
241 07:03:04.329392 output: Load Address: 01080000
242 07:03:04.329592 output: Entry Point: 01080000
243 07:03:04.329788 output:
244 07:03:04.330124 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 07:03:04.330389 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 07:03:04.330654 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 07:03:04.330910 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 07:03:04.331167 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 07:03:04.331430 Building ramdisk /var/lib/lava/dispatcher/tmp/714841/extract-overlay-ramdisk-vzwh8qxs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/714841/extract-overlay-ramdisk-vzwh8qxs/ramdisk
250 07:03:06.445063 >> 165160 blocks
251 07:03:15.335898 Adding RAMdisk u-boot header.
252 07:03:15.336646 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/714841/extract-overlay-ramdisk-vzwh8qxs/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/714841/extract-overlay-ramdisk-vzwh8qxs/ramdisk.cpio.gz.uboot
253 07:03:15.594767 output: Image Name:
254 07:03:15.595195 output: Created: Fri Sep 6 07:03:15 2024
255 07:03:15.595406 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 07:03:15.595613 output: Data Size: 23258119 Bytes = 22713.01 KiB = 22.18 MiB
257 07:03:15.595816 output: Load Address: 00000000
258 07:03:15.596091 output: Entry Point: 00000000
259 07:03:15.596540 output:
260 07:03:15.597741 rename /var/lib/lava/dispatcher/tmp/714841/extract-overlay-ramdisk-vzwh8qxs/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/ramdisk/ramdisk.cpio.gz.uboot
261 07:03:15.598522 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 07:03:15.599124 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 07:03:15.599755 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 07:03:15.600309 No LXC device requested
265 07:03:15.600868 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 07:03:15.601431 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 07:03:15.601979 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 07:03:15.602434 Checking files for TFTP limit of 4294967296 bytes.
269 07:03:15.605398 end: 1 tftp-deploy (duration 00:01:04) [common]
270 07:03:15.606041 start: 2 uboot-action (timeout 00:05:00) [common]
271 07:03:15.606614 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 07:03:15.607157 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 07:03:15.607709 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 07:03:15.608327 Using kernel file from prepare-kernel: 714841/tftp-deploy-jutn8jb4/kernel/uImage
275 07:03:15.609023 substitutions:
276 07:03:15.609470 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 07:03:15.609913 - {DTB_ADDR}: 0x01070000
278 07:03:15.610352 - {DTB}: 714841/tftp-deploy-jutn8jb4/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 07:03:15.610793 - {INITRD}: 714841/tftp-deploy-jutn8jb4/ramdisk/ramdisk.cpio.gz.uboot
280 07:03:15.611232 - {KERNEL_ADDR}: 0x01080000
281 07:03:15.611664 - {KERNEL}: 714841/tftp-deploy-jutn8jb4/kernel/uImage
282 07:03:15.612134 - {LAVA_MAC}: None
283 07:03:15.612616 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/714841/extract-nfsrootfs-89w_7ax1
284 07:03:15.613057 - {NFS_SERVER_IP}: 192.168.6.2
285 07:03:15.613486 - {PRESEED_CONFIG}: None
286 07:03:15.613914 - {PRESEED_LOCAL}: None
287 07:03:15.614340 - {RAMDISK_ADDR}: 0x08000000
288 07:03:15.614762 - {RAMDISK}: 714841/tftp-deploy-jutn8jb4/ramdisk/ramdisk.cpio.gz.uboot
289 07:03:15.615191 - {ROOT_PART}: None
290 07:03:15.615623 - {ROOT}: None
291 07:03:15.616106 - {SERVER_IP}: 192.168.6.2
292 07:03:15.616549 - {TEE_ADDR}: 0x83000000
293 07:03:15.616977 - {TEE}: None
294 07:03:15.617410 Parsed boot commands:
295 07:03:15.617825 - setenv autoload no
296 07:03:15.618252 - setenv initrd_high 0xffffffff
297 07:03:15.618675 - setenv fdt_high 0xffffffff
298 07:03:15.619098 - dhcp
299 07:03:15.619522 - setenv serverip 192.168.6.2
300 07:03:15.619945 - tftpboot 0x01080000 714841/tftp-deploy-jutn8jb4/kernel/uImage
301 07:03:15.620408 - tftpboot 0x08000000 714841/tftp-deploy-jutn8jb4/ramdisk/ramdisk.cpio.gz.uboot
302 07:03:15.620834 - tftpboot 0x01070000 714841/tftp-deploy-jutn8jb4/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 07:03:15.621260 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/714841/extract-nfsrootfs-89w_7ax1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 07:03:15.621700 - bootm 0x01080000 0x08000000 0x01070000
305 07:03:15.622252 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 07:03:15.623890 start: 2.3 connect-device (timeout 00:05:00) [common]
308 07:03:15.624402 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 07:03:15.639917 Setting prompt string to ['lava-test: # ']
310 07:03:15.641587 end: 2.3 connect-device (duration 00:00:00) [common]
311 07:03:15.642251 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 07:03:15.642861 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 07:03:15.643440 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 07:03:15.644720 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 07:03:15.682582 >> OK - accepted request
316 07:03:15.685017 Returned 0 in 0 seconds
317 07:03:15.786246 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 07:03:15.788091 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 07:03:15.788735 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 07:03:15.789320 Setting prompt string to ['Hit any key to stop autoboot']
322 07:03:15.789837 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 07:03:15.791592 Trying 192.168.56.21...
324 07:03:15.792175 Connected to conserv1.
325 07:03:15.792650 Escape character is '^]'.
326 07:03:15.793107
327 07:03:15.793571 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 07:03:15.794031
329 07:03:22.667819 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 07:03:22.668543 bl2_stage_init 0x01
331 07:03:22.669007 bl2_stage_init 0x81
332 07:03:22.673390 hw id: 0x0000 - pwm id 0x01
333 07:03:22.673884 bl2_stage_init 0xc1
334 07:03:22.679046 bl2_stage_init 0x02
335 07:03:22.679525
336 07:03:22.680004 L0:00000000
337 07:03:22.680470 L1:00000703
338 07:03:22.680906 L2:00008067
339 07:03:22.681343 L3:15000000
340 07:03:22.684672 S1:00000000
341 07:03:22.685160 B2:20282000
342 07:03:22.685608 B1:a0f83180
343 07:03:22.686049
344 07:03:22.686489 TE: 68957
345 07:03:22.686927
346 07:03:22.690126 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 07:03:22.690603
348 07:03:22.695742 Board ID = 1
349 07:03:22.696243 Set cpu clk to 24M
350 07:03:22.696685 Set clk81 to 24M
351 07:03:22.701342 Use GP1_pll as DSU clk.
352 07:03:22.701810 DSU clk: 1200 Mhz
353 07:03:22.702246 CPU clk: 1200 MHz
354 07:03:22.706890 Set clk81 to 166.6M
355 07:03:22.712570 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 07:03:22.713036 board id: 1
357 07:03:22.718965 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 07:03:22.730687 fw parse done
359 07:03:22.736669 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 07:03:22.779726 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 07:03:22.790841 PIEI prepare done
362 07:03:22.791320 fastboot data load
363 07:03:22.791765 fastboot data verify
364 07:03:22.796421 verify result: 266
365 07:03:22.801982 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 07:03:22.802449 LPDDR4 probe
367 07:03:22.802880 ddr clk to 1584MHz
368 07:03:22.809932 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 07:03:22.847168
370 07:03:22.847649 dmc_version 0001
371 07:03:22.854503 Check phy result
372 07:03:22.860725 INFO : End of CA training
373 07:03:22.861250 INFO : End of initialization
374 07:03:22.866430 INFO : Training has run successfully!
375 07:03:22.866981 Check phy result
376 07:03:22.871922 INFO : End of initialization
377 07:03:22.872446 INFO : End of read enable training
378 07:03:22.875315 INFO : End of fine write leveling
379 07:03:22.880867 INFO : End of Write leveling coarse delay
380 07:03:22.886459 INFO : Training has run successfully!
381 07:03:22.886944 Check phy result
382 07:03:22.887397 INFO : End of initialization
383 07:03:22.892084 INFO : End of read dq deskew training
384 07:03:22.895468 INFO : End of MPR read delay center optimization
385 07:03:22.900973 INFO : End of write delay center optimization
386 07:03:22.906589 INFO : End of read delay center optimization
387 07:03:22.907078 INFO : End of max read latency training
388 07:03:22.912217 INFO : Training has run successfully!
389 07:03:22.912699 1D training succeed
390 07:03:22.919667 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 07:03:22.967867 Check phy result
392 07:03:22.968460 INFO : End of initialization
393 07:03:22.995703 INFO : End of 2D read delay Voltage center optimization
394 07:03:23.019739 INFO : End of 2D read delay Voltage center optimization
395 07:03:23.076014 INFO : End of 2D write delay Voltage center optimization
396 07:03:23.130932 INFO : End of 2D write delay Voltage center optimization
397 07:03:23.136442 INFO : Training has run successfully!
398 07:03:23.136729
399 07:03:23.136951 channel==0
400 07:03:23.142077 RxClkDly_Margin_A0==78 ps 8
401 07:03:23.142514 TxDqDly_Margin_A0==98 ps 10
402 07:03:23.145359 RxClkDly_Margin_A1==88 ps 9
403 07:03:23.145775 TxDqDly_Margin_A1==88 ps 9
404 07:03:23.150984 TrainedVREFDQ_A0==74
405 07:03:23.151268 TrainedVREFDQ_A1==74
406 07:03:23.151484 VrefDac_Margin_A0==24
407 07:03:23.156563 DeviceVref_Margin_A0==40
408 07:03:23.156830 VrefDac_Margin_A1==22
409 07:03:23.162264 DeviceVref_Margin_A1==40
410 07:03:23.162533
411 07:03:23.162745
412 07:03:23.162955 channel==1
413 07:03:23.163161 RxClkDly_Margin_A0==78 ps 8
414 07:03:23.165528 TxDqDly_Margin_A0==98 ps 10
415 07:03:23.171121 RxClkDly_Margin_A1==78 ps 8
416 07:03:23.171404 TxDqDly_Margin_A1==78 ps 8
417 07:03:23.171620 TrainedVREFDQ_A0==78
418 07:03:23.176743 TrainedVREFDQ_A1==75
419 07:03:23.177245 VrefDac_Margin_A0==22
420 07:03:23.182368 DeviceVref_Margin_A0==36
421 07:03:23.182846 VrefDac_Margin_A1==22
422 07:03:23.183284 DeviceVref_Margin_A1==39
423 07:03:23.183715
424 07:03:23.191351 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 07:03:23.191823
426 07:03:23.219376 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000061
427 07:03:23.219956 2D training succeed
428 07:03:23.224904 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 07:03:23.230505 auto size-- 65535DDR cs0 size: 2048MB
430 07:03:23.230972 DDR cs1 size: 2048MB
431 07:03:23.236101 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 07:03:23.236574 cs0 DataBus test pass
433 07:03:23.241699 cs1 DataBus test pass
434 07:03:23.242162 cs0 AddrBus test pass
435 07:03:23.247349 cs1 AddrBus test pass
436 07:03:23.247815
437 07:03:23.248296 100bdlr_step_size ps== 471
438 07:03:23.248744 result report
439 07:03:23.252881 boot times 0Enable ddr reg access
440 07:03:23.258706 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 07:03:23.272623 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 07:03:23.931868 bl2z: ptr: 05129330, size: 00001e40
443 07:03:23.940081 0.0;M3 CHK:0;cm4_sp_mode 0
444 07:03:23.940620 MVN_1=0x00000000
445 07:03:23.941087 MVN_2=0x00000000
446 07:03:23.951568 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 07:03:23.952115 OPS=0x04
448 07:03:23.952583 ring efuse init
449 07:03:23.957215 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 07:03:23.957713 [0.017354 Inits done]
451 07:03:23.958164 secure task start!
452 07:03:23.964336 high task start!
453 07:03:23.964816 low task start!
454 07:03:23.965270 run into bl31
455 07:03:23.973247 NOTICE: BL31: v1.3(release):4fc40b1
456 07:03:23.980507 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 07:03:23.981021 NOTICE: BL31: G12A normal boot!
458 07:03:23.996601 NOTICE: BL31: BL33 decompress pass
459 07:03:24.001433 ERROR: Error initializing runtime service opteed_fast
460 07:03:25.219062 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 07:03:25.219726 bl2_stage_init 0x01
462 07:03:25.220258 bl2_stage_init 0x81
463 07:03:25.224588 hw id: 0x0000 - pwm id 0x01
464 07:03:25.225074 bl2_stage_init 0xc1
465 07:03:25.230178 bl2_stage_init 0x02
466 07:03:25.230651
467 07:03:25.231108 L0:00000000
468 07:03:25.231557 L1:00000703
469 07:03:25.232039 L2:00008067
470 07:03:25.232489 L3:15000000
471 07:03:25.235794 S1:00000000
472 07:03:25.236304 B2:20282000
473 07:03:25.236754 B1:a0f83180
474 07:03:25.237198
475 07:03:25.237644 TE: 70633
476 07:03:25.238086
477 07:03:25.241402 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 07:03:25.241888
479 07:03:25.246978 Board ID = 1
480 07:03:25.247457 Set cpu clk to 24M
481 07:03:25.247906 Set clk81 to 24M
482 07:03:25.252582 Use GP1_pll as DSU clk.
483 07:03:25.253067 DSU clk: 1200 Mhz
484 07:03:25.253520 CPU clk: 1200 MHz
485 07:03:25.258159 Set clk81 to 166.6M
486 07:03:25.263772 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 07:03:25.264282 board id: 1
488 07:03:25.270480 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 07:03:25.281933 fw parse done
490 07:03:25.286988 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 07:03:25.330427 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 07:03:25.342127 PIEI prepare done
493 07:03:25.342614 fastboot data load
494 07:03:25.343072 fastboot data verify
495 07:03:25.347727 verify result: 266
496 07:03:25.353324 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 07:03:25.353812 LPDDR4 probe
498 07:03:25.354260 ddr clk to 1584MHz
499 07:03:26.717090 Load ddrfw from SPI, src: 0x00018000, des: SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
500 07:03:26.717497 bl2_stage_init 0x01
501 07:03:26.717726 bl2_stage_init 0x81
502 07:03:26.722719 hw id: 0x0000 - pwm id 0x01
503 07:03:26.723000 bl2_stage_init 0xc1
504 07:03:26.728321 bl2_stage_init 0x02
505 07:03:26.728599
506 07:03:26.728813 L0:00000000
507 07:03:26.729019 L1:00000703
508 07:03:26.729222 L2:00008067
509 07:03:26.729425 L3:15000000
510 07:03:26.733888 S1:00000000
511 07:03:26.734146 B2:20282000
512 07:03:26.734358 B1:a0f83180
513 07:03:26.734564
514 07:03:26.734768 TE: 69957
515 07:03:26.734972
516 07:03:26.739480 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
517 07:03:26.739740
518 07:03:26.745065 Board ID = 1
519 07:03:26.745334 Set cpu clk to 24M
520 07:03:26.745544 Set clk81 to 24M
521 07:03:26.750762 Use GP1_pll as DSU clk.
522 07:03:26.751049 DSU clk: 1200 Mhz
523 07:03:26.751254 CPU clk: 1200 MHz
524 07:03:26.756272 Set clk81 to 166.6M
525 07:03:26.761841 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
526 07:03:26.762075 board id: 1
527 07:03:26.769022 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
528 07:03:26.779791 fw parse done
529 07:03:26.785856 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
530 07:03:26.828375 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
531 07:03:26.839250 PIEI prepare done
532 07:03:26.839777 fastboot data load
533 07:03:26.840266 fastboot data verify
534 07:03:26.844892 verify result: 266
535 07:03:26.850468 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
536 07:03:26.851021 LPDDR4 probe
537 07:03:26.851464 ddr clk to 1584MHz
538 07:03:26.858440 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 07:03:26.895751
540 07:03:26.896346 dmc_version 0001
541 07:03:26.902351 Check phy result
542 07:03:26.908260 INFO : End of CA training
543 07:03:26.908750 INFO : End of initialization
544 07:03:26.913864 INFO : Training has run successfully!
545 07:03:26.914410 Check phy result
546 07:03:26.919490 INFO : End of initialization
547 07:03:26.920032 INFO : End of read enable training
548 07:03:26.922767 INFO : End of fine write leveling
549 07:03:26.928330 INFO : End of Write leveling coarse delay
550 07:03:26.933917 INFO : Training has run successfully!
551 07:03:26.934452 Check phy result
552 07:03:26.934896 INFO : End of initialization
553 07:03:26.939497 INFO : End of read dq deskew training
554 07:03:26.945106 INFO : End of MPR read delay center optimization
555 07:03:26.945654 INFO : End of write delay center optimization
556 07:03:26.950790 INFO : End of read delay center optimization
557 07:03:26.956301 INFO : End of max read latency training
558 07:03:26.956794 INFO : Training has run successfully!
559 07:03:26.961916 1D training succeed
560 07:03:26.967890 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
561 07:03:27.015488 Check phy result
562 07:03:27.016075 INFO : End of initialization
563 07:03:27.037912 INFO : End of 2D read delay Voltage center optimization
564 07:03:27.056984 INFO : End of 2D read delay Voltage center optimization
565 07:03:27.108906 INFO : End of 2D write delay Voltage center optimization
566 07:03:27.158104 INFO : End of 2D write delay Voltage center optimization
567 07:03:27.163663 INFO : Training has run successfully!
568 07:03:27.164203
569 07:03:27.164671 channel==0
570 07:03:27.169212 RxClkDly_Margin_A0==78 ps 8
571 07:03:27.169699 TxDqDly_Margin_A0==98 ps 10
572 07:03:27.174824 RxClkDly_Margin_A1==88 ps 9
573 07:03:27.175306 TxDqDly_Margin_A1==98 ps 10
574 07:03:27.175751 TrainedVREFDQ_A0==74
575 07:03:27.180383 TrainedVREFDQ_A1==74
576 07:03:27.180869 VrefDac_Margin_A0==24
577 07:03:27.181309 DeviceVref_Margin_A0==40
578 07:03:27.185989 VrefDac_Margin_A1==23
579 07:03:27.186474 DeviceVref_Margin_A1==40
580 07:03:27.186914
581 07:03:27.187354
582 07:03:27.191646 channel==1
583 07:03:27.192154 RxClkDly_Margin_A0==78 ps 8
584 07:03:27.192597 TxDqDly_Margin_A0==98 ps 10
585 07:03:27.197198 RxClkDly_Margin_A1==88 ps 9
586 07:03:27.197672 TxDqDly_Margin_A1==88 ps 9
587 07:03:27.202827 TrainedVREFDQ_A0==78
588 07:03:27.203309 TrainedVREFDQ_A1==75
589 07:03:27.203760 VrefDac_Margin_A0==23
590 07:03:27.208440 DeviceVref_Margin_A0==36
591 07:03:27.208936 VrefDac_Margin_A1==23
592 07:03:27.214005 DeviceVref_Margin_A1==39
593 07:03:27.214483
594 07:03:27.214926 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
595 07:03:27.215368
596 07:03:27.247735 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
597 07:03:27.248375 2D training succeed
598 07:03:27.253231 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
599 07:03:27.258875 auto size-- 65535DDR cs0 size: 2048MB
600 07:03:27.259404 DDR cs1 size: 2048MB
601 07:03:27.264429 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
602 07:03:27.264989 cs0 DataBus test pass
603 07:03:27.270006 cs1 DataBus test pass
604 07:03:27.270555 cs0 AddrBus test pass
605 07:03:27.271026 cs1 AddrBus test pass
606 07:03:27.271473
607 07:03:27.275643 100bdlr_step_size ps== 478
608 07:03:27.276200 result report
609 07:03:27.281191 boot times 0Enable ddr reg access
610 07:03:27.286445 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
611 07:03:27.300312 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
612 07:03:27.956310 bl2z: ptr: 05129330, size: 00001e40
613 07:03:27.964107 0.0;M3 CHK:0;cm4_sp_mode 0
614 07:03:27.964669 MVN_1=0x00000000
615 07:03:27.965148 MVN_2=0x00000000
616 07:03:27.975606 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
617 07:03:27.976227 OPS=0x04
618 07:03:27.976716 ring efuse init
619 07:03:27.981257 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
620 07:03:27.981794 [0.017318 Inits done]
621 07:03:27.982266 secure task start!
622 07:03:27.988517 high task start!
623 07:03:27.989085 low task start!
624 07:03:27.989561 run into bl31
625 07:03:27.997122 NOTICE: BL31: v1.3(release):4fc40b1
626 07:03:28.004989 NOTICE: BL31: Built : 15:57:33, May 22 2019
627 07:03:28.005565 NOTICE: BL31: G12A normal boot!
628 07:03:28.020406 NOTICE: BL31: BL33 decompress pass
629 07:03:28.026088 ERROR: Error initializing runtime service opteed_fast
630 07:03:29.267534 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
631 07:03:29.268186 bl2_stage_init 0x01
632 07:03:29.268679 bl2_stage_init 0x81
633 07:03:29.273035 hw id: 0x0000 - pwm id 0x01
634 07:03:29.273548 bl2_stage_init 0xc1
635 07:03:29.278605 bl2_stage_init 0x02
636 07:03:29.279119
637 07:03:29.279601 L0:00000000
638 07:03:29.280101 L1:00000703
639 07:03:29.280565 L2:00008067
640 07:03:29.281015 L3:15000000
641 07:03:29.284319 S1:00000000
642 07:03:29.284828 B2:20282000
643 07:03:29.285285 B1:a0f83180
644 07:03:29.285734
645 07:03:29.286188 TE: 68496
646 07:03:29.286637
647 07:03:29.289775 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
648 07:03:29.290284
649 07:03:29.295423 Board ID = 1
650 07:03:29.295929 Set cpu clk to 24M
651 07:03:29.296436 Set clk81 to 24M
652 07:03:29.301067 Use GP1_pll as DSU clk.
653 07:03:29.301655 DSU clk: 1200 Mhz
654 07:03:29.302122 CPU clk: 1200 MHz
655 07:03:29.306613 Set clk81 to 166.6M
656 07:03:29.312233 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
657 07:03:29.312747 board id: 1
658 07:03:29.319518 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
659 07:03:29.330100 fw parse done
660 07:03:29.336093 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
661 07:03:29.377781 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
662 07:03:29.389480 PIEI prepare done
663 07:03:29.390067 fastboot data load
664 07:03:29.390556 fastboot data verify
665 07:03:29.395101 verify result: 266
666 07:03:29.400631 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
667 07:03:29.401161 LPDDR4 probe
668 07:03:29.401626 ddr clk to 1584MHz
669 07:03:29.407728 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
670 07:03:29.445903
671 07:03:29.446468 dmc_version 0001
672 07:03:29.451605 Check phy result
673 07:03:29.458524 INFO : End of CA training
674 07:03:29.459073 INFO : End of initialization
675 07:03:29.464147 INFO : Training has run successfully!
676 07:03:29.464681 Check phy result
677 07:03:29.469665 INFO : End of initialization
678 07:03:29.470170 INFO : End of read enable training
679 07:03:29.473132 INFO : End of fine write leveling
680 07:03:29.478532 INFO : End of Write leveling coarse delay
681 07:03:29.484196 INFO : Training has run successfully!
682 07:03:29.484718 Check phy result
683 07:03:29.485187 INFO : End of initialization
684 07:03:29.489803 INFO : End of read dq deskew training
685 07:03:29.495355 INFO : End of MPR read delay center optimization
686 07:03:29.495892 INFO : End of write delay center optimization
687 07:03:29.500992 INFO : End of read delay center optimization
688 07:03:29.506519 INFO : End of max read latency training
689 07:03:29.507066 INFO : Training has run successfully!
690 07:03:29.512114 1D training succeed
691 07:03:29.518218 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
692 07:03:29.565237 Check phy result
693 07:03:29.565819 INFO : End of initialization
694 07:03:29.587554 INFO : End of 2D read delay Voltage center optimization
695 07:03:29.607224 INFO : End of 2D read delay Voltage center optimization
696 07:03:29.659059 INFO : End of 2D write delay Voltage center optimization
697 07:03:29.708357 INFO : End of 2D write delay Voltage center optimization
698 07:03:29.713833 INFO : Training has run successfully!
699 07:03:29.714430
700 07:03:29.714910 channel==0
701 07:03:29.719358 RxClkDly_Margin_A0==78 ps 8
702 07:03:29.719869 TxDqDly_Margin_A0==88 ps 9
703 07:03:29.725005 RxClkDly_Margin_A1==88 ps 9
704 07:03:29.725509 TxDqDly_Margin_A1==98 ps 10
705 07:03:29.725976 TrainedVREFDQ_A0==74
706 07:03:29.730574 TrainedVREFDQ_A1==75
707 07:03:29.731166 VrefDac_Margin_A0==23
708 07:03:29.731653 DeviceVref_Margin_A0==40
709 07:03:29.736236 VrefDac_Margin_A1==23
710 07:03:29.736770 DeviceVref_Margin_A1==39
711 07:03:29.737235
712 07:03:29.737690
713 07:03:29.738143 channel==1
714 07:03:29.741758 RxClkDly_Margin_A0==78 ps 8
715 07:03:29.742266 TxDqDly_Margin_A0==108 ps 11
716 07:03:29.747424 RxClkDly_Margin_A1==78 ps 8
717 07:03:29.748035 TxDqDly_Margin_A1==88 ps 9
718 07:03:29.753005 TrainedVREFDQ_A0==78
719 07:03:29.753530 TrainedVREFDQ_A1==75
720 07:03:29.754001 VrefDac_Margin_A0==22
721 07:03:29.758751 DeviceVref_Margin_A0==36
722 07:03:29.759335 VrefDac_Margin_A1==22
723 07:03:29.764356 DeviceVref_Margin_A1==39
724 07:03:29.764912
725 07:03:29.765386 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
726 07:03:29.765850
727 07:03:29.797825 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
728 07:03:29.798436 2D training succeed
729 07:03:29.803376 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
730 07:03:29.809113 auto size-- 65535DDR cs0 size: 2048MB
731 07:03:29.809693 DDR cs1 size: 2048MB
732 07:03:29.814597 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
733 07:03:29.815148 cs0 DataBus test pass
734 07:03:29.820199 cs1 DataBus test pass
735 07:03:29.820707 cs0 AddrBus test pass
736 07:03:29.821168 cs1 AddrBus test pass
737 07:03:29.821624
738 07:03:29.825805 100bdlr_step_size ps== 478
739 07:03:29.826454 result report
740 07:03:29.831370 boot times 0Enable ddr reg access
741 07:03:29.836644 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
742 07:03:29.850507 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
743 07:03:30.505405 bl2z: ptr: 05129330, size: 00001e40
744 07:03:30.512937 0.0;M3 CHK:0;cm4_sp_mode 0
745 07:03:30.513499 MVN_1=0x00000000
746 07:03:30.513971 MVN_2=0x00000000
747 07:03:30.524453 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
748 07:03:30.524968 OPS=0x04
749 07:03:30.525438 ring efuse init
750 07:03:30.530064 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
751 07:03:30.530576 [0.017319 Inits done]
752 07:03:30.531038 secure task start!
753 07:03:30.536936 high task start!
754 07:03:30.537438 low task start!
755 07:03:30.537898 run into bl31
756 07:03:30.546238 NOTICE: BL31: v1.3(release):4fc40b1
757 07:03:30.554032 NOTICE: BL31: Built : 15:57:33, May 22 2019
758 07:03:30.554536 NOTICE: BL31: G12A normal boot!
759 07:03:30.569544 NOTICE: BL31: BL33 decompress pass
760 07:03:30.575260 ERROR: Error initializing runtime service opteed_fast
761 07:03:31.370680
762 07:03:31.371308
763 07:03:31.376079 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
764 07:03:31.376602
765 07:03:31.379555 Model: Libre Computer AML-S905D3-CC Solitude
766 07:03:31.526627 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
767 07:03:31.541983 DRAM: 2 GiB (effective 3.8 GiB)
768 07:03:31.642940 Core: 406 devices, 33 uclasses, devicetree: separate
769 07:03:31.648819 WDT: Not starting watchdog@f0d0
770 07:03:31.673904 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
771 07:03:31.686156 Loading Environment from FAT... Card did not respond to voltage select! : -110
772 07:03:31.691144 ** Bad device specification mmc 0 **
773 07:03:31.701237 Card did not respond to voltage select! : -110
774 07:03:31.708868 ** Bad device specification mmc 0 **
775 07:03:31.709366 Couldn't find partition mmc 0
776 07:03:31.717224 Card did not respond to voltage select! : -110
777 07:03:31.722717 ** Bad device specification mmc 0 **
778 07:03:31.723287 Couldn't find partition mmc 0
779 07:03:31.727817 Error: could not access storage.
780 07:03:32.025263 Net: eth0: ethernet@ff3f0000
781 07:03:32.025890 starting USB...
782 07:03:32.269852 Bus usb@ff500000: Register 3000140 NbrPorts 3
783 07:03:32.270374 Starting the controller
784 07:03:32.276858 USB XHCI 1.10
785 07:03:33.831169 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
786 07:03:33.839483 scanning usb for storage devices... 0 Storage Device(s) found
788 07:03:33.891141 Hit any key to stop autoboot: 1
789 07:03:33.892002 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
790 07:03:33.892677 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
791 07:03:33.893221 Setting prompt string to ['=>']
792 07:03:33.893774 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
793 07:03:33.905495 0
794 07:03:33.906446 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
796 07:03:34.007770 => setenv autoload no
797 07:03:34.008508 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
798 07:03:34.013843 setenv autoload no
800 07:03:34.115408 => setenv initrd_high 0xffffffff
801 07:03:34.116083 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
802 07:03:34.120605 setenv initrd_high 0xffffffff
804 07:03:34.222175 => setenv fdt_high 0xffffffff
805 07:03:34.222874 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
806 07:03:34.227192 setenv fdt_high 0xffffffff
808 07:03:34.328822 => dhcp
809 07:03:34.329542 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
810 07:03:34.333593 dhcp
811 07:03:35.439664 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
812 07:03:35.440314 Speed: 1000, full duplex
813 07:03:35.440798 BOOTP broadcast 1
814 07:03:35.687915 BOOTP broadcast 2
815 07:03:36.188691 BOOTP broadcast 3
816 07:03:37.189901 BOOTP broadcast 4
817 07:03:39.191121 BOOTP broadcast 5
818 07:03:39.202856 DHCP client bound to address 192.168.6.12 (3762 ms)
820 07:03:39.304468 => setenv serverip 192.168.6.2
821 07:03:39.305158 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
822 07:03:39.309758 setenv serverip 192.168.6.2
824 07:03:39.411284 => tftpboot 0x01080000 714841/tftp-deploy-jutn8jb4/kernel/uImage
825 07:03:39.411972 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
826 07:03:39.418687 tftpboot 0x01080000 714841/tftp-deploy-jutn8jb4/kernel/uImage
827 07:03:39.419216 Speed: 1000, full duplex
828 07:03:39.419681 Using ethernet@ff3f0000 device
829 07:03:39.424192 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
830 07:03:39.429707 Filename '714841/tftp-deploy-jutn8jb4/kernel/uImage'.
831 07:03:39.433638 Load address: 0x1080000
832 07:03:42.485268 Loading: *################################################## 43.2 MiB
833 07:03:42.485949 14.2 MiB/s
834 07:03:42.486441 done
835 07:03:42.489443 Bytes transferred = 45308480 (2b35a40 hex)
837 07:03:42.591217 => tftpboot 0x08000000 714841/tftp-deploy-jutn8jb4/ramdisk/ramdisk.cpio.gz.uboot
838 07:03:42.592080 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
839 07:03:42.599122 tftpboot 0x08000000 714841/tftp-deploy-jutn8jb4/ramdisk/ramdisk.cpio.gz.uboot
840 07:03:42.599668 Speed: 1000, full duplex
841 07:03:42.600154 Using ethernet@ff3f0000 device
842 07:03:42.604622 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
843 07:03:42.614252 Filename '714841/tftp-deploy-jutn8jb4/ramdisk/ramdisk.cpio.gz.uboot'.
844 07:03:42.614800 Load address: 0x8000000
845 07:03:44.117122 Loading: *################################################# UDP wrong checksum 00000005 00001d92
846 07:03:49.116882 T UDP wrong checksum 00000005 00001d92
847 07:03:50.952052 UDP wrong checksum 000000ff 0000c53c
848 07:03:50.968539 UDP wrong checksum 000000ff 00005d2f
849 07:03:51.534997 UDP wrong checksum 000000ff 00000ea1
850 07:03:51.544300 UDP wrong checksum 000000ff 00009193
851 07:03:55.023721 T UDP wrong checksum 000000ff 0000ab58
852 07:03:55.037705 UDP wrong checksum 000000ff 0000454b
853 07:03:59.118975 T UDP wrong checksum 00000005 00001d92
854 07:04:00.272772 UDP wrong checksum 000000ff 0000801a
855 07:04:00.285820 UDP wrong checksum 000000ff 00001d0d
856 07:04:03.363011 UDP wrong checksum 000000ff 0000d3f5
857 07:04:03.375053 UDP wrong checksum 000000ff 000068e8
858 07:04:05.758569 T UDP wrong checksum 000000ff 000079be
859 07:04:05.788128 UDP wrong checksum 000000ff 000009b1
860 07:04:19.122834 T T T UDP wrong checksum 00000005 00001d92
861 07:04:39.127806 T T T
862 07:04:39.128551 Retry count exceeded; starting again
864 07:04:39.130191 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
867 07:04:39.132397 end: 2.4 uboot-commands (duration 00:01:23) [common]
869 07:04:39.133971 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
871 07:04:39.135153 end: 2 uboot-action (duration 00:01:24) [common]
873 07:04:39.136896 Cleaning after the job
874 07:04:39.137505 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/ramdisk
875 07:04:39.138998 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/kernel
876 07:04:39.188272 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/dtb
877 07:04:39.189165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/nfsrootfs
878 07:04:39.500864 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/714841/tftp-deploy-jutn8jb4/modules
879 07:04:39.520118 start: 4.1 power-off (timeout 00:00:30) [common]
880 07:04:39.520841 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
881 07:04:39.555073 >> OK - accepted request
882 07:04:39.557366 Returned 0 in 0 seconds
883 07:04:39.658271 end: 4.1 power-off (duration 00:00:00) [common]
885 07:04:39.659371 start: 4.2 read-feedback (timeout 00:10:00) [common]
886 07:04:39.660128 Listened to connection for namespace 'common' for up to 1s
887 07:04:40.660995 Finalising connection for namespace 'common'
888 07:04:40.661452 Disconnecting from shell: Finalise
889 07:04:40.661729 =>
890 07:04:40.762331 end: 4.2 read-feedback (duration 00:00:01) [common]
891 07:04:40.762657 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/714841
892 07:04:43.311377 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/714841
893 07:04:43.312017 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.