Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 29
- Errors: 0
- Boot result: PASS
- Kernel Errors: 66
1 04:49:15.694705 lava-dispatcher, installed at version: 2024.01
2 04:49:15.695467 start: 0 validate
3 04:49:15.695943 Start time: 2024-09-02 04:49:15.695914+00:00 (UTC)
4 04:49:15.696493 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:49:15.697036 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 04:49:15.735662 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:49:15.736224 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fkernel%2FzImage exists
8 04:49:15.767300 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:49:15.768227 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 04:49:15.798761 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:49:15.799605 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 04:49:15.829797 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:49:15.830277 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fclang-15%2Fmodules.tar.xz exists
14 04:49:15.871512 validate duration: 0.18
16 04:49:15.873050 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:49:15.873655 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:49:15.874212 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:49:15.875168 Not decompressing ramdisk as can be used compressed.
20 04:49:15.875895 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 04:49:15.876406 saving as /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/ramdisk/initrd.cpio.gz
22 04:49:15.876903 total size: 4775763 (4 MB)
23 04:49:15.915430 progress 0 % (0 MB)
24 04:49:15.922944 progress 5 % (0 MB)
25 04:49:15.929969 progress 10 % (0 MB)
26 04:49:15.936865 progress 15 % (0 MB)
27 04:49:15.944474 progress 20 % (0 MB)
28 04:49:15.950601 progress 25 % (1 MB)
29 04:49:15.954522 progress 30 % (1 MB)
30 04:49:15.958060 progress 35 % (1 MB)
31 04:49:15.961184 progress 40 % (1 MB)
32 04:49:15.964356 progress 45 % (2 MB)
33 04:49:15.967476 progress 50 % (2 MB)
34 04:49:15.971007 progress 55 % (2 MB)
35 04:49:15.974152 progress 60 % (2 MB)
36 04:49:15.977267 progress 65 % (2 MB)
37 04:49:15.980784 progress 70 % (3 MB)
38 04:49:15.983871 progress 75 % (3 MB)
39 04:49:15.986959 progress 80 % (3 MB)
40 04:49:15.990061 progress 85 % (3 MB)
41 04:49:15.993525 progress 90 % (4 MB)
42 04:49:15.996439 progress 95 % (4 MB)
43 04:49:15.999245 progress 100 % (4 MB)
44 04:49:15.999884 4 MB downloaded in 0.12 s (37.04 MB/s)
45 04:49:16.000435 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:49:16.001318 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:49:16.001609 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:49:16.001882 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:49:16.002347 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-15/kernel/zImage
51 04:49:16.002593 saving as /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/kernel/zImage
52 04:49:16.002802 total size: 11964928 (11 MB)
53 04:49:16.003014 No compression specified
54 04:49:16.038818 progress 0 % (0 MB)
55 04:49:16.047064 progress 5 % (0 MB)
56 04:49:16.054928 progress 10 % (1 MB)
57 04:49:16.062747 progress 15 % (1 MB)
58 04:49:16.070937 progress 20 % (2 MB)
59 04:49:16.078552 progress 25 % (2 MB)
60 04:49:16.086300 progress 30 % (3 MB)
61 04:49:16.093892 progress 35 % (4 MB)
62 04:49:16.102095 progress 40 % (4 MB)
63 04:49:16.109697 progress 45 % (5 MB)
64 04:49:16.117469 progress 50 % (5 MB)
65 04:49:16.125188 progress 55 % (6 MB)
66 04:49:16.133269 progress 60 % (6 MB)
67 04:49:16.140989 progress 65 % (7 MB)
68 04:49:16.148555 progress 70 % (8 MB)
69 04:49:16.156123 progress 75 % (8 MB)
70 04:49:16.164065 progress 80 % (9 MB)
71 04:49:16.171584 progress 85 % (9 MB)
72 04:49:16.179136 progress 90 % (10 MB)
73 04:49:16.186765 progress 95 % (10 MB)
74 04:49:16.194369 progress 100 % (11 MB)
75 04:49:16.194865 11 MB downloaded in 0.19 s (59.41 MB/s)
76 04:49:16.195337 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:49:16.196197 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:49:16.196476 start: 1.3 download-retry (timeout 00:10:00) [common]
80 04:49:16.196743 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 04:49:16.197207 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-15/dtbs/ti/omap/am335x-boneblack.dtb
82 04:49:16.197474 saving as /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/dtb/am335x-boneblack.dtb
83 04:49:16.197682 total size: 70308 (0 MB)
84 04:49:16.197892 No compression specified
85 04:49:16.232486 progress 46 % (0 MB)
86 04:49:16.233285 progress 93 % (0 MB)
87 04:49:16.233958 progress 100 % (0 MB)
88 04:49:16.234336 0 MB downloaded in 0.04 s (1.83 MB/s)
89 04:49:16.234785 end: 1.3.1 http-download (duration 00:00:00) [common]
91 04:49:16.235603 end: 1.3 download-retry (duration 00:00:00) [common]
92 04:49:16.235866 start: 1.4 download-retry (timeout 00:10:00) [common]
93 04:49:16.236160 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 04:49:16.236607 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 04:49:16.236849 saving as /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/nfsrootfs/full.rootfs.tar
96 04:49:16.237055 total size: 117747780 (112 MB)
97 04:49:16.237267 Using unxz to decompress xz
98 04:49:16.272803 progress 0 % (0 MB)
99 04:49:16.997902 progress 5 % (5 MB)
100 04:49:17.740339 progress 10 % (11 MB)
101 04:49:18.505258 progress 15 % (16 MB)
102 04:49:19.215118 progress 20 % (22 MB)
103 04:49:19.788235 progress 25 % (28 MB)
104 04:49:20.584509 progress 30 % (33 MB)
105 04:49:21.380319 progress 35 % (39 MB)
106 04:49:21.707351 progress 40 % (44 MB)
107 04:49:22.052621 progress 45 % (50 MB)
108 04:49:22.712676 progress 50 % (56 MB)
109 04:49:23.514780 progress 55 % (61 MB)
110 04:49:24.235043 progress 60 % (67 MB)
111 04:49:24.940108 progress 65 % (73 MB)
112 04:49:25.687438 progress 70 % (78 MB)
113 04:49:26.438548 progress 75 % (84 MB)
114 04:49:27.158398 progress 80 % (89 MB)
115 04:49:27.859890 progress 85 % (95 MB)
116 04:49:28.635923 progress 90 % (101 MB)
117 04:49:29.386950 progress 95 % (106 MB)
118 04:49:30.190001 progress 100 % (112 MB)
119 04:49:30.202185 112 MB downloaded in 13.97 s (8.04 MB/s)
120 04:49:30.203112 end: 1.4.1 http-download (duration 00:00:14) [common]
122 04:49:30.204968 end: 1.4 download-retry (duration 00:00:14) [common]
123 04:49:30.205669 start: 1.5 download-retry (timeout 00:09:46) [common]
124 04:49:30.206243 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 04:49:30.207131 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-15/modules.tar.xz
126 04:49:30.207645 saving as /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/modules/modules.tar
127 04:49:30.208139 total size: 6914240 (6 MB)
128 04:49:30.208610 Using unxz to decompress xz
129 04:49:30.252086 progress 0 % (0 MB)
130 04:49:30.287661 progress 5 % (0 MB)
131 04:49:30.343876 progress 10 % (0 MB)
132 04:49:30.395403 progress 15 % (1 MB)
133 04:49:30.452506 progress 20 % (1 MB)
134 04:49:30.502289 progress 25 % (1 MB)
135 04:49:30.558753 progress 30 % (2 MB)
136 04:49:30.610043 progress 35 % (2 MB)
137 04:49:30.666421 progress 40 % (2 MB)
138 04:49:30.717188 progress 45 % (2 MB)
139 04:49:30.772256 progress 50 % (3 MB)
140 04:49:30.828307 progress 55 % (3 MB)
141 04:49:30.880379 progress 60 % (3 MB)
142 04:49:30.936217 progress 65 % (4 MB)
143 04:49:30.984750 progress 70 % (4 MB)
144 04:49:31.045812 progress 75 % (4 MB)
145 04:49:31.099870 progress 80 % (5 MB)
146 04:49:31.155066 progress 85 % (5 MB)
147 04:49:31.196819 progress 90 % (5 MB)
148 04:49:31.245121 progress 95 % (6 MB)
149 04:49:31.292424 progress 100 % (6 MB)
150 04:49:31.302571 6 MB downloaded in 1.09 s (6.03 MB/s)
151 04:49:31.303165 end: 1.5.1 http-download (duration 00:00:01) [common]
153 04:49:31.304063 end: 1.5 download-retry (duration 00:00:01) [common]
154 04:49:31.304666 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 04:49:31.305250 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 04:49:47.094859 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5
157 04:49:47.095467 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 04:49:47.095758 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
159 04:49:47.096561 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7
160 04:49:47.097019 makedir: /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin
161 04:49:47.097351 makedir: /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/tests
162 04:49:47.097664 makedir: /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/results
163 04:49:47.097998 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-add-keys
164 04:49:47.098565 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-add-sources
165 04:49:47.099109 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-background-process-start
166 04:49:47.099608 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-background-process-stop
167 04:49:47.100158 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-common-functions
168 04:49:47.100668 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-echo-ipv4
169 04:49:47.101144 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-install-packages
170 04:49:47.101614 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-installed-packages
171 04:49:47.102079 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-os-build
172 04:49:47.102648 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-probe-channel
173 04:49:47.103163 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-probe-ip
174 04:49:47.103639 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-target-ip
175 04:49:47.104141 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-target-mac
176 04:49:47.104630 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-target-storage
177 04:49:47.105111 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-test-case
178 04:49:47.105583 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-test-event
179 04:49:47.106070 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-test-feedback
180 04:49:47.106582 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-test-raise
181 04:49:47.107057 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-test-reference
182 04:49:47.107533 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-test-runner
183 04:49:47.108026 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-test-set
184 04:49:47.108514 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-test-shell
185 04:49:47.109019 Updating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-add-keys (debian)
186 04:49:47.109551 Updating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-add-sources (debian)
187 04:49:47.110057 Updating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-install-packages (debian)
188 04:49:47.110555 Updating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-installed-packages (debian)
189 04:49:47.111039 Updating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/bin/lava-os-build (debian)
190 04:49:47.111467 Creating /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/environment
191 04:49:47.111828 LAVA metadata
192 04:49:47.112112 - LAVA_JOB_ID=689582
193 04:49:47.112333 - LAVA_DISPATCHER_IP=192.168.6.2
194 04:49:47.112689 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
195 04:49:47.113631 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 04:49:47.113949 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
197 04:49:47.114159 skipped lava-vland-overlay
198 04:49:47.114401 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 04:49:47.114658 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
200 04:49:47.114878 skipped lava-multinode-overlay
201 04:49:47.115121 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 04:49:47.115372 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
203 04:49:47.115618 Loading test definitions
204 04:49:47.115894 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
205 04:49:47.116153 Using /lava-689582 at stage 0
206 04:49:47.117218 uuid=689582_1.6.2.4.1 testdef=None
207 04:49:47.117520 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 04:49:47.117783 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
209 04:49:47.119298 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 04:49:47.120113 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
212 04:49:47.122089 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 04:49:47.122927 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
215 04:49:47.124824 runner path: /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/0/tests/0_timesync-off test_uuid 689582_1.6.2.4.1
216 04:49:47.125382 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 04:49:47.126210 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
219 04:49:47.126435 Using /lava-689582 at stage 0
220 04:49:47.126785 Fetching tests from https://github.com/kernelci/test-definitions.git
221 04:49:47.127077 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/0/tests/1_kselftest-dt'
222 04:49:50.564724 Running '/usr/bin/git checkout kernelci.org
223 04:49:51.060958 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 04:49:51.062444 uuid=689582_1.6.2.4.5 testdef=None
225 04:49:51.062797 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 04:49:51.063581 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 04:49:51.066602 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 04:49:51.067544 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 04:49:51.075017 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 04:49:51.076871 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 04:49:51.082296 runner path: /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/0/tests/1_kselftest-dt test_uuid 689582_1.6.2.4.5
235 04:49:51.082618 BOARD='beaglebone-black'
236 04:49:51.082839 BRANCH='mainline'
237 04:49:51.083046 SKIPFILE='/dev/null'
238 04:49:51.083252 SKIP_INSTALL='True'
239 04:49:51.083456 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz'
240 04:49:51.083665 TST_CASENAME=''
241 04:49:51.083868 TST_CMDFILES='dt'
242 04:49:51.084518 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 04:49:51.085340 Creating lava-test-runner.conf files
245 04:49:51.085557 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/689582/lava-overlay-57dlscu7/lava-689582/0 for stage 0
246 04:49:51.085924 - 0_timesync-off
247 04:49:51.086177 - 1_kselftest-dt
248 04:49:51.086527 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 04:49:51.086826 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 04:50:14.809660 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 04:50:14.810105 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 04:50:14.810405 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 04:50:14.810720 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 04:50:14.811019 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 04:50:15.172524 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 04:50:15.173001 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 04:50:15.173260 extracting modules file /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5
258 04:50:16.046596 extracting modules file /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/689582/extract-overlay-ramdisk-f211_uc5/ramdisk
259 04:50:16.942809 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 04:50:16.943282 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 04:50:16.943561 [common] Applying overlay to NFS
262 04:50:16.943779 [common] Applying overlay /var/lib/lava/dispatcher/tmp/689582/compress-overlay-9cxtem85/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5
263 04:50:19.689809 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 04:50:19.690278 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 04:50:19.690561 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 04:50:19.690844 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 04:50:19.691101 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 04:50:19.691362 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 04:50:19.691617 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 04:50:19.691876 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 04:50:19.692159 Building ramdisk /var/lib/lava/dispatcher/tmp/689582/extract-overlay-ramdisk-f211_uc5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/689582/extract-overlay-ramdisk-f211_uc5/ramdisk
272 04:50:20.730797 >> 78982 blocks
273 04:50:25.728950 Adding RAMdisk u-boot header.
274 04:50:25.729726 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/689582/extract-overlay-ramdisk-f211_uc5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/689582/extract-overlay-ramdisk-f211_uc5/ramdisk.cpio.gz.uboot
275 04:50:25.905283 output: Image Name:
276 04:50:25.905713 output: Created: Mon Sep 2 04:50:25 2024
277 04:50:25.905928 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 04:50:25.906135 output: Data Size: 15350669 Bytes = 14990.89 KiB = 14.64 MiB
279 04:50:25.906340 output: Load Address: 00000000
280 04:50:25.906542 output: Entry Point: 00000000
281 04:50:25.906740 output:
282 04:50:25.907385 rename /var/lib/lava/dispatcher/tmp/689582/extract-overlay-ramdisk-f211_uc5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/ramdisk/ramdisk.cpio.gz.uboot
283 04:50:25.907812 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 04:50:25.908247 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 04:50:25.908799 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 04:50:25.909260 No LXC device requested
287 04:50:25.909756 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 04:50:25.910263 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 04:50:25.910756 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 04:50:25.911167 Checking files for TFTP limit of 4294967296 bytes.
291 04:50:25.913855 end: 1 tftp-deploy (duration 00:01:10) [common]
292 04:50:25.914439 start: 2 uboot-action (timeout 00:05:00) [common]
293 04:50:25.914965 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 04:50:25.915463 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 04:50:25.915962 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 04:50:25.916752 substitutions:
297 04:50:25.917167 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 04:50:25.917572 - {DTB_ADDR}: 0x88000000
299 04:50:25.917968 - {DTB}: 689582/tftp-deploy-ovyw3or_/dtb/am335x-boneblack.dtb
300 04:50:25.918363 - {INITRD}: 689582/tftp-deploy-ovyw3or_/ramdisk/ramdisk.cpio.gz.uboot
301 04:50:25.918756 - {KERNEL_ADDR}: 0x82000000
302 04:50:25.919143 - {KERNEL}: 689582/tftp-deploy-ovyw3or_/kernel/zImage
303 04:50:25.919537 - {LAVA_MAC}: None
304 04:50:25.919968 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5
305 04:50:25.920430 - {NFS_SERVER_IP}: 192.168.6.2
306 04:50:25.920830 - {PRESEED_CONFIG}: None
307 04:50:25.921221 - {PRESEED_LOCAL}: None
308 04:50:25.921609 - {RAMDISK_ADDR}: 0x83000000
309 04:50:25.921998 - {RAMDISK}: 689582/tftp-deploy-ovyw3or_/ramdisk/ramdisk.cpio.gz.uboot
310 04:50:25.922391 - {ROOT_PART}: None
311 04:50:25.922779 - {ROOT}: None
312 04:50:25.923173 - {SERVER_IP}: 192.168.6.2
313 04:50:25.923562 - {TEE_ADDR}: 0x83000000
314 04:50:25.923945 - {TEE}: None
315 04:50:25.924363 Parsed boot commands:
316 04:50:25.924740 - setenv autoload no
317 04:50:25.925124 - setenv initrd_high 0xffffffff
318 04:50:25.925508 - setenv fdt_high 0xffffffff
319 04:50:25.925889 - dhcp
320 04:50:25.926268 - setenv serverip 192.168.6.2
321 04:50:25.926649 - tftp 0x82000000 689582/tftp-deploy-ovyw3or_/kernel/zImage
322 04:50:25.927035 - tftp 0x83000000 689582/tftp-deploy-ovyw3or_/ramdisk/ramdisk.cpio.gz.uboot
323 04:50:25.927422 - setenv initrd_size ${filesize}
324 04:50:25.927805 - tftp 0x88000000 689582/tftp-deploy-ovyw3or_/dtb/am335x-boneblack.dtb
325 04:50:25.928216 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 04:50:25.928616 - bootz 0x82000000 0x83000000 0x88000000
327 04:50:25.929109 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 04:50:25.930587 start: 2.3 connect-device (timeout 00:05:00) [common]
330 04:50:25.931004 [common] connect-device Connecting to device using 'telnet conserv3 3001'
331 04:50:25.945466 Setting prompt string to ['lava-test: # ']
332 04:50:25.946923 end: 2.3 connect-device (duration 00:00:00) [common]
333 04:50:25.947509 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 04:50:25.948083 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 04:50:25.948627 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 04:50:25.949832 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-04'
337 04:50:25.985838 >> OK - accepted request
338 04:50:25.987587 Returned 0 in 0 seconds
339 04:50:26.088665 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 04:50:26.090234 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 04:50:26.090799 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 04:50:26.091308 Setting prompt string to ['Hit any key to stop autoboot']
344 04:50:26.091761 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 04:50:26.093348 Trying 192.168.56.22...
346 04:50:26.093820 Connected to conserv3.
347 04:50:26.094231 Escape character is '^]'.
348 04:50:26.094631
349 04:50:26.095042 ser2net port telnet,3001 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 04:50:26.095459
351 04:51:02.887408
352 04:51:02.894251 U-Boot SPL 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
353 04:51:02.894712 Trying to boot from MMC1
354 04:51:03.469662
355 04:51:03.470151
356 04:51:03.475065 U-Boot 2023.01-rc4-00047-g3089d12a02 (Jan 01 2023 - 22:23:32 +0000)
357 04:51:03.475497
358 04:51:03.475914 CPU : AM335X-GP rev 2.0
359 04:51:03.480289 Model: TI AM335x BeagleBone Black
360 04:51:03.480726 DRAM: 512 MiB
361 04:51:03.563806 Core: 160 devices, 18 uclasses, devicetree: separate
362 04:51:03.577662 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
363 04:51:03.979386 NAND: 0 MiB
364 04:51:03.989564 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
365 04:51:04.064205 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
366 04:51:04.085483 <ethaddr> not set. Validating first E-fuse MAC
367 04:51:04.115319 Net: eth2: ethernet@4a100000, eth3: usb_ether
369 04:51:04.173755 Hit any key to stop autoboot: 2
370 04:51:04.174611 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
371 04:51:04.175313 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
372 04:51:04.175852 Setting prompt string to ['=>']
373 04:51:04.176450 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
374 04:51:04.183679 0
375 04:51:04.184646 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
376 04:51:04.185216 Sending with 10 millisecond of delay
378 04:51:05.320133 => setenv autoload no
379 04:51:05.330893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
380 04:51:05.336247 setenv autoload no
381 04:51:05.337041 Sending with 10 millisecond of delay
383 04:51:07.134095 => setenv initrd_high 0xffffffff
384 04:51:07.144847 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
385 04:51:07.145695 setenv initrd_high 0xffffffff
386 04:51:07.146468 Sending with 10 millisecond of delay
388 04:51:08.763365 => setenv fdt_high 0xffffffff
389 04:51:08.774286 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
390 04:51:08.775269 setenv fdt_high 0xffffffff
391 04:51:08.776060 Sending with 10 millisecond of delay
393 04:51:09.068131 => dhcp
394 04:51:09.078971 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
395 04:51:09.079934 dhcp
396 04:51:09.081560 link up on port 0, speed 100, full duplex
397 04:51:09.082141 BOOTP broadcast 1
398 04:51:09.114066 DHCP client bound to address 192.168.6.28 (30 ms)
399 04:51:09.114914 Sending with 10 millisecond of delay
401 04:51:10.791664 => setenv serverip 192.168.6.2
402 04:51:10.802528 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
403 04:51:10.803480 setenv serverip 192.168.6.2
404 04:51:10.804328 Sending with 10 millisecond of delay
406 04:51:14.289609 => tftp 0x82000000 689582/tftp-deploy-ovyw3or_/kernel/zImage
407 04:51:14.300432 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
408 04:51:14.301396 tftp 0x82000000 689582/tftp-deploy-ovyw3or_/kernel/zImage
409 04:51:14.301876 link up on port 0, speed 100, full duplex
410 04:51:14.305330 Using ethernet@4a100000 device
411 04:51:14.310775 TFTP from server 192.168.6.2; our IP address is 192.168.6.28
412 04:51:14.318016 Filename '689582/tftp-deploy-ovyw3or_/kernel/zImage'.
413 04:51:14.318542 Load address: 0x82000000
414 04:51:16.521393 Loading: *################################################## 11.4 MiB
415 04:51:16.522077 5.2 MiB/s
416 04:51:16.522561 done
417 04:51:16.525398 Bytes transferred = 11964928 (b69200 hex)
418 04:51:16.526185 Sending with 10 millisecond of delay
420 04:51:20.972935 => tftp 0x83000000 689582/tftp-deploy-ovyw3or_/ramdisk/ramdisk.cpio.gz.uboot
421 04:51:20.983753 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
422 04:51:20.984730 tftp 0x83000000 689582/tftp-deploy-ovyw3or_/ramdisk/ramdisk.cpio.gz.uboot
423 04:51:20.985206 link up on port 0, speed 100, full duplex
424 04:51:20.988620 Using ethernet@4a100000 device
425 04:51:20.994222 TFTP from server 192.168.6.2; our IP address is 192.168.6.28
426 04:51:21.002931 Filename '689582/tftp-deploy-ovyw3or_/ramdisk/ramdisk.cpio.gz.uboot'.
427 04:51:21.003478 Load address: 0x83000000
428 04:51:23.877236 Loading: *################################################## 14.6 MiB
429 04:51:23.877833 5.1 MiB/s
430 04:51:23.878268 done
431 04:51:23.881746 Bytes transferred = 15350733 (ea3bcd hex)
432 04:51:23.882541 Sending with 10 millisecond of delay
434 04:51:25.739102 => setenv initrd_size ${filesize}
435 04:51:25.749626 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
436 04:51:25.750118 setenv initrd_size ${filesize}
437 04:51:25.750961 Sending with 10 millisecond of delay
439 04:51:29.896741 => tftp 0x88000000 689582/tftp-deploy-ovyw3or_/dtb/am335x-boneblack.dtb
440 04:51:29.907694 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:56)
441 04:51:29.908880 tftp 0x88000000 689582/tftp-deploy-ovyw3or_/dtb/am335x-boneblack.dtb
442 04:51:29.909452 link up on port 0, speed 100, full duplex
443 04:51:29.912167 Using ethernet@4a100000 device
444 04:51:29.917765 TFTP from server 192.168.6.2; our IP address is 192.168.6.28
445 04:51:29.930359 Filename '689582/tftp-deploy-ovyw3or_/dtb/am335x-boneblack.dtb'.
446 04:51:29.930937 Load address: 0x88000000
447 04:51:29.938444 Loading: *################################################## 68.7 KiB
448 04:51:29.947858 4.5 MiB/s
449 04:51:29.948451 done
450 04:51:29.948965 Bytes transferred = 70308 (112a4 hex)
451 04:51:29.949763 Sending with 10 millisecond of delay
453 04:51:43.127657 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
454 04:51:43.138535 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
455 04:51:43.139448 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
456 04:51:43.140214 Sending with 10 millisecond of delay
458 04:51:45.478385 => bootz 0x82000000 0x83000000 0x88000000
459 04:51:45.489277 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
460 04:51:45.489907 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:40)
461 04:51:45.491013 bootz 0x82000000 0x83000000 0x88000000
462 04:51:45.491526 Kernel image @ 0x82000000 [ 0x000000 - 0xb69200 ]
463 04:51:45.492126 ## Loading init Ramdisk from Legacy Image at 83000000 ...
464 04:51:45.496829 Image Name:
465 04:51:45.497347 Created: 2024-09-02 4:50:25 UTC
466 04:51:45.500213 Image Type: ARM Linux RAMDisk Image (uncompressed)
467 04:51:45.505719 Data Size: 15350669 Bytes = 14.6 MiB
468 04:51:45.514086 Load Address: 00000000
469 04:51:45.514597 Entry Point: 00000000
470 04:51:45.688639 Verifying Checksum ... OK
471 04:51:45.688970 ## Flattened Device Tree blob at 88000000
472 04:51:45.695273 Booting using the fdt blob at 0x88000000
473 04:51:45.696245 Working FDT set to 88000000
474 04:51:45.700808 Using Device Tree in place at 88000000, end 880142a3
475 04:51:45.705169 Working FDT set to 88000000
476 04:51:45.718379
477 04:51:45.718841 Starting kernel ...
478 04:51:45.719242
479 04:51:45.720145 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
480 04:51:45.720720 start: 2.4.4 auto-login-action (timeout 00:03:40) [common]
481 04:51:45.721170 Setting prompt string to ['Linux version [0-9]']
482 04:51:45.721607 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
483 04:51:45.722067 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
484 04:51:46.545766 [ 0.000000] Booting Linux on physical CPU 0x0
485 04:51:46.551911 start: 2.4.4.1 login-action (timeout 00:03:39) [common]
486 04:51:46.552525 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
487 04:51:46.553006 Setting prompt string to []
488 04:51:46.553500 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
489 04:51:46.553967 Using line separator: #'\n'#
490 04:51:46.554378 No login prompt set.
491 04:51:46.554805 Parsing kernel messages
492 04:51:46.555204 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
493 04:51:46.555964 [login-action] Waiting for messages, (timeout 00:03:39)
494 04:51:46.556448 Waiting using forced prompt support (timeout 00:01:50)
495 04:51:46.562897 [ 0.000000] Linux version 6.11.0-rc6 (KernelCI@build-j304803-arm-clang-15-multi-v7-defconfig-npc2m) (Debian clang version 15.0.7, Debian LLD 15.0.7) #1 SMP Mon Sep 2 03:53:10 UTC 2024
496 04:51:46.568505 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
497 04:51:46.579944 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
498 04:51:46.585664 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
499 04:51:46.591552 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
500 04:51:46.597246 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
501 04:51:46.603902 [ 0.000000] Memory policy: Data cache writeback
502 04:51:46.604366 [ 0.000000] efi: UEFI not found.
503 04:51:46.612672 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
504 04:51:46.618501 [ 0.000000] Zone ranges:
505 04:51:46.624283 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
506 04:51:46.624731 [ 0.000000] Normal empty
507 04:51:46.630000 [ 0.000000] HighMem empty
508 04:51:46.635731 [ 0.000000] Movable zone start for each node
509 04:51:46.636198 [ 0.000000] Early memory node ranges
510 04:51:46.641396 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
511 04:51:46.651087 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
512 04:51:46.669126 [ 0.000000] CPU: All CPU(s) started in SVC mode.
513 04:51:46.674789 [ 0.000000] AM335X ES2.0 (sgx neon)
514 04:51:46.686556 [ 0.000000] percpu: Embedded 17 pages/cpu s40268 r8192 d21172 u69632
515 04:51:46.704310 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
516 04:51:46.715797 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
517 04:51:46.721540 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
518 04:51:46.727312 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
519 04:51:46.737383 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
520 04:51:46.766442 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
521 04:51:46.772415 <6>[ 0.000000] trace event string verifier disabled
522 04:51:46.772872 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
523 04:51:46.778152 <6>[ 0.000000] rcu: RCU event tracing is enabled.
524 04:51:46.789571 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
525 04:51:46.795342 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
526 04:51:46.802597 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
527 04:51:46.817709 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
528 04:51:46.835708 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
529 04:51:46.842464 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
530 04:51:46.945869 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
531 04:51:46.954458 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
532 04:51:46.966869 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
533 04:51:46.975239 <6>[ 0.019227] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
534 04:51:46.984837 <6>[ 0.034394] Console: colour dummy device 80x30
535 04:51:46.990958 Matched prompt #6: WARNING:
536 04:51:46.991449 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
537 04:51:46.996444 <3>[ 0.039295] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
538 04:51:46.999188 <3>[ 0.046367] This ensures that you still see kernel messages. Please
539 04:51:47.005521 <3>[ 0.053094] update your kernel commandline.
540 04:51:47.045696 <6>[ 0.057708] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
541 04:51:47.051439 <6>[ 0.096233] CPU: Testing write buffer coherency: ok
542 04:51:47.057462 <6>[ 0.101605] CPU0: Spectre v2: using BPIALL workaround
543 04:51:47.057904 <6>[ 0.107069] pid_max: default: 32768 minimum: 301
544 04:51:47.068853 <6>[ 0.112265] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
545 04:51:47.075822 <6>[ 0.120094] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
546 04:51:47.082826 <6>[ 0.129450] CPU0: thread -1, cpu 0, socket -1, mpidr 0
547 04:51:47.091464 <6>[ 0.136360] Setting up static identity map for 0x80300000 - 0x803000ac
548 04:51:47.097086 <6>[ 0.146083] rcu: Hierarchical SRCU implementation.
549 04:51:47.104733 <6>[ 0.151366] rcu: Max phase no-delay instances is 1000.
550 04:51:47.113639 <6>[ 0.162874] EFI services will not be available.
551 04:51:47.119503 <6>[ 0.168149] smp: Bringing up secondary CPUs ...
552 04:51:47.125205 <6>[ 0.173200] smp: Brought up 1 node, 1 CPU
553 04:51:47.130968 <6>[ 0.177600] SMP: Total of 1 processors activated (996.14 BogoMIPS).
554 04:51:47.136921 <6>[ 0.184352] CPU: All CPU(s) started in SVC mode.
555 04:51:47.157278 <6>[ 0.189566] Memory: 405444K/522240K available (17408K kernel code, 2536K rwdata, 6644K rodata, 2048K init, 432K bss, 49592K reserved, 65536K cma-reserved, 0K highmem)
556 04:51:47.157727 <6>[ 0.205834] devtmpfs: initialized
557 04:51:47.180823 <6>[ 0.224239] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
558 04:51:47.192450 <6>[ 0.232857] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
559 04:51:47.198285 <6>[ 0.243297] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
560 04:51:47.208985 <6>[ 0.255586] pinctrl core: initialized pinctrl subsystem
561 04:51:47.218655 <6>[ 0.266584] DMI not present or invalid.
562 04:51:47.226980 <6>[ 0.272457] NET: Registered PF_NETLINK/PF_ROUTE protocol family
563 04:51:47.236530 <6>[ 0.281395] DMA: preallocated 256 KiB pool for atomic coherent allocations
564 04:51:47.251679 <6>[ 0.292970] thermal_sys: Registered thermal governor 'step_wise'
565 04:51:47.252166 <6>[ 0.293130] cpuidle: using governor menu
566 04:51:47.279129 <6>[ 0.328540] No ATAGs?
567 04:51:47.285301 <6>[ 0.331273] hw-breakpoint: debug architecture 0x4 unsupported.
568 04:51:47.295771 <6>[ 0.343545] Serial: AMBA PL011 UART driver
569 04:51:47.335809 <6>[ 0.385251] iommu: Default domain type: Translated
570 04:51:47.344935 <6>[ 0.390597] iommu: DMA domain TLB invalidation policy: strict mode
571 04:51:47.362575 <5>[ 0.410609] SCSI subsystem initialized
572 04:51:47.376729 <6>[ 0.420561] usbcore: registered new interface driver usbfs
573 04:51:47.383698 <6>[ 0.426523] usbcore: registered new interface driver hub
574 04:51:47.384190 <6>[ 0.432345] usbcore: registered new device driver usb
575 04:51:47.389485 <6>[ 0.438912] pps_core: LinuxPPS API ver. 1 registered
576 04:51:47.400905 <6>[ 0.444343] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
577 04:51:47.406055 <6>[ 0.454036] PTP clock support registered
578 04:51:47.443888 <6>[ 0.492745] EDAC MC: Ver: 3.0.0
579 04:51:47.449965 <6>[ 0.496963] scmi_core: SCMI protocol bus registered
580 04:51:47.477044 <6>[ 0.526237] vgaarb: loaded
581 04:51:47.500970 <6>[ 0.550529] clocksource: Switched to clocksource dmtimer
582 04:51:47.531768 <6>[ 0.580957] NET: Registered PF_INET protocol family
583 04:51:47.544533 <6>[ 0.586581] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
584 04:51:47.550316 <6>[ 0.595638] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
585 04:51:47.561802 <6>[ 0.604566] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
586 04:51:47.567581 <6>[ 0.612827] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
587 04:51:47.579071 <6>[ 0.621114] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
588 04:51:47.584939 <6>[ 0.628816] TCP: Hash tables configured (established 4096 bind 4096)
589 04:51:47.590714 <6>[ 0.635736] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
590 04:51:47.596639 <6>[ 0.642776] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
591 04:51:47.603275 <6>[ 0.650390] NET: Registered PF_UNIX/PF_LOCAL protocol family
592 04:51:47.626906 <6>[ 0.670768] RPC: Registered named UNIX socket transport module.
593 04:51:47.627361 <6>[ 0.677154] RPC: Registered udp transport module.
594 04:51:47.632669 <6>[ 0.682316] RPC: Registered tcp transport module.
595 04:51:47.638517 <6>[ 0.687423] RPC: Registered tcp-with-tls transport module.
596 04:51:47.651521 <6>[ 0.693344] RPC: Registered tcp NFSv4.1 backchannel transport module.
597 04:51:47.651967 <6>[ 0.700276] PCI: CLS 0 bytes, default 64
598 04:51:47.658706 <5>[ 0.706145] Initialise system trusted keyrings
599 04:51:47.679234 <6>[ 0.725705] Trying to unpack rootfs image as initramfs...
600 04:51:47.707327 <6>[ 0.750548] workingset: timestamp_bits=30 max_order=17 bucket_order=0
601 04:51:47.711072 <6>[ 0.758017] squashfs: version 4.0 (2009/01/31) Phillip Lougher
602 04:51:47.751152 <5>[ 0.800628] NFS: Registering the id_resolver key type
603 04:51:47.756950 <5>[ 0.806231] Key type id_resolver registered
604 04:51:47.762765 <5>[ 0.810900] Key type id_legacy registered
605 04:51:47.771281 <6>[ 0.815339] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
606 04:51:47.778127 <6>[ 0.822534] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
607 04:51:47.817170 <5>[ 0.866664] Key type asymmetric registered
608 04:51:47.823016 <5>[ 0.871278] Asymmetric key parser 'x509' registered
609 04:51:47.834552 <6>[ 0.876707] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
610 04:51:47.834997 <6>[ 0.884633] io scheduler mq-deadline registered
611 04:51:47.840375 <6>[ 0.889563] io scheduler kyber registered
612 04:51:47.845072 <6>[ 0.894047] io scheduler bfq registered
613 04:51:48.186266 <6>[ 1.231838] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
614 04:51:48.246296 <6>[ 1.295374] msm_serial: driver initialized
615 04:51:48.252181 <6>[ 1.300374] SuperH (H)SCI(F) driver initialized
616 04:51:48.258140 <6>[ 1.305523] STMicroelectronics ASC driver initialized
617 04:51:48.263380 <6>[ 1.311195] STM32 USART driver initialized
618 04:51:48.359948 <6>[ 1.408803] brd: module loaded
619 04:51:48.393197 <6>[ 1.441957] loop: module loaded
620 04:51:48.439920 <6>[ 1.488463] CAN device driver interface
621 04:51:48.446606 <6>[ 1.493769] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
622 04:51:48.452363 <6>[ 1.500850] e1000e: Intel(R) PRO/1000 Network Driver
623 04:51:48.459113 <6>[ 1.506237] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
624 04:51:48.464741 <6>[ 1.512695] igb: Intel(R) Gigabit Ethernet Network Driver
625 04:51:48.472186 <6>[ 1.518517] igb: Copyright (c) 2007-2014 Intel Corporation.
626 04:51:48.483912 <6>[ 1.527718] pegasus: Pegasus/Pegasus II USB Ethernet driver
627 04:51:48.489735 <6>[ 1.533875] usbcore: registered new interface driver pegasus
628 04:51:48.495514 <6>[ 1.540003] usbcore: registered new interface driver asix
629 04:51:48.501279 <6>[ 1.545888] usbcore: registered new interface driver ax88179_178a
630 04:51:48.507051 <6>[ 1.552480] usbcore: registered new interface driver cdc_ether
631 04:51:48.512860 <6>[ 1.558782] usbcore: registered new interface driver smsc75xx
632 04:51:48.518645 <6>[ 1.565022] usbcore: registered new interface driver smsc95xx
633 04:51:48.524385 <6>[ 1.571256] usbcore: registered new interface driver net1080
634 04:51:48.530172 <6>[ 1.577375] usbcore: registered new interface driver cdc_subset
635 04:51:48.536002 <6>[ 1.583799] usbcore: registered new interface driver zaurus
636 04:51:48.543754 <6>[ 1.589869] usbcore: registered new interface driver cdc_ncm
637 04:51:48.553517 <6>[ 1.599346] usbcore: registered new interface driver usb-storage
638 04:51:48.645191 <6>[ 1.692816] i2c_dev: i2c /dev entries driver
639 04:51:48.713351 <5>[ 1.754729] cpuidle: enable-method property 'ti,am3352' found operations
640 04:51:48.719292 <6>[ 1.764354] sdhci: Secure Digital Host Controller Interface driver
641 04:51:48.726768 <6>[ 1.771146] sdhci: Copyright(c) Pierre Ossman
642 04:51:48.734011 <6>[ 1.777587] Synopsys Designware Multimedia Card Interface Driver
643 04:51:48.739501 <6>[ 1.785610] sdhci-pltfm: SDHCI platform and OF driver helper
644 04:51:48.802681 <6>[ 1.848443] ledtrig-cpu: registered to indicate activity on CPUs
645 04:51:48.847343 <6>[ 1.889219] usbcore: registered new interface driver usbhid
646 04:51:48.848102 <6>[ 1.895395] usbhid: USB HID core driver
647 04:51:48.888995 <6>[ 1.936501] NET: Registered PF_INET6 protocol family
648 04:51:48.942582 <6>[ 1.991982] Segment Routing with IPv6
649 04:51:48.948595 <6>[ 1.996128] In-situ OAM (IOAM) with IPv6
650 04:51:48.955198 <6>[ 2.000662] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
651 04:51:48.961007 <6>[ 2.007990] NET: Registered PF_PACKET protocol family
652 04:51:48.966848 <6>[ 2.013554] can: controller area network core
653 04:51:48.972640 <6>[ 2.018386] NET: Registered PF_CAN protocol family
654 04:51:48.973152 <6>[ 2.023620] can: raw protocol
655 04:51:48.978392 <6>[ 2.026947] can: broadcast manager protocol
656 04:51:48.984906 <6>[ 2.031549] can: netlink gateway - max_hops=1
657 04:51:48.991018 <5>[ 2.037046] Key type dns_resolver registered
658 04:51:48.997301 <6>[ 2.042110] ThumbEE CPU extension supported.
659 04:51:48.997804 <5>[ 2.046797] Registering SWP/SWPB emulation handler
660 04:51:49.007009 <3>[ 2.052491] omap_voltage_late_init: Voltage driver support not added
661 04:51:49.091395 <5>[ 2.138399] Loading compiled-in X.509 certificates
662 04:51:49.274942 <6>[ 2.311487] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
663 04:51:49.282151 <6>[ 2.328135] pinctrl-single 44e10800.pinmux: 142 pins, size 568
664 04:51:49.309061 <3>[ 2.352466] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
665 04:51:49.397275 <3>[ 2.440678] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
666 04:51:49.484083 <6>[ 2.531715] OMAP GPIO hardware version 0.1
667 04:51:49.504225 <6>[ 2.550916] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
668 04:51:49.573134 <4>[ 2.618602] at24 2-0054: supply vcc not found, using dummy regulator
669 04:51:49.640855 <4>[ 2.687238] at24 2-0055: supply vcc not found, using dummy regulator
670 04:51:49.694283 <4>[ 2.739737] at24 2-0056: supply vcc not found, using dummy regulator
671 04:51:49.733110 <4>[ 2.778566] at24 2-0057: supply vcc not found, using dummy regulator
672 04:51:49.769716 <6>[ 2.815903] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
673 04:51:49.847664 <3>[ 2.890816] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
674 04:51:49.873469 <6>[ 2.912057] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
675 04:51:49.894748 <4>[ 2.938968] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
676 04:51:49.926336 <4>[ 2.970573] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
677 04:51:50.001574 <6>[ 3.047208] omap_rng 48310000.rng: Random Number Generator ver. 20
678 04:51:50.025436 <5>[ 3.073879] random: crng init done
679 04:51:50.136613 <6>[ 3.180701] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
680 04:51:50.675628 <6>[ 3.723398] Freeing initrd memory: 14992K
681 04:51:50.719156 <6>[ 3.762536] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
682 04:51:50.725051 <6>[ 3.772769] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
683 04:51:50.736740 <6>[ 3.780124] cpsw-switch 4a100000.switch: ALE Table size 1024
684 04:51:50.742599 <6>[ 3.786533] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
685 04:51:50.754106 <6>[ 3.794666] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
686 04:51:50.761659 <6>[ 3.806301] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:c2:c5:7d
687 04:51:50.773700 <5>[ 3.815472] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
688 04:51:50.802230 <3>[ 3.846038] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
689 04:51:50.808183 <6>[ 3.854626] edma 49000000.dma: TI EDMA DMA engine driver
690 04:51:50.880233 <3>[ 3.923847] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
691 04:51:50.894554 <6>[ 3.938292] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
692 04:51:50.913513 <3>[ 3.960397] l3-aon-clkctrl:0000:0: failed to disable
693 04:51:50.947493 <6>[ 3.991246] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
694 04:51:50.953208 <6>[ 4.000711] printk: legacy console [ttyS0] enabled
695 04:51:50.958886 <6>[ 4.000711] printk: legacy console [ttyS0] enabled
696 04:51:50.964572 <6>[ 4.011030] printk: legacy bootconsole [omap8250] disabled
697 04:51:50.970405 <6>[ 4.011030] printk: legacy bootconsole [omap8250] disabled
698 04:51:51.028187 <4>[ 4.070916] tps65217-pmic: Failed to locate of_node [id: -1]
699 04:51:51.031793 <4>[ 4.078318] tps65217-bl: Failed to locate of_node [id: -1]
700 04:51:51.048407 <6>[ 4.098127] tps65217 0-0024: TPS65217 ID 0xe version 1.2
701 04:51:51.066912 <6>[ 4.105112] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
702 04:51:51.078598 <6>[ 4.118891] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
703 04:51:51.084372 <6>[ 4.130787] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
704 04:51:51.107077 <6>[ 4.151120] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
705 04:51:51.112911 <6>[ 4.160278] sdhci-omap 48060000.mmc: Got CD GPIO
706 04:51:51.120927 <4>[ 4.165404] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
707 04:51:51.135818 <4>[ 4.179086] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
708 04:51:51.142247 <4>[ 4.187869] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
709 04:51:51.152196 <4>[ 4.196509] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
710 04:51:51.276251 <6>[ 4.321207] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
711 04:51:51.318816 <6>[ 4.363030] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
712 04:51:51.342236 <6>[ 4.385131] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
713 04:51:51.348963 <6>[ 4.394465] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
714 04:51:51.398450 <6>[ 4.438974] mmc0: new high speed SDHC card at address 0001
715 04:51:51.398995 <6>[ 4.446916] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
716 04:51:51.404560 <4>[ 4.453025] mmc1: unexpected status 0x2000980 after switch
717 04:51:51.417789 <4>[ 4.461367] mmc1: unexpected status 0x2000900 after switch
718 04:51:51.424744 <4>[ 4.467759] mmc1: unexpected status 0x2000900 after switch
719 04:51:51.425270 <6>[ 4.473839] mmcblk0: p1
720 04:51:51.431759 <4>[ 4.477623] mmc1: unexpected status 0x2000900 after switch
721 04:51:51.440275 <6>[ 4.483513] mmc1: new high speed MMC card at address 0001
722 04:51:51.446329 <6>[ 4.491886] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
723 04:51:51.456454 <6>[ 4.497921] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
724 04:51:53.151316 <4>[ 6.193214] mmc1: unexpected status 0x2000980 after switch
725 04:51:53.157569 <4>[ 6.201055] mmc1: unexpected status 0x2000900 after switch
726 04:51:53.159195 <4>[ 6.207580] mmc1: unexpected status 0x2000900 after switch
727 04:51:53.168123 <4>[ 6.214657] mmc1: unexpected status 0x2000900 after switch
728 04:51:53.547381 <6>[ 6.591076] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
729 04:51:53.931698 <5>[ 6.630075] Sending DHCP requests .
730 04:51:53.941267 <3>[ 6.981118] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
731 04:51:54.710312 <3>[ 7.753660] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
732 04:51:55.478955 <3>[ 8.522446] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
733 04:51:56.247552 <3>[ 9.291131] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
734 04:51:57.010404 <4>[ 9.300175] .
735 04:51:57.018503 <3>[ 10.060138] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
736 04:51:57.786980 <3>[ 10.830466] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
737 04:51:58.555189 <3>[ 11.598797] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
738 04:51:59.322997 <3>[ 12.367200] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
739 04:51:59.330019 <3>[ 12.376128] Buffer I/O error on dev mmcblk1, logical block 0, async page read
740 04:52:01.030421 <4>[ 14.024410] ., OK
741 04:52:01.036160 <6>[ 14.082596] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.28
742 04:52:01.041724 <6>[ 14.090756] IP-Config: Complete:
743 04:52:01.050442 <6>[ 14.094292] device=eth0, hwaddr=c8:a0:30:c2:c5:7d, ipaddr=192.168.6.28, mask=255.255.255.0, gw=192.168.6.1
744 04:52:01.056098 <6>[ 14.104817] host=192.168.6.28, domain=, nis-domain=(none)
745 04:52:01.068455 <6>[ 14.111057] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
746 04:52:01.068972 <6>[ 14.111092] nameserver0=10.255.253.1
747 04:52:01.074478 <6>[ 14.123699] clk: Disabling unused clocks
748 04:52:01.080996 <6>[ 14.128310] PM: genpd: Disabling unused power domains
749 04:52:01.100149 <6>[ 14.146562] Freeing unused kernel image (initmem) memory: 2048K
750 04:52:01.107660 <6>[ 14.156346] Run /init as init process
751 04:52:01.130803 Loading, please wait...
752 04:52:01.207073 Starting systemd-udevd version 252.22-1~deb12u1
753 04:52:02.502868 <3>[ 15.546799] I/O error, dev mmcblk1, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
754 04:52:03.242168 <3>[ 16.286170] I/O error, dev mmcblk1, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
755 04:52:03.992007 <3>[ 17.035846] I/O error, dev mmcblk1, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
756 04:52:04.440303 <4>[ 17.482855] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
757 04:52:04.640274 <4>[ 17.682883] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
758 04:52:04.766057 <3>[ 17.809800] I/O error, dev mmcblk1, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
759 04:52:04.800291 <6>[ 17.850288] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
760 04:52:04.811142 <6>[ 17.855967] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
761 04:52:04.843239 <6>[ 17.891664] hub 1-0:1.0: USB hub found
762 04:52:04.909025 <6>[ 17.957399] hub 1-0:1.0: 1 port detected
763 04:52:05.207627 <6>[ 18.255735] tda998x 0-0070: found TDA19988
764 04:52:05.533648 <6>[ 18.579493] usb 1-1: new low-speed USB device number 2 using musb-hdrc
765 04:52:05.585647 <3>[ 18.629505] I/O error, dev mmcblk1, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
766 04:52:05.853403 <3>[ 18.900263] usb 1-1: device descriptor read/64, error -71
767 04:52:06.133541 <3>[ 19.180300] usb 1-1: device descriptor read/64, error -71
768 04:52:06.336538 <3>[ 19.380369] I/O error, dev mmcblk1, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
769 04:52:06.484438 <6>[ 19.530302] usb 1-1: new low-speed USB device number 3 using musb-hdrc
770 04:52:06.643569 <3>[ 19.690373] usb 1-1: device descriptor read/64, error -71
771 04:52:06.947116 <3>[ 19.994020] usb 1-1: device descriptor read/64, error -71
772 04:52:07.075518 <3>[ 20.119378] I/O error, dev mmcblk1, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
773 04:52:07.108601 <6>[ 20.156351] usb usb1-port1: attempt power cycle
774 04:52:07.344489 <6>[ 20.390385] usb 1-1: new low-speed USB device number 4 using musb-hdrc
775 04:52:07.812589 <3>[ 20.857072] I/O error, dev mmcblk1, sector 7 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
776 04:52:07.820810 <3>[ 20.866035] Buffer I/O error on dev mmcblk1, logical block 0, async page read
777 04:52:07.851652 <6>[ 20.899103] mmcblk1: unable to read partition table
778 04:52:07.884061 <6>[ 20.931558] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
779 04:52:07.935944 <6>[ 20.983488] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
780 04:52:07.971811 <6>[ 21.018075] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
781 04:52:08.008671 <6>[ 21.054585] usb 1-1: new low-speed USB device number 5 using musb-hdrc
782 04:52:11.260736 <3>[ 24.303820] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
783 04:52:12.030757 <3>[ 25.073985] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
784 04:52:12.800163 <3>[ 25.843262] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
785 04:52:13.570080 <3>[ 26.613308] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
786 04:52:14.340085 <3>[ 27.383366] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
787 04:52:15.110272 <3>[ 28.153485] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
788 04:52:15.880312 <3>[ 28.923570] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
789 04:52:16.649522 <3>[ 29.692853] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
790 04:52:19.881634 <3>[ 32.925407] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
791 04:52:20.650730 <3>[ 33.694304] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
792 04:52:21.420525 <3>[ 34.464309] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
793 04:52:22.189788 <3>[ 35.233586] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
794 04:52:22.959674 <3>[ 36.003520] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
795 04:52:23.729552 <3>[ 36.773431] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
796 04:52:24.498598 <3>[ 37.542512] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
797 04:52:25.267193 <3>[ 38.312214] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
798 04:52:25.276285 <3>[ 38.321655] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
799 04:52:25.342050 Begin: Loading essential drivers ... done.
800 04:52:25.347469 Begin: Running /scripts/init-premount ... done.
801 04:52:25.353007 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
802 04:52:25.363242 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
803 04:52:25.375108 Device /sys/class/net/eth0 found
804 04:52:25.375601 done.
805 04:52:25.434107 Begin: Waiting up to 180 secs for any network device to become available ... done.
806 04:52:25.502985 IP-Config: eth0 hardware address c8:a0:30:c2:c5:7d mtu 1500 DHCP
807 04:52:25.583688 IP-Config: eth0 guessed broadcast address 192.168.6.255
808 04:52:25.589343 IP-Config: eth0 complete (dhcp from 192.168.6.1):
809 04:52:25.594929 address: 192.168.6.28 broadcast: 192.168.6.255 netmask: 255.255.255.0
810 04:52:25.606005 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
811 04:52:25.606500 rootserver: 192.168.6.1 rootpath:
812 04:52:25.609559 filename :
813 04:52:25.739770 done.
814 04:52:25.746756 Begin: Running /scripts/nfs-bottom ... done.
815 04:52:25.810231 Begin: Running /scripts/init-bottom ... done.
816 04:52:27.204889 <30>[ 40.251265] systemd[1]: System time before build time, advancing clock.
817 04:52:27.374855 <30>[ 40.395086] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
818 04:52:27.388821 <30>[ 40.437033] systemd[1]: Detected architecture arm.
819 04:52:27.402895
820 04:52:27.403411 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
821 04:52:27.403845
822 04:52:27.442677 <30>[ 40.489775] systemd[1]: Hostname set to <debian-bookworm-armhf>.
823 04:52:29.661041 <30>[ 42.706894] systemd[1]: Queued start job for default target graphical.target.
824 04:52:29.678137 <30>[ 42.721851] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
825 04:52:29.685509 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
826 04:52:29.719967 <30>[ 42.762862] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
827 04:52:29.727412 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
828 04:52:29.762403 <30>[ 42.805925] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
829 04:52:29.769779 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
830 04:52:29.807152 <30>[ 42.851965] systemd[1]: Created slice user.slice - User and Session Slice.
831 04:52:29.813861 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
832 04:52:29.850173 <30>[ 42.892294] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
833 04:52:29.863520 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
834 04:52:29.896996 <30>[ 42.941371] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
835 04:52:29.908079 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
836 04:52:29.947613 <30>[ 42.981179] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
837 04:52:29.954099 <30>[ 43.001698] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
838 04:52:29.962645 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
839 04:52:29.995778 <30>[ 43.040471] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
840 04:52:30.004097 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
841 04:52:30.036267 <30>[ 43.081555] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
842 04:52:30.049886 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
843 04:52:30.086499 <30>[ 43.131033] systemd[1]: Reached target paths.target - Path Units.
844 04:52:30.091611 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
845 04:52:30.128967 <30>[ 43.171353] systemd[1]: Reached target remote-fs.target - Remote File Systems.
846 04:52:30.135389 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
847 04:52:30.167236 <30>[ 43.211216] systemd[1]: Reached target slices.target - Slice Units.
848 04:52:30.172697 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
849 04:52:30.206065 <30>[ 43.250795] systemd[1]: Reached target swap.target - Swaps.
850 04:52:30.210211 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
851 04:52:30.246455 <30>[ 43.290804] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
852 04:52:30.254346 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
853 04:52:30.287354 <30>[ 43.331690] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
854 04:52:30.295556 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
855 04:52:30.386716 <30>[ 43.426326] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
856 04:52:30.399367 <30>[ 43.443719] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
857 04:52:30.407771 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
858 04:52:30.438436 <30>[ 43.484342] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
859 04:52:30.451288 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
860 04:52:30.488966 <30>[ 43.532902] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
861 04:52:30.497139 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
862 04:52:30.532738 <30>[ 43.577824] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
863 04:52:30.546336 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
864 04:52:30.577921 <30>[ 43.622258] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
865 04:52:30.586526 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
866 04:52:30.623578 <30>[ 43.661900] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
867 04:52:30.640195 <30>[ 43.678611] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
868 04:52:30.677347 <30>[ 43.722696] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
869 04:52:30.695496 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
870 04:52:30.761060 <30>[ 43.806021] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
871 04:52:30.775905 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
872 04:52:30.849892 <30>[ 43.894108] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
873 04:52:30.875046 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
874 04:52:30.939668 <30>[ 43.984479] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
875 04:52:30.955140 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
876 04:52:31.026249 <30>[ 44.071420] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
877 04:52:31.044835 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
878 04:52:31.106655 <30>[ 44.151260] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
879 04:52:31.113533 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
880 04:52:31.176731 <30>[ 44.221283] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
881 04:52:31.204305 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
882 04:52:31.269326 <30>[ 44.314882] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
883 04:52:31.296565 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
884 04:52:31.359396 <30>[ 44.404900] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
885 04:52:31.386331 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
886 04:52:31.422627 <28>[ 44.462254] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
887 04:52:31.431201 <28>[ 44.475911] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
888 04:52:31.478821 <30>[ 44.524676] systemd[1]: Starting systemd-journald.service - Journal Service...
889 04:52:31.494768 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
890 04:52:31.566023 <30>[ 44.611349] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
891 04:52:31.585205 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
892 04:52:31.665909 <30>[ 44.711529] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
893 04:52:31.707432 Starting [0;1;39msystemd-network-g… units from Kernel command line...
894 04:52:31.767579 <30>[ 44.811477] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
895 04:52:31.825012 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
896 04:52:31.880860 <30>[ 44.925441] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
897 04:52:31.941017 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
898 04:52:32.003476 <30>[ 45.049093] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
899 04:52:32.075999 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
900 04:52:32.107924 <30>[ 45.153115] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
901 04:52:32.137697 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
902 04:52:32.172159 <30>[ 45.216500] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
903 04:52:32.200079 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
904 04:52:32.349167 <30>[ 45.395375] systemd[1]: modprobe@configfs.service: Deactivated successfully.
905 04:52:32.386999 <30>[ 45.431873] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
906 04:52:32.406678 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
907 04:52:32.437131 <30>[ 45.481785] systemd[1]: Started systemd-journald.service - Journal Service.
908 04:52:32.444109 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
909 04:52:32.477089 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
910 04:52:32.521496 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
911 04:52:32.568350 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
912 04:52:32.607111 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
913 04:52:32.645563 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
914 04:52:32.678458 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
915 04:52:32.709342 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
916 04:52:32.728206 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
917 04:52:32.760556 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
918 04:52:32.835433 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
919 04:52:32.888349 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
920 04:52:32.985967 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
921 04:52:33.063341 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
922 04:52:33.184793 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
923 04:52:33.210426 <46>[ 46.255888] systemd-journald[164]: Received client request to flush runtime journal.
924 04:52:33.284076 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
925 04:52:33.416112 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
926 04:52:33.983864 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
927 04:52:34.295250 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
928 04:52:34.358430 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
929 04:52:35.147471 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
930 04:52:35.229256 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
931 04:52:35.268114 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
932 04:52:35.296917 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
933 04:52:35.390729 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
934 04:52:35.459303 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
935 04:52:36.381806 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
936 04:52:36.481183 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
937 04:52:36.846318 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
938 04:52:37.022095 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
939 04:52:37.106164 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
940 04:52:38.312446 <4>[ 51.360313] mmc1: unexpected status 0x2000980 after switch
941 04:52:38.380696 <4>[ 51.428516] mmc1: unexpected status 0x2000900 after switch
942 04:52:38.456860 <4>[ 51.505055] mmc1: unexpected status 0x2000900 after switch
943 04:52:38.513008 <4>[ 51.560998] mmc1: unexpected status 0x2000900 after switch
944 04:52:38.975942 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
945 04:52:39.299017 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
946 04:52:39.999305 <5>[ 53.046271] cfg80211: Loading compiled-in X.509 certificates for regulatory database
947 04:52:40.129099 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
948 04:52:41.546682 <5>[ 54.595805] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
949 04:52:41.559598 <3>[ 54.605051] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
950 04:52:41.600677 <5>[ 54.645319] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
951 04:52:41.606345 <4>[ 54.654131] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
952 04:52:41.613237 <6>[ 54.663238] cfg80211: failed to load regulatory.db
953 04:52:41.825878 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
954 04:52:42.016650 <46>[ 55.053756] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
955 04:52:42.093304 <46>[ 55.133346] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
956 04:52:42.309069 <3>[ 55.354519] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
957 04:52:42.569289 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
958 04:52:43.083515 <3>[ 56.128760] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
959 04:52:43.835251 <3>[ 56.880643] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
960 04:52:44.584951 <3>[ 57.630394] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
961 04:52:45.329931 <3>[ 58.374480] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
962 04:52:46.074234 <3>[ 59.118807] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
963 04:52:46.836377 <3>[ 59.880971] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
964 04:52:49.974990 <3>[ 63.019791] I/O error, dev mmcblk1, sector 3751808 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
965 04:52:50.708827 <3>[ 63.753769] I/O error, dev mmcblk1, sector 3751809 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
966 04:52:51.271336 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
967 04:52:51.306692 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
968 04:52:51.340043 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
969 04:52:51.376422 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
970 04:52:51.480166 <3>[ 64.525088] I/O error, dev mmcblk1, sector 3751810 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
971 04:52:51.578551 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
972 04:52:51.662694 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
973 04:52:51.718166 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
974 04:52:51.790774 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
975 04:52:51.850344 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
976 04:52:51.875622 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
977 04:52:51.923479 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
978 04:52:51.973127 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
979 04:52:52.017734 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
980 04:52:52.065821 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
981 04:52:52.106409 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
982 04:52:52.143732 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
983 04:52:52.180269 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
984 04:52:52.220721 <3>[ 65.265589] I/O error, dev mmcblk1, sector 3751811 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
985 04:52:52.253354 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
986 04:52:52.295884 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
987 04:52:52.324380 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
988 04:52:52.371928 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
989 04:52:52.404325 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
990 04:52:52.440212 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
991 04:52:52.524768 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
992 04:52:52.586948 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
993 04:52:52.725801 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
994 04:52:52.815389 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
995 04:52:52.887381 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
996 04:52:52.957209 <3>[ 66.002212] I/O error, dev mmcblk1, sector 3751812 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
997 04:52:53.028973 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
998 04:52:53.043505 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
999 04:52:53.183512 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1000 04:52:53.246636 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1001 04:52:53.318946 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1002 04:52:53.356583 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1003 04:52:53.387287 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1004 04:52:53.605658 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1005 04:52:53.691463 <3>[ 66.736413] I/O error, dev mmcblk1, sector 3751813 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1006 04:52:53.937250 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1007 04:52:53.996107 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1008 04:52:54.029868 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1009 04:52:54.119967 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1010 04:52:54.326092 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1011 04:52:54.425214 <3>[ 67.470297] I/O error, dev mmcblk1, sector 3751814 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1012 04:52:54.526263
1013 04:52:54.526829 Debian GNU/Linux 12worm-armhf login: root (automatic login)
1014 04:52:54.529538
1015 04:52:54.862242 Linux debian-bookworm-armhf 6.11.0-rc6 #1 SMP Mon Sep 2 03:53:10 UTC 2024 armv7l
1016 04:52:54.862830
1017 04:52:54.867850 The programs included with the Debian GNU/Linux system are free software;
1018 04:52:54.873386 the exact distribution terms for each program are described in the
1019 04:52:54.878986 individual files in /usr/share/doc/*/copyright.
1020 04:52:54.879502
1021 04:52:54.887089 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1022 04:52:54.887620 permitted by applicable law.
1023 04:52:55.170577 <3>[ 68.216609] I/O error, dev mmcblk1, sector 3751815 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
1024 04:52:55.179568 <3>[ 68.226049] Buffer I/O error on dev mmcblk1, logical block 468976, async page read
1025 04:52:59.871229 Unable to match end of the kernel message
1027 04:52:59.873035 Setting prompt string to ['/ #']
1028 04:52:59.873671 end: 2.4.4.1 login-action (duration 00:01:13) [common]
1030 04:52:59.875237 end: 2.4.4 auto-login-action (duration 00:01:14) [common]
1031 04:52:59.875860 start: 2.4.5 expect-shell-connection (timeout 00:02:26) [common]
1032 04:52:59.876423 Setting prompt string to ['/ #']
1033 04:52:59.876900 Forcing a shell prompt, looking for ['/ #']
1035 04:52:59.927974 / #
1036 04:52:59.928677 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1037 04:52:59.929204 Waiting using forced prompt support (timeout 00:02:30)
1038 04:52:59.932686
1039 04:52:59.943147 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1040 04:52:59.943799 start: 2.4.6 export-device-env (timeout 00:02:26) [common]
1041 04:52:59.944382 Sending with 10 millisecond of delay
1043 04:53:04.935708 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5'
1044 04:53:04.947524 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/689582/extract-nfsrootfs-gkg_ljr5'
1045 04:53:04.951813 Sending with 10 millisecond of delay
1047 04:53:07.050200 / # export NFS_SERVER_IP='192.168.6.2'
1048 04:53:07.061123 export NFS_SERVER_IP='192.168.6.2'
1049 04:53:07.062385 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1050 04:53:07.062979 end: 2.4 uboot-commands (duration 00:02:41) [common]
1051 04:53:07.063553 end: 2 uboot-action (duration 00:02:41) [common]
1052 04:53:07.064144 start: 3 lava-test-retry (timeout 00:06:09) [common]
1053 04:53:07.064717 start: 3.1 lava-test-shell (timeout 00:06:09) [common]
1054 04:53:07.065170 Using namespace: common
1056 04:53:07.166298 / # #
1057 04:53:07.166960 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1058 04:53:07.170687 #
1059 04:53:07.178159 Using /lava-689582
1061 04:53:07.279309 / # export SHELL=/bin/bash
1062 04:53:07.284683 export SHELL=/bin/bash
1064 04:53:07.391393 / # . /lava-689582/environment
1065 04:53:07.396378 . /lava-689582/environment
1067 04:53:07.509934 / # /lava-689582/bin/lava-test-runner /lava-689582/0
1068 04:53:07.510596 Test shell timeout: 10s (minimum of the action and connection timeout)
1069 04:53:07.515122 /lava-689582/bin/lava-test-runner /lava-689582/0
1070 04:53:07.899221 + export TESTRUN_ID=0_timesync-off
1071 04:53:07.906759 + TESTRUN_ID=0_timesync-off
1072 04:53:07.907157 + cd /lava-689582/0/tests/0_timesync-off
1073 04:53:07.907374 ++ cat uuid
1074 04:53:07.922519 + UUID=689582_1.6.2.4.1
1075 04:53:07.922800 + set +x
1076 04:53:07.931034 <LAVA_SIGNAL_STARTRUN 0_timesync-off 689582_1.6.2.4.1>
1077 04:53:07.931342 + systemctl stop systemd-timesyncd
1078 04:53:07.931789 Received signal: <STARTRUN> 0_timesync-off 689582_1.6.2.4.1
1079 04:53:07.932039 Starting test lava.0_timesync-off (689582_1.6.2.4.1)
1080 04:53:07.932559 Skipping test definition patterns.
1081 04:53:08.214327 + set +x
1082 04:53:08.214696 <LAVA_SIGNAL_ENDRUN 0_timesync-off 689582_1.6.2.4.1>
1083 04:53:08.215129 Received signal: <ENDRUN> 0_timesync-off 689582_1.6.2.4.1
1084 04:53:08.215399 Ending use of test pattern.
1085 04:53:08.215611 Ending test lava.0_timesync-off (689582_1.6.2.4.1), duration 0.28
1087 04:53:08.383573 + export TESTRUN_ID=1_kselftest-dt
1088 04:53:08.391292 + TESTRUN_ID=1_kselftest-dt
1089 04:53:08.391569 + cd /lava-689582/0/tests/1_kselftest-dt
1090 04:53:08.391786 ++ cat uuid
1091 04:53:08.406662 + UUID=689582_1.6.2.4.5
1092 04:53:08.406937 + set +x
1093 04:53:08.412320 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 689582_1.6.2.4.5>
1094 04:53:08.412856 + cd ./automated/linux/kselftest/
1095 04:53:08.413543 Received signal: <STARTRUN> 1_kselftest-dt 689582_1.6.2.4.5
1096 04:53:08.413997 Starting test lava.1_kselftest-dt (689582_1.6.2.4.5)
1097 04:53:08.414585 Skipping test definition patterns.
1098 04:53:08.440431 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1099 04:53:08.540081 INFO: install_deps skipped
1100 04:53:09.225394 --2024-09-02 04:53:09-- http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-15/kselftest.tar.xz
1101 04:53:09.482854 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1102 04:53:09.624024 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1103 04:53:09.764325 HTTP request sent, awaiting response... 200 OK
1104 04:53:09.764889 Length: 2104336 (2.0M) [application/octet-stream]
1105 04:53:09.769896 Saving to: 'kselftest_armhf.tar.gz'
1106 04:53:09.770363
1107 04:53:12.067632
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1108 04:53:12.068688
1109 04:53:12.441563 2024-09-02 04:53:12 (897 KB/s) - 'kselftest_armhf.tar.gz' saved [2104336/2104336]
1110 04:53:12.442234
1111 04:53:21.338895 skiplist:
1112 04:53:21.339638 ========================================
1113 04:53:21.343756 ========================================
1114 04:53:21.442100 dt:test_unprobed_devices.sh
1115 04:53:21.470722 ============== Tests to run ===============
1116 04:53:21.480146 dt:test_unprobed_devices.sh
1117 04:53:21.483113 ===========End Tests to run ===============
1118 04:53:21.493791 shardfile-dt pass
1119 04:53:21.709946 <12>[ 94.761871] kselftest: Running tests in dt
1120 04:53:21.739779 TAP version 13
1121 04:53:21.762334 1..1
1122 04:53:21.817676 # timeout set to 45
1123 04:53:21.818174 # selftests: dt: test_unprobed_devices.sh
1124 04:53:22.696457 # TAP version 13
1125 04:53:35.053471 # 1..255
1126 04:53:35.225558 # ok 1 / # SKIP
1127 04:53:35.248433 # ok 2 /clk_mcasp0
1128 04:53:35.319642 # ok 3 /clk_mcasp0_fixed # SKIP
1129 04:53:35.388600 # ok 4 /cpus/cpu@0 # SKIP
1130 04:53:35.458568 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1131 04:53:35.484465 # ok 6 /fixedregulator0
1132 04:53:35.504903 # ok 7 /leds
1133 04:53:35.521873 # ok 8 /ocp
1134 04:53:35.545887 # ok 9 /ocp/interconnect@44c00000
1135 04:53:35.569417 # ok 10 /ocp/interconnect@44c00000/segment@0
1136 04:53:35.592473 # ok 11 /ocp/interconnect@44c00000/segment@100000
1137 04:53:35.620458 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1138 04:53:35.691946 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1139 04:53:35.713951 # ok 14 /ocp/interconnect@44c00000/segment@200000
1140 04:53:35.739562 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1141 04:53:35.841372 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1142 04:53:35.915710 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1143 04:53:35.988891 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1144 04:53:36.060825 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1145 04:53:36.132769 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1146 04:53:36.204724 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1147 04:53:36.267236 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1148 04:53:36.347291 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1149 04:53:36.410706 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1150 04:53:36.484236 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1151 04:53:36.560887 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1152 04:53:36.634590 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1153 04:53:36.704247 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1154 04:53:36.776170 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1155 04:53:36.843417 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1156 04:53:36.919875 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1157 04:53:36.992486 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1158 04:53:37.065394 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1159 04:53:37.128274 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1160 04:53:37.204691 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1161 04:53:37.278657 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1162 04:53:37.353199 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1163 04:53:37.419036 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1164 04:53:37.497626 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1165 04:53:37.564494 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1166 04:53:37.644066 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1167 04:53:37.708688 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1168 04:53:37.788269 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1169 04:53:37.855185 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1170 04:53:37.933853 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1171 04:53:37.999205 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1172 04:53:38.077996 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1173 04:53:38.150693 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1174 04:53:38.223359 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1175 04:53:38.294598 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1176 04:53:38.364845 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1177 04:53:38.438165 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1178 04:53:38.513356 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1179 04:53:38.582210 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1180 04:53:38.656913 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1181 04:53:38.732297 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1182 04:53:38.805045 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1183 04:53:38.876726 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1184 04:53:38.940692 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1185 04:53:39.017405 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1186 04:53:39.089747 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1187 04:53:39.164080 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1188 04:53:39.228043 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1189 04:53:39.308087 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1190 04:53:39.369832 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1191 04:53:39.445274 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1192 04:53:39.524372 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1193 04:53:39.594822 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1194 04:53:39.658110 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1195 04:53:39.737873 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1196 04:53:39.810398 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1197 04:53:39.885465 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1198 04:53:39.948037 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1199 04:53:40.027711 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1200 04:53:40.102685 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1201 04:53:40.175259 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1202 04:53:40.238931 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1203 04:53:40.317577 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1204 04:53:40.384093 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1205 04:53:40.463309 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1206 04:53:40.528357 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1207 04:53:40.606703 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1208 04:53:40.670284 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1209 04:53:40.744858 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1210 04:53:40.822171 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1211 04:53:40.887676 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1212 04:53:40.966562 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1213 04:53:41.031011 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1214 04:53:41.114589 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1215 04:53:41.186206 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1216 04:53:41.256575 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1217 04:53:41.326774 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1218 04:53:41.404191 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1219 04:53:41.470317 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1220 04:53:41.494814 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1221 04:53:41.521827 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1222 04:53:41.544843 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1223 04:53:41.562370 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1224 04:53:41.594482 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1225 04:53:41.612643 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1226 04:53:41.642681 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1227 04:53:41.662208 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1228 04:53:41.763724 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1229 04:53:41.791756 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1230 04:53:41.819935 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1231 04:53:41.845115 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1232 04:53:41.944691 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1233 04:53:42.026692 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1234 04:53:42.098127 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1235 04:53:42.167966 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1236 04:53:42.243545 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1237 04:53:42.313492 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1238 04:53:42.386199 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1239 04:53:42.458679 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1240 04:53:42.525668 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1241 04:53:42.605292 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1242 04:53:42.676210 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1243 04:53:42.749717 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1244 04:53:42.822451 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1245 04:53:42.897104 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1246 04:53:42.969804 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1247 04:53:43.044394 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1248 04:53:43.057529 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1249 04:53:43.136021 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1250 04:53:43.203290 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1251 04:53:43.272753 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1252 04:53:43.293753 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1253 04:53:43.373626 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1254 04:53:43.391376 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1255 04:53:43.463037 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1256 04:53:43.489196 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1257 04:53:43.511157 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1258 04:53:43.539157 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1259 04:53:43.561809 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1260 04:53:43.583692 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1261 04:53:43.609693 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1262 04:53:43.636373 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1263 04:53:43.658605 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1264 04:53:43.684793 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1265 04:53:43.749967 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1266 04:53:43.830913 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1267 04:53:43.845105 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1268 04:53:43.922984 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1269 04:53:43.993292 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1270 04:53:44.089834 # not ok 145 /ocp/interconnect@47c00000
1271 04:53:44.162548 # not ok 146 /ocp/interconnect@47c00000/segment@0
1272 04:53:44.184430 # ok 147 /ocp/interconnect@48000000
1273 04:53:44.211223 # ok 148 /ocp/interconnect@48000000/segment@0
1274 04:53:44.233373 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1275 04:53:44.263326 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1276 04:53:44.279247 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1277 04:53:44.307407 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1278 04:53:44.332424 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1279 04:53:44.350324 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1280 04:53:44.379227 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1281 04:53:44.452997 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1282 04:53:44.521031 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1283 04:53:44.549099 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1284 04:53:44.565860 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1285 04:53:44.590667 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1286 04:53:44.619209 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1287 04:53:44.642373 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1288 04:53:44.660369 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1289 04:53:44.689659 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1290 04:53:44.713263 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1291 04:53:44.730826 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1292 04:53:44.759755 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1293 04:53:44.777413 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1294 04:53:44.802595 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1295 04:53:44.829955 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1296 04:53:44.848335 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1297 04:53:44.880445 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1298 04:53:44.895338 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1299 04:53:44.921583 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1300 04:53:44.947634 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1301 04:53:44.973215 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1302 04:53:44.992352 # ok 177 /ocp/interconnect@48000000/segment@100000
1303 04:53:45.018940 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1304 04:53:45.042091 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1305 04:53:45.111043 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1306 04:53:45.183894 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1307 04:53:45.253859 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1308 04:53:45.325276 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1309 04:53:45.350554 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1310 04:53:45.374333 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1311 04:53:45.389035 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1312 04:53:45.418091 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1313 04:53:45.443707 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1314 04:53:45.465189 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1315 04:53:45.489452 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1316 04:53:45.514590 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1317 04:53:45.532179 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1318 04:53:45.559650 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1319 04:53:45.583646 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1320 04:53:45.602727 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1321 04:53:45.627317 # ok 196 /ocp/interconnect@48000000/segment@200000
1322 04:53:45.652217 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1323 04:53:45.722198 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1324 04:53:45.747278 # ok 199 /ocp/interconnect@48000000/segment@300000
1325 04:53:45.770335 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1326 04:53:45.793698 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1327 04:53:45.813112 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1328 04:53:45.840203 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1329 04:53:45.858093 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1330 04:53:45.888072 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1331 04:53:45.960223 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1332 04:53:45.978511 # ok 207 /ocp/interconnect@4a000000
1333 04:53:45.996764 # ok 208 /ocp/interconnect@4a000000/segment@0
1334 04:53:46.026418 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1335 04:53:46.053291 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1336 04:53:46.072542 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1337 04:53:46.101255 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1338 04:53:46.165732 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1339 04:53:46.273895 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1340 04:53:46.344670 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1341 04:53:46.452961 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1342 04:53:46.523312 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1343 04:53:46.594939 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1344 04:53:46.685334 # not ok 219 /ocp/interconnect@4b140000
1345 04:53:46.757582 # not ok 220 /ocp/interconnect@4b140000/segment@0
1346 04:53:46.828244 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1347 04:53:46.857139 # ok 222 /ocp/target-module@40300000
1348 04:53:46.873139 # ok 223 /ocp/target-module@40300000/sram@0
1349 04:53:46.948450 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1350 04:53:47.016377 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1351 04:53:47.037946 # ok 226 /ocp/target-module@47400000
1352 04:53:47.063062 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1353 04:53:47.088412 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1354 04:53:47.108936 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1355 04:53:47.135086 # ok 230 /ocp/target-module@47400000/usb@1400
1356 04:53:47.153843 # ok 231 /ocp/target-module@47400000/usb@1800
1357 04:53:47.178439 # ok 232 /ocp/target-module@47810000
1358 04:53:47.204209 # ok 233 /ocp/target-module@49000000
1359 04:53:47.226566 # ok 234 /ocp/target-module@49000000/dma@0
1360 04:53:47.247298 # ok 235 /ocp/target-module@49800000
1361 04:53:47.272697 # ok 236 /ocp/target-module@49800000/dma@0
1362 04:53:47.294317 # ok 237 /ocp/target-module@49900000
1363 04:53:47.318047 # ok 238 /ocp/target-module@49900000/dma@0
1364 04:53:47.336358 # ok 239 /ocp/target-module@49a00000
1365 04:53:47.358482 # ok 240 /ocp/target-module@49a00000/dma@0
1366 04:53:47.385822 # ok 241 /ocp/target-module@4c000000
1367 04:53:47.456876 # not ok 242 /ocp/target-module@4c000000/emif@0
1368 04:53:47.477415 # ok 243 /ocp/target-module@50000000
1369 04:53:47.496938 # ok 244 /ocp/target-module@53100000
1370 04:53:47.570346 # not ok 245 /ocp/target-module@53100000/sham@0
1371 04:53:47.590211 # ok 246 /ocp/target-module@53500000
1372 04:53:47.666739 # not ok 247 /ocp/target-module@53500000/aes@0
1373 04:53:47.683532 # ok 248 /ocp/target-module@56000000
1374 04:53:47.788668 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1375 04:53:47.856632 # ok 250 /opp-table # SKIP
1376 04:53:47.923906 # ok 251 /soc # SKIP
1377 04:53:47.951464 # ok 252 /sound
1378 04:53:47.970637 # ok 253 /target-module@4b000000
1379 04:53:47.994883 # ok 254 /target-module@4b000000/target-module@140000
1380 04:53:48.016362 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1381 04:53:48.024563 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1382 04:53:48.032847 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1383 04:53:50.207478 dt_test_unprobed_devices_sh_ skip
1384 04:53:50.213089 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1385 04:53:50.218859 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1386 04:53:50.219390 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1387 04:53:50.224257 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1388 04:53:50.229898 dt_test_unprobed_devices_sh_fixedregulator0 pass
1389 04:53:50.235437 dt_test_unprobed_devices_sh_leds pass
1390 04:53:50.235933 dt_test_unprobed_devices_sh_ocp pass
1391 04:53:50.241114 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1392 04:53:50.246696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1393 04:53:50.252281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1394 04:53:50.263420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1395 04:53:50.269101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1396 04:53:50.274680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1397 04:53:50.285801 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1398 04:53:50.291585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1399 04:53:50.302675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1400 04:53:50.313935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1401 04:53:50.325184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1402 04:53:50.330681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1403 04:53:50.341876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1404 04:53:50.353089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1405 04:53:50.364274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1406 04:53:50.375581 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1407 04:53:50.381103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1408 04:53:50.392269 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1409 04:53:50.403478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1410 04:53:50.414627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1411 04:53:50.425854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1412 04:53:50.431488 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1413 04:53:50.442651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1414 04:53:50.453832 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1415 04:53:50.465022 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1416 04:53:50.470624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1417 04:53:50.481758 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1418 04:53:50.492995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1419 04:53:50.504202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1420 04:53:50.515374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1421 04:53:50.520985 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1422 04:53:50.532195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1423 04:53:50.543326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1424 04:53:50.554638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1425 04:53:50.565738 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1426 04:53:50.576874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1427 04:53:50.588154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1428 04:53:50.599294 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1429 04:53:50.610501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1430 04:53:50.621682 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1431 04:53:50.632880 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1432 04:53:50.644077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1433 04:53:50.655246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1434 04:53:50.666483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1435 04:53:50.677604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1436 04:53:50.688826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1437 04:53:50.700051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1438 04:53:50.711169 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1439 04:53:50.722396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1440 04:53:50.733644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1441 04:53:50.744783 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1442 04:53:50.755938 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1443 04:53:50.767126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1444 04:53:50.778349 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1445 04:53:50.789527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1446 04:53:50.800716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1447 04:53:50.806351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1448 04:53:50.817523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1449 04:53:50.828710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1450 04:53:50.839883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1451 04:53:50.851095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1452 04:53:50.862278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1453 04:53:50.873452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1454 04:53:50.884658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1455 04:53:50.895844 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1456 04:53:50.907117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1457 04:53:50.918217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1458 04:53:50.929442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1459 04:53:50.940658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1460 04:53:50.951813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1461 04:53:50.963008 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1462 04:53:50.974175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1463 04:53:50.985365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1464 04:53:50.996555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1465 04:53:51.002202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1466 04:53:51.013352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1467 04:53:51.024540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1468 04:53:51.035712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1469 04:53:51.046937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1470 04:53:51.052593 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1471 04:53:51.069293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1472 04:53:51.080539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1473 04:53:51.086128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1474 04:53:51.102871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1475 04:53:51.114061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1476 04:53:51.125246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1477 04:53:51.130873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1478 04:53:51.142016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1479 04:53:51.153213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1480 04:53:51.158862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1481 04:53:51.169972 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1482 04:53:51.181237 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1483 04:53:51.186817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1484 04:53:51.197989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1485 04:53:51.203609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1486 04:53:51.214760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1487 04:53:51.225982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1488 04:53:51.237138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1489 04:53:51.248310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1490 04:53:51.259579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1491 04:53:51.270761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1492 04:53:51.281902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1493 04:53:51.293117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1494 04:53:51.304310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1495 04:53:51.315489 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1496 04:53:51.326714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1497 04:53:51.337885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1498 04:53:51.354725 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1499 04:53:51.365865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1500 04:53:51.377068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1501 04:53:51.388229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1502 04:53:51.399427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1503 04:53:51.416216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1504 04:53:51.427422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1505 04:53:51.438601 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1506 04:53:51.449791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1507 04:53:51.455423 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1508 04:53:51.466623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1509 04:53:51.477776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1510 04:53:51.483380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1511 04:53:51.494529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1512 04:53:51.500180 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1513 04:53:51.511328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1514 04:53:51.516958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1515 04:53:51.528145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1516 04:53:51.533791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1517 04:53:51.544897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1518 04:53:51.550517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1519 04:53:51.561755 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1520 04:53:51.572904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1521 04:53:51.584078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1522 04:53:51.589773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1523 04:53:51.600883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1524 04:53:51.612083 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1525 04:53:51.617870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1526 04:53:51.628857 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1527 04:53:51.634503 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1528 04:53:51.640111 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1529 04:53:51.645682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1530 04:53:51.651281 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1531 04:53:51.662407 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1532 04:53:51.668108 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1533 04:53:51.676477 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1534 04:53:51.684866 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1535 04:53:51.690390 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1536 04:53:51.701644 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1537 04:53:51.707211 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1538 04:53:51.718375 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1539 04:53:51.724009 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1540 04:53:51.729621 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1541 04:53:51.740733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1542 04:53:51.746374 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1543 04:53:51.757510 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1544 04:53:51.763112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1545 04:53:51.774274 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1546 04:53:51.779890 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1547 04:53:51.791091 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1548 04:53:51.796725 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1549 04:53:51.807889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1550 04:53:51.813502 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1551 04:53:51.824759 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1552 04:53:51.830293 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1553 04:53:51.841468 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1554 04:53:51.847043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1555 04:53:51.852738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1556 04:53:51.863848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1557 04:53:51.869453 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1558 04:53:51.880636 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1559 04:53:51.886240 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1560 04:53:51.897459 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1561 04:53:51.903034 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1562 04:53:51.914205 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1563 04:53:51.925401 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1564 04:53:51.936640 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1565 04:53:51.942182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1566 04:53:51.953391 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1567 04:53:51.958972 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1568 04:53:51.970162 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1569 04:53:51.975788 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1570 04:53:51.986907 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1571 04:53:51.992517 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1572 04:53:52.003780 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1573 04:53:52.014928 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1574 04:53:52.020497 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1575 04:53:52.031783 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1576 04:53:52.037306 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1577 04:53:52.048471 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1578 04:53:52.054072 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1579 04:53:52.059665 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1580 04:53:52.070849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1581 04:53:52.076448 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1582 04:53:52.082041 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1583 04:53:52.093235 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1584 04:53:52.098853 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1585 04:53:52.110038 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1586 04:53:52.115669 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1587 04:53:52.126857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1588 04:53:52.132430 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1589 04:53:52.138020 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1590 04:53:52.143577 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1591 04:53:52.154806 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1592 04:53:52.160387 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1593 04:53:52.171581 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1594 04:53:52.177188 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1595 04:53:52.188359 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1596 04:53:52.199530 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1597 04:53:52.210816 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1598 04:53:52.216329 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1599 04:53:52.227549 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1600 04:53:52.238824 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1601 04:53:52.244308 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1602 04:53:52.249915 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1603 04:53:52.255529 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1604 04:53:52.261092 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1605 04:53:52.266741 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1606 04:53:52.272353 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1607 04:53:52.283528 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1608 04:53:52.289139 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1609 04:53:52.294833 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1610 04:53:52.300337 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1611 04:53:52.306084 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1612 04:53:52.311702 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1613 04:53:52.317258 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1614 04:53:52.322905 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1615 04:53:52.328493 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1616 04:53:52.334037 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1617 04:53:52.339703 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1618 04:53:52.345252 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1619 04:53:52.350875 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1620 04:53:52.356478 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1621 04:53:52.362048 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1622 04:53:52.367665 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1623 04:53:52.373269 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1624 04:53:52.378879 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1625 04:53:52.384449 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1626 04:53:52.390098 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1627 04:53:52.395753 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1628 04:53:52.401263 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1629 04:53:52.406858 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1630 04:53:52.412435 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1631 04:53:52.418063 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1632 04:53:52.423691 dt_test_unprobed_devices_sh_opp-table skip
1633 04:53:52.429265 dt_test_unprobed_devices_sh_soc skip
1634 04:53:52.429722 dt_test_unprobed_devices_sh_sound pass
1635 04:53:52.434868 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1636 04:53:52.440499 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1637 04:53:52.451688 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1638 04:53:52.452183 dt_test_unprobed_devices_sh fail
1639 04:53:52.457277 + ../../utils/send-to-lava.sh ./output/result.txt
1640 04:53:52.462686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1641 04:53:52.463558 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1643 04:53:52.526798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1644 04:53:52.527570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1646 04:53:52.619369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1647 04:53:52.620112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1649 04:53:52.710389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1650 04:53:52.711182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1652 04:53:52.802237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1653 04:53:52.803019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1655 04:53:52.893569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1656 04:53:52.894373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1658 04:53:52.981018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1659 04:53:52.981585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1661 04:53:53.063159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1662 04:53:53.063950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1664 04:53:53.147246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1665 04:53:53.148037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1667 04:53:53.234031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1668 04:53:53.234808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1670 04:53:53.326270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1671 04:53:53.327084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1673 04:53:53.416499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1674 04:53:53.417272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1676 04:53:53.502307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1677 04:53:53.503071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1679 04:53:53.588588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1680 04:53:53.589374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1682 04:53:53.676563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1683 04:53:53.677341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1685 04:53:53.762355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1686 04:53:53.763127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1688 04:53:53.853447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1689 04:53:53.854222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1691 04:53:53.939600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1692 04:53:53.940402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1694 04:53:54.026780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1695 04:53:54.027555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1697 04:53:54.115412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1698 04:53:54.116188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1700 04:53:54.206928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1701 04:53:54.207692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1703 04:53:54.298171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1704 04:53:54.298933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1706 04:53:54.389685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1707 04:53:54.390462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1709 04:53:54.480447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1710 04:53:54.481209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1712 04:53:54.570221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1713 04:53:54.570998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1715 04:53:54.660207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1716 04:53:54.660996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1718 04:53:54.745113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1719 04:53:54.745885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1721 04:53:54.836780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1722 04:53:54.837603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1724 04:53:54.927086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1725 04:53:54.927884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1727 04:53:55.012799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1728 04:53:55.013614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1730 04:53:55.102668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1731 04:53:55.103489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1733 04:53:55.188480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1734 04:53:55.189429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1736 04:53:55.277706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1737 04:53:55.278639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1739 04:53:55.370602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1740 04:53:55.371454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1742 04:53:55.454602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1743 04:53:55.455380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1745 04:53:55.541165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1746 04:53:55.541936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1748 04:53:55.624227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1749 04:53:55.625011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1751 04:53:55.707668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1752 04:53:55.708625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1754 04:53:55.792388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1755 04:53:55.793296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1757 04:53:55.878155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1758 04:53:55.879208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1760 04:53:55.969218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1761 04:53:55.970092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1763 04:53:56.059291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1764 04:53:56.060121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1766 04:53:56.149494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1767 04:53:56.150339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1769 04:53:56.234113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1770 04:53:56.234953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1772 04:53:56.318819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1773 04:53:56.319647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1775 04:53:56.410619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1776 04:53:56.411432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1778 04:53:56.495377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1779 04:53:56.496227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1781 04:53:56.586560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1782 04:53:56.587403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1784 04:53:56.671595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1785 04:53:56.672451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1787 04:53:56.762994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1788 04:53:56.763829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1790 04:53:56.847197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1791 04:53:56.848037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1793 04:53:56.938875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1794 04:53:56.939706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1796 04:53:57.023885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1797 04:53:57.024830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1799 04:53:57.110730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1800 04:53:57.111687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1802 04:53:57.202110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1803 04:53:57.202961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1805 04:53:57.285874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1806 04:53:57.286795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1808 04:53:57.379605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1809 04:53:57.380522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1811 04:53:57.472364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1812 04:53:57.473280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1814 04:53:57.562646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1815 04:53:57.563528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1817 04:53:57.648656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1818 04:53:57.649534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1820 04:53:57.739942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1821 04:53:57.741019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1823 04:53:57.830655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1824 04:53:57.831686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1826 04:53:57.915929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1827 04:53:57.916764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1829 04:53:58.007126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1830 04:53:58.007939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1832 04:53:58.098054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1833 04:53:58.098851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1835 04:53:58.188234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1836 04:53:58.189036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1838 04:53:58.282354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1839 04:53:58.283340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1841 04:53:58.372961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1842 04:53:58.373765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1844 04:53:58.456197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1845 04:53:58.457004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1847 04:53:58.546874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1848 04:53:58.547675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1850 04:53:58.638440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1851 04:53:58.639232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1853 04:53:58.722937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1854 04:53:58.723739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1856 04:53:58.814092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1857 04:53:58.814891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1859 04:53:58.898044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1860 04:53:58.899039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1862 04:53:58.982459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1863 04:53:58.983463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1865 04:53:59.067271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1866 04:53:59.068086 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1868 04:53:59.157720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1869 04:53:59.158521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1871 04:53:59.242927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1872 04:53:59.243725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1874 04:53:59.332618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1875 04:53:59.333415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1877 04:53:59.417221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1878 04:53:59.418020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1880 04:53:59.508846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1881 04:53:59.509637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1883 04:53:59.600201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1884 04:53:59.601000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1886 04:53:59.690643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1887 04:53:59.691490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1889 04:53:59.779123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1890 04:53:59.779948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1892 04:53:59.870467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1893 04:53:59.871275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1895 04:53:59.956893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1896 04:53:59.957729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1898 04:54:00.049095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1899 04:54:00.049913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1901 04:54:00.133228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1902 04:54:00.134037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1904 04:54:00.217967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1905 04:54:00.218977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1907 04:54:00.304354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1908 04:54:00.305170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1910 04:54:00.395600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1911 04:54:00.396447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1913 04:54:00.483777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1914 04:54:00.484613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1916 04:54:00.571187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1917 04:54:00.572001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1919 04:54:00.661098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1920 04:54:00.661914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1922 04:54:00.745752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1923 04:54:00.746556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1925 04:54:00.835190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1926 04:54:00.836228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1928 04:54:00.919632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1929 04:54:00.920175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1931 04:54:01.010366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1932 04:54:01.011009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1934 04:54:01.093421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1935 04:54:01.094411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1937 04:54:01.184913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1938 04:54:01.186041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1940 04:54:01.270225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1941 04:54:01.271180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1943 04:54:01.360061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1944 04:54:01.360883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1946 04:54:01.443630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1947 04:54:01.444491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1949 04:54:01.534615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1950 04:54:01.535430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1952 04:54:01.626368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1953 04:54:01.627180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1955 04:54:01.719568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1956 04:54:01.720398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1958 04:54:01.808895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1959 04:54:01.809887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1961 04:54:01.892273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1962 04:54:01.893071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1964 04:54:01.977631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1965 04:54:01.978432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1967 04:54:02.061265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1968 04:54:02.062045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1970 04:54:02.145078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1971 04:54:02.145860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1973 04:54:02.239165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1974 04:54:02.240465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1976 04:54:02.332450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1977 04:54:02.333181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1979 04:54:02.417147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1980 04:54:02.418214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1982 04:54:02.502450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1983 04:54:02.503303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1985 04:54:02.592957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1986 04:54:02.593756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1988 04:54:02.678372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1989 04:54:02.679138 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1991 04:54:02.769472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1992 04:54:02.770238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1994 04:54:02.853556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1995 04:54:02.854329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1997 04:54:02.944561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1998 04:54:02.945333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2000 04:54:03.035336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2002 04:54:03.038396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2003 04:54:03.121505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2005 04:54:03.124575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2006 04:54:03.212103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2008 04:54:03.215130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2009 04:54:03.299575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2010 04:54:03.300444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2012 04:54:03.390092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2013 04:54:03.390918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2015 04:54:03.479599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2016 04:54:03.480466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2018 04:54:03.565001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2019 04:54:03.565783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2021 04:54:03.656995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2022 04:54:03.657795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2024 04:54:03.742488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2025 04:54:03.743335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2027 04:54:03.827697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2028 04:54:03.828592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2030 04:54:03.917881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2031 04:54:03.918682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2033 04:54:04.000838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2034 04:54:04.001627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2036 04:54:04.086932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2037 04:54:04.087771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2039 04:54:04.176457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2040 04:54:04.177293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2042 04:54:04.267167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2043 04:54:04.268233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2045 04:54:04.357910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2046 04:54:04.358922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2048 04:54:04.448870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2049 04:54:04.449875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2051 04:54:04.536307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2052 04:54:04.537310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2054 04:54:04.627268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2055 04:54:04.628095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2057 04:54:04.716372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2058 04:54:04.717189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2060 04:54:04.802940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2061 04:54:04.803740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2063 04:54:04.894474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2064 04:54:04.895278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2066 04:54:04.982184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2067 04:54:04.982985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2069 04:54:05.068558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2070 04:54:05.069366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2072 04:54:05.150903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2073 04:54:05.151703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2075 04:54:05.231032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2076 04:54:05.231821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2078 04:54:05.315403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2079 04:54:05.316198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2081 04:54:05.397493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2082 04:54:05.398291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2084 04:54:05.481659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2085 04:54:05.482440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2087 04:54:05.566867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2088 04:54:05.567652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2090 04:54:05.650850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2091 04:54:05.651646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2093 04:54:05.734373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2094 04:54:05.735373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2096 04:54:05.827486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2097 04:54:05.828316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2099 04:54:05.916887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2100 04:54:05.917878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2102 04:54:06.003399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2103 04:54:06.004207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2105 04:54:06.087631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2106 04:54:06.088456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2108 04:54:06.176134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2109 04:54:06.176927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2111 04:54:06.260732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2112 04:54:06.261727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2114 04:54:06.349804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2115 04:54:06.350794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2117 04:54:06.434334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2118 04:54:06.435131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2120 04:54:06.524199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2121 04:54:06.525004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2123 04:54:06.610367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2124 04:54:06.611168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2126 04:54:06.699323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2127 04:54:06.700339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2129 04:54:06.785652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2130 04:54:06.786462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2132 04:54:06.875784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2133 04:54:06.876608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2135 04:54:06.967849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2136 04:54:06.968681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2138 04:54:07.057178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2139 04:54:07.057980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2141 04:54:07.147459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2142 04:54:07.148296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2144 04:54:07.237461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2145 04:54:07.238264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2147 04:54:07.323173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2148 04:54:07.324102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2150 04:54:07.416464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2151 04:54:07.417318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2153 04:54:07.508099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2154 04:54:07.508893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2156 04:54:07.592427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2157 04:54:07.593269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2159 04:54:07.682930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2160 04:54:07.683711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2162 04:54:07.768719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2163 04:54:07.769510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2165 04:54:07.852428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2166 04:54:07.853408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2168 04:54:07.938511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2169 04:54:07.939292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2171 04:54:08.020246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2172 04:54:08.021037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2174 04:54:08.105595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2175 04:54:08.106373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2177 04:54:08.199187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2178 04:54:08.199970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2180 04:54:08.285245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2181 04:54:08.286028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2183 04:54:08.376557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2184 04:54:08.377339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2186 04:54:08.466650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2187 04:54:08.467423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2189 04:54:08.551853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2190 04:54:08.552657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2192 04:54:08.640343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2193 04:54:08.641252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2195 04:54:08.725313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2196 04:54:08.726153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2198 04:54:08.816362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2199 04:54:08.817170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2201 04:54:08.907924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2202 04:54:08.908760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2204 04:54:08.997379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2205 04:54:08.998276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2207 04:54:09.090880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2208 04:54:09.092693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2210 04:54:09.180331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2211 04:54:09.181144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2213 04:54:09.265511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2214 04:54:09.266371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2216 04:54:09.355867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2217 04:54:09.356750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2219 04:54:09.445650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2220 04:54:09.446512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2222 04:54:09.537573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2223 04:54:09.538409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2225 04:54:09.622826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2226 04:54:09.623630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2228 04:54:09.704748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2229 04:54:09.705560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2231 04:54:09.797972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2232 04:54:09.799023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2234 04:54:09.889505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2235 04:54:09.890509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2237 04:54:09.971793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2238 04:54:09.972830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2240 04:54:10.063447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2241 04:54:10.064475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2243 04:54:10.148312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2244 04:54:10.149302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2246 04:54:10.239058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2247 04:54:10.240127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2249 04:54:10.327217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2250 04:54:10.328114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2252 04:54:10.420083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2253 04:54:10.420898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2255 04:54:10.510903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2256 04:54:10.511719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2258 04:54:10.597231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2259 04:54:10.598054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2261 04:54:10.683266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2262 04:54:10.684072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2264 04:54:10.768896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2265 04:54:10.769717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2267 04:54:10.862115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2268 04:54:10.862929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2270 04:54:10.956327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2271 04:54:10.957233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2273 04:54:11.047632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2274 04:54:11.048761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2276 04:54:11.135882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2277 04:54:11.136903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2279 04:54:11.220852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2280 04:54:11.221694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2282 04:54:11.306447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2283 04:54:11.307473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2285 04:54:11.400634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2286 04:54:11.401648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2288 04:54:11.489528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2289 04:54:11.490546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2291 04:54:11.574418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2292 04:54:11.575431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2294 04:54:11.665637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2295 04:54:11.666475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2297 04:54:11.753024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2298 04:54:11.753847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2300 04:54:11.843636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2301 04:54:11.844481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2303 04:54:11.935834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2304 04:54:11.936662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2306 04:54:12.019308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2307 04:54:12.020207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2309 04:54:12.103908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2310 04:54:12.104750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2312 04:54:12.197797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2313 04:54:12.198603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2315 04:54:12.285307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2317 04:54:12.288378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2318 04:54:12.368826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2319 04:54:12.369617 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2321 04:54:12.455756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2322 04:54:12.456590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2324 04:54:12.543898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2325 04:54:12.544722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2327 04:54:12.627843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2328 04:54:12.628675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2330 04:54:12.711340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2331 04:54:12.712116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2333 04:54:12.795899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2334 04:54:12.796779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2336 04:54:12.878995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2337 04:54:12.879795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2339 04:54:12.964220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2340 04:54:12.965004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2342 04:54:13.056478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2343 04:54:13.057304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2345 04:54:13.139463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2346 04:54:13.140281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2348 04:54:13.230647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2349 04:54:13.231431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2351 04:54:13.315008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2352 04:54:13.315799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2354 04:54:13.406042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2355 04:54:13.406811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2357 04:54:13.489382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2358 04:54:13.490162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2360 04:54:13.580468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2361 04:54:13.581248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2363 04:54:13.665099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2364 04:54:13.665876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2366 04:54:13.755686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2367 04:54:13.756899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2369 04:54:13.840163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2370 04:54:13.840942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2372 04:54:13.930635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2373 04:54:13.931404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2375 04:54:14.023083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2376 04:54:14.023876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2378 04:54:14.113404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2379 04:54:14.114159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2381 04:54:14.204203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2382 04:54:14.204957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2384 04:54:14.295299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2385 04:54:14.296079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2387 04:54:14.386390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2388 04:54:14.387154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2390 04:54:14.473414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2391 04:54:14.474192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2393 04:54:14.563152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2394 04:54:14.564340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2396 04:54:14.648334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2397 04:54:14.649359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2399 04:54:14.740351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2400 04:54:14.741499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2402 04:54:14.826698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2403 04:54:14.827951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2405 04:54:14.915407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2406 04:54:14.916581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2408 04:54:15.000801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2409 04:54:15.001508 + set +x
2410 04:54:15.002487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2412 04:54:15.005073 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 689582_1.6.2.4.5>
2413 04:54:15.006050 Received signal: <ENDRUN> 1_kselftest-dt 689582_1.6.2.4.5
2414 04:54:15.006807 Ending use of test pattern.
2415 04:54:15.007455 Ending test lava.1_kselftest-dt (689582_1.6.2.4.5), duration 66.59
2417 04:54:15.010474 <LAVA_TEST_RUNNER EXIT>
2418 04:54:15.011530 ok: lava_test_shell seems to have completed
2419 04:54:15.026650 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2420 04:54:15.028966 end: 3.1 lava-test-shell (duration 00:01:08) [common]
2421 04:54:15.029788 end: 3 lava-test-retry (duration 00:01:08) [common]
2422 04:54:15.030618 start: 4 finalize (timeout 00:05:01) [common]
2423 04:54:15.031432 start: 4.1 power-off (timeout 00:00:30) [common]
2424 04:54:15.032742 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-04'
2425 04:54:15.067803 >> OK - accepted request
2426 04:54:15.069979 Returned 0 in 0 seconds
2427 04:54:15.171392 end: 4.1 power-off (duration 00:00:00) [common]
2429 04:54:15.173617 start: 4.2 read-feedback (timeout 00:05:01) [common]
2430 04:54:15.175013 Listened to connection for namespace 'common' for up to 1s
2431 04:54:15.176141 Listened to connection for namespace 'common' for up to 1s
2432 04:54:16.175879 Finalising connection for namespace 'common'
2433 04:54:16.176868 Disconnecting from shell: Finalise
2434 04:54:16.177482 / #
2435 04:54:16.278584 end: 4.2 read-feedback (duration 00:00:01) [common]
2436 04:54:16.279500 end: 4 finalize (duration 00:00:01) [common]
2437 04:54:16.280468 Cleaning after the job
2438 04:54:16.281262 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/ramdisk
2439 04:54:16.291517 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/kernel
2440 04:54:16.299930 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/dtb
2441 04:54:16.301503 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/nfsrootfs
2442 04:54:16.445025 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689582/tftp-deploy-ovyw3or_/modules
2443 04:54:16.455186 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/689582
2444 04:54:19.827121 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/689582
2445 04:54:19.827822 Job finished correctly