Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 05:00:56.149120 lava-dispatcher, installed at version: 2024.01
2 05:00:56.149914 start: 0 validate
3 05:00:56.150404 Start time: 2024-09-02 05:00:56.150373+00:00 (UTC)
4 05:00:56.150941 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 05:00:56.151478 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 05:00:56.192210 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 05:00:56.192755 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fkernel%2FzImage exists
8 05:00:56.221619 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 05:00:56.222211 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 05:00:56.250374 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 05:00:56.250842 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 05:00:56.283236 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 05:00:56.283692 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fmodules.tar.xz exists
14 05:00:56.317661 validate duration: 0.17
16 05:00:56.318553 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 05:00:56.318893 start: 1.1 download-retry (timeout 00:10:00) [common]
18 05:00:56.319200 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 05:00:56.319778 Not decompressing ramdisk as can be used compressed.
20 05:00:56.320224 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 05:00:56.320494 saving as /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/ramdisk/initrd.cpio.gz
22 05:00:56.320764 total size: 4775763 (4 MB)
23 05:00:56.357831 progress 0 % (0 MB)
24 05:00:56.361450 progress 5 % (0 MB)
25 05:00:56.364802 progress 10 % (0 MB)
26 05:00:56.368055 progress 15 % (0 MB)
27 05:00:56.371658 progress 20 % (0 MB)
28 05:00:56.374840 progress 25 % (1 MB)
29 05:00:56.378054 progress 30 % (1 MB)
30 05:00:56.381589 progress 35 % (1 MB)
31 05:00:56.384711 progress 40 % (1 MB)
32 05:00:56.387830 progress 45 % (2 MB)
33 05:00:56.390969 progress 50 % (2 MB)
34 05:00:56.394476 progress 55 % (2 MB)
35 05:00:56.397589 progress 60 % (2 MB)
36 05:00:56.400707 progress 65 % (2 MB)
37 05:00:56.404314 progress 70 % (3 MB)
38 05:00:56.407408 progress 75 % (3 MB)
39 05:00:56.410532 progress 80 % (3 MB)
40 05:00:56.413647 progress 85 % (3 MB)
41 05:00:56.417175 progress 90 % (4 MB)
42 05:00:56.420197 progress 95 % (4 MB)
43 05:00:56.423043 progress 100 % (4 MB)
44 05:00:56.423685 4 MB downloaded in 0.10 s (44.26 MB/s)
45 05:00:56.424238 end: 1.1.1 http-download (duration 00:00:00) [common]
47 05:00:56.425151 end: 1.1 download-retry (duration 00:00:00) [common]
48 05:00:56.425458 start: 1.2 download-retry (timeout 00:10:00) [common]
49 05:00:56.425738 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 05:00:56.426221 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kernel/zImage
51 05:00:56.426476 saving as /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/kernel/zImage
52 05:00:56.426695 total size: 11952640 (11 MB)
53 05:00:56.426914 No compression specified
54 05:00:56.466699 progress 0 % (0 MB)
55 05:00:56.474551 progress 5 % (0 MB)
56 05:00:56.482282 progress 10 % (1 MB)
57 05:00:56.489957 progress 15 % (1 MB)
58 05:00:56.497687 progress 20 % (2 MB)
59 05:00:56.505786 progress 25 % (2 MB)
60 05:00:56.513350 progress 30 % (3 MB)
61 05:00:56.520983 progress 35 % (4 MB)
62 05:00:56.528653 progress 40 % (4 MB)
63 05:00:56.536799 progress 45 % (5 MB)
64 05:00:56.546848 progress 50 % (5 MB)
65 05:00:56.554722 progress 55 % (6 MB)
66 05:00:56.562539 progress 60 % (6 MB)
67 05:00:56.570630 progress 65 % (7 MB)
68 05:00:56.578332 progress 70 % (8 MB)
69 05:00:56.585878 progress 75 % (8 MB)
70 05:00:56.593487 progress 80 % (9 MB)
71 05:00:56.601450 progress 85 % (9 MB)
72 05:00:56.608996 progress 90 % (10 MB)
73 05:00:56.616667 progress 95 % (10 MB)
74 05:00:56.623869 progress 100 % (11 MB)
75 05:00:56.624613 11 MB downloaded in 0.20 s (57.60 MB/s)
76 05:00:56.625109 end: 1.2.1 http-download (duration 00:00:00) [common]
78 05:00:56.625936 end: 1.2 download-retry (duration 00:00:00) [common]
79 05:00:56.626215 start: 1.3 download-retry (timeout 00:10:00) [common]
80 05:00:56.626479 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 05:00:56.626929 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
82 05:00:56.627214 saving as /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/dtb/am335x-boneblack.dtb
83 05:00:56.627424 total size: 70308 (0 MB)
84 05:00:56.627633 No compression specified
85 05:00:56.667943 progress 46 % (0 MB)
86 05:00:56.668822 progress 93 % (0 MB)
87 05:00:56.669506 progress 100 % (0 MB)
88 05:00:56.669901 0 MB downloaded in 0.04 s (1.58 MB/s)
89 05:00:56.670375 end: 1.3.1 http-download (duration 00:00:00) [common]
91 05:00:56.671200 end: 1.3 download-retry (duration 00:00:00) [common]
92 05:00:56.671467 start: 1.4 download-retry (timeout 00:10:00) [common]
93 05:00:56.671735 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 05:00:56.672215 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 05:00:56.672490 saving as /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/nfsrootfs/full.rootfs.tar
96 05:00:56.672699 total size: 117747780 (112 MB)
97 05:00:56.672911 Using unxz to decompress xz
98 05:00:56.710850 progress 0 % (0 MB)
99 05:00:57.427560 progress 5 % (5 MB)
100 05:00:58.160040 progress 10 % (11 MB)
101 05:00:58.924218 progress 15 % (16 MB)
102 05:00:59.642100 progress 20 % (22 MB)
103 05:01:00.220499 progress 25 % (28 MB)
104 05:01:01.165397 progress 30 % (33 MB)
105 05:01:02.100317 progress 35 % (39 MB)
106 05:01:02.480344 progress 40 % (44 MB)
107 05:01:02.882299 progress 45 % (50 MB)
108 05:01:03.612660 progress 50 % (56 MB)
109 05:01:04.413111 progress 55 % (61 MB)
110 05:01:05.137252 progress 60 % (67 MB)
111 05:01:05.838225 progress 65 % (73 MB)
112 05:01:06.591422 progress 70 % (78 MB)
113 05:01:07.343564 progress 75 % (84 MB)
114 05:01:08.060324 progress 80 % (89 MB)
115 05:01:08.758317 progress 85 % (95 MB)
116 05:01:09.530676 progress 90 % (101 MB)
117 05:01:10.273814 progress 95 % (106 MB)
118 05:01:11.073517 progress 100 % (112 MB)
119 05:01:11.085707 112 MB downloaded in 14.41 s (7.79 MB/s)
120 05:01:11.086383 end: 1.4.1 http-download (duration 00:00:14) [common]
122 05:01:11.088058 end: 1.4 download-retry (duration 00:00:14) [common]
123 05:01:11.088599 start: 1.5 download-retry (timeout 00:09:45) [common]
124 05:01:11.089122 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 05:01:11.090039 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/modules.tar.xz
126 05:01:11.090509 saving as /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/modules/modules.tar
127 05:01:11.090925 total size: 6914168 (6 MB)
128 05:01:11.091348 Using unxz to decompress xz
129 05:01:11.139443 progress 0 % (0 MB)
130 05:01:11.175228 progress 5 % (0 MB)
131 05:01:11.221461 progress 10 % (0 MB)
132 05:01:11.264099 progress 15 % (1 MB)
133 05:01:11.314889 progress 20 % (1 MB)
134 05:01:11.359472 progress 25 % (1 MB)
135 05:01:11.406765 progress 30 % (2 MB)
136 05:01:11.449302 progress 35 % (2 MB)
137 05:01:11.497133 progress 40 % (2 MB)
138 05:01:11.539875 progress 45 % (2 MB)
139 05:01:11.587043 progress 50 % (3 MB)
140 05:01:11.633197 progress 55 % (3 MB)
141 05:01:11.677398 progress 60 % (3 MB)
142 05:01:11.725640 progress 65 % (4 MB)
143 05:01:11.768694 progress 70 % (4 MB)
144 05:01:11.816115 progress 75 % (4 MB)
145 05:01:11.860652 progress 80 % (5 MB)
146 05:01:11.909958 progress 85 % (5 MB)
147 05:01:11.952820 progress 90 % (5 MB)
148 05:01:11.999738 progress 95 % (6 MB)
149 05:01:12.046925 progress 100 % (6 MB)
150 05:01:12.056828 6 MB downloaded in 0.97 s (6.83 MB/s)
151 05:01:12.057383 end: 1.5.1 http-download (duration 00:00:01) [common]
153 05:01:12.058208 end: 1.5 download-retry (duration 00:00:01) [common]
154 05:01:12.058474 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 05:01:12.058741 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 05:01:27.902102 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9
157 05:01:27.902707 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 05:01:27.902994 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 05:01:27.903701 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y
160 05:01:27.904193 makedir: /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin
161 05:01:27.904528 makedir: /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/tests
162 05:01:27.904838 makedir: /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/results
163 05:01:27.905167 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-add-keys
164 05:01:27.905690 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-add-sources
165 05:01:27.906214 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-background-process-start
166 05:01:27.906779 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-background-process-stop
167 05:01:27.907421 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-common-functions
168 05:01:27.907946 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-echo-ipv4
169 05:01:27.908476 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-install-packages
170 05:01:27.908945 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-installed-packages
171 05:01:27.909406 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-os-build
172 05:01:27.909871 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-probe-channel
173 05:01:27.910381 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-probe-ip
174 05:01:27.910910 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-target-ip
175 05:01:27.911446 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-target-mac
176 05:01:27.911930 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-target-storage
177 05:01:27.912471 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-test-case
178 05:01:27.912955 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-test-event
179 05:01:27.913417 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-test-feedback
180 05:01:27.913882 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-test-raise
181 05:01:27.914365 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-test-reference
182 05:01:27.914877 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-test-runner
183 05:01:27.915356 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-test-set
184 05:01:27.915830 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-test-shell
185 05:01:27.916349 Updating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-add-keys (debian)
186 05:01:27.916882 Updating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-add-sources (debian)
187 05:01:27.917385 Updating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-install-packages (debian)
188 05:01:27.917878 Updating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-installed-packages (debian)
189 05:01:27.918362 Updating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/bin/lava-os-build (debian)
190 05:01:27.918784 Creating /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/environment
191 05:01:27.919142 LAVA metadata
192 05:01:27.919398 - LAVA_JOB_ID=689642
193 05:01:27.919613 - LAVA_DISPATCHER_IP=192.168.6.2
194 05:01:27.919967 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 05:01:27.920933 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 05:01:27.921242 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 05:01:27.921449 skipped lava-vland-overlay
198 05:01:27.921688 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 05:01:27.921942 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 05:01:27.922159 skipped lava-multinode-overlay
201 05:01:27.922402 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 05:01:27.922650 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 05:01:27.922896 Loading test definitions
204 05:01:27.923171 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 05:01:27.923388 Using /lava-689642 at stage 0
206 05:01:27.924467 uuid=689642_1.6.2.4.1 testdef=None
207 05:01:27.924772 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 05:01:27.925036 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 05:01:27.926575 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 05:01:27.927363 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 05:01:27.929286 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 05:01:27.930110 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 05:01:27.931900 runner path: /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/0/tests/0_timesync-off test_uuid 689642_1.6.2.4.1
216 05:01:27.932462 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 05:01:27.933269 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 05:01:27.933492 Using /lava-689642 at stage 0
220 05:01:27.933835 Fetching tests from https://github.com/kernelci/test-definitions.git
221 05:01:27.934122 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/0/tests/1_kselftest-dt'
222 05:01:31.392251 Running '/usr/bin/git checkout kernelci.org
223 05:01:31.726888 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 05:01:31.728372 uuid=689642_1.6.2.4.5 testdef=None
225 05:01:31.728727 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 05:01:31.729475 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 05:01:31.732320 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 05:01:31.733139 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 05:01:31.736826 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 05:01:31.737678 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 05:01:31.741245 runner path: /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/0/tests/1_kselftest-dt test_uuid 689642_1.6.2.4.5
235 05:01:31.741537 BOARD='beaglebone-black'
236 05:01:31.741745 BRANCH='mainline'
237 05:01:31.741945 SKIPFILE='/dev/null'
238 05:01:31.742140 SKIP_INSTALL='True'
239 05:01:31.742334 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
240 05:01:31.742536 TST_CASENAME=''
241 05:01:31.742731 TST_CMDFILES='dt'
242 05:01:31.743315 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 05:01:31.744153 Creating lava-test-runner.conf files
245 05:01:31.744364 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/689642/lava-overlay-tqzcaj2y/lava-689642/0 for stage 0
246 05:01:31.744883 - 0_timesync-off
247 05:01:31.745164 - 1_kselftest-dt
248 05:01:31.745527 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 05:01:31.745822 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 05:01:55.482174 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 05:01:55.482699 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 05:01:55.483016 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 05:01:55.483347 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 05:01:55.483675 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 05:01:55.844435 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 05:01:55.844912 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 05:01:55.845166 extracting modules file /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9
258 05:01:56.731201 extracting modules file /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/689642/extract-overlay-ramdisk-kvqi04rn/ramdisk
259 05:01:57.657001 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 05:01:57.657490 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 05:01:57.657772 [common] Applying overlay to NFS
262 05:01:57.657987 [common] Applying overlay /var/lib/lava/dispatcher/tmp/689642/compress-overlay-lvarecku/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9
263 05:02:00.392523 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 05:02:00.392989 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 05:02:00.393267 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 05:02:00.393547 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 05:02:00.393803 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 05:02:00.394061 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 05:02:00.394312 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 05:02:00.394569 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 05:02:00.394822 Building ramdisk /var/lib/lava/dispatcher/tmp/689642/extract-overlay-ramdisk-kvqi04rn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/689642/extract-overlay-ramdisk-kvqi04rn/ramdisk
272 05:02:01.434274 >> 78946 blocks
273 05:02:06.418281 Adding RAMdisk u-boot header.
274 05:02:06.419004 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/689642/extract-overlay-ramdisk-kvqi04rn/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/689642/extract-overlay-ramdisk-kvqi04rn/ramdisk.cpio.gz.uboot
275 05:02:06.597747 output: Image Name:
276 05:02:06.598159 output: Created: Mon Sep 2 05:02:06 2024
277 05:02:06.598374 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 05:02:06.598579 output: Data Size: 15335477 Bytes = 14976.05 KiB = 14.63 MiB
279 05:02:06.598781 output: Load Address: 00000000
280 05:02:06.598981 output: Entry Point: 00000000
281 05:02:06.599180 output:
282 05:02:06.599803 rename /var/lib/lava/dispatcher/tmp/689642/extract-overlay-ramdisk-kvqi04rn/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/ramdisk/ramdisk.cpio.gz.uboot
283 05:02:06.600403 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 05:02:06.600951 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 05:02:06.601474 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 05:02:06.601924 No LXC device requested
287 05:02:06.602418 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 05:02:06.602923 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 05:02:06.603412 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 05:02:06.603822 Checking files for TFTP limit of 4294967296 bytes.
291 05:02:06.606506 end: 1 tftp-deploy (duration 00:01:10) [common]
292 05:02:06.607069 start: 2 uboot-action (timeout 00:05:00) [common]
293 05:02:06.607587 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 05:02:06.608109 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 05:02:06.608610 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 05:02:06.609354 substitutions:
297 05:02:06.609766 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 05:02:06.610166 - {DTB_ADDR}: 0x88000000
299 05:02:06.610563 - {DTB}: 689642/tftp-deploy-8lhy1ly2/dtb/am335x-boneblack.dtb
300 05:02:06.610955 - {INITRD}: 689642/tftp-deploy-8lhy1ly2/ramdisk/ramdisk.cpio.gz.uboot
301 05:02:06.611346 - {KERNEL_ADDR}: 0x82000000
302 05:02:06.611733 - {KERNEL}: 689642/tftp-deploy-8lhy1ly2/kernel/zImage
303 05:02:06.612148 - {LAVA_MAC}: None
304 05:02:06.612577 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9
305 05:02:06.612973 - {NFS_SERVER_IP}: 192.168.6.2
306 05:02:06.613361 - {PRESEED_CONFIG}: None
307 05:02:06.613747 - {PRESEED_LOCAL}: None
308 05:02:06.614134 - {RAMDISK_ADDR}: 0x83000000
309 05:02:06.614517 - {RAMDISK}: 689642/tftp-deploy-8lhy1ly2/ramdisk/ramdisk.cpio.gz.uboot
310 05:02:06.614907 - {ROOT_PART}: None
311 05:02:06.615291 - {ROOT}: None
312 05:02:06.615681 - {SERVER_IP}: 192.168.6.2
313 05:02:06.616091 - {TEE_ADDR}: 0x83000000
314 05:02:06.616477 - {TEE}: None
315 05:02:06.616861 Parsed boot commands:
316 05:02:06.617235 - setenv autoload no
317 05:02:06.617617 - setenv initrd_high 0xffffffff
318 05:02:06.617999 - setenv fdt_high 0xffffffff
319 05:02:06.618378 - dhcp
320 05:02:06.618762 - setenv serverip 192.168.6.2
321 05:02:06.619143 - tftp 0x82000000 689642/tftp-deploy-8lhy1ly2/kernel/zImage
322 05:02:06.619526 - tftp 0x83000000 689642/tftp-deploy-8lhy1ly2/ramdisk/ramdisk.cpio.gz.uboot
323 05:02:06.619910 - setenv initrd_size ${filesize}
324 05:02:06.620311 - tftp 0x88000000 689642/tftp-deploy-8lhy1ly2/dtb/am335x-boneblack.dtb
325 05:02:06.620695 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 05:02:06.621091 - bootz 0x82000000 0x83000000 0x88000000
327 05:02:06.621575 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 05:02:06.623044 start: 2.3 connect-device (timeout 00:05:00) [common]
330 05:02:06.623460 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 05:02:06.637688 Setting prompt string to ['lava-test: # ']
332 05:02:06.639157 end: 2.3 connect-device (duration 00:00:00) [common]
333 05:02:06.639739 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 05:02:06.640324 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 05:02:06.640870 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 05:02:06.642057 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 05:02:06.678007 >> OK - accepted request
338 05:02:06.680166 Returned 0 in 0 seconds
339 05:02:06.781251 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 05:02:06.782826 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 05:02:06.783377 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 05:02:06.783879 Setting prompt string to ['Hit any key to stop autoboot']
344 05:02:06.784391 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 05:02:06.785940 Trying 192.168.56.21...
346 05:02:06.786413 Connected to conserv1.
347 05:02:06.786826 Escape character is '^]'.
348 05:02:06.787227
349 05:02:06.787642 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 05:02:06.788084
351 05:02:14.647698
352 05:02:14.648321 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 05:02:14.652798 Trying to boot from MMC1
354 05:02:15.224948
355 05:02:15.225424
356 05:02:15.225849 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 05:02:15.226262
358 05:02:15.230449 CPU : AM335X-GP rev 2.1
359 05:02:15.230907 Model: TI AM335x BeagleBone Black
360 05:02:15.234612 DRAM: 512 MiB
361 05:02:15.317447 Core: 160 devices, 18 uclasses, devicetree: separate
362 05:02:15.326957 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 05:02:18.693633 7[r[999;999H[6n8NAND:
364 05:02:18.694252 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 05:02:18.698942 Trying to boot from MMC1
366 05:02:19.270766
367 05:02:19.271238
368 05:02:19.271668 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 05:02:19.272165
370 05:02:19.276103 CPU : AM335X-GP rev 2.1
371 05:02:19.276547 Model: TI AM335x BeagleBone Black
372 05:02:19.280398 DRAM: 512 MiB
373 05:02:19.363104 Core: 160 devices, 18 uclasses, devicetree: separate
374 05:02:19.372624 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 05:02:21.392546 7[r[999;999H[6n8NAND:
376 05:02:21.393073 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 05:02:21.397665 Trying to boot from MMC1
378 05:02:21.969527
379 05:02:21.969976
380 05:02:21.970389 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 05:02:21.970797
382 05:02:21.974952 CPU : AM335X-GP rev 2.1
383 05:02:21.975379 Model: TI AM335x BeagleBone Black
384 05:02:21.979209 DRAM: 512 MiB
385 05:02:22.061853 Core: 160 devices, 18 uclasses, devicetree: separate
386 05:02:22.071507 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 05:02:22.576636 7[r[999;999H[6n8NAND: 0 MiB
388 05:02:22.586934 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 05:02:22.659948 Loading Environment from FAT... Unable to use mmc 0:1...
390 05:02:22.681213 <ethaddr> not set. Validating first E-fuse MAC
391 05:02:22.711481 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 05:02:22.770224 Hit any key to stop autoboot: 2
394 05:02:22.771340 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 05:02:22.772066 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 05:02:22.772624 Setting prompt string to ['=>']
397 05:02:22.773164 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 05:02:22.780056 0
399 05:02:22.781016 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 05:02:22.781573 Sending with 10 millisecond of delay
402 05:02:23.916858 => setenv autoload no
403 05:02:23.928187 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 05:02:23.930738 setenv autoload no
405 05:02:23.931224 Sending with 10 millisecond of delay
407 05:02:25.728322 => setenv initrd_high 0xffffffff
408 05:02:25.739194 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 05:02:25.740321 setenv initrd_high 0xffffffff
410 05:02:25.741272 Sending with 10 millisecond of delay
412 05:02:27.358208 => setenv fdt_high 0xffffffff
413 05:02:27.369007 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 05:02:27.369956 setenv fdt_high 0xffffffff
415 05:02:27.370755 Sending with 10 millisecond of delay
417 05:02:27.662724 => dhcp
418 05:02:27.673486 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 05:02:27.674392 dhcp
420 05:02:27.676348 link up on port 0, speed 100, full duplex
421 05:02:27.676903 BOOTP broadcast 1
422 05:02:27.927803 BOOTP broadcast 2
423 05:02:27.953560 DHCP client bound to address 192.168.6.30 (274 ms)
424 05:02:27.954382 Sending with 10 millisecond of delay
426 05:02:29.631509 => setenv serverip 192.168.6.2
427 05:02:29.642138 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
428 05:02:29.642799 setenv serverip 192.168.6.2
429 05:02:29.643401 Sending with 10 millisecond of delay
431 05:02:33.130104 => tftp 0x82000000 689642/tftp-deploy-8lhy1ly2/kernel/zImage
432 05:02:33.140924 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
433 05:02:33.141858 tftp 0x82000000 689642/tftp-deploy-8lhy1ly2/kernel/zImage
434 05:02:33.142368 link up on port 0, speed 100, full duplex
435 05:02:33.145846 Using ethernet@4a100000 device
436 05:02:33.151497 TFTP from server 192.168.6.2; our IP address is 192.168.6.30
437 05:02:33.158837 Filename '689642/tftp-deploy-8lhy1ly2/kernel/zImage'.
438 05:02:33.159424 Load address: 0x82000000
439 05:02:35.495025 Loading: *################################################## 11.4 MiB
440 05:02:35.495686 4.9 MiB/s
441 05:02:35.496235 done
442 05:02:35.499492 Bytes transferred = 11952640 (b66200 hex)
443 05:02:35.500411 Sending with 10 millisecond of delay
445 05:02:39.946182 => tftp 0x83000000 689642/tftp-deploy-8lhy1ly2/ramdisk/ramdisk.cpio.gz.uboot
446 05:02:39.956987 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
447 05:02:39.957893 tftp 0x83000000 689642/tftp-deploy-8lhy1ly2/ramdisk/ramdisk.cpio.gz.uboot
448 05:02:39.958391 link up on port 0, speed 100, full duplex
449 05:02:39.961744 Using ethernet@4a100000 device
450 05:02:39.967366 TFTP from server 192.168.6.2; our IP address is 192.168.6.30
451 05:02:39.976228 Filename '689642/tftp-deploy-8lhy1ly2/ramdisk/ramdisk.cpio.gz.uboot'.
452 05:02:39.976818 Load address: 0x83000000
453 05:02:43.104868 Loading: *################################################## 14.6 MiB
454 05:02:43.105510 4.7 MiB/s
455 05:02:43.106000 done
456 05:02:43.109378 Bytes transferred = 15335541 (ea0075 hex)
457 05:02:43.110720 Sending with 10 millisecond of delay
459 05:02:44.970683 => setenv initrd_size ${filesize}
460 05:02:44.981444 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
461 05:02:44.982311 setenv initrd_size ${filesize}
462 05:02:44.983082 Sending with 10 millisecond of delay
464 05:02:49.127791 => tftp 0x88000000 689642/tftp-deploy-8lhy1ly2/dtb/am335x-boneblack.dtb
465 05:02:49.138661 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
466 05:02:49.139592 tftp 0x88000000 689642/tftp-deploy-8lhy1ly2/dtb/am335x-boneblack.dtb
467 05:02:49.140119 link up on port 0, speed 100, full duplex
468 05:02:49.143397 Using ethernet@4a100000 device
469 05:02:49.148933 TFTP from server 192.168.6.2; our IP address is 192.168.6.30
470 05:02:49.160255 Filename '689642/tftp-deploy-8lhy1ly2/dtb/am335x-boneblack.dtb'.
471 05:02:49.160743 Load address: 0x88000000
472 05:02:49.170949 Loading: *################################################## 68.7 KiB
473 05:02:49.171427 4.5 MiB/s
474 05:02:49.179528 done
475 05:02:49.180060 Bytes transferred = 70308 (112a4 hex)
476 05:02:49.180788 Sending with 10 millisecond of delay
478 05:03:02.357479 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 05:03:02.368295 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
480 05:03:02.369168 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 05:03:02.369894 Sending with 10 millisecond of delay
483 05:03:04.708850 => bootz 0x82000000 0x83000000 0x88000000
484 05:03:04.719610 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
485 05:03:04.720179 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
486 05:03:04.721221 bootz 0x82000000 0x83000000 0x88000000
487 05:03:04.721696 Kernel image @ 0x82000000 [ 0x000000 - 0xb66200 ]
488 05:03:04.722232 ## Loading init Ramdisk from Legacy Image at 83000000 ...
489 05:03:04.727154 Image Name:
490 05:03:04.727676 Created: 2024-09-02 5:02:06 UTC
491 05:03:04.736008 Image Type: ARM Linux RAMDisk Image (uncompressed)
492 05:03:04.736479 Data Size: 15335477 Bytes = 14.6 MiB
493 05:03:04.744562 Load Address: 00000000
494 05:03:04.745021 Entry Point: 00000000
495 05:03:04.919121 Verifying Checksum ... OK
496 05:03:04.919649 ## Flattened Device Tree blob at 88000000
497 05:03:04.925681 Booting using the fdt blob at 0x88000000
498 05:03:04.930373 Using Device Tree in place at 88000000, end 880142a3
499 05:03:04.943902
500 05:03:04.944394 Starting kernel ...
501 05:03:04.944823
502 05:03:04.945716 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
503 05:03:04.946293 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
504 05:03:04.946751 Setting prompt string to ['Linux version [0-9]']
505 05:03:04.947204 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
506 05:03:04.947707 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
507 05:03:05.775699 [ 0.000000] Booting Linux on physical CPU 0x0
508 05:03:05.784531 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
509 05:03:05.785087 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 05:03:05.785557 Setting prompt string to []
511 05:03:05.786056 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 05:03:05.786513 Using line separator: #'\n'#
513 05:03:05.786923 No login prompt set.
514 05:03:05.787358 Parsing kernel messages
515 05:03:05.787759 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 05:03:05.788561 [login-action] Waiting for messages, (timeout 00:04:01)
517 05:03:05.789013 Waiting using forced prompt support (timeout 00:02:00)
518 05:03:05.792554 [ 0.000000] Linux version 6.11.0-rc6 (KernelCI@build-j304696-arm-clang-16-multi-v7-defconfig-hgvd9) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Mon Sep 2 03:54:42 UTC 2024
519 05:03:05.804036 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 05:03:05.809684 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 05:03:05.815486 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 05:03:05.821145 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 05:03:05.827108 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 05:03:05.832849 [ 0.000000] Memory policy: Data cache writeback
525 05:03:05.839405 [ 0.000000] efi: UEFI not found.
526 05:03:05.839832 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 05:03:05.848201 [ 0.000000] Zone ranges:
528 05:03:05.853807 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 05:03:05.859540 [ 0.000000] Normal empty
530 05:03:05.859968 [ 0.000000] HighMem empty
531 05:03:05.865273 [ 0.000000] Movable zone start for each node
532 05:03:05.865703 [ 0.000000] Early memory node ranges
533 05:03:05.876738 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 05:03:05.882032 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 05:03:05.900063 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 05:03:05.905710 [ 0.000000] AM335X ES2.1 (sgx neon)
537 05:03:05.917370 [ 0.000000] percpu: Embedded 17 pages/cpu s40268 r8192 d21172 u69632
538 05:03:05.937797 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 05:03:05.943640 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 05:03:05.955082 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 05:03:05.960816 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 05:03:05.968139 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 05:03:05.997156 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 05:03:06.003118 <6>[ 0.000000] trace event string verifier disabled
545 05:03:06.003546 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 05:03:06.011269 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 05:03:06.017002 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 05:03:06.028454 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 05:03:06.033293 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 05:03:06.048293 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 05:03:06.065958 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 05:03:06.072612 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 05:03:06.171802 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 05:03:06.183254 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 05:03:06.190069 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 05:03:06.203085 <6>[ 0.019177] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 05:03:06.210616 <6>[ 0.034147] Console: colour dummy device 80x30
558 05:03:06.216761 Matched prompt #6: WARNING:
559 05:03:06.217335 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 05:03:06.222185 <3>[ 0.039048] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 05:03:06.224776 <3>[ 0.046126] This ensures that you still see kernel messages. Please
562 05:03:06.231131 <3>[ 0.052853] update your kernel commandline.
563 05:03:06.271593 <6>[ 0.057464] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 05:03:06.277399 <6>[ 0.096186] CPU: Testing write buffer coherency: ok
565 05:03:06.283326 <6>[ 0.101553] CPU0: Spectre v2: using BPIALL workaround
566 05:03:06.283848 <6>[ 0.107018] pid_max: default: 32768 minimum: 301
567 05:03:06.294753 <6>[ 0.112209] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 05:03:06.301657 <6>[ 0.120033] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 05:03:06.308727 <6>[ 0.129361] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 05:03:06.317126 <6>[ 0.136265] Setting up static identity map for 0x80300000 - 0x803000ac
571 05:03:06.322907 <6>[ 0.145906] rcu: Hierarchical SRCU implementation.
572 05:03:06.330559 <6>[ 0.151186] rcu: Max phase no-delay instances is 1000.
573 05:03:06.339153 <6>[ 0.162436] EFI services will not be available.
574 05:03:06.345080 <6>[ 0.167706] smp: Bringing up secondary CPUs ...
575 05:03:06.350742 <6>[ 0.172756] smp: Brought up 1 node, 1 CPU
576 05:03:06.356534 <6>[ 0.177155] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 05:03:06.362444 <6>[ 0.183913] CPU: All CPU(s) started in SVC mode.
578 05:03:06.382722 <6>[ 0.189098] Memory: 405456K/522240K available (17408K kernel code, 2536K rwdata, 6644K rodata, 2048K init, 432K bss, 49580K reserved, 65536K cma-reserved, 0K highmem)
579 05:03:06.383275 <6>[ 0.205357] devtmpfs: initialized
580 05:03:06.405481 <6>[ 0.222953] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 05:03:06.417037 <6>[ 0.231556] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 05:03:06.422975 <6>[ 0.241995] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 05:03:06.433673 <6>[ 0.254287] pinctrl core: initialized pinctrl subsystem
584 05:03:06.443202 <6>[ 0.265134] DMI not present or invalid.
585 05:03:06.451522 <6>[ 0.271005] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 05:03:06.460992 <6>[ 0.279947] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 05:03:06.476005 <6>[ 0.291421] thermal_sys: Registered thermal governor 'step_wise'
588 05:03:06.476554 <6>[ 0.291573] cpuidle: using governor menu
589 05:03:06.503445 <6>[ 0.326876] No ATAGs?
590 05:03:06.509621 <6>[ 0.329610] hw-breakpoint: debug architecture 0x4 unsupported.
591 05:03:06.520056 <6>[ 0.341802] Serial: AMBA PL011 UART driver
592 05:03:06.561125 <6>[ 0.384580] iommu: Default domain type: Translated
593 05:03:06.570139 <6>[ 0.389922] iommu: DMA domain TLB invalidation policy: strict mode
594 05:03:06.578485 <5>[ 0.400631] SCSI subsystem initialized
595 05:03:06.602058 <6>[ 0.420097] usbcore: registered new interface driver usbfs
596 05:03:06.609124 <6>[ 0.426063] usbcore: registered new interface driver hub
597 05:03:06.609427 <6>[ 0.431889] usbcore: registered new device driver usb
598 05:03:06.614770 <6>[ 0.438435] pps_core: LinuxPPS API ver. 1 registered
599 05:03:06.626209 <6>[ 0.443871] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 05:03:06.631382 <6>[ 0.453578] PTP clock support registered
601 05:03:06.667020 <6>[ 0.490047] EDAC MC: Ver: 3.0.0
602 05:03:06.673204 <6>[ 0.494258] scmi_core: SCMI protocol bus registered
603 05:03:06.690962 <6>[ 0.514325] vgaarb: loaded
604 05:03:06.703403 <6>[ 0.527152] clocksource: Switched to clocksource dmtimer
605 05:03:06.742012 <6>[ 0.565411] NET: Registered PF_INET protocol family
606 05:03:06.754729 <6>[ 0.571095] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 05:03:06.761696 <6>[ 0.580081] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 05:03:06.773246 <6>[ 0.589008] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 05:03:06.779055 <6>[ 0.597270] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 05:03:06.784813 <6>[ 0.605541] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 05:03:06.790562 <6>[ 0.613256] TCP: Hash tables configured (established 4096 bind 4096)
612 05:03:06.802212 <6>[ 0.620174] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 05:03:06.808113 <6>[ 0.627214] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 05:03:06.814488 <6>[ 0.634790] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 05:03:06.849038 <6>[ 0.666952] RPC: Registered named UNIX socket transport module.
616 05:03:06.849576 <6>[ 0.673386] RPC: Registered udp transport module.
617 05:03:06.854804 <6>[ 0.678519] RPC: Registered tcp transport module.
618 05:03:06.860521 <6>[ 0.683622] RPC: Registered tcp-with-tls transport module.
619 05:03:06.873574 <6>[ 0.689547] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 05:03:06.874078 <6>[ 0.696457] PCI: CLS 0 bytes, default 64
621 05:03:06.880768 <5>[ 0.702312] Initialise system trusted keyrings
622 05:03:06.900913 <6>[ 0.721506] Trying to unpack rootfs image as initramfs...
623 05:03:06.920086 <6>[ 0.737423] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 05:03:06.924739 <6>[ 0.744897] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 05:03:06.984074 <5>[ 0.807562] NFS: Registering the id_resolver key type
626 05:03:06.989783 <5>[ 0.813182] Key type id_resolver registered
627 05:03:06.995574 <5>[ 0.817822] Key type id_legacy registered
628 05:03:07.001318 <6>[ 0.822258] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 05:03:07.010905 <6>[ 0.829449] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 05:03:07.054298 <5>[ 0.877888] Key type asymmetric registered
631 05:03:07.060208 <5>[ 0.882412] Asymmetric key parser 'x509' registered
632 05:03:07.071682 <6>[ 0.887970] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 05:03:07.072227 <6>[ 0.895858] io scheduler mq-deadline registered
634 05:03:07.077469 <6>[ 0.900828] io scheduler kyber registered
635 05:03:07.083072 <6>[ 0.905276] io scheduler bfq registered
636 05:03:07.452154 <6>[ 1.271867] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 05:03:07.486697 <6>[ 1.310139] msm_serial: driver initialized
638 05:03:07.492739 <6>[ 1.314924] SuperH (H)SCI(F) driver initialized
639 05:03:07.498668 <6>[ 1.320243] STMicroelectronics ASC driver initialized
640 05:03:07.503809 <6>[ 1.325852] STM32 USART driver initialized
641 05:03:07.607410 <6>[ 1.430212] brd: module loaded
642 05:03:07.641194 <6>[ 1.464046] loop: module loaded
643 05:03:07.682185 <6>[ 1.504909] CAN device driver interface
644 05:03:07.688666 <6>[ 1.510091] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 05:03:07.694458 <6>[ 1.517017] e1000e: Intel(R) PRO/1000 Network Driver
646 05:03:07.700274 <6>[ 1.522464] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 05:03:07.705973 <6>[ 1.528897] igb: Intel(R) Gigabit Ethernet Network Driver
648 05:03:07.714285 <6>[ 1.534723] igb: Copyright (c) 2007-2014 Intel Corporation.
649 05:03:07.726010 <6>[ 1.543959] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 05:03:07.731812 <6>[ 1.550113] usbcore: registered new interface driver pegasus
651 05:03:07.737613 <6>[ 1.556242] usbcore: registered new interface driver asix
652 05:03:07.743424 <6>[ 1.562129] usbcore: registered new interface driver ax88179_178a
653 05:03:07.749201 <6>[ 1.568745] usbcore: registered new interface driver cdc_ether
654 05:03:07.754997 <6>[ 1.575050] usbcore: registered new interface driver smsc75xx
655 05:03:07.760798 <6>[ 1.581302] usbcore: registered new interface driver smsc95xx
656 05:03:07.766541 <6>[ 1.587535] usbcore: registered new interface driver net1080
657 05:03:07.772332 <6>[ 1.593656] usbcore: registered new interface driver cdc_subset
658 05:03:07.778180 <6>[ 1.600066] usbcore: registered new interface driver zaurus
659 05:03:07.785840 <6>[ 1.606134] usbcore: registered new interface driver cdc_ncm
660 05:03:07.795604 <6>[ 1.615614] usbcore: registered new interface driver usb-storage
661 05:03:07.896163 <6>[ 1.717747] i2c_dev: i2c /dev entries driver
662 05:03:07.956415 <5>[ 1.772181] cpuidle: enable-method property 'ti,am3352' found operations
663 05:03:07.962305 <6>[ 1.781773] sdhci: Secure Digital Host Controller Interface driver
664 05:03:07.970253 <6>[ 1.788559] sdhci: Copyright(c) Pierre Ossman
665 05:03:07.977021 <6>[ 1.794950] Synopsys Designware Multimedia Card Interface Driver
666 05:03:07.982467 <6>[ 1.802875] sdhci-pltfm: SDHCI platform and OF driver helper
667 05:03:08.055063 <6>[ 1.875027] ledtrig-cpu: registered to indicate activity on CPUs
668 05:03:08.082081 <6>[ 1.898322] usbcore: registered new interface driver usbhid
669 05:03:08.082639 <6>[ 1.904361] usbhid: USB HID core driver
670 05:03:08.133613 <6>[ 1.954661] NET: Registered PF_INET6 protocol family
671 05:03:08.184981 <6>[ 2.008615] Segment Routing with IPv6
672 05:03:08.190846 <6>[ 2.012760] In-situ OAM (IOAM) with IPv6
673 05:03:08.197538 <6>[ 2.017275] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 05:03:08.204966 <6>[ 2.024581] NET: Registered PF_PACKET protocol family
675 05:03:08.210825 <6>[ 2.030155] can: controller area network core
676 05:03:08.211314 <6>[ 2.034983] NET: Registered PF_CAN protocol family
677 05:03:08.216555 <6>[ 2.040211] can: raw protocol
678 05:03:08.222330 <6>[ 2.043535] can: broadcast manager protocol
679 05:03:08.229249 <6>[ 2.048134] can: netlink gateway - max_hops=1
680 05:03:08.229749 <5>[ 2.053643] Key type dns_resolver registered
681 05:03:08.234975 <6>[ 2.058705] ThumbEE CPU extension supported.
682 05:03:08.241303 <5>[ 2.063392] Registering SWP/SWPB emulation handler
683 05:03:08.249469 <3>[ 2.069089] omap_voltage_late_init: Voltage driver support not added
684 05:03:08.336757 <5>[ 2.158013] Loading compiled-in X.509 certificates
685 05:03:08.503807 <6>[ 2.314302] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 05:03:08.510985 <6>[ 2.331170] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 05:03:08.537554 <3>[ 2.355164] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 05:03:08.628563 <3>[ 2.446074] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 05:03:08.716824 <6>[ 2.538666] OMAP GPIO hardware version 0.1
690 05:03:08.737830 <6>[ 2.557746] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 05:03:08.789672 <4>[ 2.609306] at24 2-0054: supply vcc not found, using dummy regulator
692 05:03:08.844296 <4>[ 2.663940] at24 2-0055: supply vcc not found, using dummy regulator
693 05:03:08.893342 <4>[ 2.712986] at24 2-0056: supply vcc not found, using dummy regulator
694 05:03:08.947712 <4>[ 2.767326] at24 2-0057: supply vcc not found, using dummy regulator
695 05:03:08.987475 <6>[ 2.807829] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 05:03:09.076628 <3>[ 2.893051] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 05:03:09.101358 <6>[ 2.914109] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 05:03:09.134247 <4>[ 2.952650] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 05:03:09.169309 <4>[ 2.987708] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 05:03:09.227538 <6>[ 3.047372] omap_rng 48310000.rng: Random Number Generator ver. 20
701 05:03:09.251088 <5>[ 3.073694] random: crng init done
702 05:03:09.356341 <6>[ 3.174639] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 05:03:09.897146 <6>[ 3.719179] Freeing initrd memory: 14980K
704 05:03:09.940875 <6>[ 3.758536] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 05:03:09.946662 <6>[ 3.768764] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 05:03:09.958472 <6>[ 3.776032] cpsw-switch 4a100000.switch: ALE Table size 1024
707 05:03:09.964262 <6>[ 3.782459] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 05:03:09.975778 <6>[ 3.790589] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 05:03:09.983290 <6>[ 3.802230] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
710 05:03:09.995343 <5>[ 3.811366] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 05:03:10.023664 <3>[ 3.841711] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 05:03:10.029440 <6>[ 3.850281] edma 49000000.dma: TI EDMA DMA engine driver
713 05:03:10.101643 <3>[ 3.918962] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 05:03:10.115335 <6>[ 3.933356] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
715 05:03:10.134109 <3>[ 3.955217] l3-aon-clkctrl:0000:0: failed to disable
716 05:03:10.170222 <6>[ 3.988322] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 05:03:10.175890 <6>[ 3.997783] printk: legacy console [ttyS0] enabled
718 05:03:10.178764 <6>[ 3.997783] printk: legacy console [ttyS0] enabled
719 05:03:10.184424 <6>[ 4.008106] printk: legacy bootconsole [omap8250] disabled
720 05:03:10.190054 <6>[ 4.008106] printk: legacy bootconsole [omap8250] disabled
721 05:03:10.250901 <4>[ 4.067851] tps65217-pmic: Failed to locate of_node [id: -1]
722 05:03:10.254582 <4>[ 4.075245] tps65217-bl: Failed to locate of_node [id: -1]
723 05:03:10.271008 <6>[ 4.094908] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 05:03:10.289436 <6>[ 4.101884] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 05:03:10.301193 <6>[ 4.115590] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 05:03:10.307035 <6>[ 4.127578] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 05:03:10.329969 <6>[ 4.148258] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 05:03:10.335974 <6>[ 4.157412] sdhci-omap 48060000.mmc: Got CD GPIO
729 05:03:10.343831 <4>[ 4.162533] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 05:03:10.359372 <4>[ 4.176597] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 05:03:10.365819 <4>[ 4.185672] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 05:03:10.375687 <4>[ 4.194324] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 05:03:10.497542 <6>[ 4.316867] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 05:03:10.532272 <6>[ 4.350701] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 05:03:10.555420 <6>[ 4.372925] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 05:03:10.562201 <6>[ 4.381855] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 05:03:10.614788 <6>[ 4.428194] mmc0: new high speed SDHC card at address 1234
738 05:03:10.615339 <6>[ 4.436596] mmcblk0: mmc0:1234 SA32G 29.1 GiB
739 05:03:10.628936 <6>[ 4.450209] mmcblk0: p1
740 05:03:10.636089 <6>[ 4.455668] mmc1: new high speed MMC card at address 0001
741 05:03:10.641154 <6>[ 4.462905] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 05:03:10.648981 <6>[ 4.471867] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 05:03:10.661943 <6>[ 4.478097] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
744 05:03:10.669445 <6>[ 4.490762] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
745 05:03:10.683184 <6>[ 4.503247] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
746 05:03:12.790277 <6>[ 6.608132] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
747 05:03:19.383281 <5>[ 6.657364] Sending DHCP requests ..., OK
748 05:03:19.394503 <6>[ 13.211731] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.30
749 05:03:19.395099 <6>[ 13.219908] IP-Config: Complete:
750 05:03:19.405814 <6>[ 13.223443] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.30, mask=255.255.255.0, gw=192.168.6.1
751 05:03:19.411417 <6>[ 13.233965] host=192.168.6.30, domain=, nis-domain=(none)
752 05:03:19.423868 <6>[ 13.240177] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
753 05:03:19.424425 <6>[ 13.240211] nameserver0=10.255.253.1
754 05:03:19.429977 <6>[ 13.252781] clk: Disabling unused clocks
755 05:03:19.435972 <6>[ 13.257545] PM: genpd: Disabling unused power domains
756 05:03:19.454258 <6>[ 13.275017] Freeing unused kernel image (initmem) memory: 2048K
757 05:03:19.461818 <6>[ 13.284799] Run /init as init process
758 05:03:19.487491 Loading, please wait...
759 05:03:19.563346 Starting systemd-udevd version 252.22-1~deb12u1
760 05:03:22.555469 <4>[ 16.372558] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 05:03:22.714188 <4>[ 16.531306] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 05:03:22.972071 <6>[ 16.796634] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
763 05:03:22.982986 <6>[ 16.802539] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
764 05:03:23.133510 <6>[ 16.956634] hub 1-0:1.0: USB hub found
765 05:03:23.155921 <6>[ 16.978919] hub 1-0:1.0: 1 port detected
766 05:03:23.161966 <6>[ 16.984772] tda998x 0-0070: found TDA19988
767 05:03:26.105118 Begin: Loading essential drivers ... done.
768 05:03:26.110593 Begin: Running /scripts/init-premount ... done.
769 05:03:26.116211 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 05:03:26.126453 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 05:03:26.137690 Device /sys/class/net/eth0 found
772 05:03:26.138241 done.
773 05:03:26.217333 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 05:03:26.285957 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
775 05:03:26.310415 IP-Config: eth0 guessed broadcast address 192.168.6.255
776 05:03:26.316025 IP-Config: eth0 complete (dhcp from 192.168.6.1):
777 05:03:26.321499 address: 192.168.6.30 broadcast: 192.168.6.255 netmask: 255.255.255.0
778 05:03:26.332624 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
779 05:03:26.333143 rootserver: 192.168.6.1 rootpath:
780 05:03:26.336265 filename :
781 05:03:26.461155 done.
782 05:03:26.473621 Begin: Running /scripts/nfs-bottom ... done.
783 05:03:26.545693 Begin: Running /scripts/init-bottom ... done.
784 05:03:27.841678 <30>[ 21.662006] systemd[1]: System time before build time, advancing clock.
785 05:03:28.096769 <30>[ 21.890946] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
786 05:03:28.105652 <30>[ 21.927785] systemd[1]: Detected architecture arm.
787 05:03:28.117869
788 05:03:28.118407 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
789 05:03:28.118877
790 05:03:28.157135 <30>[ 21.978095] systemd[1]: Hostname set to <debian-bookworm-armhf>.
791 05:03:30.314950 <30>[ 24.134882] systemd[1]: Queued start job for default target graphical.target.
792 05:03:30.332185 <30>[ 24.149999] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
793 05:03:30.339726 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
794 05:03:30.373112 <30>[ 24.189963] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
795 05:03:30.380497 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
796 05:03:30.415602 <30>[ 24.233036] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
797 05:03:30.422999 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
798 05:03:30.460385 <30>[ 24.279013] systemd[1]: Created slice user.slice - User and Session Slice.
799 05:03:30.466976 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
800 05:03:30.507449 <30>[ 24.319363] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
801 05:03:30.513572 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
802 05:03:30.550881 <30>[ 24.368222] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
803 05:03:30.562039 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
804 05:03:30.600870 <30>[ 24.408369] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
805 05:03:30.607391 <30>[ 24.428885] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
806 05:03:30.615859 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
807 05:03:30.648830 <30>[ 24.467567] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
808 05:03:30.657096 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
809 05:03:30.689550 <30>[ 24.507910] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
810 05:03:30.697993 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
811 05:03:30.729505 <30>[ 24.548047] systemd[1]: Reached target paths.target - Path Units.
812 05:03:30.734539 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
813 05:03:30.769199 <30>[ 24.587834] systemd[1]: Reached target remote-fs.target - Remote File Systems.
814 05:03:30.776706 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
815 05:03:30.809134 <30>[ 24.627716] systemd[1]: Reached target slices.target - Slice Units.
816 05:03:30.814610 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
817 05:03:30.850734 <30>[ 24.668723] systemd[1]: Reached target swap.target - Swaps.
818 05:03:30.854814 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
819 05:03:30.889915 <30>[ 24.708622] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
820 05:03:30.902494 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
821 05:03:30.940612 <30>[ 24.758709] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
822 05:03:30.948699 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
823 05:03:31.038972 <30>[ 24.852559] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
824 05:03:31.051644 <30>[ 24.870081] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
825 05:03:31.060110 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
826 05:03:31.091577 <30>[ 24.909477] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
827 05:03:31.099002 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
828 05:03:31.132476 <30>[ 24.950710] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
829 05:03:31.140672 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
830 05:03:31.175963 <30>[ 24.994940] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
831 05:03:31.189212 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
832 05:03:31.221012 <30>[ 25.039300] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
833 05:03:31.229688 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
834 05:03:31.266740 <30>[ 25.078980] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
835 05:03:31.283292 <30>[ 25.095695] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
836 05:03:31.320340 <30>[ 25.139666] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
837 05:03:31.338521 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
838 05:03:31.391054 <30>[ 25.210241] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
839 05:03:31.412631 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
840 05:03:31.530202 <30>[ 25.348350] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
841 05:03:31.559156 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
842 05:03:31.622512 <30>[ 25.441320] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
843 05:03:31.638788 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
844 05:03:31.669691 <30>[ 25.488723] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
845 05:03:31.688513 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
846 05:03:31.741169 <30>[ 25.560834] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
847 05:03:31.756198 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
848 05:03:31.822550 <30>[ 25.640956] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
849 05:03:31.858058 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
850 05:03:31.931085 <30>[ 25.750561] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
851 05:03:31.958225 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
852 05:03:32.022392 <30>[ 25.841825] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
853 05:03:32.049483 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
854 05:03:32.085914 <28>[ 25.899354] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
855 05:03:32.094532 <28>[ 25.913039] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
856 05:03:32.141602 <30>[ 25.961573] systemd[1]: Starting systemd-journald.service - Journal Service...
857 05:03:32.157729 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
858 05:03:32.230267 <30>[ 26.049373] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
859 05:03:32.255609 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
860 05:03:32.320988 <30>[ 26.140406] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
861 05:03:32.359165 Starting [0;1;39msystemd-network-g… units from Kernel command line...
862 05:03:32.422744 <30>[ 26.240609] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
863 05:03:32.459597 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
864 05:03:32.529711 <30>[ 26.348468] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
865 05:03:32.570726 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
866 05:03:32.630147 <30>[ 26.449728] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
867 05:03:32.671522 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
868 05:03:32.690407 <30>[ 26.509292] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
869 05:03:32.739028 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
870 05:03:32.772143 <30>[ 26.590494] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
871 05:03:32.802987 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
872 05:03:32.969705 <30>[ 26.789827] systemd[1]: modprobe@configfs.service: Deactivated successfully.
873 05:03:32.999949 <30>[ 26.818860] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
874 05:03:33.028990 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
875 05:03:33.060109 <30>[ 26.878885] systemd[1]: Started systemd-journald.service - Journal Service.
876 05:03:33.066982 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
877 05:03:33.109438 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
878 05:03:33.150053 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
879 05:03:33.200458 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
880 05:03:33.240327 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
881 05:03:33.274570 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
882 05:03:33.319075 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
883 05:03:33.351456 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
884 05:03:33.382374 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
885 05:03:33.423463 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
886 05:03:33.501142 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
887 05:03:33.558213 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
888 05:03:33.621868 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
889 05:03:33.741781 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
890 05:03:33.819324 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
891 05:03:33.961106 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
892 05:03:33.980129 <46>[ 27.799564] systemd-journald[164]: Received client request to flush runtime journal.
893 05:03:34.013683 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
894 05:03:34.185730 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
895 05:03:35.098127 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
896 05:03:35.174801 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
897 05:03:35.722283 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
898 05:03:35.898325 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
899 05:03:35.929905 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
900 05:03:35.958650 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
901 05:03:36.021130 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
902 05:03:36.067102 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
903 05:03:36.986464 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
904 05:03:37.035506 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
905 05:03:37.400531 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
906 05:03:37.519794 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
907 05:03:37.598847 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
908 05:03:39.630437 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
909 05:03:40.152157 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 05:03:40.590395 <5>[ 34.410322] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 05:03:40.677806 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
912 05:03:42.059875 <5>[ 35.877915] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
913 05:03:42.065238 <5>[ 35.885915] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 05:03:42.080731 <4>[ 35.900738] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 05:03:42.086625 <6>[ 35.909814] cfg80211: failed to load regulatory.db
916 05:03:42.509623 <46>[ 36.320651] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
917 05:03:42.651678 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
918 05:03:42.694251 <46>[ 36.507394] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
919 05:03:43.400084 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
920 05:03:51.246178 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
921 05:03:51.284487 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
922 05:03:51.320526 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
923 05:03:51.356350 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
924 05:03:51.434028 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
925 05:03:51.510055 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
926 05:03:51.560387 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
927 05:03:51.592357 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
928 05:03:51.653775 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
929 05:03:51.694811 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
930 05:03:51.744023 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
931 05:03:51.793514 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
932 05:03:51.846366 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
933 05:03:51.893977 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
934 05:03:51.931599 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
935 05:03:51.973503 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
936 05:03:52.018152 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
937 05:03:52.061409 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
938 05:03:52.102520 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
939 05:03:52.137265 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
940 05:03:52.179944 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
941 05:03:52.208193 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
942 05:03:52.243409 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
943 05:03:52.321229 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
944 05:03:52.356576 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
945 05:03:52.469959 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
946 05:03:52.573376 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
947 05:03:52.614273 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
948 05:03:52.656626 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
949 05:03:52.673415 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
950 05:03:52.858971 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
951 05:03:52.909428 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
952 05:03:52.962376 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
953 05:03:52.998492 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
954 05:03:53.029880 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
955 05:03:53.324105 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
956 05:03:53.650417 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
957 05:03:53.719956 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
958 05:03:53.769277 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
959 05:03:53.870587 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
960 05:03:54.049362 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
961 05:03:54.221760
962 05:03:54.225112 Debian GNU/Linux 12 worm-armhf login: root (automatic login)
963 05:03:54.225661
964 05:03:54.540473 Linux debian-bookworm-armhf 6.11.0-rc6 #1 SMP Mon Sep 2 03:54:42 UTC 2024 armv7l
965 05:03:54.541084
966 05:03:54.546053 The programs included with the Debian GNU/Linux system are free software;
967 05:03:54.551633 the exact distribution terms for each program are described in the
968 05:03:54.557276 individual files in /usr/share/doc/*/copyright.
969 05:03:54.557827
970 05:03:54.565313 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
971 05:03:54.565864 permitted by applicable law.
972 05:03:59.216976 Unable to match end of the kernel message
974 05:03:59.218721 Setting prompt string to ['/ #']
975 05:03:59.219372 end: 2.4.4.1 login-action (duration 00:00:53) [common]
977 05:03:59.221024 end: 2.4.4 auto-login-action (duration 00:00:54) [common]
978 05:03:59.221708 start: 2.4.5 expect-shell-connection (timeout 00:03:07) [common]
979 05:03:59.222273 Setting prompt string to ['/ #']
980 05:03:59.222818 Forcing a shell prompt, looking for ['/ #']
982 05:03:59.273899 / #
983 05:03:59.274536 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
984 05:03:59.275109 Waiting using forced prompt support (timeout 00:02:30)
985 05:03:59.278400
986 05:03:59.285888 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
987 05:03:59.286556 start: 2.4.6 export-device-env (timeout 00:03:07) [common]
988 05:03:59.287062 Sending with 10 millisecond of delay
990 05:04:04.274244 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9'
991 05:04:04.285241 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/689642/extract-nfsrootfs-t54_5pb9'
992 05:04:04.286353 Sending with 10 millisecond of delay
994 05:04:06.384248 / # export NFS_SERVER_IP='192.168.6.2'
995 05:04:06.395315 export NFS_SERVER_IP='192.168.6.2'
996 05:04:06.396458 end: 2.4.6 export-device-env (duration 00:00:07) [common]
997 05:04:06.396975 end: 2.4 uboot-commands (duration 00:02:00) [common]
998 05:04:06.397371 end: 2 uboot-action (duration 00:02:00) [common]
999 05:04:06.397721 start: 3 lava-test-retry (timeout 00:06:50) [common]
1000 05:04:06.398070 start: 3.1 lava-test-shell (timeout 00:06:50) [common]
1001 05:04:06.398349 Using namespace: common
1003 05:04:06.499144 / # #
1004 05:04:06.500022 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1005 05:04:06.504584 #
1006 05:04:06.510804 Using /lava-689642
1008 05:04:06.611637 / # export SHELL=/bin/bash
1009 05:04:06.615971 export SHELL=/bin/bash
1011 05:04:06.723814 / # . /lava-689642/environment
1012 05:04:06.729216 . /lava-689642/environment
1014 05:04:06.842223 / # /lava-689642/bin/lava-test-runner /lava-689642/0
1015 05:04:06.842929 Test shell timeout: 10s (minimum of the action and connection timeout)
1016 05:04:06.847383 /lava-689642/bin/lava-test-runner /lava-689642/0
1017 05:04:07.273073 + export TESTRUN_ID=0_timesync-off
1018 05:04:07.281103 + TESTRUN_ID=0_timesync-off
1019 05:04:07.281460 + cd /lava-689642/0/tests/0_timesync-off
1020 05:04:07.281703 ++ cat uuid
1021 05:04:07.296697 + UUID=689642_1.6.2.4.1
1022 05:04:07.297007 + set +x
1023 05:04:07.305290 <LAVA_SIGNAL_STARTRUN 0_timesync-off 689642_1.6.2.4.1>
1024 05:04:07.305575 + systemctl stop systemd-timesyncd
1025 05:04:07.306033 Received signal: <STARTRUN> 0_timesync-off 689642_1.6.2.4.1
1026 05:04:07.306280 Starting test lava.0_timesync-off (689642_1.6.2.4.1)
1027 05:04:07.306869 Skipping test definition patterns.
1028 05:04:07.586313 + set +x
1029 05:04:07.586974 <LAVA_SIGNAL_ENDRUN 0_timesync-off 689642_1.6.2.4.1>
1030 05:04:07.587707 Received signal: <ENDRUN> 0_timesync-off 689642_1.6.2.4.1
1031 05:04:07.588301 Ending use of test pattern.
1032 05:04:07.588754 Ending test lava.0_timesync-off (689642_1.6.2.4.1), duration 0.28
1034 05:04:07.765052 + export TESTRUN_ID=1_kselftest-dt
1035 05:04:07.773084 + TESTRUN_ID=1_kselftest-dt
1036 05:04:07.773629 + cd /lava-689642/0/tests/1_kselftest-dt
1037 05:04:07.774094 ++ cat uuid
1038 05:04:07.788669 + UUID=689642_1.6.2.4.5
1039 05:04:07.789196 + set +x
1040 05:04:07.794222 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 689642_1.6.2.4.5>
1041 05:04:07.794743 + cd ./automated/linux/kselftest/
1042 05:04:07.795474 Received signal: <STARTRUN> 1_kselftest-dt 689642_1.6.2.4.5
1043 05:04:07.795948 Starting test lava.1_kselftest-dt (689642_1.6.2.4.5)
1044 05:04:07.796525 Skipping test definition patterns.
1045 05:04:07.822628 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1046 05:04:07.962714 INFO: install_deps skipped
1047 05:04:08.453484 --2024-09-02 05:04:08-- http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
1048 05:04:08.488987 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1049 05:04:08.631314 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1050 05:04:08.771240 HTTP request sent, awaiting response... 200 OK
1051 05:04:08.771525 Length: 2287464 (2.2M) [application/octet-stream]
1052 05:04:08.776659 Saving to: 'kselftest_armhf.tar.gz'
1053 05:04:08.776927
1054 05:04:10.106013
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 2%[ ] 49.92K 179KB/s
kselftest_armhf.tar 9%[> ] 218.67K 392KB/s
kselftest_armhf.tar 32%[=====> ] 729.57K 827KB/s
kselftest_armhf.tar 57%[==========> ] 1.24M 1.12MB/s
kselftest_armhf.tar 93%[=================> ] 2.04M 1.55MB/s
kselftest_armhf.tar 100%[===================>] 2.18M 1.64MB/s in 1.3s
1055 05:04:10.106628
1056 05:04:10.415405 2024-09-02 05:04:10 (1.64 MB/s) - 'kselftest_armhf.tar.gz' saved [2287464/2287464]
1057 05:04:10.416108
1058 05:04:19.422101 skiplist:
1059 05:04:19.422787 ========================================
1060 05:04:19.427767 ========================================
1061 05:04:19.521577 dt:test_unprobed_devices.sh
1062 05:04:19.552180 ============== Tests to run ===============
1063 05:04:19.560492 dt:test_unprobed_devices.sh
1064 05:04:19.564478 ===========End Tests to run ===============
1065 05:04:19.573491 shardfile-dt pass
1066 05:04:19.799463 <12>[ 73.625004] kselftest: Running tests in dt
1067 05:04:19.827437 TAP version 13
1068 05:04:19.851016 1..1
1069 05:04:19.903577 # timeout set to 45
1070 05:04:19.904136 # selftests: dt: test_unprobed_devices.sh
1071 05:04:20.765511 # TAP version 13
1072 05:04:33.010769 # 1..255
1073 05:04:33.172223 # ok 1 / # SKIP
1074 05:04:33.193379 # ok 2 /clk_mcasp0
1075 05:04:33.263589 # ok 3 /clk_mcasp0_fixed # SKIP
1076 05:04:33.337533 # ok 4 /cpus/cpu@0 # SKIP
1077 05:04:33.407342 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1078 05:04:33.428742 # ok 6 /fixedregulator0
1079 05:04:33.453470 # ok 7 /leds
1080 05:04:33.470134 # ok 8 /ocp
1081 05:04:33.493703 # ok 9 /ocp/interconnect@44c00000
1082 05:04:33.516521 # ok 10 /ocp/interconnect@44c00000/segment@0
1083 05:04:33.541031 # ok 11 /ocp/interconnect@44c00000/segment@100000
1084 05:04:33.563937 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1085 05:04:33.635454 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1086 05:04:33.660529 # ok 14 /ocp/interconnect@44c00000/segment@200000
1087 05:04:33.683250 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1088 05:04:33.782497 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1089 05:04:33.855095 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1090 05:04:33.930368 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1091 05:04:34.003403 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1092 05:04:34.074026 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1093 05:04:34.145402 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1094 05:04:34.209636 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1095 05:04:34.286050 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1096 05:04:34.350514 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1097 05:04:34.428780 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1098 05:04:34.495210 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1099 05:04:34.573111 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1100 05:04:34.636657 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1101 05:04:34.712553 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1102 05:04:34.784279 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1103 05:04:34.855967 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1104 05:04:34.917941 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1105 05:04:34.994988 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1106 05:04:35.065892 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1107 05:04:35.130029 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1108 05:04:35.200398 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1109 05:04:35.277216 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1110 05:04:35.347263 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1111 05:04:35.420495 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1112 05:04:35.493999 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1113 05:04:35.560256 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1114 05:04:35.636081 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1115 05:04:35.706280 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1116 05:04:35.776702 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1117 05:04:35.847278 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1118 05:04:35.919635 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1119 05:04:35.986293 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1120 05:04:36.056659 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1121 05:04:36.132154 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1122 05:04:36.204923 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1123 05:04:36.276673 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1124 05:04:36.341239 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1125 05:04:36.418063 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1126 05:04:36.482839 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1127 05:04:36.559873 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1128 05:04:36.631488 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1129 05:04:36.697679 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1130 05:04:36.767450 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1131 05:04:36.845325 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1132 05:04:36.916606 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1133 05:04:36.989076 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1134 05:04:37.052611 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1135 05:04:37.126589 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1136 05:04:37.201804 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1137 05:04:37.274893 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1138 05:04:37.339210 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1139 05:04:37.419307 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1140 05:04:37.487357 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1141 05:04:37.553996 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1142 05:04:37.631317 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1143 05:04:37.702260 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1144 05:04:37.775901 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1145 05:04:37.839124 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1146 05:04:37.918889 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1147 05:04:37.991172 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1148 05:04:38.064875 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1149 05:04:38.129654 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1150 05:04:38.209613 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1151 05:04:38.279366 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1152 05:04:38.346190 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1153 05:04:38.424409 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1154 05:04:38.493656 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1155 05:04:38.567100 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1156 05:04:38.630141 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1157 05:04:38.702024 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1158 05:04:38.778584 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1159 05:04:38.850373 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1160 05:04:38.921895 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1161 05:04:38.994311 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1162 05:04:39.067064 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1163 05:04:39.138272 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1164 05:04:39.208720 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1165 05:04:39.274073 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1166 05:04:39.350757 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1167 05:04:39.374203 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1168 05:04:39.396705 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1169 05:04:39.417876 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1170 05:04:39.442471 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1171 05:04:39.466596 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1172 05:04:39.485576 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1173 05:04:39.515736 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1174 05:04:39.533591 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1175 05:04:39.638968 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1176 05:04:39.666089 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1177 05:04:39.682384 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1178 05:04:39.714092 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1179 05:04:39.809264 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1180 05:04:39.890444 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1181 05:04:39.960471 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1182 05:04:40.026568 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1183 05:04:40.105409 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1184 05:04:40.170543 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1185 05:04:40.248895 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1186 05:04:40.312272 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1187 05:04:40.390133 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1188 05:04:40.458721 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1189 05:04:40.535920 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1190 05:04:40.606768 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1191 05:04:40.672271 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1192 05:04:40.750249 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1193 05:04:40.819434 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1194 05:04:40.896940 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1195 05:04:40.918425 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1196 05:04:40.979851 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1197 05:04:41.052605 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1198 05:04:41.118647 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1199 05:04:41.143493 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1200 05:04:41.214093 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1201 05:04:41.242565 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1202 05:04:41.313224 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1203 05:04:41.335385 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1204 05:04:41.352484 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1205 05:04:41.380758 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1206 05:04:41.406485 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1207 05:04:41.422303 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1208 05:04:41.446295 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1209 05:04:41.476553 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1210 05:04:41.496680 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1211 05:04:41.524280 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1212 05:04:41.595689 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1213 05:04:41.666585 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1214 05:04:41.684289 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1215 05:04:41.755653 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1216 05:04:41.829693 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1217 05:04:41.925389 # not ok 145 /ocp/interconnect@47c00000
1218 05:04:41.989587 # not ok 146 /ocp/interconnect@47c00000/segment@0
1219 05:04:42.015121 # ok 147 /ocp/interconnect@48000000
1220 05:04:42.037657 # ok 148 /ocp/interconnect@48000000/segment@0
1221 05:04:42.062097 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 05:04:42.083287 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 05:04:42.104242 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 05:04:42.131810 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 05:04:42.155147 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 05:04:42.179409 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 05:04:42.204259 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 05:04:42.266239 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 05:04:42.338885 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 05:04:42.365992 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 05:04:42.392502 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 05:04:42.411898 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 05:04:42.432391 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 05:04:42.460078 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 05:04:42.483719 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 05:04:42.509047 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 05:04:42.526584 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 05:04:42.549465 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 05:04:42.578649 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 05:04:42.602106 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 05:04:42.624209 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 05:04:42.642242 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 05:04:42.673288 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 05:04:42.690260 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1245 05:04:42.718836 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1246 05:04:42.742907 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1247 05:04:42.765295 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1248 05:04:42.783669 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1249 05:04:42.810623 # ok 177 /ocp/interconnect@48000000/segment@100000
1250 05:04:42.828952 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1251 05:04:42.853891 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1252 05:04:42.931246 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1253 05:04:42.994234 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 05:04:43.072092 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1255 05:04:43.138190 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1256 05:04:43.162755 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1257 05:04:43.178124 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1258 05:04:43.204039 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1259 05:04:43.230664 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1260 05:04:43.253202 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1261 05:04:43.281178 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1262 05:04:43.302125 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1263 05:04:43.324696 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1264 05:04:43.344801 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1265 05:04:43.368225 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1266 05:04:43.393390 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1267 05:04:43.422581 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1268 05:04:43.444160 # ok 196 /ocp/interconnect@48000000/segment@200000
1269 05:04:43.460962 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1270 05:04:43.538302 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1271 05:04:43.560652 # ok 199 /ocp/interconnect@48000000/segment@300000
1272 05:04:43.577385 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1273 05:04:43.602297 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1274 05:04:43.632262 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1275 05:04:43.655048 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1276 05:04:43.672172 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1277 05:04:43.698867 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1278 05:04:43.771280 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1279 05:04:43.791563 # ok 207 /ocp/interconnect@4a000000
1280 05:04:43.810448 # ok 208 /ocp/interconnect@4a000000/segment@0
1281 05:04:43.833964 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1282 05:04:43.863555 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1283 05:04:43.882246 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1284 05:04:43.909602 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1285 05:04:43.983023 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1286 05:04:44.081640 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1287 05:04:44.157290 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1288 05:04:44.261911 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1289 05:04:44.337460 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1290 05:04:44.403211 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1291 05:04:44.498696 # not ok 219 /ocp/interconnect@4b140000
1292 05:04:44.573039 # not ok 220 /ocp/interconnect@4b140000/segment@0
1293 05:04:44.645606 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1294 05:04:44.667202 # ok 222 /ocp/target-module@40300000
1295 05:04:44.693074 # ok 223 /ocp/target-module@40300000/sram@0
1296 05:04:44.757310 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1297 05:04:44.829078 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1298 05:04:44.852531 # ok 226 /ocp/target-module@47400000
1299 05:04:44.877929 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1300 05:04:44.899343 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1301 05:04:44.921501 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1302 05:04:44.940536 # ok 230 /ocp/target-module@47400000/usb@1400
1303 05:04:44.967862 # ok 231 /ocp/target-module@47400000/usb@1800
1304 05:04:44.989194 # ok 232 /ocp/target-module@47810000
1305 05:04:45.010319 # ok 233 /ocp/target-module@49000000
1306 05:04:45.028313 # ok 234 /ocp/target-module@49000000/dma@0
1307 05:04:45.056879 # ok 235 /ocp/target-module@49800000
1308 05:04:45.078889 # ok 236 /ocp/target-module@49800000/dma@0
1309 05:04:45.099202 # ok 237 /ocp/target-module@49900000
1310 05:04:45.119031 # ok 238 /ocp/target-module@49900000/dma@0
1311 05:04:45.140864 # ok 239 /ocp/target-module@49a00000
1312 05:04:45.163672 # ok 240 /ocp/target-module@49a00000/dma@0
1313 05:04:45.190279 # ok 241 /ocp/target-module@4c000000
1314 05:04:45.263670 # not ok 242 /ocp/target-module@4c000000/emif@0
1315 05:04:45.279195 # ok 243 /ocp/target-module@50000000
1316 05:04:45.305078 # ok 244 /ocp/target-module@53100000
1317 05:04:45.370632 # not ok 245 /ocp/target-module@53100000/sham@0
1318 05:04:45.399688 # ok 246 /ocp/target-module@53500000
1319 05:04:45.462659 # not ok 247 /ocp/target-module@53500000/aes@0
1320 05:04:45.483331 # ok 248 /ocp/target-module@56000000
1321 05:04:45.590423 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1322 05:04:45.658208 # ok 250 /opp-table # SKIP
1323 05:04:45.725490 # ok 251 /soc # SKIP
1324 05:04:45.740913 # ok 252 /sound
1325 05:04:45.768940 # ok 253 /target-module@4b000000
1326 05:04:45.789044 # ok 254 /target-module@4b000000/target-module@140000
1327 05:04:45.812612 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1328 05:04:45.818741 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1329 05:04:45.824572 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1330 05:04:48.017364 dt_test_unprobed_devices_sh_ skip
1331 05:04:48.022729 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1332 05:04:48.028359 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1333 05:04:48.028929 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1334 05:04:48.037221 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1335 05:04:48.037788 dt_test_unprobed_devices_sh_fixedregulator0 pass
1336 05:04:48.042844 dt_test_unprobed_devices_sh_leds pass
1337 05:04:48.048484 dt_test_unprobed_devices_sh_ocp pass
1338 05:04:48.051916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1339 05:04:48.057509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1340 05:04:48.063101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1341 05:04:48.074265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1342 05:04:48.079913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1343 05:04:48.085508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1344 05:04:48.096661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1345 05:04:48.102373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1346 05:04:48.113684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1347 05:04:48.124745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1348 05:04:48.130373 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1349 05:04:48.141582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1350 05:04:48.152805 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1351 05:04:48.164080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1352 05:04:48.175209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1353 05:04:48.180838 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1354 05:04:48.191964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1355 05:04:48.203150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1356 05:04:48.214413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1357 05:04:48.225556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1358 05:04:48.231174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1359 05:04:48.242332 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1360 05:04:48.253517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1361 05:04:48.264710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1362 05:04:48.270364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1363 05:04:48.281501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1364 05:04:48.292696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1365 05:04:48.303884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1366 05:04:48.309543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1367 05:04:48.320670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1368 05:04:48.331866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1369 05:04:48.343087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1370 05:04:48.354252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1371 05:04:48.365459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1372 05:04:48.376619 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1373 05:04:48.387836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1374 05:04:48.399097 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1375 05:04:48.410239 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1376 05:04:48.421417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1377 05:04:48.432607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1378 05:04:48.443811 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1379 05:04:48.454986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1380 05:04:48.466176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1381 05:04:48.477375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1382 05:04:48.488548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1383 05:04:48.499780 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1384 05:04:48.511037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1385 05:04:48.522171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1386 05:04:48.533366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1387 05:04:48.544532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1388 05:04:48.555737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1389 05:04:48.566931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1390 05:04:48.578130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1391 05:04:48.589304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1392 05:04:48.594967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1393 05:04:48.606140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1394 05:04:48.617289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1395 05:04:48.628481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1396 05:04:48.639665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1397 05:04:48.650886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1398 05:04:48.662062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1399 05:04:48.673241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1400 05:04:48.684438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1401 05:04:48.695625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1402 05:04:48.706826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1403 05:04:48.718024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1404 05:04:48.729197 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1405 05:04:48.740416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1406 05:04:48.751610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1407 05:04:48.762813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1408 05:04:48.774003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1409 05:04:48.785213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1410 05:04:48.790834 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1411 05:04:48.801793 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1412 05:04:48.813079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1413 05:04:48.824171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1414 05:04:48.835358 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1415 05:04:48.846555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1416 05:04:48.852258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1417 05:04:48.863352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1418 05:04:48.874535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1419 05:04:48.885876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1420 05:04:48.897126 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1421 05:04:48.908336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1422 05:04:48.919295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1423 05:04:48.936293 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1424 05:04:48.941882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1425 05:04:48.952896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1426 05:04:48.964077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1427 05:04:48.969681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1428 05:04:48.980870 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1429 05:04:48.992088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1430 05:04:48.997781 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1431 05:04:49.009001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1432 05:04:49.014587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1433 05:04:49.025770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1434 05:04:49.036959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1435 05:04:49.048229 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1436 05:04:49.053772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1437 05:04:49.064944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1438 05:04:49.081731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1439 05:04:49.092923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1440 05:04:49.104181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1441 05:04:49.115287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1442 05:04:49.126499 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1443 05:04:49.137694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1444 05:04:49.148890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1445 05:04:49.160077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1446 05:04:49.176862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1447 05:04:49.188074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1448 05:04:49.199245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1449 05:04:49.210432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1450 05:04:49.227197 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1451 05:04:49.238413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1452 05:04:49.249605 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1453 05:04:49.260799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1454 05:04:49.266407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1455 05:04:49.277587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1456 05:04:49.283225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1457 05:04:49.294382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1458 05:04:49.299996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1459 05:04:49.311179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1460 05:04:49.316772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1461 05:04:49.327952 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1462 05:04:49.333543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1463 05:04:49.344747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1464 05:04:49.355930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1465 05:04:49.361536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1466 05:04:49.372697 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1467 05:04:49.383904 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1468 05:04:49.389531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1469 05:04:49.400699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1470 05:04:49.411902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1471 05:04:49.423078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1472 05:04:49.428692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1473 05:04:49.439869 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1474 05:04:49.445476 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1475 05:04:49.451074 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1476 05:04:49.456660 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1477 05:04:49.462234 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1478 05:04:49.467837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1479 05:04:49.479065 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1480 05:04:49.484645 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1481 05:04:49.495843 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1482 05:04:49.501439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1483 05:04:49.507029 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1484 05:04:49.518224 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1485 05:04:49.523790 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1486 05:04:49.535001 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1487 05:04:49.540597 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1488 05:04:49.551787 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1489 05:04:49.557389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1490 05:04:49.568575 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1491 05:04:49.574213 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1492 05:04:49.585389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1493 05:04:49.590991 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1494 05:04:49.602211 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1495 05:04:49.607754 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1496 05:04:49.618969 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1497 05:04:49.624574 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1498 05:04:49.630219 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1499 05:04:49.641354 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1500 05:04:49.646945 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1501 05:04:49.658224 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1502 05:04:49.663717 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1503 05:04:49.674932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1504 05:04:49.680522 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1505 05:04:49.691719 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1506 05:04:49.697318 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1507 05:04:49.702922 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1508 05:04:49.714114 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1509 05:04:49.725300 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1510 05:04:49.736485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1511 05:04:49.742111 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1512 05:04:49.753286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1513 05:04:49.764476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1514 05:04:49.770090 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1515 05:04:49.781283 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1516 05:04:49.786869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1517 05:04:49.798069 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1518 05:04:49.803669 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1519 05:04:49.814862 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1520 05:04:49.820453 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1521 05:04:49.831629 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1522 05:04:49.837248 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1523 05:04:49.848414 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1524 05:04:49.854030 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1525 05:04:49.865244 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1526 05:04:49.870797 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1527 05:04:49.876399 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1528 05:04:49.887553 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1529 05:04:49.893234 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1530 05:04:49.904364 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1531 05:04:49.909969 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1532 05:04:49.921150 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1533 05:04:49.926750 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1534 05:04:49.937898 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1535 05:04:49.943549 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1536 05:04:49.949131 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1537 05:04:49.954734 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1538 05:04:49.965903 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1539 05:04:49.971545 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1540 05:04:49.982737 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1541 05:04:49.988327 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1542 05:04:49.999512 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1543 05:04:50.010703 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1544 05:04:50.021877 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1545 05:04:50.027489 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1546 05:04:50.038685 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1547 05:04:50.049885 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1548 05:04:50.055481 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1549 05:04:50.061050 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1550 05:04:50.066685 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1551 05:04:50.072280 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1552 05:04:50.077877 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1553 05:04:50.083472 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1554 05:04:50.089073 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1555 05:04:50.094682 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1556 05:04:50.105902 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1557 05:04:50.111488 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1558 05:04:50.117181 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1559 05:04:50.122820 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1560 05:04:50.128397 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1561 05:04:50.133978 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1562 05:04:50.139598 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1563 05:04:50.145190 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1564 05:04:50.150784 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1565 05:04:50.156411 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1566 05:04:50.161976 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1567 05:04:50.167606 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1568 05:04:50.173197 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1569 05:04:50.178791 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1570 05:04:50.184405 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1571 05:04:50.189977 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1572 05:04:50.195586 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1573 05:04:50.201175 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1574 05:04:50.206772 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1575 05:04:50.212414 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1576 05:04:50.218026 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1577 05:04:50.223614 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1578 05:04:50.229168 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1579 05:04:50.234762 dt_test_unprobed_devices_sh_opp-table skip
1580 05:04:50.235321 dt_test_unprobed_devices_sh_soc skip
1581 05:04:50.240369 dt_test_unprobed_devices_sh_sound pass
1582 05:04:50.245955 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1583 05:04:50.251560 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1584 05:04:50.257162 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1585 05:04:50.262752 dt_test_unprobed_devices_sh fail
1586 05:04:50.268377 + ../../utils/send-to-lava.sh ./output/result.txt
1587 05:04:50.272572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1588 05:04:50.273584 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1590 05:04:50.334964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1591 05:04:50.335835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1593 05:04:50.426733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1594 05:04:50.427746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1596 05:04:50.517444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1597 05:04:50.518312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1599 05:04:50.601391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1600 05:04:50.602256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1602 05:04:50.693607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1603 05:04:50.694474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1605 05:04:50.782321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1606 05:04:50.783182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1608 05:04:50.866486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1609 05:04:50.867337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1611 05:04:50.955943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1612 05:04:50.956827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1614 05:04:51.042012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1615 05:04:51.042865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1617 05:04:51.132922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1618 05:04:51.133841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1620 05:04:51.217633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1621 05:04:51.218500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1623 05:04:51.308834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1624 05:04:51.309875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1626 05:04:51.400573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1627 05:04:51.401451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1629 05:04:51.488708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1630 05:04:51.489565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1632 05:04:51.579478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1633 05:04:51.580528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1635 05:04:51.670254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1636 05:04:51.671129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1638 05:04:51.759129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1639 05:04:51.760065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1641 05:04:51.844797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1642 05:04:51.845673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1644 05:04:51.930097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1645 05:04:51.930970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1647 05:04:52.018783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1648 05:04:52.019676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1650 05:04:52.105514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1651 05:04:52.106387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1653 05:04:52.194303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1654 05:04:52.195228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1656 05:04:52.278421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1657 05:04:52.279328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1659 05:04:52.369359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1660 05:04:52.370240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1662 05:04:52.459928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1663 05:04:52.460847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1665 05:04:52.549313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1666 05:04:52.550192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1668 05:04:52.639922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1669 05:04:52.640920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1671 05:04:52.724395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1672 05:04:52.725179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1674 05:04:52.808650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1675 05:04:52.809428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1677 05:04:52.899408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1678 05:04:52.900341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1680 05:04:52.990519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1681 05:04:52.991251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1683 05:04:53.078814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1684 05:04:53.079517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1686 05:04:53.170832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1687 05:04:53.171691 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1689 05:04:53.260824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1690 05:04:53.261658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1692 05:04:53.351627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1693 05:04:53.352536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1695 05:04:53.441040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1696 05:04:53.442968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1698 05:04:53.532283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1699 05:04:53.533145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1701 05:04:53.622456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1702 05:04:53.623318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1704 05:04:53.713678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1705 05:04:53.714534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1707 05:04:53.798314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1708 05:04:53.799188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1710 05:04:53.888605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1711 05:04:53.889453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1713 05:04:53.972564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1714 05:04:53.973422 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1716 05:04:54.055310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1717 05:04:54.056168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1719 05:04:54.138048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1720 05:04:54.140019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1722 05:04:54.222339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1723 05:04:54.223929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1725 05:04:54.311646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1726 05:04:54.312225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1728 05:04:54.405410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1729 05:04:54.405961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1731 05:04:54.495164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1732 05:04:54.495964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1734 05:04:54.580086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1735 05:04:54.580945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1737 05:04:54.668907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1738 05:04:54.669783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1740 05:04:54.759110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1741 05:04:54.759969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1743 05:04:54.848657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1744 05:04:54.849506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1746 05:04:54.932347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1747 05:04:54.933193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1749 05:04:55.016652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1750 05:04:55.017501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1752 05:04:55.099400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1753 05:04:55.100291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1755 05:04:55.183529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1756 05:04:55.184534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1758 05:04:55.273549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1759 05:04:55.274288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1761 05:04:55.358975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1762 05:04:55.360091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1764 05:04:55.450184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1765 05:04:55.450985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1767 05:04:55.541695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1768 05:04:55.542506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1770 05:04:55.631904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1771 05:04:55.632720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1773 05:04:55.722289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1774 05:04:55.723051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1776 05:04:55.813630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1777 05:04:55.814428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1779 05:04:55.899376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1780 05:04:55.900141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1782 05:04:55.988751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1783 05:04:55.989509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1785 05:04:56.074773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1786 05:04:56.075531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1788 05:04:56.165783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1789 05:04:56.166530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1791 05:04:56.256523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1792 05:04:56.257269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1794 05:04:56.341779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1795 05:04:56.342633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1797 05:04:56.432211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1798 05:04:56.433153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1800 05:04:56.523032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1801 05:04:56.523869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1803 05:04:56.606973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1804 05:04:56.609193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1806 05:04:56.696807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1807 05:04:56.697645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1809 05:04:56.780290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1810 05:04:56.781252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1812 05:04:56.865585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1813 05:04:56.866529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1815 05:04:56.950807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1816 05:04:56.951715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1818 05:04:57.042331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1819 05:04:57.043199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1821 05:04:57.133653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1822 05:04:57.135676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1824 05:04:57.222679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1825 05:04:57.223373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1827 05:04:57.314715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1828 05:04:57.315305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1830 05:04:57.399712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1831 05:04:57.400549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1833 05:04:57.490651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1834 05:04:57.491513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1836 05:04:57.580632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1837 05:04:57.581492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1839 05:04:57.671107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1840 05:04:57.671962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1842 05:04:57.760599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1843 05:04:57.763045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1845 05:04:57.852964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1846 05:04:57.853631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1848 05:04:57.936965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1849 05:04:57.938045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1851 05:04:58.027612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1852 05:04:58.028727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1854 05:04:58.114930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1855 05:04:58.115874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1857 05:04:58.207871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1858 05:04:58.208857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1860 05:04:58.296403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1861 05:04:58.297315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1863 05:04:58.383582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1864 05:04:58.384542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1866 05:04:58.475920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1867 05:04:58.476913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1869 05:04:58.566791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1870 05:04:58.567801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1872 05:04:58.650824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1873 05:04:58.651728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1875 05:04:58.741451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1876 05:04:58.742492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1878 05:04:58.826440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1879 05:04:58.827425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1881 05:04:58.917631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1882 05:04:58.918560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1884 05:04:59.008832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1885 05:04:59.009746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1887 05:04:59.099452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1888 05:04:59.100385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1890 05:04:59.190228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1891 05:04:59.191168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1893 05:04:59.278926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1894 05:04:59.279871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1896 05:04:59.370847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1897 05:04:59.371776 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1899 05:04:59.461773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1900 05:04:59.462828 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1902 05:04:59.551186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1903 05:04:59.552112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1905 05:04:59.641686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1906 05:04:59.642576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1908 05:04:59.731271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1909 05:04:59.732155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1911 05:04:59.823320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1912 05:04:59.824192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1914 05:04:59.914412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1915 05:04:59.916605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1917 05:04:59.998644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1918 05:04:59.999524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1920 05:05:00.089568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1921 05:05:00.090427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1923 05:05:00.180315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1924 05:05:00.182408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1926 05:05:00.270600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1927 05:05:00.271475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1929 05:05:00.360067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1930 05:05:00.360924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1932 05:05:00.445642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1933 05:05:00.446507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1935 05:05:00.531810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1936 05:05:00.532724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1938 05:05:00.624362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1939 05:05:00.625247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1941 05:05:00.714583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1942 05:05:00.716781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1944 05:05:00.802954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1945 05:05:00.803557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1947 05:05:00.893513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1949 05:05:00.896518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1950 05:05:00.979795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1952 05:05:00.982838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1953 05:05:01.070426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1955 05:05:01.073524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1956 05:05:01.160505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1957 05:05:01.161331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1959 05:05:01.249760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1960 05:05:01.250675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1962 05:05:01.333454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1963 05:05:01.334341 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1965 05:05:01.420271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1966 05:05:01.421169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1968 05:05:01.510008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1969 05:05:01.510892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1971 05:05:01.602579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1972 05:05:01.603460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1974 05:05:01.689146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1975 05:05:01.690109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1977 05:05:01.779836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1978 05:05:01.780788 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1980 05:05:01.869633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1981 05:05:01.870537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1983 05:05:01.960241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1984 05:05:01.961118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1986 05:05:02.049146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1987 05:05:02.050039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1989 05:05:02.143839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1990 05:05:02.144533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1992 05:05:02.233146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1993 05:05:02.233778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1995 05:05:02.324400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1996 05:05:02.325053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1998 05:05:02.411551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1999 05:05:02.412190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2001 05:05:02.500850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2002 05:05:02.501794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2004 05:05:02.594702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2005 05:05:02.595622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2007 05:05:02.686510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2008 05:05:02.687554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2010 05:05:02.771366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2011 05:05:02.772356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2013 05:05:02.859589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2014 05:05:02.860541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2016 05:05:02.953180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2017 05:05:02.954121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2019 05:05:03.037722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2020 05:05:03.038644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2022 05:05:03.124199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2023 05:05:03.125091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2025 05:05:03.215435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2026 05:05:03.216415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2028 05:05:03.306519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2029 05:05:03.307335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2031 05:05:03.396718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2032 05:05:03.397503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2034 05:05:03.488968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2035 05:05:03.489848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2037 05:05:03.578491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2038 05:05:03.579311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2040 05:05:03.662934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2041 05:05:03.663868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2043 05:05:03.748559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2044 05:05:03.749499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2046 05:05:03.837907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2047 05:05:03.838840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2049 05:05:03.929924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2050 05:05:03.930839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2052 05:05:04.013081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2053 05:05:04.014069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2055 05:05:04.103603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2056 05:05:04.104534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2058 05:05:04.189505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2059 05:05:04.190412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2061 05:05:04.277479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2062 05:05:04.278385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2064 05:05:04.370284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2065 05:05:04.371188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2067 05:05:04.453991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2068 05:05:04.454889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2070 05:05:04.545009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2071 05:05:04.545926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2073 05:05:04.630558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2074 05:05:04.631439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2076 05:05:04.723546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2077 05:05:04.724465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2079 05:05:04.808409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2080 05:05:04.809241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2082 05:05:04.899098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2083 05:05:04.899952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2085 05:05:04.988208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2086 05:05:04.989038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2088 05:05:05.079604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2089 05:05:05.080525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2091 05:05:05.163085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2092 05:05:05.163974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2094 05:05:05.249046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2095 05:05:05.249959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2097 05:05:05.339104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2098 05:05:05.340023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2100 05:05:05.429409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2101 05:05:05.430231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2103 05:05:05.518469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2104 05:05:05.519263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2106 05:05:05.609005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2107 05:05:05.609795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2109 05:05:05.699949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2110 05:05:05.700809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2112 05:05:05.788234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2113 05:05:05.789055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2115 05:05:05.878964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2116 05:05:05.879759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2118 05:05:05.957314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2119 05:05:05.958147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2121 05:05:06.042390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2122 05:05:06.043293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2124 05:05:06.126594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2125 05:05:06.127682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2127 05:05:06.218041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2128 05:05:06.218957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2130 05:05:06.301728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2131 05:05:06.302634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2133 05:05:06.385350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2134 05:05:06.386204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2136 05:05:06.470268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2137 05:05:06.471082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2139 05:05:06.562311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2140 05:05:06.563112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2142 05:05:06.651113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2143 05:05:06.652044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2145 05:05:06.736042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2146 05:05:06.736975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2148 05:05:06.831234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2149 05:05:06.832188 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2151 05:05:06.922617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2152 05:05:06.923551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2154 05:05:07.027919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2155 05:05:07.028884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2157 05:05:07.119226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2158 05:05:07.120111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2160 05:05:07.209387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2161 05:05:07.210261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2163 05:05:07.297582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2164 05:05:07.298452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2166 05:05:07.381847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2167 05:05:07.382705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2169 05:05:07.473920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2170 05:05:07.474789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2172 05:05:07.565161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2173 05:05:07.566038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2175 05:05:07.647501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2176 05:05:07.648385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2178 05:05:07.740244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2179 05:05:07.741088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2181 05:05:07.831021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2182 05:05:07.831883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2184 05:05:07.913005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2185 05:05:07.913867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2187 05:05:08.004454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2188 05:05:08.005313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2190 05:05:08.090524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2191 05:05:08.091377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2193 05:05:08.181357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2194 05:05:08.182230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2196 05:05:08.272772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2197 05:05:08.273657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2199 05:05:08.357415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2200 05:05:08.358258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2202 05:05:08.440881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2203 05:05:08.441492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2205 05:05:08.526728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2206 05:05:08.527512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2208 05:05:08.613330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2209 05:05:08.614231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2211 05:05:08.699250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2212 05:05:08.700168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2214 05:05:08.790809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2215 05:05:08.791853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2217 05:05:08.876550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2218 05:05:08.877445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2220 05:05:08.967959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2221 05:05:08.968902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2223 05:05:09.051313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2224 05:05:09.053170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2226 05:05:09.142950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2227 05:05:09.145334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2229 05:05:09.229447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2230 05:05:09.231061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2232 05:05:09.316044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2233 05:05:09.316961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2235 05:05:09.400222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2236 05:05:09.401117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2238 05:05:09.490976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2239 05:05:09.491874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2241 05:05:09.580906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2242 05:05:09.581858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2244 05:05:09.665321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2245 05:05:09.666234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2247 05:05:09.757391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2248 05:05:09.758330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2250 05:05:09.841843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2251 05:05:09.842765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2253 05:05:09.931546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2254 05:05:09.932499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2256 05:05:10.017585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2257 05:05:10.018491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2259 05:05:10.109330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2260 05:05:10.110421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2262 05:05:10.191390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2264 05:05:10.194382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2265 05:05:10.283594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2266 05:05:10.284482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2268 05:05:10.376460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2269 05:05:10.377273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2271 05:05:10.466145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2272 05:05:10.467112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2274 05:05:10.550773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2275 05:05:10.551658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2277 05:05:10.634975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2278 05:05:10.635790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2280 05:05:10.725626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2281 05:05:10.726279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2283 05:05:10.815534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2284 05:05:10.816580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2286 05:05:10.904355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2287 05:05:10.905161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2289 05:05:10.988807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2290 05:05:10.989530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2292 05:05:11.072402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2293 05:05:11.073146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2295 05:05:11.157139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2296 05:05:11.157875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2298 05:05:11.241014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2299 05:05:11.241762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2301 05:05:11.325896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2302 05:05:11.326803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2304 05:05:11.415593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2305 05:05:11.416509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2307 05:05:11.504975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2308 05:05:11.505840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2310 05:05:11.588069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2311 05:05:11.588939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2313 05:05:11.671469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2314 05:05:11.672373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2316 05:05:11.754406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2317 05:05:11.755265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2319 05:05:11.844038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2320 05:05:11.844896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2322 05:05:11.935877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2323 05:05:11.936786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2325 05:05:12.023593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2326 05:05:12.024483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2328 05:05:12.115500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2329 05:05:12.116497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2331 05:05:12.205403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2332 05:05:12.206280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2334 05:05:12.297118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2335 05:05:12.298005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2337 05:05:12.378895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2338 05:05:12.379746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2340 05:05:12.463206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2341 05:05:12.464079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2343 05:05:12.554580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2344 05:05:12.555442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2346 05:05:12.644875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2347 05:05:12.645724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2349 05:05:12.730100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2350 05:05:12.730975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2352 05:05:12.814878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2353 05:05:12.815747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2355 05:05:12.901174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2356 05:05:12.901772 + set +x
2357 05:05:12.902510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2359 05:05:12.910795 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 689642_1.6.2.4.5>
2360 05:05:12.911351 <LAVA_TEST_RUNNER EXIT>
2361 05:05:12.912081 Received signal: <ENDRUN> 1_kselftest-dt 689642_1.6.2.4.5
2362 05:05:12.912596 Ending use of test pattern.
2363 05:05:12.913051 Ending test lava.1_kselftest-dt (689642_1.6.2.4.5), duration 65.12
2365 05:05:12.914802 ok: lava_test_shell seems to have completed
2366 05:05:12.929219 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2367 05:05:12.931326 end: 3.1 lava-test-shell (duration 00:01:07) [common]
2368 05:05:12.932001 end: 3 lava-test-retry (duration 00:01:07) [common]
2369 05:05:12.932643 start: 4 finalize (timeout 00:05:43) [common]
2370 05:05:12.933281 start: 4.1 power-off (timeout 00:00:30) [common]
2371 05:05:12.934392 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2372 05:05:12.969702 >> OK - accepted request
2373 05:05:12.971761 Returned 0 in 0 seconds
2374 05:05:13.073083 end: 4.1 power-off (duration 00:00:00) [common]
2376 05:05:13.074945 start: 4.2 read-feedback (timeout 00:05:43) [common]
2377 05:05:13.076205 Listened to connection for namespace 'common' for up to 1s
2378 05:05:13.077179 Listened to connection for namespace 'common' for up to 1s
2379 05:05:14.076430 Finalising connection for namespace 'common'
2380 05:05:14.077200 Disconnecting from shell: Finalise
2381 05:05:14.077827 / #
2382 05:05:14.178913 end: 4.2 read-feedback (duration 00:00:01) [common]
2383 05:05:14.179682 end: 4 finalize (duration 00:00:01) [common]
2384 05:05:14.180450 Cleaning after the job
2385 05:05:14.181107 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/ramdisk
2386 05:05:14.190819 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/kernel
2387 05:05:14.199271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/dtb
2388 05:05:14.200680 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/nfsrootfs
2389 05:05:14.352479 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689642/tftp-deploy-8lhy1ly2/modules
2390 05:05:14.362529 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/689642
2391 05:05:17.192624 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/689642
2392 05:05:17.193216 Job finished correctly