Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 07:57:28.156476 lava-dispatcher, installed at version: 2023.08
2 07:57:28.156776 start: 0 validate
3 07:57:28.156969 Start time: 2024-09-02 07:57:28.156958+00:00 (UTC)
4 07:57:28.157205 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 07:57:28.525929 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kernel/zImage exists
6 07:57:28.642651 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb exists
7 07:57:28.759417 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 07:57:28.875966 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/modules.tar.xz exists
9 07:57:28.997479 validate duration: 0.84
11 07:57:28.998221 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 07:57:28.998567 start: 1.1 download-retry (timeout 00:10:00) [common]
13 07:57:28.998871 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 07:57:28.999315 Not decompressing ramdisk as can be used compressed.
15 07:57:28.999613 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 07:57:28.999841 saving as /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/ramdisk/initrd.cpio.gz
17 07:57:29.000073 total size: 4775763 (4 MB)
18 07:57:29.232687 progress 0 % (0 MB)
19 07:57:29.577723 progress 5 % (0 MB)
20 07:57:29.804227 progress 10 % (0 MB)
21 07:57:29.826159 progress 15 % (0 MB)
22 07:57:29.920251 progress 20 % (0 MB)
23 07:57:29.935917 progress 25 % (1 MB)
24 07:57:30.039924 progress 30 % (1 MB)
25 07:57:30.148781 progress 35 % (1 MB)
26 07:57:30.171678 progress 40 % (1 MB)
27 07:57:30.274982 progress 45 % (2 MB)
28 07:57:30.378439 progress 50 % (2 MB)
29 07:57:30.405294 progress 55 % (2 MB)
30 07:57:30.507716 progress 60 % (2 MB)
31 07:57:30.609592 progress 65 % (2 MB)
32 07:57:30.667139 progress 70 % (3 MB)
33 07:57:30.737311 progress 75 % (3 MB)
34 07:57:30.838132 progress 80 % (3 MB)
35 07:57:30.860686 progress 85 % (3 MB)
36 07:57:30.964293 progress 90 % (4 MB)
37 07:57:31.064917 progress 95 % (4 MB)
38 07:57:31.085921 progress 100 % (4 MB)
39 07:57:31.086681 4 MB downloaded in 2.09 s (2.18 MB/s)
40 07:57:31.087164 end: 1.1.1 http-download (duration 00:00:02) [common]
42 07:57:31.088011 end: 1.1 download-retry (duration 00:00:02) [common]
43 07:57:31.088332 start: 1.2 download-retry (timeout 00:09:58) [common]
44 07:57:31.088626 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 07:57:31.089038 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kernel/zImage
46 07:57:31.089274 saving as /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/kernel/zImage
47 07:57:31.089494 total size: 11952640 (11 MB)
48 07:57:31.089718 No compression specified
49 07:57:31.211319 progress 0 % (0 MB)
50 07:57:31.555109 progress 5 % (0 MB)
51 07:57:31.787505 progress 10 % (1 MB)
52 07:57:32.020966 progress 15 % (1 MB)
53 07:57:32.252289 progress 20 % (2 MB)
54 07:57:32.485603 progress 25 % (2 MB)
55 07:57:32.713564 progress 30 % (3 MB)
56 07:57:32.940724 progress 35 % (4 MB)
57 07:57:33.166457 progress 40 % (4 MB)
58 07:57:33.395011 progress 45 % (5 MB)
59 07:57:33.619370 progress 50 % (5 MB)
60 07:57:33.844744 progress 55 % (6 MB)
61 07:57:34.062748 progress 60 % (6 MB)
62 07:57:34.214425 progress 65 % (7 MB)
63 07:57:34.438380 progress 70 % (8 MB)
64 07:57:34.662601 progress 75 % (8 MB)
65 07:57:34.886038 progress 80 % (9 MB)
66 07:57:35.109654 progress 85 % (9 MB)
67 07:57:35.330909 progress 90 % (10 MB)
68 07:57:35.476037 progress 95 % (10 MB)
69 07:57:35.699207 progress 100 % (11 MB)
70 07:57:35.699611 11 MB downloaded in 4.61 s (2.47 MB/s)
71 07:57:35.699835 end: 1.2.1 http-download (duration 00:00:05) [common]
73 07:57:35.700225 end: 1.2 download-retry (duration 00:00:05) [common]
74 07:57:35.700371 start: 1.3 download-retry (timeout 00:09:53) [common]
75 07:57:35.700499 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 07:57:35.700701 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
77 07:57:35.700803 saving as /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/dtb/am335x-boneblack.dtb
78 07:57:35.700900 total size: 70308 (0 MB)
79 07:57:35.700998 No compression specified
80 07:57:35.818704 progress 46 % (0 MB)
81 07:57:35.821527 progress 93 % (0 MB)
82 07:57:35.822505 progress 100 % (0 MB)
83 07:57:35.822876 0 MB downloaded in 0.12 s (0.55 MB/s)
84 07:57:35.823268 end: 1.3.1 http-download (duration 00:00:00) [common]
86 07:57:35.824079 end: 1.3 download-retry (duration 00:00:00) [common]
87 07:57:35.824368 start: 1.4 download-retry (timeout 00:09:53) [common]
88 07:57:35.824653 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 07:57:35.824977 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 07:57:35.825207 saving as /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/nfsrootfs/full.rootfs.tar
91 07:57:35.825408 total size: 117747780 (112 MB)
92 07:57:35.825623 Using unxz to decompress xz
93 07:57:35.943974 progress 0 % (0 MB)
94 07:57:38.579613 progress 5 % (5 MB)
95 07:57:40.659652 progress 10 % (11 MB)
96 07:57:42.723089 progress 15 % (16 MB)
97 07:57:44.775996 progress 20 % (22 MB)
98 07:57:46.636409 progress 25 % (28 MB)
99 07:57:48.223206 progress 30 % (33 MB)
100 07:57:49.543122 progress 35 % (39 MB)
101 07:57:50.598193 progress 40 % (44 MB)
102 07:57:51.485876 progress 45 % (50 MB)
103 07:57:52.236245 progress 50 % (56 MB)
104 07:57:52.902135 progress 55 % (61 MB)
105 07:57:53.491305 progress 60 % (67 MB)
106 07:57:54.016472 progress 65 % (73 MB)
107 07:57:54.635365 progress 70 % (78 MB)
108 07:57:55.144250 progress 75 % (84 MB)
109 07:57:55.736695 progress 80 % (89 MB)
110 07:57:56.301177 progress 85 % (95 MB)
111 07:57:56.842178 progress 90 % (101 MB)
112 07:57:57.361808 progress 95 % (106 MB)
113 07:57:57.869161 progress 100 % (112 MB)
114 07:57:57.872843 112 MB downloaded in 22.05 s (5.09 MB/s)
115 07:57:57.873210 end: 1.4.1 http-download (duration 00:00:22) [common]
117 07:57:57.873884 end: 1.4 download-retry (duration 00:00:22) [common]
118 07:57:57.874126 start: 1.5 download-retry (timeout 00:09:31) [common]
119 07:57:57.874368 start: 1.5.1 http-download (timeout 00:09:31) [common]
120 07:57:57.874699 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/modules.tar.xz
121 07:57:57.874865 saving as /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/modules/modules.tar
122 07:57:57.875050 total size: 6914168 (6 MB)
123 07:57:57.875237 Using unxz to decompress xz
124 07:57:57.993672 progress 0 % (0 MB)
125 07:57:58.230441 progress 5 % (0 MB)
126 07:57:58.453716 progress 10 % (0 MB)
127 07:57:58.482642 progress 15 % (1 MB)
128 07:57:58.567247 progress 20 % (1 MB)
129 07:57:58.597234 progress 25 % (1 MB)
130 07:57:58.624490 progress 30 % (2 MB)
131 07:57:58.812951 progress 35 % (2 MB)
132 07:57:58.840627 progress 40 % (2 MB)
133 07:57:58.865256 progress 45 % (2 MB)
134 07:57:58.912552 progress 50 % (3 MB)
135 07:57:58.946143 progress 55 % (3 MB)
136 07:57:59.032896 progress 60 % (3 MB)
137 07:57:59.063500 progress 65 % (4 MB)
138 07:57:59.148089 progress 70 % (4 MB)
139 07:57:59.179088 progress 75 % (4 MB)
140 07:57:59.263232 progress 80 % (5 MB)
141 07:57:59.293967 progress 85 % (5 MB)
142 07:57:59.375807 progress 90 % (5 MB)
143 07:57:59.408218 progress 95 % (6 MB)
144 07:57:59.489024 progress 100 % (6 MB)
145 07:57:59.494054 6 MB downloaded in 1.62 s (4.07 MB/s)
146 07:57:59.494510 end: 1.5.1 http-download (duration 00:00:02) [common]
148 07:57:59.495265 end: 1.5 download-retry (duration 00:00:02) [common]
149 07:57:59.495539 start: 1.6 prepare-tftp-overlay (timeout 00:09:30) [common]
150 07:57:59.495810 start: 1.6.1 extract-nfsrootfs (timeout 00:09:30) [common]
151 07:58:05.016993 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9
152 07:58:05.017282 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 07:58:05.017413 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
154 07:58:05.017687 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls
155 07:58:05.017856 makedir: /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin
156 07:58:05.017997 makedir: /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/tests
157 07:58:05.018127 makedir: /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/results
158 07:58:05.018269 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-add-keys
159 07:58:05.018474 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-add-sources
160 07:58:05.018645 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-background-process-start
161 07:58:05.018817 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-background-process-stop
162 07:58:05.019001 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-common-functions
163 07:58:05.019171 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-echo-ipv4
164 07:58:05.019342 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-install-packages
165 07:58:05.019508 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-installed-packages
166 07:58:05.019673 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-os-build
167 07:58:05.019839 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-probe-channel
168 07:58:05.020004 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-probe-ip
169 07:58:05.020171 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-target-ip
170 07:58:05.020362 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-target-mac
171 07:58:05.020527 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-target-storage
172 07:58:05.020694 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-test-case
173 07:58:05.020859 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-test-event
174 07:58:05.021023 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-test-feedback
175 07:58:05.021187 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-test-raise
176 07:58:05.021351 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-test-reference
177 07:58:05.021516 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-test-runner
178 07:58:05.021681 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-test-set
179 07:58:05.021845 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-test-shell
180 07:58:05.022011 Updating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-add-keys (debian)
181 07:58:05.022233 Updating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-add-sources (debian)
182 07:58:05.022420 Updating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-install-packages (debian)
183 07:58:05.022606 Updating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-installed-packages (debian)
184 07:58:05.022791 Updating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/bin/lava-os-build (debian)
185 07:58:05.022955 Creating /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/environment
186 07:58:05.023079 LAVA metadata
187 07:58:05.023176 - LAVA_JOB_ID=1187704
188 07:58:05.023268 - LAVA_DISPATCHER_IP=192.168.11.5
189 07:58:05.023407 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
190 07:58:05.023725 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 07:58:05.023878 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
192 07:58:05.023967 skipped lava-vland-overlay
193 07:58:05.024075 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 07:58:05.024335 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
195 07:58:05.024432 skipped lava-multinode-overlay
196 07:58:05.024542 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 07:58:05.024654 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
198 07:58:05.024753 Loading test definitions
199 07:58:05.024871 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
200 07:58:05.024968 Using /lava-1187704 at stage 0
201 07:58:05.025362 uuid=1187704_1.6.2.4.1 testdef=None
202 07:58:05.025481 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 07:58:05.025595 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
204 07:58:05.026212 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 07:58:05.026535 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
207 07:58:05.027338 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 07:58:05.027669 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
210 07:58:05.028441 runner path: /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/0/tests/0_timesync-off test_uuid 1187704_1.6.2.4.1
211 07:58:05.028630 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 07:58:05.028957 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
214 07:58:05.029053 Using /lava-1187704 at stage 0
215 07:58:05.029187 Fetching tests from https://github.com/kernelci/test-definitions.git
216 07:58:05.029287 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/0/tests/1_kselftest-dt'
217 07:58:10.472617 Running '/usr/bin/git checkout kernelci.org
218 07:58:10.771937 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 07:58:10.772949 uuid=1187704_1.6.2.4.5 testdef=None
220 07:58:10.773217 end: 1.6.2.4.5 git-repo-action (duration 00:00:06) [common]
222 07:58:10.773818 start: 1.6.2.4.6 test-overlay (timeout 00:09:18) [common]
223 07:58:10.775810 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 07:58:10.776459 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:18) [common]
226 07:58:10.808881 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 07:58:10.809726 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:18) [common]
229 07:58:10.850512 runner path: /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/0/tests/1_kselftest-dt test_uuid 1187704_1.6.2.4.5
230 07:58:10.850794 BOARD='beaglebone-black'
231 07:58:10.851017 BRANCH='mainline'
232 07:58:10.851233 SKIPFILE='/dev/null'
233 07:58:10.851447 SKIP_INSTALL='True'
234 07:58:10.851655 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
235 07:58:10.851869 TST_CASENAME=''
236 07:58:10.852075 TST_CMDFILES='dt'
237 07:58:10.852590 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 07:58:10.853329 Creating lava-test-runner.conf files
240 07:58:10.853541 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1187704/lava-overlay-1plg3gls/lava-1187704/0 for stage 0
241 07:58:10.853839 - 0_timesync-off
242 07:58:10.854066 - 1_kselftest-dt
243 07:58:10.854386 end: 1.6.2.4 test-definition (duration 00:00:06) [common]
244 07:58:10.854665 start: 1.6.2.5 compress-overlay (timeout 00:09:18) [common]
245 07:58:19.338473 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 07:58:19.338686 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
247 07:58:19.338833 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 07:58:19.338991 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 07:58:19.339138 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
250 07:58:19.464260 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 07:58:19.464635 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
252 07:58:19.464843 extracting modules file /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9
253 07:58:19.768509 extracting modules file /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1187704/extract-overlay-ramdisk-7hd41ggn/ramdisk
254 07:58:20.071534 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 07:58:20.071749 start: 1.6.5 apply-overlay-tftp (timeout 00:09:09) [common]
256 07:58:20.071884 [common] Applying overlay to NFS
257 07:58:20.071991 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1187704/compress-overlay-gx_skrne/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9
258 07:58:21.250145 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 07:58:21.250357 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
260 07:58:21.250503 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
261 07:58:21.250652 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 07:58:21.250788 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 07:58:21.250926 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
264 07:58:21.251061 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 07:58:21.251196 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
266 07:58:21.251300 Building ramdisk /var/lib/lava/dispatcher/tmp/1187704/extract-overlay-ramdisk-7hd41ggn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1187704/extract-overlay-ramdisk-7hd41ggn/ramdisk
267 07:58:21.615126 >> 78946 blocks
268 07:58:23.749215 Adding RAMdisk u-boot header.
269 07:58:23.749503 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1187704/extract-overlay-ramdisk-7hd41ggn/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1187704/extract-overlay-ramdisk-7hd41ggn/ramdisk.cpio.gz.uboot
270 07:58:23.905837 output: Image Name:
271 07:58:23.906178 output: Created: Mon Sep 2 07:58:23 2024
272 07:58:23.906388 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 07:58:23.906590 output: Data Size: 15339111 Bytes = 14979.60 KiB = 14.63 MiB
274 07:58:23.906786 output: Load Address: 00000000
275 07:58:23.906977 output: Entry Point: 00000000
276 07:58:23.907168 output:
277 07:58:23.907477 rename /var/lib/lava/dispatcher/tmp/1187704/extract-overlay-ramdisk-7hd41ggn/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/ramdisk/ramdisk.cpio.gz.uboot
278 07:58:23.907802 end: 1.6.8 compress-ramdisk (duration 00:00:03) [common]
279 07:58:23.908071 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 07:58:23.908382 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:05) [common]
281 07:58:23.908603 No LXC device requested
282 07:58:23.908866 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 07:58:23.909138 start: 1.8 deploy-device-env (timeout 00:09:05) [common]
284 07:58:23.909400 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 07:58:23.909611 Checking files for TFTP limit of 4294967296 bytes.
286 07:58:23.910921 end: 1 tftp-deploy (duration 00:00:55) [common]
287 07:58:23.911206 start: 2 uboot-action (timeout 00:05:00) [common]
288 07:58:23.911484 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 07:58:23.911747 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 07:58:23.912014 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 07:58:23.912426 substitutions:
292 07:58:23.912640 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 07:58:23.912850 - {DTB_ADDR}: 0x88000000
294 07:58:23.913051 - {DTB}: 1187704/tftp-deploy-72yiprtd/dtb/am335x-boneblack.dtb
295 07:58:23.913256 - {INITRD}: 1187704/tftp-deploy-72yiprtd/ramdisk/ramdisk.cpio.gz.uboot
296 07:58:23.913456 - {KERNEL_ADDR}: 0x82000000
297 07:58:23.913657 - {KERNEL}: 1187704/tftp-deploy-72yiprtd/kernel/zImage
298 07:58:23.913855 - {LAVA_MAC}: None
299 07:58:23.914064 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9
300 07:58:23.914263 - {NFS_SERVER_IP}: 192.168.11.5
301 07:58:23.914459 - {PRESEED_CONFIG}: None
302 07:58:23.914653 - {PRESEED_LOCAL}: None
303 07:58:23.914851 - {RAMDISK_ADDR}: 0x83000000
304 07:58:23.915046 - {RAMDISK}: 1187704/tftp-deploy-72yiprtd/ramdisk/ramdisk.cpio.gz.uboot
305 07:58:23.915241 - {ROOT_PART}: None
306 07:58:23.915433 - {ROOT}: None
307 07:58:23.915625 - {SERVER_IP}: 192.168.11.5
308 07:58:23.915817 - {TEE_ADDR}: 0x83000000
309 07:58:23.916008 - {TEE}: None
310 07:58:23.916211 Parsed boot commands:
311 07:58:23.916403 - setenv autoload no
312 07:58:23.916597 - setenv initrd_high 0xffffffff
313 07:58:23.916790 - setenv fdt_high 0xffffffff
314 07:58:23.916983 - dhcp
315 07:58:23.917174 - setenv serverip 192.168.11.5
316 07:58:23.917367 - tftp 0x82000000 1187704/tftp-deploy-72yiprtd/kernel/zImage
317 07:58:23.917562 - tftp 0x83000000 1187704/tftp-deploy-72yiprtd/ramdisk/ramdisk.cpio.gz.uboot
318 07:58:23.917757 - setenv initrd_size ${filesize}
319 07:58:23.917950 - tftp 0x88000000 1187704/tftp-deploy-72yiprtd/dtb/am335x-boneblack.dtb
320 07:58:23.918144 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 07:58:23.918348 - bootz 0x82000000 0x83000000 0x88000000
322 07:58:23.918600 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 07:58:23.919316 start: 2.3 connect-device (timeout 00:05:00) [common]
325 07:58:23.919524 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 07:58:24.275380 Setting prompt string to ['lava-test: # ']
327 07:58:24.275760 end: 2.3 connect-device (duration 00:00:00) [common]
328 07:58:24.275903 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 07:58:24.276056 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 07:58:24.276208 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 07:58:24.276504 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 07:58:24.641084 Returned 0 in 0 seconds
333 07:58:24.741978 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 07:58:24.742848 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 07:58:24.743159 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 07:58:24.743431 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 07:58:24.743673 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 07:58:24.744445 Trying 127.0.0.1...
340 07:58:24.744673 Connected to 127.0.0.1.
341 07:58:24.744879 Escape character is '^]'.
342 07:58:29.661734
343 07:58:29.665314 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 07:58:29.721993 Trying to boot from MMC2
345 07:58:29.770290 Loading Environment from EXT4... Card did not respond to voltage select!
346 07:58:29.837523
347 07:58:29.837819
348 07:58:29.843097 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 07:58:29.843358
350 07:58:29.848184 CPU : AM335X-GP rev 2.1
351 07:58:29.902030 I2C: ready
352 07:58:29.902305 DRAM: 512 MiB
353 07:58:29.956271 No match for driver 'omap_hsmmc'
354 07:58:29.961853 No match for driver 'omap_hsmmc'
355 07:58:29.962118 Some drivers were not found
356 07:58:29.968098 Reset Source: Power-on reset has occurred.
357 07:58:29.968364 RTC 32KCLK Source: External.
358 07:58:29.975659 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 07:58:29.988962 Loading Environment from EXT4... Card did not respond to voltage select!
360 07:58:30.053490 Board: BeagleBone Black
361 07:58:30.057303 <ethaddr> not set. Validating first E-fuse MAC
362 07:58:30.113994 BeagleBone Black:
363 07:58:30.114293 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 07:58:30.119630 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 07:58:30.125503 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 07:58:30.125748 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 07:58:30.130602 Net: eth0: MII MODE
368 07:58:30.139845 cpsw, usb_ether
369 07:58:30.140110 Press SPACE to abort autoboot in 2 seconds
370 07:58:30.190900 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 07:58:30.191274 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 07:58:30.191564 Setting prompt string to ['=> ']
373 07:58:30.191821 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 07:58:30.195085 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 07:58:30.195387 Sending with 10 millisecond of delay
377 07:58:31.330040 => setenv autoload no
378 07:58:31.340616 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 07:58:31.342985 setenv autoload no
380 07:58:31.343463 Sending with 10 millisecond of delay
382 07:58:33.140302 => setenv initrd_high 0xffffffff
383 07:58:33.150818 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 07:58:33.151353 setenv initrd_high 0xffffffff
385 07:58:33.151822 Sending with 10 millisecond of delay
387 07:58:34.768284 => setenv fdt_high 0xffffffff
388 07:58:34.778785 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 07:58:34.779244 setenv fdt_high 0xffffffff
390 07:58:34.779693 Sending with 10 millisecond of delay
392 07:58:35.071187 => dhcp
393 07:58:35.081599 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 07:58:35.082042 dhcp
395 07:58:35.082269 link up on port 0, speed 100, full duplex
396 07:58:35.082486 BOOTP broadcast 1
397 07:58:35.090092 DHCP client bound to address 192.168.11.7 (4 ms)
398 07:58:35.090578 Sending with 10 millisecond of delay
400 07:58:36.827459 => setenv serverip 192.168.11.5
401 07:58:36.837953 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 07:58:36.838436 setenv serverip 192.168.11.5
403 07:58:36.838890 Sending with 10 millisecond of delay
405 07:58:40.381889 => tftp 0x82000000 1187704/tftp-deploy-72yiprtd/kernel/zImage
406 07:58:40.392416 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 07:58:40.392889 tftp 0x82000000 1187704/tftp-deploy-72yiprtd/kernel/zImage
408 07:58:40.393120 link up on port 0, speed 100, full duplex
409 07:58:40.393334 Using cpsw device
410 07:58:40.396827 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
411 07:58:40.402303 Filename '1187704/tftp-deploy-72yiprtd/kernel/zImage'.
412 07:58:40.409455 Load address: 0x82000000
413 07:58:40.602444 Loading: *#################################################################
414 07:58:40.771884 #################################################################
415 07:58:40.945054 #################################################################
416 07:58:41.117776 #################################################################
417 07:58:41.290772 #################################################################
418 07:58:41.458040 #################################################################
419 07:58:41.629672 #################################################################
420 07:58:41.802257 #################################################################
421 07:58:41.998877 #################################################################
422 07:58:42.170193 #################################################################
423 07:58:42.332286 #################################################################
424 07:58:42.506896 #################################################################
425 07:58:42.598035 ###################################
426 07:58:42.598314 5.2 MiB/s
427 07:58:42.598537 done
428 07:58:42.601946 Bytes transferred = 11952640 (b66200 hex)
429 07:58:42.602471 Sending with 10 millisecond of delay
431 07:58:47.109130 => tftp 0x83000000 1187704/tftp-deploy-72yiprtd/ramdisk/ramdisk.cpio.gz.uboot
432 07:58:47.119596 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
433 07:58:47.120055 tftp 0x83000000 1187704/tftp-deploy-72yiprtd/ramdisk/ramdisk.cpio.gz.uboot
434 07:58:47.120307 link up on port 0, speed 100, full duplex
435 07:58:47.120522 Using cpsw device
436 07:58:47.123801 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
437 07:58:47.172431 Filename '1187704/tftp-deploy-72yiprtd/ramdisk/ramdisk.cpio.gz.uboot'.
438 07:58:47.172704 Load address: 0x83000000
439 07:58:47.314983 Loading: *#################################################################
440 07:58:47.488787 #################################################################
441 07:58:47.683647 #################################################################
442 07:58:47.852989 #################################################################
443 07:58:48.028234 #################################################################
444 07:58:48.203096 #################################################################
445 07:58:48.382282 #################################################################
446 07:58:48.555740 #################################################################
447 07:58:48.729386 #################################################################
448 07:58:48.904480 #################################################################
449 07:58:49.079649 #################################################################
450 07:58:49.276038 #################################################################
451 07:58:49.448506 #################################################################
452 07:58:49.622631 #################################################################
453 07:58:49.797676 #################################################################
454 07:58:49.972169 #################################################################
455 07:58:49.982784 #####
456 07:58:49.983110 5.1 MiB/s
457 07:58:49.983341 done
458 07:58:49.986282 Bytes transferred = 15339175 (ea0ea7 hex)
459 07:58:49.986776 Sending with 10 millisecond of delay
461 07:58:51.843876 => setenv initrd_size ${filesize}
462 07:58:51.854387 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
463 07:58:51.854848 setenv initrd_size ${filesize}
464 07:58:51.855295 Sending with 10 millisecond of delay
466 07:58:56.061156 => tftp 0x88000000 1187704/tftp-deploy-72yiprtd/dtb/am335x-boneblack.dtb
467 07:58:56.071634 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
468 07:58:56.072099 tftp 0x88000000 1187704/tftp-deploy-72yiprtd/dtb/am335x-boneblack.dtb
469 07:58:56.072352 link up on port 0, speed 100, full duplex
470 07:58:56.072565 Using cpsw device
471 07:58:56.075892 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
472 07:58:56.100896 Filename '1187704/tftp-deploy-72yiprtd/dtb/am335x-boneblack.dtb'.
473 07:58:56.101213 Load address: 0x88000000
474 07:58:56.101433 Loading: *#####
475 07:58:56.101644 4.8 MiB/s
476 07:58:56.107570 done
477 07:58:56.107836 Bytes transferred = 70308 (112a4 hex)
478 07:58:56.108281 Sending with 10 millisecond of delay
480 07:59:09.407354 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 07:59:09.417844 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:14)
482 07:59:09.418294 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
483 07:59:09.418747 Sending with 10 millisecond of delay
485 07:59:11.757705 => bootz 0x82000000 0x83000000 0x88000000
486 07:59:11.768261 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
487 07:59:11.768687 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
488 07:59:11.769310 bootz 0x82000000 0x83000000 0x88000000
489 07:59:11.769548 ## Loading init Ramdisk from Legacy Image at 83000000 ...
490 07:59:11.770064 Image Name:
491 07:59:11.770296 Created: 2024-09-02 7:58:23 UTC
492 07:59:11.775458 Image Type: ARM Linux RAMDisk Image (uncompressed)
493 07:59:11.781018 Data Size: 15339111 Bytes = 14.6 MiB
494 07:59:11.781302 Load Address: 00000000
495 07:59:11.788334 Entry Point: 00000000
496 07:59:11.930530 Verifying Checksum ... OK
497 07:59:11.930812 ## Flattened Device Tree blob at 88000000
498 07:59:11.937150 Booting using the fdt blob at 0x88000000
499 07:59:11.941940 Using Device Tree in place at 88000000, end 880142a3
500 07:59:11.949579
501 07:59:11.949862 Starting kernel ...
502 07:59:11.950140
503 07:59:11.950730 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
504 07:59:11.951074 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
505 07:59:11.951347 Setting prompt string to ['Linux version [0-9]']
506 07:59:11.951634 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
507 07:59:11.951925 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
508 07:59:12.781439 [ 0.000000] Booting Linux on physical CPU 0x0
509 07:59:12.787437 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
510 07:59:12.787762 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
511 07:59:12.788049 Setting prompt string to []
512 07:59:12.788385 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
513 07:59:12.788675 Using line separator: #'\n'#
514 07:59:12.788929 No login prompt set.
515 07:59:12.789205 Parsing kernel messages
516 07:59:12.789454 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
517 07:59:12.789892 [login-action] Waiting for messages, (timeout 00:04:11)
518 07:59:12.798465 [ 0.000000] Linux version 6.11.0-rc6 (KernelCI@build-j304696-arm-clang-16-multi-v7-defconfig-hgvd9) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Mon Sep 2 03:54:42 UTC 2024
519 07:59:12.809986 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 07:59:12.815718 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 07:59:12.821341 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 07:59:12.827087 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 07:59:12.832837 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 07:59:12.838708 [ 0.000000] Memory policy: Data cache writeback
525 07:59:12.845337 [ 0.000000] efi: UEFI not found.
526 07:59:12.845619 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 07:59:12.854102 [ 0.000000] Zone ranges:
528 07:59:12.859835 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 07:59:12.865585 [ 0.000000] Normal empty
530 07:59:12.865867 [ 0.000000] HighMem empty
531 07:59:12.871211 [ 0.000000] Movable zone start for each node
532 07:59:12.871492 [ 0.000000] Early memory node ranges
533 07:59:12.882728 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 07:59:12.888061 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 07:59:12.906136 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 07:59:12.911799 [ 0.000000] AM335X ES2.1 (sgx neon)
537 07:59:12.923369 [ 0.000000] percpu: Embedded 17 pages/cpu s40268 r8192 d21172 u69632
538 07:59:12.941102 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 07:59:12.952745 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 07:59:12.958350 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 07:59:12.964098 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 07:59:12.974293 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 07:59:13.003319 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 07:59:13.009304 <6>[ 0.000000] trace event string verifier disabled
545 07:59:13.009587 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 07:59:13.014932 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 07:59:13.026478 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 07:59:13.032188 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 07:59:13.039369 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 07:59:13.054447 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 07:59:13.072068 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 07:59:13.078741 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 07:59:13.177978 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 07:59:13.189339 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 07:59:13.196101 <6>[ 0.008340] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 07:59:13.209151 <6>[ 0.019184] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 07:59:13.216738 <6>[ 0.034148] Console: colour dummy device 80x30
558 07:59:13.222664 Matched prompt #6: WARNING:
559 07:59:13.222964 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 07:59:13.228241 <3>[ 0.039045] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 07:59:13.233934 <3>[ 0.046120] This ensures that you still see kernel messages. Please
562 07:59:13.237106 <3>[ 0.052849] update your kernel commandline.
563 07:59:13.277726 <6>[ 0.057461] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 07:59:13.283471 <6>[ 0.096194] CPU: Testing write buffer coherency: ok
565 07:59:13.289435 <6>[ 0.101562] CPU0: Spectre v2: using BPIALL workaround
566 07:59:13.289716 <6>[ 0.107030] pid_max: default: 32768 minimum: 301
567 07:59:13.300789 <6>[ 0.112221] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 07:59:13.307661 <6>[ 0.120044] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 07:59:13.314782 <6>[ 0.129353] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 07:59:13.323222 <6>[ 0.136251] Setting up static identity map for 0x80300000 - 0x803000ac
571 07:59:13.328931 <6>[ 0.145889] rcu: Hierarchical SRCU implementation.
572 07:59:13.336585 <6>[ 0.151168] rcu: Max phase no-delay instances is 1000.
573 07:59:13.345172 <6>[ 0.162448] EFI services will not be available.
574 07:59:13.351035 <6>[ 0.167715] smp: Bringing up secondary CPUs ...
575 07:59:13.356842 <6>[ 0.172766] smp: Brought up 1 node, 1 CPU
576 07:59:13.362681 <6>[ 0.177163] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 07:59:13.368556 <6>[ 0.183918] CPU: All CPU(s) started in SVC mode.
578 07:59:13.388858 <6>[ 0.189099] Memory: 405456K/522240K available (17408K kernel code, 2536K rwdata, 6644K rodata, 2048K init, 432K bss, 49580K reserved, 65536K cma-reserved, 0K highmem)
579 07:59:13.389152 <6>[ 0.205378] devtmpfs: initialized
580 07:59:13.411721 <6>[ 0.222963] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 07:59:13.423100 <6>[ 0.231576] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 07:59:13.429008 <6>[ 0.242011] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 07:59:13.439911 <6>[ 0.254381] pinctrl core: initialized pinctrl subsystem
584 07:59:13.449368 <6>[ 0.265244] DMI not present or invalid.
585 07:59:13.457806 <6>[ 0.271113] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 07:59:13.467259 <6>[ 0.280048] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 07:59:13.482227 <6>[ 0.291529] thermal_sys: Registered thermal governor 'step_wise'
588 07:59:13.482507 <6>[ 0.291686] cpuidle: using governor menu
589 07:59:13.509562 <6>[ 0.326958] No ATAGs?
590 07:59:13.515754 <6>[ 0.329694] hw-breakpoint: debug architecture 0x4 unsupported.
591 07:59:13.526237 <6>[ 0.341925] Serial: AMBA PL011 UART driver
592 07:59:13.567689 <6>[ 0.385097] iommu: Default domain type: Translated
593 07:59:13.576851 <6>[ 0.390440] iommu: DMA domain TLB invalidation policy: strict mode
594 07:59:13.593699 <5>[ 0.410495] SCSI subsystem initialized
595 07:59:13.599675 <6>[ 0.415374] usbcore: registered new interface driver usbfs
596 07:59:13.605293 <6>[ 0.421434] usbcore: registered new interface driver hub
597 07:59:13.612169 <6>[ 0.427219] usbcore: registered new device driver usb
598 07:59:13.617933 <6>[ 0.433803] pps_core: LinuxPPS API ver. 1 registered
599 07:59:13.629416 <6>[ 0.439188] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 07:59:13.632975 <6>[ 0.448912] PTP clock support registered
601 07:59:13.673308 <6>[ 0.490092] EDAC MC: Ver: 3.0.0
602 07:59:13.679352 <6>[ 0.494294] scmi_core: SCMI protocol bus registered
603 07:59:13.697373 <6>[ 0.514356] vgaarb: loaded
604 07:59:13.709683 <6>[ 0.527186] clocksource: Switched to clocksource dmtimer
605 07:59:13.748330 <6>[ 0.565452] NET: Registered PF_INET protocol family
606 07:59:13.761052 <6>[ 0.571157] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 07:59:13.766792 <6>[ 0.580142] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 07:59:13.778293 <6>[ 0.589071] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 07:59:13.784040 <6>[ 0.597332] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 07:59:13.795661 <6>[ 0.605603] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 07:59:13.801538 <6>[ 0.613318] TCP: Hash tables configured (established 4096 bind 4096)
612 07:59:13.807290 <6>[ 0.620231] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 07:59:13.813167 <6>[ 0.627271] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 07:59:13.820715 <6>[ 0.634847] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 07:59:13.855295 <6>[ 0.667012] RPC: Registered named UNIX socket transport module.
616 07:59:13.855575 <6>[ 0.673445] RPC: Registered udp transport module.
617 07:59:13.861045 <6>[ 0.678581] RPC: Registered tcp transport module.
618 07:59:13.866785 <6>[ 0.683685] RPC: Registered tcp-with-tls transport module.
619 07:59:13.879782 <6>[ 0.689614] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 07:59:13.880064 <6>[ 0.696523] PCI: CLS 0 bytes, default 64
621 07:59:13.886959 <5>[ 0.702375] Initialise system trusted keyrings
622 07:59:13.907220 <6>[ 0.721570] Trying to unpack rootfs image as initramfs...
623 07:59:13.926184 <6>[ 0.737461] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 07:59:13.930961 <6>[ 0.744929] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 07:59:13.990674 <5>[ 0.808111] NFS: Registering the id_resolver key type
626 07:59:13.996520 <5>[ 0.813701] Key type id_resolver registered
627 07:59:14.002233 <5>[ 0.818402] Key type id_legacy registered
628 07:59:14.007978 <6>[ 0.822844] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 07:59:14.017643 <6>[ 0.830050] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 07:59:14.050421 <5>[ 0.867987] Key type asymmetric registered
631 07:59:14.056344 <5>[ 0.872511] Asymmetric key parser 'x509' registered
632 07:59:14.067845 <6>[ 0.878066] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 07:59:14.068106 <6>[ 0.885953] io scheduler mq-deadline registered
634 07:59:14.073720 <6>[ 0.890928] io scheduler kyber registered
635 07:59:14.079263 <6>[ 0.895375] io scheduler bfq registered
636 07:59:14.468047 <6>[ 1.281441] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 07:59:14.496641 <6>[ 1.313630] msm_serial: driver initialized
638 07:59:14.502562 <6>[ 1.318693] SuperH (H)SCI(F) driver initialized
639 07:59:14.508559 <6>[ 1.323839] STMicroelectronics ASC driver initialized
640 07:59:14.513618 <6>[ 1.329536] STM32 USART driver initialized
641 07:59:14.622268 <6>[ 1.439193] brd: module loaded
642 07:59:14.653400 <6>[ 1.470249] loop: module loaded
643 07:59:14.698845 <6>[ 1.515331] CAN device driver interface
644 07:59:14.705684 <6>[ 1.520729] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 07:59:14.711294 <6>[ 1.527876] e1000e: Intel(R) PRO/1000 Network Driver
646 07:59:14.717181 <6>[ 1.533266] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 07:59:14.722917 <6>[ 1.539726] igb: Intel(R) Gigabit Ethernet Network Driver
648 07:59:14.731099 <6>[ 1.545549] igb: Copyright (c) 2007-2014 Intel Corporation.
649 07:59:14.743271 <6>[ 1.555073] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 07:59:14.749111 <6>[ 1.561230] usbcore: registered new interface driver pegasus
651 07:59:14.754807 <6>[ 1.567405] usbcore: registered new interface driver asix
652 07:59:14.760686 <6>[ 1.573260] usbcore: registered new interface driver ax88179_178a
653 07:59:14.766427 <6>[ 1.579852] usbcore: registered new interface driver cdc_ether
654 07:59:14.772178 <6>[ 1.586153] usbcore: registered new interface driver smsc75xx
655 07:59:14.778043 <6>[ 1.592395] usbcore: registered new interface driver smsc95xx
656 07:59:14.783684 <6>[ 1.598629] usbcore: registered new interface driver net1080
657 07:59:14.789558 <6>[ 1.604751] usbcore: registered new interface driver cdc_subset
658 07:59:14.795317 <6>[ 1.611159] usbcore: registered new interface driver zaurus
659 07:59:14.803021 <6>[ 1.617251] usbcore: registered new interface driver cdc_ncm
660 07:59:14.813257 <6>[ 1.627052] usbcore: registered new interface driver usb-storage
661 07:59:14.924325 <6>[ 1.739958] i2c_dev: i2c /dev entries driver
662 07:59:15.005477 <5>[ 1.814771] cpuidle: enable-method property 'ti,am3352' found operations
663 07:59:15.011302 <6>[ 1.824529] sdhci: Secure Digital Host Controller Interface driver
664 07:59:15.019101 <6>[ 1.831300] sdhci: Copyright(c) Pierre Ossman
665 07:59:15.026337 <6>[ 1.838035] Synopsys Designware Multimedia Card Interface Driver
666 07:59:15.031726 <6>[ 1.846073] sdhci-pltfm: SDHCI platform and OF driver helper
667 07:59:15.098976 <6>[ 1.907899] ledtrig-cpu: registered to indicate activity on CPUs
668 07:59:15.105147 <6>[ 1.917108] usbcore: registered new interface driver usbhid
669 07:59:15.105390 <6>[ 1.923299] usbhid: USB HID core driver
670 07:59:15.161098 <6>[ 1.976018] NET: Registered PF_INET6 protocol family
671 07:59:15.210346 <6>[ 2.027932] Segment Routing with IPv6
672 07:59:15.216179 <6>[ 2.032072] In-situ OAM (IOAM) with IPv6
673 07:59:15.222934 <6>[ 2.036461] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 07:59:15.228794 <6>[ 2.043864] NET: Registered PF_PACKET protocol family
675 07:59:15.234540 <6>[ 2.049439] can: controller area network core
676 07:59:15.240416 <6>[ 2.054274] NET: Registered PF_CAN protocol family
677 07:59:15.240671 <6>[ 2.059498] can: raw protocol
678 07:59:15.246169 <6>[ 2.062822] can: broadcast manager protocol
679 07:59:15.252673 <6>[ 2.067418] can: netlink gateway - max_hops=1
680 07:59:15.258790 <5>[ 2.072906] Key type dns_resolver registered
681 07:59:15.265045 <6>[ 2.077972] ThumbEE CPU extension supported.
682 07:59:15.265292 <5>[ 2.082661] Registering SWP/SWPB emulation handler
683 07:59:15.274721 <3>[ 2.088361] omap_voltage_late_init: Voltage driver support not added
684 07:59:15.364912 <5>[ 2.180017] Loading compiled-in X.509 certificates
685 07:59:15.521664 <6>[ 2.326154] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 07:59:15.528709 <6>[ 2.342872] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 07:59:15.555209 <3>[ 2.366761] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 07:59:15.637201 <3>[ 2.448610] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 07:59:15.731848 <6>[ 2.547584] OMAP GPIO hardware version 0.1
690 07:59:15.752768 <6>[ 2.566414] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 07:59:15.817790 <4>[ 2.631305] at24 2-0054: supply vcc not found, using dummy regulator
692 07:59:15.889249 <4>[ 2.702742] at24 2-0055: supply vcc not found, using dummy regulator
693 07:59:15.927120 <4>[ 2.740658] at24 2-0056: supply vcc not found, using dummy regulator
694 07:59:15.974056 <4>[ 2.787491] at24 2-0057: supply vcc not found, using dummy regulator
695 07:59:16.020819 <6>[ 2.835160] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 07:59:16.083906 <3>[ 2.894175] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 07:59:16.108618 <6>[ 2.915274] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 07:59:16.130132 <4>[ 2.942426] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 07:59:16.175363 <4>[ 2.987638] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 07:59:16.213880 <6>[ 3.027607] omap_rng 48310000.rng: Random Number Generator ver. 20
701 07:59:16.237395 <5>[ 3.053943] random: crng init done
702 07:59:16.335773 <6>[ 3.147922] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 07:59:16.911072 <6>[ 3.726908] Freeing initrd memory: 14980K
704 07:59:16.955020 <6>[ 3.766458] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 07:59:16.960797 <6>[ 3.776679] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 07:59:16.972639 <6>[ 3.784009] cpsw-switch 4a100000.switch: ALE Table size 1024
707 07:59:16.978402 <6>[ 3.790409] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 07:59:16.990012 <6>[ 3.798556] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 07:59:16.997514 <6>[ 3.810215] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
710 07:59:17.009559 <5>[ 3.819361] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 07:59:17.037893 <3>[ 3.849729] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 07:59:17.043602 <6>[ 3.858277] edma 49000000.dma: TI EDMA DMA engine driver
713 07:59:17.115890 <3>[ 3.927064] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 07:59:17.129950 <6>[ 3.941753] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
715 07:59:17.148615 <3>[ 3.963547] l3-aon-clkctrl:0000:0: failed to disable
716 07:59:17.186524 <6>[ 3.998330] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 07:59:17.192150 <6>[ 4.007791] printk: legacy console [ttyS0] enabled
718 07:59:17.197894 <6>[ 4.007791] printk: legacy console [ttyS0] enabled
719 07:59:17.203519 <6>[ 4.018113] printk: legacy bootconsole [omap8250] disabled
720 07:59:17.209322 <6>[ 4.018113] printk: legacy bootconsole [omap8250] disabled
721 07:59:17.267044 <4>[ 4.077854] tps65217-pmic: Failed to locate of_node [id: -1]
722 07:59:17.270656 <4>[ 4.085248] tps65217-bl: Failed to locate of_node [id: -1]
723 07:59:17.287161 <6>[ 4.104990] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 07:59:17.305649 <6>[ 4.111965] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 07:59:17.317539 <6>[ 4.125673] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 07:59:17.323091 <6>[ 4.137657] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 07:59:17.347040 <6>[ 4.159114] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 07:59:17.352790 <6>[ 4.168290] sdhci-omap 48060000.mmc: Got CD GPIO
729 07:59:17.360819 <4>[ 4.173420] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 07:59:17.375889 <4>[ 4.186733] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 07:59:17.382264 <4>[ 4.196023] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 07:59:17.392075 <4>[ 4.204670] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 07:59:17.514141 <6>[ 4.327343] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 07:59:17.548230 <6>[ 4.360536] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 07:59:17.571539 <6>[ 4.382787] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 07:59:17.578198 <6>[ 4.391736] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 07:59:17.648189 <6>[ 4.456385] mmc1: new high speed MMC card at address 0001
738 07:59:17.648489 <6>[ 4.463929] mmcblk1: mmc1:0001 M62704 3.56 GiB
739 07:59:17.656295 <6>[ 4.472523] mmcblk1: p1
740 07:59:17.661713 <6>[ 4.476934] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
741 07:59:17.670138 <6>[ 4.485207] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
742 07:59:17.679201 <6>[ 4.493137] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
743 07:59:17.698831 <6>[ 4.508378] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
744 07:59:20.836260 <6>[ 7.648193] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
745 07:59:20.919545 <5>[ 7.697260] Sending DHCP requests ., OK
746 07:59:20.930891 <6>[ 7.741631] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.7
747 07:59:20.931165 <6>[ 7.749841] IP-Config: Complete:
748 07:59:20.942261 <6>[ 7.753376] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.7, mask=255.255.255.0, gw=192.168.11.1
749 07:59:20.947887 <6>[ 7.763993] host=192.168.11.7, domain=usen.ad.jp, nis-domain=(none)
750 07:59:20.960273 <6>[ 7.771092] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
751 07:59:20.960550 <6>[ 7.771126] nameserver0=192.168.11.1
752 07:59:20.966385 <6>[ 7.783411] clk: Disabling unused clocks
753 07:59:20.972945 <6>[ 7.788188] PM: genpd: Disabling unused power domains
754 07:59:20.990961 <6>[ 7.805255] Freeing unused kernel image (initmem) memory: 2048K
755 07:59:20.998456 <6>[ 7.815009] Run /init as init process
756 07:59:21.021100 Loading, please wait...
757 07:59:21.097104 Starting systemd-udevd version 252.22-1~deb12u1
758 07:59:24.117609 <4>[ 10.928193] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
759 07:59:24.346951 <4>[ 11.157594] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 07:59:24.479806 <6>[ 11.297892] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
761 07:59:24.490443 <6>[ 11.303563] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
762 07:59:24.647839 <6>[ 11.464385] hub 1-0:1.0: USB hub found
763 07:59:24.661987 <6>[ 11.478399] hub 1-0:1.0: 1 port detected
764 07:59:24.984645 <6>[ 11.800896] tda998x 0-0070: found TDA19988
765 07:59:27.591989 Begin: Loading essential drivers ... done.
766 07:59:27.597550 Begin: Running /scripts/init-premount ... done.
767 07:59:27.603166 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
768 07:59:27.617037 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
769 07:59:27.617306 Device /sys/class/net/eth0 found
770 07:59:27.617525 done.
771 07:59:27.689936 Begin: Waiting up to 180 secs for any network device to become available ... done.
772 07:59:27.764644 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
773 07:59:27.764927 IP-Config: eth0 guessed broadcast address 192.168.11.255
774 07:59:27.770236 IP-Config: eth0 complete (dhcp from 192.168.11.1):
775 07:59:27.781338 address: 192.168.11.7 broadcast: 192.168.11.255 netmask: 255.255.255.0
776 07:59:27.786965 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
777 07:59:27.792633 domain : usen.ad.jp
778 07:59:27.797517 rootserver: 192.168.11.1 rootpath:
779 07:59:27.797738 filename :
780 07:59:27.870357 done.
781 07:59:27.887972 Begin: Running /scripts/nfs-bottom ... done.
782 07:59:27.955787 Begin: Running /scripts/init-bottom ... done.
783 07:59:29.264292 <30>[ 16.078207] systemd[1]: System time before build time, advancing clock.
784 07:59:29.415923 <30>[ 16.203624] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 07:59:29.424918 <30>[ 16.240658] systemd[1]: Detected architecture arm.
786 07:59:29.437543
787 07:59:29.437820 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 07:59:29.438044
789 07:59:29.473717 <30>[ 16.288120] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 07:59:31.711540 <30>[ 18.525036] systemd[1]: Queued start job for default target graphical.target.
791 07:59:31.729347 <30>[ 18.540788] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 07:59:31.736945 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 07:59:31.769819 <30>[ 18.580040] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 07:59:31.777149 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 07:59:31.812336 <30>[ 18.623129] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 07:59:31.819703 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 07:59:31.856875 <30>[ 18.668994] systemd[1]: Created slice user.slice - User and Session Slice.
798 07:59:31.863555 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 07:59:31.900015 <30>[ 18.709538] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 07:59:31.913287 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 07:59:31.946667 <30>[ 18.758437] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 07:59:31.957697 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 07:59:31.997270 <30>[ 18.798213] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 07:59:32.003787 <30>[ 18.818732] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 07:59:32.012261 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 07:59:32.045396 <30>[ 18.857619] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 07:59:32.053580 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 07:59:32.086275 <30>[ 18.898018] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 07:59:32.094705 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 07:59:32.126272 <30>[ 18.938276] systemd[1]: Reached target paths.target - Path Units.
811 07:59:32.131356 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 07:59:32.165775 <30>[ 18.977817] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 07:59:32.173102 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 07:59:32.205650 <30>[ 19.017749] systemd[1]: Reached target slices.target - Slice Units.
815 07:59:32.211073 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 07:59:32.247153 <30>[ 19.058602] systemd[1]: Reached target swap.target - Swaps.
817 07:59:32.251193 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 07:59:32.286695 <30>[ 19.098941] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 07:59:32.299081 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 07:59:32.337739 <30>[ 19.148512] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 07:59:32.344827 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 07:59:32.444811 <30>[ 19.251829] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 07:59:32.457386 <30>[ 19.269357] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 07:59:32.465807 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 07:59:32.499038 <30>[ 19.309591] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 07:59:32.506320 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 07:59:32.544997 <30>[ 19.355963] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 07:59:32.553079 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 07:59:32.590133 <30>[ 19.401419] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 07:59:32.595642 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 07:59:32.638174 <30>[ 19.450791] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 07:59:32.650929 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 07:59:32.693238 <30>[ 19.498960] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 07:59:32.709798 <30>[ 19.515667] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 07:59:32.747070 <30>[ 19.559748] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 07:59:32.765028 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 07:59:32.835879 <30>[ 19.648458] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 07:59:32.857312 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 07:59:32.886672 <30>[ 19.698407] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 07:59:32.912841 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 07:59:32.948622 <30>[ 19.760902] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 07:59:32.962331 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 07:59:32.986169 <30>[ 19.798779] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 07:59:33.016227 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 07:59:33.077952 <30>[ 19.891056] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 07:59:33.104558 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 07:59:33.169914 <30>[ 19.981827] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 07:59:33.187752 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 07:59:33.258910 <30>[ 20.071869] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 07:59:33.275326 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 07:59:33.305910 <30>[ 20.118884] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 07:59:33.333827 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 07:59:33.372975 <28>[ 20.179465] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 07:59:33.381402 <28>[ 20.193613] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 07:59:33.431145 <30>[ 20.244536] systemd[1]: Starting systemd-journald.service - Journal Service...
856 07:59:33.455152 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 07:59:33.537848 <30>[ 20.350382] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 07:59:33.554873 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 07:59:33.627304 <30>[ 20.440327] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 07:59:33.667018 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 07:59:33.731570 <30>[ 20.542950] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 07:59:33.781120 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 07:59:33.836400 <30>[ 20.648697] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 07:59:33.887762 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 07:59:33.949037 <30>[ 20.762073] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 07:59:33.996802 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 07:59:34.036516 <30>[ 20.849430] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 07:59:34.071395 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 07:59:34.090155 <30>[ 20.902016] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 07:59:34.118017 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 07:59:34.270742 <30>[ 21.084427] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 07:59:34.306344 <30>[ 21.118951] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 07:59:34.335541 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 07:59:34.366894 <30>[ 21.179019] systemd[1]: Started systemd-journald.service - Journal Service.
875 07:59:34.373606 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
876 07:59:34.405816 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 07:59:34.441080 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
878 07:59:34.487100 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
879 07:59:34.536877 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
880 07:59:34.576862 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
881 07:59:34.608237 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
882 07:59:34.655733 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
883 07:59:34.687884 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
884 07:59:34.725380 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
885 07:59:34.785175 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
886 07:59:34.831538 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
887 07:59:34.911420 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
888 07:59:35.034562 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
889 07:59:35.126030 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
890 07:59:35.169322 <46>[ 21.982264] systemd-journald[163]: Received client request to flush runtime journal.
891 07:59:35.242626 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
892 07:59:35.316083 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
893 07:59:36.164620 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
894 07:59:36.205639 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
895 07:59:36.268099 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
896 07:59:36.992168 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
897 07:59:37.141005 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
898 07:59:37.158067 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
899 07:59:37.185414 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
900 07:59:37.276910 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
901 07:59:37.326069 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
902 07:59:38.267016 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
903 07:59:38.345640 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
904 07:59:38.545605 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
905 07:59:38.684475 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
906 07:59:38.819000 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
907 07:59:40.676068 [[0m[0;31m* [0m] (1 of 5) Job systemd-networkd.service/start running (8s / 1min 36s)
908 07:59:40.870482 M[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
909 07:59:40.931448 [K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
910 07:59:41.436414 <5>[ 28.249723] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 07:59:42.241027 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
912 07:59:43.020800 <5>[ 29.836221] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
913 07:59:43.070048 <5>[ 29.881919] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 07:59:43.075761 <4>[ 29.890857] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 07:59:43.083464 <6>[ 29.899933] cfg80211: failed to load regulatory.db
916 07:59:43.668737 <46>[ 30.471972] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
917 07:59:43.777933 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
918 07:59:43.849408 <46>[ 30.655892] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
919 07:59:44.481164 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
920 07:59:52.389785 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
921 07:59:52.428482 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
922 07:59:52.467421 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
923 07:59:52.497493 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
924 07:59:52.583034 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
925 07:59:52.663311 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
926 07:59:52.711072 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
927 07:59:52.743937 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
928 07:59:52.801126 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
929 07:59:52.841427 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
930 07:59:52.889370 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
931 07:59:52.950238 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
932 07:59:52.970716 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
933 07:59:53.022868 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
934 07:59:53.070382 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
935 07:59:53.107850 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
936 07:59:53.153378 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
937 07:59:53.201030 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
938 07:59:53.237030 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
939 07:59:53.271127 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
940 07:59:53.299892 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
941 07:59:53.306373 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
942 07:59:53.346902 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
943 07:59:53.437263 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
944 07:59:53.484772 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
945 07:59:53.590801 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
946 07:59:53.717080 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
947 07:59:53.813204 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
948 07:59:53.871986 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
949 07:59:53.895010 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
950 07:59:54.061361 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
951 07:59:54.079351 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
952 07:59:54.215049 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 07:59:54.253420 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 07:59:54.285487 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 07:59:54.414598 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
956 07:59:54.732972 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
957 07:59:54.804759 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
958 07:59:54.855565 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
959 07:59:54.935858 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
960 07:59:55.109297 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
961 07:59:55.263353
962 07:59:55.263625 Debian GNU/Linux 1worm-armhf login: root (automatic login)
963 07:59:55.266631
964 07:59:55.570566 Linux debian-bookworm-armhf 6.11.0-rc6 #1 SMP Mon Sep 2 03:54:42 UTC 2024 armv7l
965 07:59:55.570855
966 07:59:55.576166 The programs included with the Debian GNU/Linux system are free software;
967 07:59:55.581683 the exact distribution terms for each program are described in the
968 07:59:55.587322 individual files in /usr/share/doc/*/copyright.
969 07:59:55.587615
970 07:59:55.595294 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
971 07:59:55.595565 permitted by applicable law.
972 08:00:00.254517 Unable to match end of the kernel message
974 08:00:00.255323 Setting prompt string to ['/ #']
975 08:00:00.255626 end: 2.4.4.1 login-action (duration 00:00:47) [common]
977 08:00:00.256343 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
978 08:00:00.256638 start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
979 08:00:00.256886 Setting prompt string to ['/ #']
980 08:00:00.257097 Forcing a shell prompt, looking for ['/ #']
982 08:00:00.307622 / #
983 08:00:00.307999 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
984 08:00:00.308276 Waiting using forced prompt support (timeout 00:02:30)
985 08:00:00.312421
986 08:00:00.321870 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
987 08:00:00.322212 start: 2.4.6 export-device-env (timeout 00:03:24) [common]
988 08:00:00.322476 Sending with 10 millisecond of delay
990 08:00:05.371261 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9'
991 08:00:05.381857 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1187704/extract-nfsrootfs-fm9vapw9'
992 08:00:05.382855 Sending with 10 millisecond of delay
994 08:00:07.541363 / # export NFS_SERVER_IP='192.168.11.5'
995 08:00:07.551931 export NFS_SERVER_IP='192.168.11.5'
996 08:00:07.552840 end: 2.4.6 export-device-env (duration 00:00:07) [common]
997 08:00:07.553186 end: 2.4 uboot-commands (duration 00:01:43) [common]
998 08:00:07.553502 end: 2 uboot-action (duration 00:01:44) [common]
999 08:00:07.553811 start: 3 lava-test-retry (timeout 00:07:21) [common]
1000 08:00:07.554123 start: 3.1 lava-test-shell (timeout 00:07:21) [common]
1001 08:00:07.554375 Using namespace: common
1003 08:00:07.655095 / # #
1004 08:00:07.655477 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1005 08:00:07.659918 #
1006 08:00:07.666568 Using /lava-1187704
1008 08:00:07.767413 / # export SHELL=/bin/bash
1009 08:00:07.772277 export SHELL=/bin/bash
1011 08:00:07.879484 / # . /lava-1187704/environment
1012 08:00:07.884336 . /lava-1187704/environment
1014 08:00:07.997637 / # /lava-1187704/bin/lava-test-runner /lava-1187704/0
1015 08:00:07.998127 Test shell timeout: 10s (minimum of the action and connection timeout)
1016 08:00:08.002537 /lava-1187704/bin/lava-test-runner /lava-1187704/0
1017 08:00:08.405415 + export TESTRUN_ID=0_timesync-off
1018 08:00:08.413434 + TESTRUN_ID=0_timesync-off
1019 08:00:08.413723 + cd /lava-1187704/0/tests/0_timesync-off
1020 08:00:08.413958 ++ cat uuid
1021 08:00:08.429227 + UUID=1187704_1.6.2.4.1
1022 08:00:08.429529 + set +x
1023 08:00:08.434742 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1187704_1.6.2.4.1>
1024 08:00:08.435235 Received signal: <STARTRUN> 0_timesync-off 1187704_1.6.2.4.1
1025 08:00:08.435506 Starting test lava.0_timesync-off (1187704_1.6.2.4.1)
1026 08:00:08.435793 Skipping test definition patterns.
1027 08:00:08.437993 + systemctl stop systemd-timesyncd
1028 08:00:08.745078 + set +x
1029 08:00:08.745642 Received signal: <ENDRUN> 0_timesync-off 1187704_1.6.2.4.1
1030 08:00:08.745927 Ending use of test pattern.
1031 08:00:08.746150 Ending test lava.0_timesync-off (1187704_1.6.2.4.1), duration 0.31
1033 08:00:08.748188 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1187704_1.6.2.4.1>
1034 08:00:08.963569 + export TESTRUN_ID=1_kselftest-dt
1035 08:00:08.971564 + TESTRUN_ID=1_kselftest-dt
1036 08:00:08.971844 + cd /lava-1187704/0/tests/1_kselftest-dt
1037 08:00:08.972088 ++ cat uuid
1038 08:00:08.987021 + UUID=1187704_1.6.2.4.5
1039 08:00:08.987303 + set +x
1040 08:00:08.992620 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1187704_1.6.2.4.5>
1041 08:00:08.992930 + cd ./automated/linux/kselftest/
1042 08:00:08.993417 Received signal: <STARTRUN> 1_kselftest-dt 1187704_1.6.2.4.5
1043 08:00:08.993669 Starting test lava.1_kselftest-dt (1187704_1.6.2.4.5)
1044 08:00:08.993993 Skipping test definition patterns.
1045 08:00:09.021055 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1046 08:00:09.134220 INFO: install_deps skipped
1047 08:00:09.711930 --2024-09-02 08:00:09-- http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
1048 08:00:09.731725 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1049 08:00:09.846175 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1050 08:00:09.957887 HTTP request sent, awaiting response... 200 OK
1051 08:00:09.958177 Length: 2287464 (2.2M) [application/octet-stream]
1052 08:00:09.963608 Saving to: 'kselftest_armhf.tar.gz'
1053 08:00:09.963978
1054 08:00:11.027124 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 2%[ ] 49.92K 224KB/s kselftest_armhf.tar 9%[> ] 218.67K 487KB/s kselftest_armhf.tar 28%[====> ] 635.35K 913KB/s kselftest_armhf.tar 51%[=========> ] 1.13M 1.25MB/s kselftest_armhf.tar 100%[===================>] 2.18M 2.05MB/s in 1.1s
1055 08:00:11.027492
1056 08:00:11.375958 2024-09-02 08:00:11 (2.05 MB/s) - 'kselftest_armhf.tar.gz' saved [2287464/2287464]
1057 08:00:11.376375
1058 08:00:29.475239 skiplist:
1059 08:00:29.475572 ========================================
1060 08:00:29.480965 ========================================
1061 08:00:29.604759 dt:test_unprobed_devices.sh
1062 08:00:29.639866 ============== Tests to run ===============
1063 08:00:29.649078 dt:test_unprobed_devices.sh
1064 08:00:29.652920 ===========End Tests to run ===============
1065 08:00:29.662346 shardfile-dt pass
1066 08:00:29.891263 <12>[ 76.710097] kselftest: Running tests in dt
1067 08:00:29.920437 TAP version 13
1068 08:00:29.944272 1..1
1069 08:00:29.998644 # timeout set to 45
1070 08:00:29.998918 # selftests: dt: test_unprobed_devices.sh
1071 08:00:30.794186 # TAP version 13
1072 08:00:43.172586 # 1..255
1073 08:00:43.370632 # ok 1 / # SKIP
1074 08:00:43.393019 # ok 2 /clk_mcasp0
1075 08:00:43.465214 # ok 3 /clk_mcasp0_fixed # SKIP
1076 08:00:43.534813 # ok 4 /cpus/cpu@0 # SKIP
1077 08:00:43.607238 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1078 08:00:43.633082 # ok 6 /fixedregulator0
1079 08:00:43.648189 # ok 7 /leds
1080 08:00:43.669251 # ok 8 /ocp
1081 08:00:43.693175 # ok 9 /ocp/interconnect@44c00000
1082 08:00:43.716730 # ok 10 /ocp/interconnect@44c00000/segment@0
1083 08:00:43.744349 # ok 11 /ocp/interconnect@44c00000/segment@100000
1084 08:00:43.768497 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1085 08:00:43.840410 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1086 08:00:43.860409 # ok 14 /ocp/interconnect@44c00000/segment@200000
1087 08:00:43.889431 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1088 08:00:43.990370 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1089 08:00:44.062368 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1090 08:00:44.132877 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1091 08:00:44.212259 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1092 08:00:44.276599 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1093 08:00:44.355667 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1094 08:00:44.420259 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1095 08:00:44.497249 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1096 08:00:44.569131 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1097 08:00:44.643070 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1098 08:00:44.712413 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1099 08:00:44.782036 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1100 08:00:44.855931 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1101 08:00:44.920882 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1102 08:00:44.996750 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1103 08:00:45.063221 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1104 08:00:45.141910 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1105 08:00:45.206617 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1106 08:00:45.284437 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1107 08:00:45.349414 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1108 08:00:45.427503 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1109 08:00:45.504753 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1110 08:00:45.572407 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1111 08:00:45.650970 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1112 08:00:45.715591 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1113 08:00:45.796261 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1114 08:00:45.863347 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1115 08:00:45.943084 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1116 08:00:46.013956 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1117 08:00:46.086958 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1118 08:00:46.162209 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1119 08:00:46.227587 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1120 08:00:46.306071 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1121 08:00:46.370946 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1122 08:00:46.451568 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1123 08:00:46.524062 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1124 08:00:46.596559 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1125 08:00:46.662207 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1126 08:00:46.741133 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1127 08:00:46.814939 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1128 08:00:46.878679 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1129 08:00:46.956925 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1130 08:00:47.031172 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1131 08:00:47.095710 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1132 08:00:47.176217 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1133 08:00:47.242825 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1134 08:00:47.324086 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1135 08:00:47.394694 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1136 08:00:47.469191 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1137 08:00:47.543817 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1138 08:00:47.616075 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1139 08:00:47.682307 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1140 08:00:47.762336 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1141 08:00:47.827933 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1142 08:00:47.906680 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1143 08:00:47.981590 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1144 08:00:48.046274 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1145 08:00:48.126489 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1146 08:00:48.194233 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1147 08:00:48.270242 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1148 08:00:48.344992 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1149 08:00:48.410601 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1150 08:00:48.492606 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1151 08:00:48.566339 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1152 08:00:48.631878 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1153 08:00:48.713336 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1154 08:00:48.784222 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1155 08:00:48.850418 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1156 08:00:48.933205 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1157 08:00:49.005507 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1158 08:00:49.071363 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1159 08:00:49.152233 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1160 08:00:49.226193 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1161 08:00:49.297068 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1162 08:00:49.375068 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1163 08:00:49.445312 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1164 08:00:49.512946 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1165 08:00:49.593078 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1166 08:00:49.659931 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1167 08:00:49.688377 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1168 08:00:49.704696 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1169 08:00:49.730299 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1170 08:00:49.760313 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1171 08:00:49.783442 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1172 08:00:49.801319 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1173 08:00:49.833473 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1174 08:00:49.850539 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1175 08:00:49.961014 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1176 08:00:49.982233 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1177 08:00:50.009469 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1178 08:00:50.034597 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1179 08:00:50.134601 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1180 08:00:50.216835 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1181 08:00:50.284849 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1182 08:00:50.355209 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1183 08:00:50.434332 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1184 08:00:50.507497 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1185 08:00:50.572375 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1186 08:00:50.651903 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1187 08:00:50.724398 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1188 08:00:50.793935 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1189 08:00:50.872007 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1190 08:00:50.945511 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1191 08:00:51.016248 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1192 08:00:51.084053 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1193 08:00:51.164691 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1194 08:00:51.239056 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1195 08:00:51.260189 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1196 08:00:51.332561 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1197 08:00:51.400969 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1198 08:00:51.474464 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1199 08:00:51.489550 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1200 08:00:51.562773 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1201 08:00:51.591489 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1202 08:00:51.660096 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1203 08:00:51.687646 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1204 08:00:51.703794 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1205 08:00:51.731168 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1206 08:00:51.751166 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1207 08:00:51.779558 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1208 08:00:51.807800 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1209 08:00:51.825709 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1210 08:00:51.852010 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1211 08:00:51.880037 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1212 08:00:51.950551 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1213 08:00:52.023283 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1214 08:00:52.042549 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1215 08:00:52.115412 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1216 08:00:52.180905 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1217 08:00:52.281250 # not ok 145 /ocp/interconnect@47c00000
1218 08:00:52.354994 # not ok 146 /ocp/interconnect@47c00000/segment@0
1219 08:00:52.376496 # ok 147 /ocp/interconnect@48000000
1220 08:00:52.404139 # ok 148 /ocp/interconnect@48000000/segment@0
1221 08:00:52.429331 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 08:00:52.451333 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 08:00:52.478030 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 08:00:52.499194 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 08:00:52.522106 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 08:00:52.541687 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 08:00:52.569124 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 08:00:52.642728 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 08:00:52.708238 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 08:00:52.736364 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 08:00:52.762877 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 08:00:52.777038 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 08:00:52.803929 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 08:00:52.829076 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 08:00:52.855996 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 08:00:52.879135 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 08:00:52.896877 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 08:00:52.924279 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 08:00:52.949786 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 08:00:52.964394 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 08:00:52.994520 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 08:00:53.018927 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 08:00:53.042585 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 08:00:53.062221 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1245 08:00:53.082340 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1246 08:00:53.113331 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1247 08:00:53.128850 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1248 08:00:53.158694 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1249 08:00:53.178841 # ok 177 /ocp/interconnect@48000000/segment@100000
1250 08:00:53.198003 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1251 08:00:53.230373 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1252 08:00:53.303080 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1253 08:00:53.375442 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 08:00:53.442680 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1255 08:00:53.517822 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1256 08:00:53.539565 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1257 08:00:53.561422 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1258 08:00:53.588222 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1259 08:00:53.609488 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1260 08:00:53.632566 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1261 08:00:53.651979 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1262 08:00:53.679583 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1263 08:00:53.697798 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1264 08:00:53.728338 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1265 08:00:53.744553 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1266 08:00:53.773091 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1267 08:00:53.797078 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1268 08:00:53.819980 # ok 196 /ocp/interconnect@48000000/segment@200000
1269 08:00:53.836864 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1270 08:00:53.911055 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1271 08:00:53.938854 # ok 199 /ocp/interconnect@48000000/segment@300000
1272 08:00:53.954686 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1273 08:00:53.979110 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1274 08:00:54.009873 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1275 08:00:54.032562 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1276 08:00:54.048370 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1277 08:00:54.073118 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1278 08:00:54.149680 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1279 08:00:54.169344 # ok 207 /ocp/interconnect@4a000000
1280 08:00:54.185930 # ok 208 /ocp/interconnect@4a000000/segment@0
1281 08:00:54.212805 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1282 08:00:54.241907 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1283 08:00:54.261631 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1284 08:00:54.289415 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1285 08:00:54.359918 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1286 08:00:54.471094 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1287 08:00:54.537296 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1288 08:00:54.642469 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1289 08:00:54.716844 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1290 08:00:54.788403 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1291 08:00:54.888642 # not ok 219 /ocp/interconnect@4b140000
1292 08:00:54.957509 # not ok 220 /ocp/interconnect@4b140000/segment@0
1293 08:00:55.023063 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1294 08:00:55.043672 # ok 222 /ocp/target-module@40300000
1295 08:00:55.067149 # ok 223 /ocp/target-module@40300000/sram@0
1296 08:00:55.140539 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1297 08:00:55.217537 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1298 08:00:55.238906 # ok 226 /ocp/target-module@47400000
1299 08:00:55.261296 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1300 08:00:55.277870 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1301 08:00:55.301146 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1302 08:00:55.327263 # ok 230 /ocp/target-module@47400000/usb@1400
1303 08:00:55.347536 # ok 231 /ocp/target-module@47400000/usb@1800
1304 08:00:55.374142 # ok 232 /ocp/target-module@47810000
1305 08:00:55.391794 # ok 233 /ocp/target-module@49000000
1306 08:00:55.416901 # ok 234 /ocp/target-module@49000000/dma@0
1307 08:00:55.437010 # ok 235 /ocp/target-module@49800000
1308 08:00:55.465385 # ok 236 /ocp/target-module@49800000/dma@0
1309 08:00:55.486507 # ok 237 /ocp/target-module@49900000
1310 08:00:55.506520 # ok 238 /ocp/target-module@49900000/dma@0
1311 08:00:55.528657 # ok 239 /ocp/target-module@49a00000
1312 08:00:55.551245 # ok 240 /ocp/target-module@49a00000/dma@0
1313 08:00:55.576555 # ok 241 /ocp/target-module@4c000000
1314 08:00:55.645359 # not ok 242 /ocp/target-module@4c000000/emif@0
1315 08:00:55.671405 # ok 243 /ocp/target-module@50000000
1316 08:00:55.689386 # ok 244 /ocp/target-module@53100000
1317 08:00:55.766393 # not ok 245 /ocp/target-module@53100000/sham@0
1318 08:00:55.786374 # ok 246 /ocp/target-module@53500000
1319 08:00:55.856360 # not ok 247 /ocp/target-module@53500000/aes@0
1320 08:00:55.884806 # ok 248 /ocp/target-module@56000000
1321 08:00:55.987369 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1322 08:00:56.061204 # ok 250 /opp-table # SKIP
1323 08:00:56.131447 # ok 251 /soc # SKIP
1324 08:00:56.148255 # ok 252 /sound
1325 08:00:56.172111 # ok 253 /target-module@4b000000
1326 08:00:56.196820 # ok 254 /target-module@4b000000/target-module@140000
1327 08:00:56.218141 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1328 08:00:56.226532 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1329 08:00:56.235290 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1330 08:00:58.512755 dt_test_unprobed_devices_sh_ skip
1331 08:00:58.518307 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1332 08:00:58.523927 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1333 08:00:58.524184 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1334 08:00:58.529556 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1335 08:00:58.535178 dt_test_unprobed_devices_sh_fixedregulator0 pass
1336 08:00:58.540843 dt_test_unprobed_devices_sh_leds pass
1337 08:00:58.541093 dt_test_unprobed_devices_sh_ocp pass
1338 08:00:58.546429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1339 08:00:58.552054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1340 08:00:58.557676 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1341 08:00:58.568767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1342 08:00:58.574426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1343 08:00:58.580051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1344 08:00:58.591297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1345 08:00:58.596926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1346 08:00:58.608061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1347 08:00:58.619333 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1348 08:00:58.630565 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1349 08:00:58.636209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1350 08:00:58.647318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1351 08:00:58.658580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1352 08:00:58.669809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1353 08:00:58.681073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1354 08:00:58.686521 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1355 08:00:58.697886 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1356 08:00:58.708996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1357 08:00:58.720241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1358 08:00:58.731387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1359 08:00:58.736994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1360 08:00:58.748118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1361 08:00:58.759337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1362 08:00:58.770491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1363 08:00:58.776116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1364 08:00:58.787346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1365 08:00:58.798491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1366 08:00:58.809685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1367 08:00:58.820841 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1368 08:00:58.826418 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1369 08:00:58.837686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1370 08:00:58.848934 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1371 08:00:58.860101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1372 08:00:58.871212 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1373 08:00:58.882457 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1374 08:00:58.893594 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1375 08:00:58.904846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1376 08:00:58.916081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1377 08:00:58.927216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1378 08:00:58.938389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1379 08:00:58.949578 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1380 08:00:58.960846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1381 08:00:58.972102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1382 08:00:58.983218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1383 08:00:58.994374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1384 08:00:59.005577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1385 08:00:59.016756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1386 08:00:59.027973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1387 08:00:59.039100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1388 08:00:59.050322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1389 08:00:59.061468 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1390 08:00:59.072716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1391 08:00:59.083949 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1392 08:00:59.095215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1393 08:00:59.106372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1394 08:00:59.112084 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1395 08:00:59.123213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1396 08:00:59.134501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1397 08:00:59.145717 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1398 08:00:59.156949 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1399 08:00:59.168218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1400 08:00:59.179323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1401 08:00:59.190577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1402 08:00:59.201836 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1403 08:00:59.213080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1404 08:00:59.224181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1405 08:00:59.235429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1406 08:00:59.246588 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1407 08:00:59.257826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1408 08:00:59.269069 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1409 08:00:59.280192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1410 08:00:59.291324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1411 08:00:59.302552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1412 08:00:59.308236 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1413 08:00:59.319303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1414 08:00:59.330549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1415 08:00:59.341673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1416 08:00:59.352944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1417 08:00:59.358425 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1418 08:00:59.375294 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1419 08:00:59.386435 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1420 08:00:59.392052 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1421 08:00:59.408841 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1422 08:00:59.420050 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1423 08:00:59.431190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1424 08:00:59.436830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1425 08:00:59.448078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1426 08:00:59.459201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1427 08:00:59.464828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1428 08:00:59.476044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1429 08:00:59.487200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1430 08:00:59.492826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1431 08:00:59.504056 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1432 08:00:59.509574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1433 08:00:59.520816 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1434 08:00:59.532055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1435 08:00:59.543167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1436 08:00:59.554417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1437 08:00:59.565559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1438 08:00:59.576828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1439 08:00:59.588042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1440 08:00:59.599163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1441 08:00:59.610307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1442 08:00:59.621580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1443 08:00:59.632669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1444 08:00:59.643919 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1445 08:00:59.660689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1446 08:00:59.671931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1447 08:00:59.683080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1448 08:00:59.694289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1449 08:00:59.705445 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1450 08:00:59.722310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1451 08:00:59.733442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1452 08:00:59.744682 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1453 08:00:59.755850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1454 08:00:59.761427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1455 08:00:59.772586 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1456 08:00:59.783781 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1457 08:00:59.789463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1458 08:00:59.800589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1459 08:00:59.806208 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1460 08:00:59.817436 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1461 08:00:59.823047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1462 08:00:59.834176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1463 08:00:59.839774 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1464 08:00:59.851103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1465 08:00:59.856616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1466 08:00:59.867776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1467 08:00:59.879040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1468 08:00:59.890147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1469 08:00:59.895665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1470 08:00:59.907027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1471 08:00:59.918154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1472 08:00:59.923663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1473 08:00:59.934944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1474 08:00:59.940571 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1475 08:00:59.946178 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1476 08:00:59.951650 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1477 08:00:59.957289 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1478 08:00:59.968575 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1479 08:00:59.974053 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1480 08:00:59.979664 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1481 08:00:59.990857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1482 08:00:59.996410 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1483 08:01:00.007626 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1484 08:01:00.013267 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1485 08:01:00.024408 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1486 08:01:00.030015 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1487 08:01:00.035668 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1488 08:01:00.046775 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1489 08:01:00.052456 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1490 08:01:00.063524 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1491 08:01:00.069197 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1492 08:01:00.080416 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1493 08:01:00.086030 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1494 08:01:00.097171 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1495 08:01:00.102779 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1496 08:01:00.114014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1497 08:01:00.119519 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1498 08:01:00.130878 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1499 08:01:00.136424 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1500 08:01:00.147585 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1501 08:01:00.153222 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1502 08:01:00.158713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1503 08:01:00.170087 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1504 08:01:00.175592 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1505 08:01:00.186713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1506 08:01:00.192364 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1507 08:01:00.203572 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1508 08:01:00.209270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1509 08:01:00.220343 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1510 08:01:00.231576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1511 08:01:00.242695 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1512 08:01:00.248349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1513 08:01:00.259571 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1514 08:01:00.265208 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1515 08:01:00.276325 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1516 08:01:00.282007 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1517 08:01:00.293174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1518 08:01:00.298739 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1519 08:01:00.309989 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1520 08:01:00.321190 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1521 08:01:00.326869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1522 08:01:00.338160 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1523 08:01:00.343598 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1524 08:01:00.354858 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1525 08:01:00.360450 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1526 08:01:00.366112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1527 08:01:00.377193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1528 08:01:00.382822 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1529 08:01:00.388558 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1530 08:01:00.399627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1531 08:01:00.405275 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1532 08:01:00.416390 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1533 08:01:00.422011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1534 08:01:00.433270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1535 08:01:00.438753 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1536 08:01:00.444388 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1537 08:01:00.450001 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1538 08:01:00.461126 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1539 08:01:00.466766 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1540 08:01:00.478021 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1541 08:01:00.483624 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1542 08:01:00.494749 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1543 08:01:00.505999 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1544 08:01:00.517272 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1545 08:01:00.522768 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1546 08:01:00.534076 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1547 08:01:00.545310 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1548 08:01:00.550935 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1549 08:01:00.556576 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1550 08:01:00.562165 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1551 08:01:00.567761 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1552 08:01:00.573383 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1553 08:01:00.579004 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1554 08:01:00.590123 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1555 08:01:00.595750 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1556 08:01:00.601410 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1557 08:01:00.607018 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1558 08:01:00.612498 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1559 08:01:00.618120 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1560 08:01:00.623745 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1561 08:01:00.629372 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1562 08:01:00.634993 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1563 08:01:00.640496 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1564 08:01:00.646119 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1565 08:01:00.651741 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1566 08:01:00.657369 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1567 08:01:00.662989 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1568 08:01:00.668492 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1569 08:01:00.674114 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1570 08:01:00.679723 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1571 08:01:00.685376 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1572 08:01:00.690982 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1573 08:01:00.696495 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1574 08:01:00.702104 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1575 08:01:00.707686 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1576 08:01:00.713370 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1577 08:01:00.718962 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1578 08:01:00.724499 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1579 08:01:00.730090 dt_test_unprobed_devices_sh_opp-table skip
1580 08:01:00.735705 dt_test_unprobed_devices_sh_soc skip
1581 08:01:00.735959 dt_test_unprobed_devices_sh_sound pass
1582 08:01:00.741402 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1583 08:01:00.746980 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1584 08:01:00.758077 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1585 08:01:00.758329 dt_test_unprobed_devices_sh fail
1586 08:01:00.763691 + ../../utils/send-to-lava.sh ./output/result.txt
1587 08:01:00.769125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1588 08:01:00.769635 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1590 08:01:00.811755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1591 08:01:00.812248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1593 08:01:00.912273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1594 08:01:00.912825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1596 08:01:01.013022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1597 08:01:01.013494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1599 08:01:01.110988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1600 08:01:01.111459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1602 08:01:01.208121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1603 08:01:01.208698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1605 08:01:01.299138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1606 08:01:01.299609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1608 08:01:01.390520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1609 08:01:01.390993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1611 08:01:01.484855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1612 08:01:01.485326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1614 08:01:01.577360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1615 08:01:01.577835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1617 08:01:01.674846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1618 08:01:01.675325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1620 08:01:01.767781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1621 08:01:01.768263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1623 08:01:01.869561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1624 08:01:01.870152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1626 08:01:01.967635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1627 08:01:01.968108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1629 08:01:02.063331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1630 08:01:02.063813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1632 08:01:02.161118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1633 08:01:02.161673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1635 08:01:02.257938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1636 08:01:02.258412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1638 08:01:02.358454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1639 08:01:02.358928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1641 08:01:02.455982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1642 08:01:02.456486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1644 08:01:02.554991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1645 08:01:02.555469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1647 08:01:02.651167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1648 08:01:02.651657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1650 08:01:02.749094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1651 08:01:02.749569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1653 08:01:02.846484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1654 08:01:02.846979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1656 08:01:02.943098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1657 08:01:02.943701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1659 08:01:03.037075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1660 08:01:03.037568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1662 08:01:03.138765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1663 08:01:03.139262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1665 08:01:03.232124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1666 08:01:03.232729 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1668 08:01:03.331106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1669 08:01:03.331600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1671 08:01:03.429342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1672 08:01:03.429847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1674 08:01:03.527090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1675 08:01:03.527608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1677 08:01:03.623800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1678 08:01:03.624275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1680 08:01:03.722973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1681 08:01:03.723472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1683 08:01:03.820615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1684 08:01:03.821093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1686 08:01:03.920850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1687 08:01:03.921408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1689 08:01:04.014228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1690 08:01:04.014696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1692 08:01:04.112741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1693 08:01:04.113243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1695 08:01:04.207872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1696 08:01:04.208457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1698 08:01:04.306761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1699 08:01:04.307248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1701 08:01:04.403056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1702 08:01:04.403544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1704 08:01:04.509548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1705 08:01:04.510026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1707 08:01:04.608206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1708 08:01:04.608697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1710 08:01:04.706564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1711 08:01:04.707051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1713 08:01:04.807094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1714 08:01:04.807582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1716 08:01:04.905080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1717 08:01:04.905638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1719 08:01:05.002319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1720 08:01:05.002801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1722 08:01:05.102672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1723 08:01:05.103152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1725 08:01:05.206157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1726 08:01:05.206714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1728 08:01:05.304525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1729 08:01:05.305003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1731 08:01:05.403162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1732 08:01:05.403639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1734 08:01:05.501790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1735 08:01:05.502270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1737 08:01:05.600185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1738 08:01:05.600689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1740 08:01:05.700171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1741 08:01:05.700669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1743 08:01:05.796390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1744 08:01:05.796870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1746 08:01:05.896352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1747 08:01:05.896913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1749 08:01:05.995523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1750 08:01:05.995999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1752 08:01:06.091906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1753 08:01:06.092383 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1755 08:01:06.190262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1756 08:01:06.190821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1758 08:01:06.284404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1759 08:01:06.284885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1761 08:01:06.376990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1762 08:01:06.377517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1764 08:01:06.477384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1765 08:01:06.477864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1767 08:01:06.576496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1768 08:01:06.576986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1770 08:01:06.673515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1771 08:01:06.673997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1773 08:01:06.773345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1774 08:01:06.773822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1776 08:01:06.871640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1777 08:01:06.872120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1779 08:01:06.965125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1780 08:01:06.965681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1782 08:01:07.062087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1783 08:01:07.062563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1785 08:01:07.164475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1786 08:01:07.165035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1788 08:01:07.262581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1789 08:01:07.263058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1791 08:01:07.359996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1792 08:01:07.360494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1794 08:01:07.458453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1795 08:01:07.458930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1797 08:01:07.556873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1798 08:01:07.557352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1800 08:01:07.658969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1801 08:01:07.659449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1803 08:01:07.758224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1804 08:01:07.758707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1806 08:01:07.852125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1807 08:01:07.852627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1809 08:01:07.949773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1810 08:01:07.950320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1812 08:01:08.046758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1813 08:01:08.047238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1815 08:01:08.146558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1816 08:01:08.147038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1818 08:01:08.246000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1819 08:01:08.246548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1821 08:01:08.342285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1822 08:01:08.342766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1824 08:01:08.437805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1825 08:01:08.438293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1827 08:01:08.538542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1828 08:01:08.539019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1830 08:01:08.633023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1831 08:01:08.633513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1833 08:01:08.724867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1834 08:01:08.725337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1836 08:01:08.817980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1837 08:01:08.818449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1839 08:01:08.910247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1840 08:01:08.910799 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1842 08:01:09.006224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1843 08:01:09.006696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1845 08:01:09.100750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1846 08:01:09.101230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1848 08:01:09.202839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1849 08:01:09.203408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1851 08:01:09.299666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1852 08:01:09.300143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1854 08:01:09.398768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1855 08:01:09.399250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1857 08:01:09.495351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1858 08:01:09.495837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1860 08:01:09.590201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1861 08:01:09.590693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1863 08:01:09.690129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1864 08:01:09.690610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1866 08:01:09.787901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1867 08:01:09.788384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1869 08:01:09.885877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1870 08:01:09.886546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1872 08:01:09.979694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1873 08:01:09.980256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1875 08:01:10.072962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1876 08:01:10.073438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1878 08:01:10.166636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1879 08:01:10.167253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1881 08:01:10.261250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1882 08:01:10.261728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1884 08:01:10.363852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1885 08:01:10.364378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1887 08:01:10.462597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1888 08:01:10.463071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1890 08:01:10.553345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1891 08:01:10.553820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1893 08:01:10.646600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1894 08:01:10.647072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1896 08:01:10.743099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1897 08:01:10.743543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1899 08:01:10.846737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1900 08:01:10.847214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1902 08:01:10.945473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1903 08:01:10.946044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1905 08:01:11.041816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1906 08:01:11.042303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1908 08:01:11.141817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1909 08:01:11.142300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1911 08:01:11.240315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1912 08:01:11.240877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1914 08:01:11.338415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1915 08:01:11.338893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1917 08:01:11.437186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1918 08:01:11.437662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1920 08:01:11.536678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1921 08:01:11.537154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1923 08:01:11.633673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1924 08:01:11.634155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1926 08:01:11.728945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1927 08:01:11.729429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1929 08:01:11.829677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1930 08:01:11.830153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1932 08:01:11.929429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1933 08:01:11.929984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1935 08:01:12.029166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1936 08:01:12.029643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1938 08:01:12.126680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1939 08:01:12.127157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1941 08:01:12.225646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1942 08:01:12.226202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1944 08:01:12.322900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1945 08:01:12.323377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1947 08:01:12.417543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1949 08:01:12.420674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1950 08:01:12.515413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1952 08:01:12.518537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1953 08:01:12.612539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1955 08:01:12.615699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1956 08:01:12.708924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1957 08:01:12.709411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1959 08:01:12.808390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1960 08:01:12.808868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1962 08:01:12.906011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1963 08:01:12.906569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1965 08:01:13.003775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1966 08:01:13.004259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1968 08:01:13.107774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1969 08:01:13.108258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1971 08:01:13.215894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1972 08:01:13.216466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1974 08:01:13.313433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1975 08:01:13.313907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1977 08:01:13.413163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1978 08:01:13.413640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1980 08:01:13.512127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1981 08:01:13.512628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1983 08:01:13.612407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1984 08:01:13.612894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1986 08:01:13.709205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1987 08:01:13.709684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1989 08:01:13.804540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1990 08:01:13.805014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1992 08:01:13.902381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1993 08:01:13.903158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1995 08:01:13.999852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1996 08:01:14.000334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1998 08:01:14.097394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1999 08:01:14.097870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2001 08:01:14.195348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2002 08:01:14.195903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2004 08:01:14.293397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2005 08:01:14.293875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2007 08:01:14.391855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2008 08:01:14.392337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2010 08:01:14.490347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2011 08:01:14.490830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2013 08:01:14.588763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2014 08:01:14.589249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2016 08:01:14.691979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2017 08:01:14.692472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2019 08:01:14.788860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2020 08:01:14.789352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2022 08:01:14.880855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2023 08:01:14.881315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2025 08:01:14.981724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2026 08:01:14.982290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2028 08:01:15.078602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2029 08:01:15.079087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2031 08:01:15.178077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2032 08:01:15.178554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2034 08:01:15.276619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2035 08:01:15.277199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2037 08:01:15.374722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2038 08:01:15.375204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2040 08:01:15.472221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2041 08:01:15.472699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2043 08:01:15.571211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2044 08:01:15.571702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2046 08:01:15.669319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2047 08:01:15.669782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2049 08:01:15.764953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2050 08:01:15.765442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2052 08:01:15.861897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2053 08:01:15.862350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2055 08:01:15.964257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2056 08:01:15.964816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2058 08:01:16.063014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2059 08:01:16.063500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2061 08:01:16.159036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2062 08:01:16.159515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2064 08:01:16.258819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2065 08:01:16.259403 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2067 08:01:16.354533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2068 08:01:16.355014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2070 08:01:16.452574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2071 08:01:16.453060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2073 08:01:16.551601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2074 08:01:16.552081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2076 08:01:16.655446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2077 08:01:16.655946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2079 08:01:16.754552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2080 08:01:16.755034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2082 08:01:16.853901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2083 08:01:16.854381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2085 08:01:16.951555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2086 08:01:16.952096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2088 08:01:17.050760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2089 08:01:17.051218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2091 08:01:17.148455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2092 08:01:17.148943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2094 08:01:17.243943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2095 08:01:17.244537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2097 08:01:17.341309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2098 08:01:17.341803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2100 08:01:17.440001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2101 08:01:17.440497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2103 08:01:17.535822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2104 08:01:17.536313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2106 08:01:17.635159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2107 08:01:17.635657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2109 08:01:17.734262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2110 08:01:17.734758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2112 08:01:17.829663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2113 08:01:17.830157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2115 08:01:17.925565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2116 08:01:17.926137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2118 08:01:18.020757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2119 08:01:18.021244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2121 08:01:18.123774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2122 08:01:18.124269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2124 08:01:18.222226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2125 08:01:18.222793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2127 08:01:18.317600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2128 08:01:18.318082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2130 08:01:18.418569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2131 08:01:18.419058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2133 08:01:18.517949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2134 08:01:18.518450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2136 08:01:18.616691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2137 08:01:18.617225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2139 08:01:18.709480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2140 08:01:18.709785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2142 08:01:18.806680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2143 08:01:18.807083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2145 08:01:18.903124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2146 08:01:18.903622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2148 08:01:18.998372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2149 08:01:18.998924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2151 08:01:19.096620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2152 08:01:19.097100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2154 08:01:19.192116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2155 08:01:19.192637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2157 08:01:19.287038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2158 08:01:19.287600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2160 08:01:19.386305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2161 08:01:19.386781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2163 08:01:19.482231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2164 08:01:19.482715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2166 08:01:19.578803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2167 08:01:19.579276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2169 08:01:19.676801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2170 08:01:19.677277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2172 08:01:19.776164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2173 08:01:19.776667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2175 08:01:19.872447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2176 08:01:19.872933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2178 08:01:19.971730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2179 08:01:19.972271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2181 08:01:20.070869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2182 08:01:20.071353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2184 08:01:20.165322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2185 08:01:20.165811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2187 08:01:20.265461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2188 08:01:20.266015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2190 08:01:20.362558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2191 08:01:20.363043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2193 08:01:20.461470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2194 08:01:20.461961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2196 08:01:20.562458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2197 08:01:20.562950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2199 08:01:20.659147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2200 08:01:20.659632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2202 08:01:20.756137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2203 08:01:20.756645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2205 08:01:20.856042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2206 08:01:20.856557 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2208 08:01:20.949302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2209 08:01:20.949872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2211 08:01:21.046002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2212 08:01:21.046481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2214 08:01:21.145995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2215 08:01:21.146449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2217 08:01:21.246145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2218 08:01:21.246723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2220 08:01:21.347081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2221 08:01:21.347574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2223 08:01:21.444660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2224 08:01:21.445148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2226 08:01:21.545938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2227 08:01:21.546426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2229 08:01:21.646640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2230 08:01:21.647133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2232 08:01:21.746285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2233 08:01:21.746810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2235 08:01:21.846404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2236 08:01:21.846899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2238 08:01:21.944615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2239 08:01:21.945176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2241 08:01:22.043334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2242 08:01:22.043809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2244 08:01:22.137595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2245 08:01:22.138068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2247 08:01:22.234609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2248 08:01:22.235163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2250 08:01:22.331066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2251 08:01:22.331539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2253 08:01:22.429334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2254 08:01:22.429813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2256 08:01:22.533469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2257 08:01:22.533945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2259 08:01:22.632218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2260 08:01:22.632710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2262 08:01:22.726946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2264 08:01:22.729957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2265 08:01:22.822918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2266 08:01:22.823394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2268 08:01:22.924313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2269 08:01:22.924767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2271 08:01:23.021237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2272 08:01:23.021802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2274 08:01:23.116794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2275 08:01:23.117272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2277 08:01:23.214227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2278 08:01:23.214805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2280 08:01:23.311943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2281 08:01:23.312444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2283 08:01:23.402277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2284 08:01:23.402749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2286 08:01:23.498524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2287 08:01:23.499042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2289 08:01:23.593450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2290 08:01:23.593946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2292 08:01:23.685568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2293 08:01:23.686091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2295 08:01:23.785324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2296 08:01:23.785811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2298 08:01:23.880284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2299 08:01:23.880761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2301 08:01:23.977482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2302 08:01:23.978041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2304 08:01:24.071256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2305 08:01:24.071736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2307 08:01:24.168752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2308 08:01:24.169230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2310 08:01:24.262255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2311 08:01:24.262813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2313 08:01:24.355760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2314 08:01:24.356254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2316 08:01:24.446511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2317 08:01:24.446997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2319 08:01:24.543481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2320 08:01:24.543965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2322 08:01:24.641379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2323 08:01:24.641873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2325 08:01:24.739323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2326 08:01:24.739798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2328 08:01:24.842200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2329 08:01:24.842696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2331 08:01:24.939917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2332 08:01:24.940539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2334 08:01:25.037005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2335 08:01:25.037536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2337 08:01:25.132495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2338 08:01:25.132976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2340 08:01:25.227117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2341 08:01:25.227680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2343 08:01:25.321136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2344 08:01:25.321615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2346 08:01:25.418654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2347 08:01:25.419145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2349 08:01:25.514647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2350 08:01:25.515126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2352 08:01:25.607152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2353 08:01:25.607646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2355 08:01:25.698686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2356 08:01:25.698962 + set +x
2357 08:01:25.699418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2359 08:01:25.702996 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1187704_1.6.2.4.5>
2360 08:01:25.703439 Received signal: <ENDRUN> 1_kselftest-dt 1187704_1.6.2.4.5
2361 08:01:25.703684 Ending use of test pattern.
2362 08:01:25.703907 Ending test lava.1_kselftest-dt (1187704_1.6.2.4.5), duration 76.71
2364 08:01:25.708370 <LAVA_TEST_RUNNER EXIT>
2365 08:01:25.708806 ok: lava_test_shell seems to have completed
2366 08:01:25.714353 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2367 08:01:25.715282 end: 3.1 lava-test-shell (duration 00:01:18) [common]
2368 08:01:25.715543 end: 3 lava-test-retry (duration 00:01:18) [common]
2369 08:01:25.715807 start: 4 finalize (timeout 00:06:03) [common]
2370 08:01:25.716074 start: 4.1 power-off (timeout 00:00:30) [common]
2371 08:01:25.716440 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2372 08:01:26.083301 Returned 0 in 0 seconds
2373 08:01:26.184227 end: 4.1 power-off (duration 00:00:00) [common]
2375 08:01:26.185155 start: 4.2 read-feedback (timeout 00:06:03) [common]
2376 08:01:26.185775 Listened to connection for namespace 'common' for up to 1s
2377 08:01:26.186327 Listened to connection for namespace 'common' for up to 1s
2378 08:01:27.186694 Finalising connection for namespace 'common'
2379 08:01:27.187128 Disconnecting from shell: Finalise
2380 08:01:27.187401 / #
2381 08:01:27.288038 end: 4.2 read-feedback (duration 00:00:01) [common]
2382 08:01:27.288506 end: 4 finalize (duration 00:00:02) [common]
2383 08:01:27.288859 Cleaning after the job
2384 08:01:27.289181 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/ramdisk
2385 08:01:27.293010 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/kernel
2386 08:01:27.296029 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/dtb
2387 08:01:27.296511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/nfsrootfs
2388 08:01:27.349064 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187704/tftp-deploy-72yiprtd/modules
2389 08:01:27.352679 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1187704
2390 08:01:27.992887 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1187704
2391 08:01:27.993167 Job finished correctly