Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 14
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 04:20:14.542558 lava-dispatcher, installed at version: 2024.01
2 04:20:14.543327 start: 0 validate
3 04:20:14.543791 Start time: 2024-09-02 04:20:14.543763+00:00 (UTC)
4 04:20:14.544358 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:20:14.544889 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 04:20:14.588435 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:20:14.589013 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 04:20:14.620550 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:20:14.621196 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 04:20:14.656133 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:20:14.656718 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 04:20:14.691145 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 04:20:14.691642 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-19-g67784a74e258a%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 04:20:14.730519 validate duration: 0.19
16 04:20:14.731701 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:20:14.732090 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:20:14.732531 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:20:14.733282 Not decompressing ramdisk as can be used compressed.
20 04:20:14.733838 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 04:20:14.734176 saving as /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/ramdisk/initrd.cpio.gz
22 04:20:14.734575 total size: 4775763 (4 MB)
23 04:20:14.773293 progress 0 % (0 MB)
24 04:20:14.777023 progress 5 % (0 MB)
25 04:20:14.780469 progress 10 % (0 MB)
26 04:20:14.783744 progress 15 % (0 MB)
27 04:20:14.787518 progress 20 % (0 MB)
28 04:20:14.790794 progress 25 % (1 MB)
29 04:20:14.794097 progress 30 % (1 MB)
30 04:20:14.797722 progress 35 % (1 MB)
31 04:20:14.800980 progress 40 % (1 MB)
32 04:20:14.804368 progress 45 % (2 MB)
33 04:20:14.807606 progress 50 % (2 MB)
34 04:20:14.811213 progress 55 % (2 MB)
35 04:20:14.814402 progress 60 % (2 MB)
36 04:20:14.817672 progress 65 % (2 MB)
37 04:20:14.821333 progress 70 % (3 MB)
38 04:20:14.824563 progress 75 % (3 MB)
39 04:20:14.827773 progress 80 % (3 MB)
40 04:20:14.830906 progress 85 % (3 MB)
41 04:20:14.834299 progress 90 % (4 MB)
42 04:20:14.837285 progress 95 % (4 MB)
43 04:20:14.840255 progress 100 % (4 MB)
44 04:20:14.840936 4 MB downloaded in 0.11 s (42.83 MB/s)
45 04:20:14.841512 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:20:14.842500 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:20:14.842838 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:20:14.843131 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:20:14.843629 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 04:20:14.843890 saving as /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/kernel/zImage
52 04:20:14.844137 total size: 11354624 (10 MB)
53 04:20:14.844368 No compression specified
54 04:20:14.881064 progress 0 % (0 MB)
55 04:20:14.888510 progress 5 % (0 MB)
56 04:20:14.896104 progress 10 % (1 MB)
57 04:20:14.903874 progress 15 % (1 MB)
58 04:20:14.911899 progress 20 % (2 MB)
59 04:20:14.919249 progress 25 % (2 MB)
60 04:20:14.926279 progress 30 % (3 MB)
61 04:20:14.934521 progress 35 % (3 MB)
62 04:20:14.942093 progress 40 % (4 MB)
63 04:20:14.949257 progress 45 % (4 MB)
64 04:20:14.956778 progress 50 % (5 MB)
65 04:20:14.963888 progress 55 % (5 MB)
66 04:20:14.971439 progress 60 % (6 MB)
67 04:20:14.979211 progress 65 % (7 MB)
68 04:20:14.986171 progress 70 % (7 MB)
69 04:20:14.993505 progress 75 % (8 MB)
70 04:20:15.001014 progress 80 % (8 MB)
71 04:20:15.009171 progress 85 % (9 MB)
72 04:20:15.017316 progress 90 % (9 MB)
73 04:20:15.024613 progress 95 % (10 MB)
74 04:20:15.031100 progress 100 % (10 MB)
75 04:20:15.031701 10 MB downloaded in 0.19 s (57.74 MB/s)
76 04:20:15.032196 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:20:15.033023 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:20:15.033295 start: 1.3 download-retry (timeout 00:10:00) [common]
80 04:20:15.033561 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 04:20:15.034020 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 04:20:15.034292 saving as /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/dtb/am335x-boneblack.dtb
83 04:20:15.034500 total size: 70308 (0 MB)
84 04:20:15.034710 No compression specified
85 04:20:15.069570 progress 46 % (0 MB)
86 04:20:15.070379 progress 93 % (0 MB)
87 04:20:15.071088 progress 100 % (0 MB)
88 04:20:15.071504 0 MB downloaded in 0.04 s (1.81 MB/s)
89 04:20:15.072004 end: 1.3.1 http-download (duration 00:00:00) [common]
91 04:20:15.072926 end: 1.3 download-retry (duration 00:00:00) [common]
92 04:20:15.073271 start: 1.4 download-retry (timeout 00:10:00) [common]
93 04:20:15.073583 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 04:20:15.074087 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 04:20:15.074355 saving as /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/nfsrootfs/full.rootfs.tar
96 04:20:15.074561 total size: 117747780 (112 MB)
97 04:20:15.074770 Using unxz to decompress xz
98 04:20:15.107573 progress 0 % (0 MB)
99 04:20:15.833831 progress 5 % (5 MB)
100 04:20:16.575543 progress 10 % (11 MB)
101 04:20:17.339451 progress 15 % (16 MB)
102 04:20:18.053852 progress 20 % (22 MB)
103 04:20:18.629080 progress 25 % (28 MB)
104 04:20:19.473042 progress 30 % (33 MB)
105 04:20:20.274338 progress 35 % (39 MB)
106 04:20:20.606796 progress 40 % (44 MB)
107 04:20:20.964574 progress 45 % (50 MB)
108 04:20:21.617886 progress 50 % (56 MB)
109 04:20:22.434607 progress 55 % (61 MB)
110 04:20:23.153847 progress 60 % (67 MB)
111 04:20:23.860853 progress 65 % (73 MB)
112 04:20:24.613061 progress 70 % (78 MB)
113 04:20:25.359971 progress 75 % (84 MB)
114 04:20:26.081062 progress 80 % (89 MB)
115 04:20:26.781999 progress 85 % (95 MB)
116 04:20:27.563512 progress 90 % (101 MB)
117 04:20:28.339200 progress 95 % (106 MB)
118 04:20:29.308603 progress 100 % (112 MB)
119 04:20:29.323943 112 MB downloaded in 14.25 s (7.88 MB/s)
120 04:20:29.324815 end: 1.4.1 http-download (duration 00:00:14) [common]
122 04:20:29.326399 end: 1.4 download-retry (duration 00:00:14) [common]
123 04:20:29.326903 start: 1.5 download-retry (timeout 00:09:45) [common]
124 04:20:29.327407 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 04:20:29.328224 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 04:20:29.328681 saving as /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/modules/modules.tar
127 04:20:29.329084 total size: 6607904 (6 MB)
128 04:20:29.329494 Using unxz to decompress xz
129 04:20:29.375247 progress 0 % (0 MB)
130 04:20:29.411085 progress 5 % (0 MB)
131 04:20:29.453064 progress 10 % (0 MB)
132 04:20:29.497399 progress 15 % (0 MB)
133 04:20:29.544448 progress 20 % (1 MB)
134 04:20:29.588423 progress 25 % (1 MB)
135 04:20:29.635271 progress 30 % (1 MB)
136 04:20:29.678110 progress 35 % (2 MB)
137 04:20:29.720726 progress 40 % (2 MB)
138 04:20:29.763329 progress 45 % (2 MB)
139 04:20:29.807190 progress 50 % (3 MB)
140 04:20:29.849479 progress 55 % (3 MB)
141 04:20:29.892211 progress 60 % (3 MB)
142 04:20:29.951959 progress 65 % (4 MB)
143 04:20:30.004196 progress 70 % (4 MB)
144 04:20:30.055902 progress 75 % (4 MB)
145 04:20:30.109408 progress 80 % (5 MB)
146 04:20:30.163073 progress 85 % (5 MB)
147 04:20:30.213838 progress 90 % (5 MB)
148 04:20:30.264291 progress 95 % (6 MB)
149 04:20:30.315190 progress 100 % (6 MB)
150 04:20:30.331715 6 MB downloaded in 1.00 s (6.29 MB/s)
151 04:20:30.332754 end: 1.5.1 http-download (duration 00:00:01) [common]
153 04:20:30.334503 end: 1.5 download-retry (duration 00:00:01) [common]
154 04:20:30.335069 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 04:20:30.335635 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 04:20:47.077372 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9
157 04:20:47.077958 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 04:20:47.078243 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 04:20:47.078879 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal
160 04:20:47.079315 makedir: /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin
161 04:20:47.079635 makedir: /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/tests
162 04:20:47.079941 makedir: /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/results
163 04:20:47.080294 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-add-keys
164 04:20:47.080839 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-add-sources
165 04:20:47.081342 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-background-process-start
166 04:20:47.081825 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-background-process-stop
167 04:20:47.082373 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-common-functions
168 04:20:47.082942 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-echo-ipv4
169 04:20:47.083429 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-install-packages
170 04:20:47.083905 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-installed-packages
171 04:20:47.084418 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-os-build
172 04:20:47.084905 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-probe-channel
173 04:20:47.085378 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-probe-ip
174 04:20:47.085855 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-target-ip
175 04:20:47.086408 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-target-mac
176 04:20:47.086937 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-target-storage
177 04:20:47.087426 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-test-case
178 04:20:47.087900 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-test-event
179 04:20:47.088406 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-test-feedback
180 04:20:47.088886 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-test-raise
181 04:20:47.089346 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-test-reference
182 04:20:47.089810 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-test-runner
183 04:20:47.090309 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-test-set
184 04:20:47.090851 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-test-shell
185 04:20:47.091344 Updating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-add-keys (debian)
186 04:20:47.091869 Updating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-add-sources (debian)
187 04:20:47.092398 Updating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-install-packages (debian)
188 04:20:47.092895 Updating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-installed-packages (debian)
189 04:20:47.093382 Updating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/bin/lava-os-build (debian)
190 04:20:47.093809 Creating /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/environment
191 04:20:47.094181 LAVA metadata
192 04:20:47.094441 - LAVA_JOB_ID=689530
193 04:20:47.094656 - LAVA_DISPATCHER_IP=192.168.6.2
194 04:20:47.095020 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 04:20:47.095961 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 04:20:47.096286 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 04:20:47.096493 skipped lava-vland-overlay
198 04:20:47.096731 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 04:20:47.096982 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 04:20:47.097197 skipped lava-multinode-overlay
201 04:20:47.097435 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 04:20:47.097682 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 04:20:47.097926 Loading test definitions
204 04:20:47.098198 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 04:20:47.098414 Using /lava-689530 at stage 0
206 04:20:47.099492 uuid=689530_1.6.2.4.1 testdef=None
207 04:20:47.099799 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 04:20:47.100079 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 04:20:47.101646 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 04:20:47.102424 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 04:20:47.104329 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 04:20:47.105147 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 04:20:47.106945 runner path: /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/0/tests/0_timesync-off test_uuid 689530_1.6.2.4.1
216 04:20:47.107480 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 04:20:47.108306 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 04:20:47.108528 Using /lava-689530 at stage 0
220 04:20:47.108877 Fetching tests from https://github.com/kernelci/test-definitions.git
221 04:20:47.109169 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/0/tests/1_kselftest-dt'
222 04:20:50.631414 Running '/usr/bin/git checkout kernelci.org
223 04:20:51.086083 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 04:20:51.087502 uuid=689530_1.6.2.4.5 testdef=None
225 04:20:51.087840 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 04:20:51.089298 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 04:20:51.095176 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 04:20:51.097055 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 04:20:51.104970 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 04:20:51.106768 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 04:20:51.114376 runner path: /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/0/tests/1_kselftest-dt test_uuid 689530_1.6.2.4.5
235 04:20:51.114937 BOARD='beaglebone-black'
236 04:20:51.115377 BRANCH='mainline'
237 04:20:51.115807 SKIPFILE='/dev/null'
238 04:20:51.116268 SKIP_INSTALL='True'
239 04:20:51.116697 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 04:20:51.117137 TST_CASENAME=''
241 04:20:51.117562 TST_CMDFILES='dt'
242 04:20:51.118614 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 04:20:51.120341 Creating lava-test-runner.conf files
245 04:20:51.120783 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/689530/lava-overlay-_8e11zal/lava-689530/0 for stage 0
246 04:20:51.121467 - 0_timesync-off
247 04:20:51.121957 - 1_kselftest-dt
248 04:20:51.122632 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 04:20:51.123212 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 04:21:14.351287 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 04:21:14.351710 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 04:21:14.351973 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 04:21:14.352271 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 04:21:14.352536 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 04:21:14.731346 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 04:21:14.731832 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 04:21:14.732135 extracting modules file /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9
258 04:21:15.671075 extracting modules file /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/689530/extract-overlay-ramdisk-u2a_l_og/ramdisk
259 04:21:16.619562 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 04:21:16.620059 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 04:21:16.620355 [common] Applying overlay to NFS
262 04:21:16.620579 [common] Applying overlay /var/lib/lava/dispatcher/tmp/689530/compress-overlay-oilvkbd0/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9
263 04:21:19.340491 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 04:21:19.340928 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 04:21:19.341219 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 04:21:19.341508 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 04:21:19.341771 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 04:21:19.342041 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 04:21:19.342302 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 04:21:19.342567 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 04:21:19.342826 Building ramdisk /var/lib/lava/dispatcher/tmp/689530/extract-overlay-ramdisk-u2a_l_og/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/689530/extract-overlay-ramdisk-u2a_l_og/ramdisk
272 04:21:20.345718 >> 74799 blocks
273 04:21:24.886405 Adding RAMdisk u-boot header.
274 04:21:24.886862 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/689530/extract-overlay-ramdisk-u2a_l_og/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/689530/extract-overlay-ramdisk-u2a_l_og/ramdisk.cpio.gz.uboot
275 04:21:25.083393 output: Image Name:
276 04:21:25.083790 output: Created: Mon Sep 2 04:21:24 2024
277 04:21:25.084049 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 04:21:25.084472 output: Data Size: 14795258 Bytes = 14448.49 KiB = 14.11 MiB
279 04:21:25.084878 output: Load Address: 00000000
280 04:21:25.085275 output: Entry Point: 00000000
281 04:21:25.085666 output:
282 04:21:25.086570 rename /var/lib/lava/dispatcher/tmp/689530/extract-overlay-ramdisk-u2a_l_og/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/ramdisk/ramdisk.cpio.gz.uboot
283 04:21:25.087272 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 04:21:25.087815 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 04:21:25.088378 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 04:21:25.088842 No LXC device requested
287 04:21:25.089339 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 04:21:25.089842 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 04:21:25.090332 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 04:21:25.090742 Checking files for TFTP limit of 4294967296 bytes.
291 04:21:25.093413 end: 1 tftp-deploy (duration 00:01:10) [common]
292 04:21:25.093995 start: 2 uboot-action (timeout 00:05:00) [common]
293 04:21:25.094518 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 04:21:25.095013 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 04:21:25.095511 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 04:21:25.096278 substitutions:
297 04:21:25.096701 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 04:21:25.097105 - {DTB_ADDR}: 0x88000000
299 04:21:25.097504 - {DTB}: 689530/tftp-deploy-xsdkrgyu/dtb/am335x-boneblack.dtb
300 04:21:25.097901 - {INITRD}: 689530/tftp-deploy-xsdkrgyu/ramdisk/ramdisk.cpio.gz.uboot
301 04:21:25.098296 - {KERNEL_ADDR}: 0x82000000
302 04:21:25.098687 - {KERNEL}: 689530/tftp-deploy-xsdkrgyu/kernel/zImage
303 04:21:25.099076 - {LAVA_MAC}: None
304 04:21:25.099504 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9
305 04:21:25.099901 - {NFS_SERVER_IP}: 192.168.6.2
306 04:21:25.100320 - {PRESEED_CONFIG}: None
307 04:21:25.100709 - {PRESEED_LOCAL}: None
308 04:21:25.101097 - {RAMDISK_ADDR}: 0x83000000
309 04:21:25.101487 - {RAMDISK}: 689530/tftp-deploy-xsdkrgyu/ramdisk/ramdisk.cpio.gz.uboot
310 04:21:25.101878 - {ROOT_PART}: None
311 04:21:25.102264 - {ROOT}: None
312 04:21:25.102647 - {SERVER_IP}: 192.168.6.2
313 04:21:25.103030 - {TEE_ADDR}: 0x83000000
314 04:21:25.103412 - {TEE}: None
315 04:21:25.103795 Parsed boot commands:
316 04:21:25.104189 - setenv autoload no
317 04:21:25.104574 - setenv initrd_high 0xffffffff
318 04:21:25.104954 - setenv fdt_high 0xffffffff
319 04:21:25.105332 - dhcp
320 04:21:25.105709 - setenv serverip 192.168.6.2
321 04:21:25.106086 - tftp 0x82000000 689530/tftp-deploy-xsdkrgyu/kernel/zImage
322 04:21:25.106467 - tftp 0x83000000 689530/tftp-deploy-xsdkrgyu/ramdisk/ramdisk.cpio.gz.uboot
323 04:21:25.106846 - setenv initrd_size ${filesize}
324 04:21:25.107225 - tftp 0x88000000 689530/tftp-deploy-xsdkrgyu/dtb/am335x-boneblack.dtb
325 04:21:25.107606 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 04:21:25.108015 - bootz 0x82000000 0x83000000 0x88000000
327 04:21:25.108515 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 04:21:25.109979 start: 2.3 connect-device (timeout 00:05:00) [common]
330 04:21:25.110394 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 04:21:25.125159 Setting prompt string to ['lava-test: # ']
332 04:21:25.126644 end: 2.3 connect-device (duration 00:00:00) [common]
333 04:21:25.127244 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 04:21:25.127792 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 04:21:25.128392 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 04:21:25.129610 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 04:21:25.163719 >> OK - accepted request
338 04:21:25.165882 Returned 0 in 0 seconds
339 04:21:25.267008 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 04:21:25.268671 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 04:21:25.269226 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 04:21:25.269731 Setting prompt string to ['Hit any key to stop autoboot']
344 04:21:25.270185 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 04:21:25.271717 Trying 192.168.56.21...
346 04:21:25.272257 Connected to conserv1.
347 04:21:25.272669 Escape character is '^]'.
348 04:21:25.273073
349 04:21:25.273478 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 04:21:25.273896
351 04:21:33.089532
352 04:21:33.090121 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 04:21:33.094519 Trying to boot from MMC1
354 04:21:33.666676
355 04:21:33.667249
356 04:21:33.667672 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 04:21:33.668132
358 04:21:33.672158 CPU : AM335X-GP rev 2.1
359 04:21:33.672601 Model: TI AM335x BeagleBone Black
360 04:21:33.676283 DRAM: 512 MiB
361 04:21:33.759010 Core: 160 devices, 18 uclasses, devicetree: separate
362 04:21:33.768763 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 04:21:37.142062 7[r[999;999H[6n8NAND:
364 04:21:37.142676 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 04:21:37.146250 Trying to boot from MMC1
366 04:21:37.720713
367 04:21:37.721480
368 04:21:37.721766 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 04:21:37.721981
370 04:21:37.726617 CPU : AM335X-GP rev 2.1
371 04:21:37.726912 Model: TI AM335x BeagleBone Black
372 04:21:37.730294 DRAM: 512 MiB
373 04:21:37.813192 Core: 160 devices, 18 uclasses, devicetree: separate
374 04:21:37.822807 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 04:21:39.838189 7[r[999;999H[6n8NAND:
376 04:21:39.838581 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 04:21:39.843366 Trying to boot from MMC1
378 04:21:40.415739
379 04:21:40.416350
380 04:21:40.416607 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 04:21:40.416819
382 04:21:40.421203 CPU : AM335X-GP rev 2.1
383 04:21:40.421652 Model: TI AM335x BeagleBone Black
384 04:21:40.425337 DRAM: 512 MiB
385 04:21:40.508213 Core: 160 devices, 18 uclasses, devicetree: separate
386 04:21:40.517846 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 04:21:41.023111 7[r[999;999H[6n8NAND: 0 MiB
388 04:21:41.033267 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 04:21:41.106316 Loading Environment from FAT... Unable to use mmc 0:1...
390 04:21:41.127592 <ethaddr> not set. Validating first E-fuse MAC
391 04:21:41.157921 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 04:21:41.217121 Hit any key to stop autoboot: 2
394 04:21:41.217831 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 04:21:41.218173 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 04:21:41.218428 Setting prompt string to ['=>']
397 04:21:41.218681 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 04:21:41.226361 0
399 04:21:41.227513 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 04:21:41.227948 Sending with 10 millisecond of delay
402 04:21:42.363436 => setenv autoload no
403 04:21:42.374350 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 04:21:42.379376 setenv autoload no
405 04:21:42.380135 Sending with 10 millisecond of delay
407 04:21:44.179471 => setenv initrd_high 0xffffffff
408 04:21:44.190254 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 04:21:44.191084 setenv initrd_high 0xffffffff
410 04:21:44.191789 Sending with 10 millisecond of delay
412 04:21:45.808415 => setenv fdt_high 0xffffffff
413 04:21:45.819222 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 04:21:45.819773 setenv fdt_high 0xffffffff
415 04:21:45.820289 Sending with 10 millisecond of delay
417 04:21:46.111693 => dhcp
418 04:21:46.122226 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 04:21:46.122708 dhcp
420 04:21:46.122941 link up on port 0, speed 100, full duplex
421 04:21:46.123149 BOOTP broadcast 1
422 04:21:46.377245 BOOTP broadcast 2
423 04:21:46.412181 DHCP client bound to address 192.168.6.30 (284 ms)
424 04:21:46.412735 Sending with 10 millisecond of delay
426 04:21:48.088619 => setenv serverip 192.168.6.2
427 04:21:48.099151 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
428 04:21:48.099720 setenv serverip 192.168.6.2
429 04:21:48.100236 Sending with 10 millisecond of delay
431 04:21:51.582309 => tftp 0x82000000 689530/tftp-deploy-xsdkrgyu/kernel/zImage
432 04:21:51.593305 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
433 04:21:51.594346 tftp 0x82000000 689530/tftp-deploy-xsdkrgyu/kernel/zImage
434 04:21:51.594941 link up on port 0, speed 100, full duplex
435 04:21:51.597733 Using ethernet@4a100000 device
436 04:21:51.603336 TFTP from server 192.168.6.2; our IP address is 192.168.6.30
437 04:21:51.610245 Filename '689530/tftp-deploy-xsdkrgyu/kernel/zImage'.
438 04:21:51.610940 Load address: 0x82000000
439 04:21:53.923516 Loading: *################################################## 10.8 MiB
440 04:21:53.924215 4.7 MiB/s
441 04:21:53.924697 done
442 04:21:53.928064 Bytes transferred = 11354624 (ad4200 hex)
443 04:21:53.928928 Sending with 10 millisecond of delay
445 04:21:58.377900 => tftp 0x83000000 689530/tftp-deploy-xsdkrgyu/ramdisk/ramdisk.cpio.gz.uboot
446 04:21:58.388762 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
447 04:21:58.389733 tftp 0x83000000 689530/tftp-deploy-xsdkrgyu/ramdisk/ramdisk.cpio.gz.uboot
448 04:21:58.390258 link up on port 0, speed 100, full duplex
449 04:21:58.393775 Using ethernet@4a100000 device
450 04:21:58.399320 TFTP from server 192.168.6.2; our IP address is 192.168.6.30
451 04:21:58.402588 Filename '689530/tftp-deploy-xsdkrgyu/ramdisk/ramdisk.cpio.gz.uboot'.
452 04:21:58.407811 Load address: 0x83000000
453 04:22:01.364682 Loading: *################################################## 14.1 MiB
454 04:22:01.365499 4.8 MiB/s
455 04:22:01.366091 done
456 04:22:01.368650 Bytes transferred = 14795322 (e1c23a hex)
457 04:22:01.369642 Sending with 10 millisecond of delay
459 04:22:03.228142 => setenv initrd_size ${filesize}
460 04:22:03.238969 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
461 04:22:03.239517 setenv initrd_size ${filesize}
462 04:22:03.240163 Sending with 10 millisecond of delay
464 04:22:07.386557 => tftp 0x88000000 689530/tftp-deploy-xsdkrgyu/dtb/am335x-boneblack.dtb
465 04:22:07.397347 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
466 04:22:07.398277 tftp 0x88000000 689530/tftp-deploy-xsdkrgyu/dtb/am335x-boneblack.dtb
467 04:22:07.398772 link up on port 0, speed 100, full duplex
468 04:22:07.402330 Using ethernet@4a100000 device
469 04:22:07.407834 TFTP from server 192.168.6.2; our IP address is 192.168.6.30
470 04:22:07.411176 Filename '689530/tftp-deploy-xsdkrgyu/dtb/am335x-boneblack.dtb'.
471 04:22:07.414870 Load address: 0x88000000
472 04:22:07.431489 Loading: *################################################## 68.7 KiB
473 04:22:07.440386 3.7 MiB/s
474 04:22:07.440905 done
475 04:22:07.441339 Bytes transferred = 70308 (112a4 hex)
476 04:22:07.442077 Sending with 10 millisecond of delay
478 04:22:20.623170 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 04:22:20.633951 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
480 04:22:20.634786 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 04:22:20.635493 Sending with 10 millisecond of delay
483 04:22:22.974410 => bootz 0x82000000 0x83000000 0x88000000
484 04:22:22.985212 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
485 04:22:22.985769 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
486 04:22:22.986770 bootz 0x82000000 0x83000000 0x88000000
487 04:22:22.987243 Kernel image @ 0x82000000 [ 0x000000 - 0xad4200 ]
488 04:22:22.987756 ## Loading init Ramdisk from Legacy Image at 83000000 ...
489 04:22:22.992747 Image Name:
490 04:22:22.993223 Created: 2024-09-02 4:21:24 UTC
491 04:22:23.001714 Image Type: ARM Linux RAMDisk Image (uncompressed)
492 04:22:23.002208 Data Size: 14795258 Bytes = 14.1 MiB
493 04:22:23.009369 Load Address: 00000000
494 04:22:23.010011 Entry Point: 00000000
495 04:22:23.178782 Verifying Checksum ... OK
496 04:22:23.179579 ## Flattened Device Tree blob at 88000000
497 04:22:23.185140 Booting using the fdt blob at 0x88000000
498 04:22:23.189994 Using Device Tree in place at 88000000, end 880142a3
499 04:22:23.203503
500 04:22:23.204036 Starting kernel ...
501 04:22:23.204471
502 04:22:23.205352 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
503 04:22:23.205971 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
504 04:22:23.206466 Setting prompt string to ['Linux version [0-9]']
505 04:22:23.206951 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
506 04:22:23.207441 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
507 04:22:24.037177 [ 0.000000] Booting Linux on physical CPU 0x0
508 04:22:24.043080 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
509 04:22:24.043640 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
510 04:22:24.044152 Setting prompt string to []
511 04:22:24.044661 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
512 04:22:24.045117 Using line separator: #'\n'#
513 04:22:24.045526 No login prompt set.
514 04:22:24.045957 Parsing kernel messages
515 04:22:24.046353 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
516 04:22:24.047113 [login-action] Waiting for messages, (timeout 00:04:01)
517 04:22:24.047557 Waiting using forced prompt support (timeout 00:02:01)
518 04:22:24.060022 [ 0.000000] Linux version 6.11.0-rc6 (KernelCI@build-j304715-arm-gcc-12-multi-v7-defconfig-pzkrd) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Sep 2 03:48:51 UTC 2024
519 04:22:24.065621 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
520 04:22:24.071358 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
521 04:22:24.082752 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
522 04:22:24.088369 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
523 04:22:24.094391 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
524 04:22:24.094828 [ 0.000000] Memory policy: Data cache writeback
525 04:22:24.100897 [ 0.000000] efi: UEFI not found.
526 04:22:24.109598 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
527 04:22:24.110039 [ 0.000000] Zone ranges:
528 04:22:24.115341 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
529 04:22:24.120904 [ 0.000000] Normal empty
530 04:22:24.126660 [ 0.000000] HighMem empty
531 04:22:24.127099 [ 0.000000] Movable zone start for each node
532 04:22:24.132439 [ 0.000000] Early memory node ranges
533 04:22:24.138164 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
534 04:22:24.145839 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
535 04:22:24.170602 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 04:22:24.176392 [ 0.000000] AM335X ES2.1 (sgx neon)
537 04:22:24.187931 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
538 04:22:24.205673 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 04:22:24.217150 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 04:22:24.222926 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 04:22:24.228646 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 04:22:24.238662 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 04:22:24.267656 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 04:22:24.273633 <6>[ 0.000000] trace event string verifier disabled
545 04:22:24.274075 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 04:22:24.281765 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 04:22:24.287539 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 04:22:24.298910 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 04:22:24.302848 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 04:22:24.318960 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 04:22:24.335858 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 04:22:24.341699 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 04:22:24.435195 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 04:22:24.446662 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 04:22:24.453450 <6>[ 0.008334] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 04:22:24.466533 <6>[ 0.019164] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 04:22:24.473856 <6>[ 0.033985] Console: colour dummy device 80x30
558 04:22:24.480115 Matched prompt #6: WARNING:
559 04:22:24.480619 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 04:22:24.485403 <3>[ 0.038884] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 04:22:24.491166 <3>[ 0.045953] This ensures that you still see kernel messages. Please
562 04:22:24.494369 <3>[ 0.052678] update your kernel commandline.
563 04:22:24.535175 <6>[ 0.057288] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 04:22:24.540821 <6>[ 0.096171] CPU: Testing write buffer coherency: ok
565 04:22:24.546693 <6>[ 0.101537] CPU0: Spectre v2: using BPIALL workaround
566 04:22:24.547132 <6>[ 0.107002] pid_max: default: 32768 minimum: 301
567 04:22:24.558140 <6>[ 0.112188] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 04:22:24.564980 <6>[ 0.120007] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 04:22:24.571969 <6>[ 0.129296] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 04:22:24.580370 <6>[ 0.136129] Setting up static identity map for 0x80300000 - 0x803000ac
571 04:22:24.586196 <6>[ 0.145720] rcu: Hierarchical SRCU implementation.
572 04:22:24.592815 <6>[ 0.151002] rcu: Max phase no-delay instances is 1000.
573 04:22:24.602161 <6>[ 0.162062] EFI services will not be available.
574 04:22:24.608035 <6>[ 0.167305] smp: Bringing up secondary CPUs ...
575 04:22:24.613796 <6>[ 0.172341] smp: Brought up 1 node, 1 CPU
576 04:22:24.619503 <6>[ 0.176743] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 04:22:24.625415 <6>[ 0.183492] CPU: All CPU(s) started in SVC mode.
578 04:22:24.645736 <6>[ 0.188672] Memory: 407008K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48028K reserved, 65536K cma-reserved, 0K highmem)
579 04:22:24.646195 <6>[ 0.204902] devtmpfs: initialized
580 04:22:24.667548 <6>[ 0.221614] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 04:22:24.675813 <6>[ 0.230179] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 04:22:24.685012 <6>[ 0.240616] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 04:22:24.695777 <6>[ 0.252940] pinctrl core: initialized pinctrl subsystem
584 04:22:24.705170 <6>[ 0.263662] DMI not present or invalid.
585 04:22:24.712058 <6>[ 0.269483] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 04:22:24.722830 <6>[ 0.278329] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 04:22:24.737775 <6>[ 0.289726] thermal_sys: Registered thermal governor 'step_wise'
588 04:22:24.738226 <6>[ 0.289864] cpuidle: using governor menu
589 04:22:24.764962 <6>[ 0.325115] No ATAGs?
590 04:22:24.771280 <6>[ 0.327758] hw-breakpoint: debug architecture 0x4 unsupported.
591 04:22:24.781430 <6>[ 0.339774] Serial: AMBA PL011 UART driver
592 04:22:24.822721 <6>[ 0.382828] iommu: Default domain type: Translated
593 04:22:24.831740 <6>[ 0.388057] iommu: DMA domain TLB invalidation policy: strict mode
594 04:22:24.841998 <5>[ 0.400752] SCSI subsystem initialized
595 04:22:24.866010 <6>[ 0.420474] usbcore: registered new interface driver usbfs
596 04:22:24.872916 <6>[ 0.426427] usbcore: registered new interface driver hub
597 04:22:24.873232 <6>[ 0.432249] usbcore: registered new device driver usb
598 04:22:24.878838 <6>[ 0.438745] pps_core: LinuxPPS API ver. 1 registered
599 04:22:24.890401 <6>[ 0.444175] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 04:22:24.895426 <6>[ 0.453875] PTP clock support registered
601 04:22:24.920537 <6>[ 0.479609] EDAC MC: Ver: 3.0.0
602 04:22:24.939496 <6>[ 0.496792] scmi_core: SCMI protocol bus registered
603 04:22:24.954468 <6>[ 0.514077] vgaarb: loaded
604 04:22:24.966995 <6>[ 0.527010] clocksource: Switched to clocksource dmtimer
605 04:22:25.003228 <6>[ 0.562893] NET: Registered PF_INET protocol family
606 04:22:25.015741 <6>[ 0.568557] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 04:22:25.021569 <6>[ 0.577391] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 04:22:25.032973 <6>[ 0.586283] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 04:22:25.038835 <6>[ 0.594556] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 04:22:25.050331 <6>[ 0.602844] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 04:22:25.056260 <6>[ 0.610560] TCP: Hash tables configured (established 4096 bind 4096)
612 04:22:25.062006 <6>[ 0.617482] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 04:22:25.067899 <6>[ 0.624492] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 04:22:25.075455 <6>[ 0.632102] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 04:22:25.121334 <6>[ 0.675624] RPC: Registered named UNIX socket transport module.
616 04:22:25.121918 <6>[ 0.682061] RPC: Registered udp transport module.
617 04:22:25.127086 <6>[ 0.687192] RPC: Registered tcp transport module.
618 04:22:25.132860 <6>[ 0.692297] RPC: Registered tcp-with-tls transport module.
619 04:22:25.145794 <6>[ 0.698221] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 04:22:25.146359 <6>[ 0.705127] PCI: CLS 0 bytes, default 64
621 04:22:25.152395 <5>[ 0.710911] Initialise system trusted keyrings
622 04:22:25.158695 <6>[ 0.716552] Trying to unpack rootfs image as initramfs...
623 04:22:25.214081 <6>[ 0.767887] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 04:22:25.217959 <6>[ 0.775366] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 04:22:25.257724 <5>[ 0.817661] NFS: Registering the id_resolver key type
626 04:22:25.263473 <5>[ 0.823250] Key type id_resolver registered
627 04:22:25.269297 <5>[ 0.827885] Key type id_legacy registered
628 04:22:25.277655 <6>[ 0.832320] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 04:22:25.284680 <6>[ 0.839548] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 04:22:25.330597 <5>[ 0.890525] Key type asymmetric registered
631 04:22:25.336464 <5>[ 0.895046] Asymmetric key parser 'x509' registered
632 04:22:25.347857 <6>[ 0.900540] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 04:22:25.348461 <6>[ 0.908465] io scheduler mq-deadline registered
634 04:22:25.353742 <6>[ 0.913395] io scheduler kyber registered
635 04:22:25.359312 <6>[ 0.917865] io scheduler bfq registered
636 04:22:25.701946 <6>[ 1.258062] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 04:22:25.741546 <6>[ 1.301345] msm_serial: driver initialized
638 04:22:25.747694 <6>[ 1.306117] SuperH (H)SCI(F) driver initialized
639 04:22:25.754352 <6>[ 1.311456] STMicroelectronics ASC driver initialized
640 04:22:25.758890 <6>[ 1.317136] STM32 USART driver initialized
641 04:22:25.842896 <6>[ 1.402807] brd: module loaded
642 04:22:25.880763 <6>[ 1.439950] loop: module loaded
643 04:22:25.935341 <6>[ 1.494363] CAN device driver interface
644 04:22:25.941747 <6>[ 1.499586] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 04:22:25.947543 <6>[ 1.506468] e1000e: Intel(R) PRO/1000 Network Driver
646 04:22:25.954387 <6>[ 1.511918] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 04:22:25.960122 <6>[ 1.518351] igb: Intel(R) Gigabit Ethernet Network Driver
648 04:22:25.966321 <6>[ 1.524170] igb: Copyright (c) 2007-2014 Intel Corporation.
649 04:22:25.978923 <6>[ 1.533266] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 04:22:25.984784 <6>[ 1.539418] usbcore: registered new interface driver pegasus
651 04:22:25.987413 <6>[ 1.545543] usbcore: registered new interface driver asix
652 04:22:25.993192 <6>[ 1.551425] usbcore: registered new interface driver ax88179_178a
653 04:22:25.999018 <6>[ 1.558010] usbcore: registered new interface driver cdc_ether
654 04:22:26.004782 <6>[ 1.564308] usbcore: registered new interface driver smsc75xx
655 04:22:26.016260 <6>[ 1.570565] usbcore: registered new interface driver smsc95xx
656 04:22:26.022054 <6>[ 1.576773] usbcore: registered new interface driver net1080
657 04:22:26.027787 <6>[ 1.582916] usbcore: registered new interface driver cdc_subset
658 04:22:26.033713 <6>[ 1.589321] usbcore: registered new interface driver zaurus
659 04:22:26.038537 <6>[ 1.595392] usbcore: registered new interface driver cdc_ncm
660 04:22:26.048279 <6>[ 1.604746] usbcore: registered new interface driver usb-storage
661 04:22:26.151289 <6>[ 1.709462] i2c_dev: i2c /dev entries driver
662 04:22:26.206740 <5>[ 1.763349] cpuidle: enable-method property 'ti,am3352' found operations
663 04:22:26.220137 <6>[ 1.772901] sdhci: Secure Digital Host Controller Interface driver
664 04:22:26.220507 <6>[ 1.779667] sdhci: Copyright(c) Pierre Ossman
665 04:22:26.227459 <6>[ 1.785977] Synopsys Designware Multimedia Card Interface Driver
666 04:22:26.237011 <6>[ 1.793859] sdhci-pltfm: SDHCI platform and OF driver helper
667 04:22:26.291524 <6>[ 1.847813] ledtrig-cpu: registered to indicate activity on CPUs
668 04:22:26.329027 <6>[ 1.881570] usbcore: registered new interface driver usbhid
669 04:22:26.329561 <6>[ 1.887767] usbhid: USB HID core driver
670 04:22:26.375679 <6>[ 1.933449] NET: Registered PF_INET6 protocol family
671 04:22:26.431721 <6>[ 1.991684] Segment Routing with IPv6
672 04:22:26.437588 <6>[ 1.995824] In-situ OAM (IOAM) with IPv6
673 04:22:26.444606 <6>[ 2.000267] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 04:22:26.449934 <6>[ 2.007574] NET: Registered PF_PACKET protocol family
675 04:22:26.455817 <6>[ 2.013062] can: controller area network core
676 04:22:26.461572 <6>[ 2.017934] NET: Registered PF_CAN protocol family
677 04:22:26.462125 <6>[ 2.023132] can: raw protocol
678 04:22:26.467344 <6>[ 2.026454] can: broadcast manager protocol
679 04:22:26.473779 <6>[ 2.031056] can: netlink gateway - max_hops=1
680 04:22:26.479918 <5>[ 2.036534] Key type dns_resolver registered
681 04:22:26.486160 <6>[ 2.041600] ThumbEE CPU extension supported.
682 04:22:26.486715 <5>[ 2.046286] Registering SWP/SWPB emulation handler
683 04:22:26.495867 <3>[ 2.051982] omap_voltage_late_init: Voltage driver support not added
684 04:22:26.580143 <5>[ 2.137640] Loading compiled-in X.509 certificates
685 04:22:26.718434 <6>[ 2.265558] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 04:22:26.725706 <6>[ 2.282203] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 04:22:26.751817 <3>[ 2.305789] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 04:22:26.842284 <3>[ 2.396297] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 04:22:26.929897 <6>[ 2.488122] OMAP GPIO hardware version 0.1
690 04:22:26.950321 <6>[ 2.506633] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 04:22:27.011925 <4>[ 2.567988] at24 2-0054: supply vcc not found, using dummy regulator
692 04:22:27.070724 <4>[ 2.626782] at24 2-0055: supply vcc not found, using dummy regulator
693 04:22:27.118135 <4>[ 2.674624] at24 2-0056: supply vcc not found, using dummy regulator
694 04:22:27.155210 <4>[ 2.711303] at24 2-0057: supply vcc not found, using dummy regulator
695 04:22:27.203370 <6>[ 2.760229] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 04:22:27.280285 <3>[ 2.833074] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 04:22:27.304726 <6>[ 2.853838] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 04:22:27.325452 <4>[ 2.880291] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 04:22:27.363036 <4>[ 2.917893] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 04:22:27.421350 <6>[ 2.977631] omap_rng 48310000.rng: Random Number Generator ver. 20
701 04:22:27.444943 <5>[ 3.004020] random: crng init done
702 04:22:27.546235 <6>[ 3.100996] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 04:22:28.223504 <6>[ 3.781865] Freeing initrd memory: 14452K
704 04:22:28.265792 <6>[ 3.819472] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 04:22:28.271126 <6>[ 3.829676] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
706 04:22:28.283324 <6>[ 3.836943] cpsw-switch 4a100000.switch: ALE Table size 1024
707 04:22:28.289177 <6>[ 3.843401] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
708 04:22:28.300349 <6>[ 3.851538] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
709 04:22:28.307750 <6>[ 3.863170] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
710 04:22:28.320116 <5>[ 3.872206] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
711 04:22:28.348138 <3>[ 3.901865] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
712 04:22:28.353234 <6>[ 3.910437] edma 49000000.dma: TI EDMA DMA engine driver
713 04:22:28.423859 <3>[ 3.977610] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
714 04:22:28.436581 <6>[ 3.991857] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
715 04:22:28.456106 <3>[ 4.013695] l3-aon-clkctrl:0000:0: failed to disable
716 04:22:28.493778 <6>[ 4.048137] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
717 04:22:28.499410 <6>[ 4.057588] printk: legacy console [ttyS0] enabled
718 04:22:28.504953 <6>[ 4.057588] printk: legacy console [ttyS0] enabled
719 04:22:28.510788 <6>[ 4.067910] printk: legacy bootconsole [omap8250] disabled
720 04:22:28.516670 <6>[ 4.067910] printk: legacy bootconsole [omap8250] disabled
721 04:22:28.574303 <4>[ 4.127721] tps65217-pmic: Failed to locate of_node [id: -1]
722 04:22:28.577843 <4>[ 4.135088] tps65217-bl: Failed to locate of_node [id: -1]
723 04:22:28.593860 <6>[ 4.154281] tps65217 0-0024: TPS65217 ID 0xe version 1.2
724 04:22:28.612304 <6>[ 4.161218] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
725 04:22:28.623879 <6>[ 4.174901] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
726 04:22:28.629629 <6>[ 4.186745] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
727 04:22:28.652035 <6>[ 4.206675] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
728 04:22:28.657895 <6>[ 4.215915] sdhci-omap 48060000.mmc: Got CD GPIO
729 04:22:28.665999 <4>[ 4.221082] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
730 04:22:28.680599 <4>[ 4.234346] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
731 04:22:28.687132 <4>[ 4.243295] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
732 04:22:28.696933 <4>[ 4.252092] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
733 04:22:28.819648 <6>[ 4.375449] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
734 04:22:28.845240 <6>[ 4.400138] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 04:22:28.870478 <6>[ 4.424482] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
736 04:22:28.877323 <6>[ 4.433415] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
737 04:22:28.923025 <6>[ 4.474183] mmc1: new high speed MMC card at address 0001
738 04:22:28.923632 <6>[ 4.482058] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
739 04:22:28.928436 <6>[ 4.488253] mmc0: new high speed SDHC card at address 1234
740 04:22:28.937750 <6>[ 4.496053] mmcblk0: mmc0:1234 SA32G 29.1 GiB
741 04:22:28.947064 <6>[ 4.505746] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
742 04:22:28.955797 <6>[ 4.513562] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
743 04:22:28.963212 <6>[ 4.522452] mmcblk0: p1
744 04:22:28.969124 <6>[ 4.526445] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 04:22:28.985875 <6>[ 4.538183] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
746 04:22:31.053517 <6>[ 6.607978] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
747 04:22:37.896819 <5>[ 6.647008] Sending DHCP requests ..., OK
748 04:22:37.908064 <6>[ 13.461612] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.30
749 04:22:37.908636 <6>[ 13.469771] IP-Config: Complete:
750 04:22:37.919247 <6>[ 13.473308] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.30, mask=255.255.255.0, gw=192.168.6.1
751 04:22:37.924942 <6>[ 13.483820] host=192.168.6.30, domain=, nis-domain=(none)
752 04:22:37.937073 <6>[ 13.490027] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
753 04:22:37.937570 <6>[ 13.490060] nameserver0=10.255.253.1
754 04:22:37.943191 <6>[ 13.502582] clk: Disabling unused clocks
755 04:22:37.949312 <6>[ 13.507295] PM: genpd: Disabling unused power domains
756 04:22:37.968839 <6>[ 13.526022] Freeing unused kernel image (initmem) memory: 2048K
757 04:22:37.976192 <6>[ 13.535677] Run /init as init process
758 04:22:38.001497 Loading, please wait...
759 04:22:38.074916 Starting systemd-udevd version 252.22-1~deb12u1
760 04:22:41.276352 <4>[ 16.829944] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 04:22:41.414352 <4>[ 16.968006] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
762 04:22:41.580245 <6>[ 17.141322] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
763 04:22:41.590477 <6>[ 17.147127] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
764 04:22:41.696010 <6>[ 17.256004] hub 1-0:1.0: USB hub found
765 04:22:41.731320 <6>[ 17.291256] tda998x 0-0070: found TDA19988
766 04:22:41.756419 <6>[ 17.315925] hub 1-0:1.0: 1 port detected
767 04:22:44.608369 Begin: Loading essential drivers ... done.
768 04:22:44.614093 Begin: Running /scripts/init-premount ... done.
769 04:22:44.619522 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
770 04:22:44.629893 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
771 04:22:44.640814 Device /sys/class/net/eth0 found
772 04:22:44.641324 done.
773 04:22:44.716540 Begin: Waiting up to 180 secs for any network device to become available ... done.
774 04:22:44.789165 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
775 04:22:44.811241 IP-Config: eth0 guessed broadcast address 192.168.6.255
776 04:22:44.816863 IP-Config: eth0 complete (dhcp from 192.168.6.1):
777 04:22:44.822420 address: 192.168.6.30 broadcast: 192.168.6.255 netmask: 255.255.255.0
778 04:22:44.831262 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
779 04:22:44.837221 rootserver: 192.168.6.1 rootpath:
780 04:22:44.837728 filename :
781 04:22:44.904887 done.
782 04:22:44.918000 Begin: Running /scripts/nfs-bottom ... done.
783 04:22:44.987544 Begin: Running /scripts/init-bottom ... done.
784 04:22:46.310038 <30>[ 21.866772] systemd[1]: System time before build time, advancing clock.
785 04:22:46.545845 <30>[ 22.076427] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
786 04:22:46.554486 <30>[ 22.113056] systemd[1]: Detected architecture arm.
787 04:22:46.566431
788 04:22:46.566948 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
789 04:22:46.567415
790 04:22:46.599911 <30>[ 22.157312] systemd[1]: Hostname set to <debian-bookworm-armhf>.
791 04:22:48.800028 <30>[ 24.356394] systemd[1]: Queued start job for default target graphical.target.
792 04:22:48.817145 <30>[ 24.371436] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
793 04:22:48.824726 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
794 04:22:48.856381 <30>[ 24.409827] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
795 04:22:48.863781 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
796 04:22:48.898801 <30>[ 24.452795] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
797 04:22:48.906397 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
798 04:22:48.943709 <30>[ 24.498838] systemd[1]: Created slice user.slice - User and Session Slice.
799 04:22:48.949763 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
800 04:22:48.986516 <30>[ 24.539277] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
801 04:22:48.999054 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
802 04:22:49.033482 <30>[ 24.588229] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
803 04:22:49.043617 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
804 04:22:49.084246 <30>[ 24.628042] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
805 04:22:49.090661 <30>[ 24.648573] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
806 04:22:49.098864 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
807 04:22:49.132435 <30>[ 24.687455] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
808 04:22:49.139643 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
809 04:22:49.173838 <30>[ 24.728505] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
810 04:22:49.185922 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
811 04:22:49.223112 <30>[ 24.778088] systemd[1]: Reached target paths.target - Path Units.
812 04:22:49.227936 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
813 04:22:49.262691 <30>[ 24.817609] systemd[1]: Reached target remote-fs.target - Remote File Systems.
814 04:22:49.269113 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
815 04:22:49.304010 <30>[ 24.858469] systemd[1]: Reached target slices.target - Slice Units.
816 04:22:49.309573 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
817 04:22:49.342805 <30>[ 24.897766] systemd[1]: Reached target swap.target - Swaps.
818 04:22:49.346705 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
819 04:22:49.383351 <30>[ 24.938942] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
820 04:22:49.395025 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
821 04:22:49.434445 <30>[ 24.988286] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
822 04:22:49.441819 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
823 04:22:49.545229 <30>[ 25.095874] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
824 04:22:49.558481 <30>[ 25.113246] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
825 04:22:49.566823 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
826 04:22:49.604130 <30>[ 25.161023] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
827 04:22:49.617075 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
828 04:22:49.656380 <30>[ 25.210696] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
829 04:22:49.664771 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
830 04:22:49.701927 <30>[ 25.258015] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
831 04:22:49.713368 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
832 04:22:49.744286 <30>[ 25.298558] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
833 04:22:49.751861 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
834 04:22:49.791555 <30>[ 25.340510] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
835 04:22:49.812150 <30>[ 25.361074] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
836 04:22:49.859283 <30>[ 25.415302] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
837 04:22:49.868679 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
838 04:22:49.933213 <30>[ 25.488936] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
839 04:22:49.950486 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
840 04:22:50.023047 <30>[ 25.578128] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
841 04:22:50.040658 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
842 04:22:50.115940 <30>[ 25.671783] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
843 04:22:50.132041 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
844 04:22:50.181799 <30>[ 25.738192] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
845 04:22:50.200274 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
846 04:22:50.275273 <30>[ 25.831246] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
847 04:22:50.310547 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
848 04:22:50.376458 <30>[ 25.931450] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
849 04:22:50.409119 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
850 04:22:50.484404 <30>[ 26.040828] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
851 04:22:50.512760 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
852 04:22:50.572990 <30>[ 26.128714] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
853 04:22:50.589392 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
854 04:22:50.630615 <28>[ 26.179334] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
855 04:22:50.637202 <28>[ 26.192940] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
856 04:22:50.677156 <30>[ 26.233690] systemd[1]: Starting systemd-journald.service - Journal Service...
857 04:22:50.701140 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
858 04:22:50.781889 <30>[ 26.338293] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
859 04:22:50.806994 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
860 04:22:50.872642 <30>[ 26.428515] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
861 04:22:50.913201 Starting [0;1;39msystemd-network-g… units from Kernel command line...
862 04:22:50.993253 <30>[ 26.548533] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
863 04:22:51.031281 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
864 04:22:51.106079 <30>[ 26.661393] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
865 04:22:51.150953 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
866 04:22:51.180029 <30>[ 26.736683] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
867 04:22:51.234392 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
868 04:22:51.253474 <30>[ 26.809868] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
869 04:22:51.294828 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
870 04:22:51.324989 <30>[ 26.879971] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
871 04:22:51.359887 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
872 04:22:51.513086 <30>[ 27.068130] systemd[1]: Started systemd-journald.service - Journal Service.
873 04:22:51.520040 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
874 04:22:51.553281 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
875 04:22:51.587073 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
876 04:22:51.607183 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
877 04:22:51.652899 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
878 04:22:51.687864 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
879 04:22:51.727632 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
880 04:22:51.772389 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
881 04:22:51.804123 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
882 04:22:51.851724 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
883 04:22:51.885943 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
884 04:22:51.964491 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
885 04:22:52.018735 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
886 04:22:52.063191 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
887 04:22:52.174547 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
888 04:22:52.231047 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
889 04:22:52.396386 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
890 04:22:52.441096 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice<46>[ 27.992211] systemd-journald[164]: Received client request to flush runtime journal.
891 04:22:52.441866 [0m - Load/Save Random Seed.
892 04:22:52.601433 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
893 04:22:53.403674 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
894 04:22:53.512013 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
895 04:22:54.206118 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
896 04:22:54.374119 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
897 04:22:54.411548 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
898 04:22:54.441129 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
899 04:22:54.501528 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
900 04:22:54.534151 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
901 04:22:55.501705 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
902 04:22:55.609173 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
903 04:22:55.712384 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
904 04:22:55.813944 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
905 04:22:55.880707 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
906 04:22:57.678891 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
907 04:22:57.816665 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
908 04:22:59.023448 <5>[ 34.579955] cfg80211: Loading compiled-in X.509 certificates for regulatory database
909 04:22:59.091852 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
910 04:23:00.322766 <46>[ 35.870246] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
911 04:23:00.470929 <5>[ 36.029632] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
912 04:23:00.507680 <46>[ 36.057281] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
913 04:23:00.554618 <5>[ 36.109217] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
914 04:23:00.565861 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - N<4>[ 36.121018] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
915 04:23:00.571439 etwork Time Synchronization.
916 04:23:00.576367 <6>[ 36.133385] cfg80211: failed to load regulatory.db
917 04:23:02.666238 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
918 04:23:09.463189 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
919 04:23:09.507137 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
920 04:23:09.542334 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
921 04:23:09.578635 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
922 04:23:09.657557 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
923 04:23:09.736450 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
924 04:23:09.780498 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
925 04:23:09.812127 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
926 04:23:09.861370 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
927 04:23:09.897842 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
928 04:23:09.946986 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
929 04:23:09.989361 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
930 04:23:10.068948 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
931 04:23:10.118957 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
932 04:23:10.157357 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
933 04:23:10.196474 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
934 04:23:10.241354 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
935 04:23:10.286612 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
936 04:23:10.323640 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
937 04:23:10.352458 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
938 04:23:10.385098 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
939 04:23:10.397245 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
940 04:23:10.431134 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
941 04:23:10.515355 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
942 04:23:10.547182 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
943 04:23:10.619107 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
944 04:23:10.721456 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
945 04:23:10.813276 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
946 04:23:10.860869 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
947 04:23:10.896181 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
948 04:23:11.045696 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
949 04:23:11.132481 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
950 04:23:11.204085 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
951 04:23:11.232227 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
952 04:23:11.263771 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
953 04:23:11.512282 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
954 04:23:11.777418 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
955 04:23:11.841773 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
956 04:23:11.888676 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
957 04:23:11.977262 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
958 04:23:12.170351 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
959 04:23:12.328292
960 04:23:12.328874 Debian GNU/Linux 1worm-armhf login: root (automatic login)
961 04:23:12.332685
962 04:23:12.637699 Linux debian-bookworm-armhf 6.11.0-rc6 #1 SMP Mon Sep 2 03:48:51 UTC 2024 armv7l
963 04:23:12.638299
964 04:23:12.643430 The programs included with the Debian GNU/Linux system are free software;
965 04:23:12.649116 the exact distribution terms for each program are described in the
966 04:23:12.654606 individual files in /usr/share/doc/*/copyright.
967 04:23:12.655148
968 04:23:12.661636 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
969 04:23:12.662183 permitted by applicable law.
970 04:23:17.377855 Unable to match end of the kernel message
972 04:23:17.379613 Setting prompt string to ['/ #']
973 04:23:17.380310 end: 2.4.4.1 login-action (duration 00:00:53) [common]
975 04:23:17.381825 end: 2.4.4 auto-login-action (duration 00:00:54) [common]
976 04:23:17.382402 start: 2.4.5 expect-shell-connection (timeout 00:03:08) [common]
977 04:23:17.382891 Setting prompt string to ['/ #']
978 04:23:17.383361 Forcing a shell prompt, looking for ['/ #']
980 04:23:17.434508 / #
981 04:23:17.435285 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
982 04:23:17.435837 Waiting using forced prompt support (timeout 00:02:30)
983 04:23:17.439902
984 04:23:17.448893 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
985 04:23:17.449552 start: 2.4.6 export-device-env (timeout 00:03:08) [common]
986 04:23:17.450062 Sending with 10 millisecond of delay
988 04:23:22.440088 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9'
989 04:23:22.451193 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/689530/extract-nfsrootfs-kdzm7ns9'
990 04:23:22.452553 Sending with 10 millisecond of delay
992 04:23:24.552362 / # export NFS_SERVER_IP='192.168.6.2'
993 04:23:24.563352 export NFS_SERVER_IP='192.168.6.2'
994 04:23:24.564407 end: 2.4.6 export-device-env (duration 00:00:07) [common]
995 04:23:24.565075 end: 2.4 uboot-commands (duration 00:01:59) [common]
996 04:23:24.565738 end: 2 uboot-action (duration 00:01:59) [common]
997 04:23:24.566373 start: 3 lava-test-retry (timeout 00:06:50) [common]
998 04:23:24.567007 start: 3.1 lava-test-shell (timeout 00:06:50) [common]
999 04:23:24.567521 Using namespace: common
1001 04:23:24.668943 / # #
1002 04:23:24.669752 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1003 04:23:24.674271 #
1004 04:23:24.680199 Using /lava-689530
1006 04:23:24.781555 / # export SHELL=/bin/bash
1007 04:23:24.786967 export SHELL=/bin/bash
1009 04:23:24.893957 / # . /lava-689530/environment
1010 04:23:24.899332 . /lava-689530/environment
1012 04:23:25.012257 / # /lava-689530/bin/lava-test-runner /lava-689530/0
1013 04:23:25.013072 Test shell timeout: 10s (minimum of the action and connection timeout)
1014 04:23:25.017705 /lava-689530/bin/lava-test-runner /lava-689530/0
1015 04:23:25.439448 + export TESTRUN_ID=0_timesync-off
1016 04:23:25.447242 + TESTRUN_ID=0_timesync-off
1017 04:23:25.447750 + cd /lava-689530/0/tests/0_timesync-off
1018 04:23:25.448246 ++ cat uuid
1019 04:23:25.463071 + UUID=689530_1.6.2.4.1
1020 04:23:25.463612 + set +x
1021 04:23:25.471534 <LAVA_SIGNAL_STARTRUN 0_timesync-off 689530_1.6.2.4.1>
1022 04:23:25.472056 + systemctl stop systemd-timesyncd
1023 04:23:25.472809 Received signal: <STARTRUN> 0_timesync-off 689530_1.6.2.4.1
1024 04:23:25.473296 Starting test lava.0_timesync-off (689530_1.6.2.4.1)
1025 04:23:25.473878 Skipping test definition patterns.
1026 04:23:25.775369 + set +x
1027 04:23:25.775826 <LAVA_SIGNAL_ENDRUN 0_timesync-off 689530_1.6.2.4.1>
1028 04:23:25.776581 Received signal: <ENDRUN> 0_timesync-off 689530_1.6.2.4.1
1029 04:23:25.777096 Ending use of test pattern.
1030 04:23:25.777507 Ending test lava.0_timesync-off (689530_1.6.2.4.1), duration 0.30
1032 04:23:25.970428 + export TESTRUN_ID=1_kselftest-dt
1033 04:23:25.978200 + TESTRUN_ID=1_kselftest-dt
1034 04:23:25.978715 + cd /lava-689530/0/tests/1_kselftest-dt
1035 04:23:25.979183 ++ cat uuid
1036 04:23:25.993303 + UUID=689530_1.6.2.4.5
1037 04:23:25.993816 + set +x
1038 04:23:25.998807 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 689530_1.6.2.4.5>
1039 04:23:25.999296 + cd ./automated/linux/kselftest/
1040 04:23:26.000072 Received signal: <STARTRUN> 1_kselftest-dt 689530_1.6.2.4.5
1041 04:23:26.000558 Starting test lava.1_kselftest-dt (689530_1.6.2.4.5)
1042 04:23:26.001099 Skipping test definition patterns.
1043 04:23:26.026952 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1044 04:23:26.137370 INFO: install_deps skipped
1045 04:23:26.771294 --2024-09-02 04:23:26-- http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1046 04:23:26.805369 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1047 04:23:26.946819 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1048 04:23:27.087545 HTTP request sent, awaiting response... 200 OK
1049 04:23:27.088228 Length: 3607880 (3.4M) [application/octet-stream]
1050 04:23:27.093289 Saving to: 'kselftest_armhf.tar.gz'
1051 04:23:27.093928
1052 04:23:28.419631
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 44.73K 163KB/s
kselftest_armhf.tar 5%[> ] 208.82K 378KB/s
kselftest_armhf.tar 20%[===> ] 727.29K 933KB/s
kselftest_armhf.tar 52%[=========> ] 1.81M 1.85MB/s
kselftest_armhf.tar 67%[============> ] 2.31M 1.95MB/s
kselftest_armhf.tar 100%[===================>] 3.44M 2.60MB/s in 1.3s
1053 04:23:28.420482
1054 04:23:28.986432 2024-09-02 04:23:28 (2.60 MB/s) - 'kselftest_armhf.tar.gz' saved [3607880/3607880]
1055 04:23:28.987102
1056 04:23:39.778440 skiplist:
1057 04:23:39.779127 ========================================
1058 04:23:39.784138 ========================================
1059 04:23:39.879448 dt:test_unprobed_devices.sh
1060 04:23:39.927027 ============== Tests to run ===============
1061 04:23:39.935452 dt:test_unprobed_devices.sh
1062 04:23:39.939336 ===========End Tests to run ===============
1063 04:23:39.948754 shardfile-dt pass
1064 04:23:40.178537 <12>[ 75.740462] kselftest: Running tests in dt
1065 04:23:40.207670 TAP version 13
1066 04:23:40.233130 1..1
1067 04:23:40.287915 # timeout set to 45
1068 04:23:40.288616 # selftests: dt: test_unprobed_devices.sh
1069 04:23:41.083238 # TAP version 13
1070 04:23:53.111468 # 1..255
1071 04:23:53.274034 # ok 1 / # SKIP
1072 04:23:53.294180 # ok 2 /clk_mcasp0
1073 04:23:53.367548 # ok 3 /clk_mcasp0_fixed # SKIP
1074 04:23:53.432235 # ok 4 /cpus/cpu@0 # SKIP
1075 04:23:53.500506 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1076 04:23:53.520152 # ok 6 /fixedregulator0
1077 04:23:53.543256 # ok 7 /leds
1078 04:23:53.561123 # ok 8 /ocp
1079 04:23:53.584091 # ok 9 /ocp/interconnect@44c00000
1080 04:23:53.611631 # ok 10 /ocp/interconnect@44c00000/segment@0
1081 04:23:53.634563 # ok 11 /ocp/interconnect@44c00000/segment@100000
1082 04:23:53.657523 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1083 04:23:53.724401 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1084 04:23:53.752075 # ok 14 /ocp/interconnect@44c00000/segment@200000
1085 04:23:53.773121 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1086 04:23:53.874289 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1087 04:23:53.945945 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1088 04:23:54.013358 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1089 04:23:54.085649 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1090 04:23:54.155441 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1091 04:23:54.221131 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1092 04:23:54.287747 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1093 04:23:54.363438 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1094 04:23:54.436069 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1095 04:23:54.497587 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1096 04:23:54.571300 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1097 04:23:54.641896 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1098 04:23:54.712770 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1099 04:23:54.781740 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1100 04:23:54.849650 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1101 04:23:54.921835 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1102 04:23:54.985710 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1103 04:23:55.061912 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1104 04:23:55.128734 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1105 04:23:55.200428 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1106 04:23:55.264221 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1107 04:23:55.341900 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1108 04:23:55.403890 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1109 04:23:55.479601 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1110 04:23:55.552751 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1111 04:23:55.619943 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1112 04:23:55.690991 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1113 04:23:55.767301 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1114 04:23:55.830334 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1115 04:23:55.907947 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1116 04:23:55.971161 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1117 04:23:56.049146 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1118 04:23:56.112133 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1119 04:23:56.193047 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1120 04:23:56.257218 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1121 04:23:56.333068 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1122 04:23:56.403199 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1123 04:23:56.478999 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1124 04:23:56.543439 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1125 04:23:56.619368 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1126 04:23:56.687605 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1127 04:23:56.759905 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1128 04:23:56.826648 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1129 04:23:56.898826 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1130 04:23:56.967580 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1131 04:23:57.041510 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1132 04:23:57.104237 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1133 04:23:57.179810 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1134 04:23:57.249848 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1135 04:23:57.321229 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1136 04:23:57.392279 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1137 04:23:57.463390 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1138 04:23:57.530706 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1139 04:23:57.599391 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1140 04:23:57.669327 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1141 04:23:57.746683 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1142 04:23:57.808847 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1143 04:23:57.880322 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1144 04:23:57.957543 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1145 04:23:58.024656 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1146 04:23:58.094925 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1147 04:23:58.167336 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1148 04:23:58.236365 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1149 04:23:58.319284 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1150 04:23:58.378869 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1151 04:23:58.447426 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1152 04:23:58.520752 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1153 04:23:58.590811 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1154 04:23:58.658097 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1155 04:23:58.728711 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1156 04:23:58.800394 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1157 04:23:58.870557 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1158 04:23:58.941724 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1159 04:23:59.013324 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1160 04:23:59.081302 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1161 04:23:59.151353 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1162 04:23:59.226937 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1163 04:23:59.295476 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1164 04:23:59.368992 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1165 04:23:59.388649 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1166 04:23:59.405124 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1167 04:23:59.433758 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1168 04:23:59.459242 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1169 04:23:59.480213 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1170 04:23:59.505612 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1171 04:23:59.527811 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1172 04:23:59.554558 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1173 04:23:59.652021 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1174 04:23:59.672587 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1175 04:23:59.704793 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1176 04:23:59.727542 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1177 04:23:59.826067 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1178 04:23:59.901279 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1179 04:23:59.969805 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1180 04:24:00.041583 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1181 04:24:00.110482 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1182 04:24:00.181314 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1183 04:24:00.251344 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1184 04:24:00.319592 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1185 04:24:00.385486 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1186 04:24:00.464251 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1187 04:24:00.534385 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1188 04:24:00.601708 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1189 04:24:00.676687 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1190 04:24:00.745748 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1191 04:24:00.820480 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1192 04:24:00.890147 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1193 04:24:00.910687 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1194 04:24:00.974572 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1195 04:24:01.046900 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1196 04:24:01.116039 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1197 04:24:01.132709 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1198 04:24:01.208132 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1199 04:24:01.226514 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1200 04:24:01.304502 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1201 04:24:01.325905 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1202 04:24:01.340956 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1203 04:24:01.367016 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1204 04:24:01.394191 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1205 04:24:01.418967 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1206 04:24:01.436963 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1207 04:24:01.467973 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1208 04:24:01.488036 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1209 04:24:01.511895 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1210 04:24:01.583801 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1211 04:24:01.655262 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1212 04:24:01.675542 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1213 04:24:01.744530 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1214 04:24:01.814400 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1215 04:24:01.911610 # not ok 145 /ocp/interconnect@47c00000
1216 04:24:01.978157 # not ok 146 /ocp/interconnect@47c00000/segment@0
1217 04:24:01.993039 # ok 147 /ocp/interconnect@48000000
1218 04:24:02.022813 # ok 148 /ocp/interconnect@48000000/segment@0
1219 04:24:02.045202 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1220 04:24:02.065118 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1221 04:24:02.095531 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1222 04:24:02.110253 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1223 04:24:02.133679 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1224 04:24:02.162174 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1225 04:24:02.184717 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1226 04:24:02.255726 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1227 04:24:02.326585 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1228 04:24:02.339975 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1229 04:24:02.366020 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1230 04:24:02.387035 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1231 04:24:02.417873 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1232 04:24:02.432227 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1233 04:24:02.456696 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1234 04:24:02.485188 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1235 04:24:02.505603 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1236 04:24:02.525992 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1237 04:24:02.553585 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1238 04:24:02.574260 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1239 04:24:02.596712 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1240 04:24:02.617268 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1241 04:24:02.645593 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1242 04:24:02.666227 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1243 04:24:02.685846 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1244 04:24:02.715863 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1245 04:24:02.737196 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1246 04:24:02.762553 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1247 04:24:02.783091 # ok 177 /ocp/interconnect@48000000/segment@100000
1248 04:24:02.808173 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1249 04:24:02.825629 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1250 04:24:02.903765 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1251 04:24:02.984077 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1252 04:24:03.055385 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1253 04:24:03.123854 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1254 04:24:03.144265 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1255 04:24:03.168505 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1256 04:24:03.185203 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1257 04:24:03.214548 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1258 04:24:03.231524 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1259 04:24:03.256945 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1260 04:24:03.282177 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1261 04:24:03.309313 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1262 04:24:03.329035 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1263 04:24:03.347100 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1264 04:24:03.375143 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1265 04:24:03.399025 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1266 04:24:03.418911 # ok 196 /ocp/interconnect@48000000/segment@200000
1267 04:24:03.441793 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1268 04:24:03.516184 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1269 04:24:03.536415 # ok 199 /ocp/interconnect@48000000/segment@300000
1270 04:24:03.552923 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1271 04:24:03.577555 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1272 04:24:03.604831 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1273 04:24:03.628973 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1274 04:24:03.648186 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1275 04:24:03.667127 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1276 04:24:03.738381 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1277 04:24:03.762787 # ok 207 /ocp/interconnect@4a000000
1278 04:24:03.779418 # ok 208 /ocp/interconnect@4a000000/segment@0
1279 04:24:03.807743 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1280 04:24:03.828735 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1281 04:24:03.852725 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1282 04:24:03.875115 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1283 04:24:03.946145 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1284 04:24:04.054752 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1285 04:24:04.122080 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1286 04:24:04.226100 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1287 04:24:04.299202 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1288 04:24:04.365497 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1289 04:24:04.460066 # not ok 219 /ocp/interconnect@4b140000
1290 04:24:04.523887 # not ok 220 /ocp/interconnect@4b140000/segment@0
1291 04:24:04.594563 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1292 04:24:04.613063 # ok 222 /ocp/target-module@40300000
1293 04:24:04.640831 # ok 223 /ocp/target-module@40300000/sram@0
1294 04:24:04.711595 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1295 04:24:04.780713 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1296 04:24:04.802005 # ok 226 /ocp/target-module@47400000
1297 04:24:04.823226 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1298 04:24:04.843690 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1299 04:24:04.863535 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1300 04:24:04.890461 # ok 230 /ocp/target-module@47400000/usb@1400
1301 04:24:04.911294 # ok 231 /ocp/target-module@47400000/usb@1800
1302 04:24:04.935153 # ok 232 /ocp/target-module@47810000
1303 04:24:04.948448 # ok 233 /ocp/target-module@49000000
1304 04:24:04.971721 # ok 234 /ocp/target-module@49000000/dma@0
1305 04:24:04.998397 # ok 235 /ocp/target-module@49800000
1306 04:24:05.019717 # ok 236 /ocp/target-module@49800000/dma@0
1307 04:24:05.040552 # ok 237 /ocp/target-module@49900000
1308 04:24:05.062549 # ok 238 /ocp/target-module@49900000/dma@0
1309 04:24:05.083448 # ok 239 /ocp/target-module@49a00000
1310 04:24:05.106079 # ok 240 /ocp/target-module@49a00000/dma@0
1311 04:24:05.123362 # ok 241 /ocp/target-module@4c000000
1312 04:24:05.191947 # not ok 242 /ocp/target-module@4c000000/emif@0
1313 04:24:05.216892 # ok 243 /ocp/target-module@50000000
1314 04:24:05.238622 # ok 244 /ocp/target-module@53100000
1315 04:24:05.303598 # not ok 245 /ocp/target-module@53100000/sham@0
1316 04:24:05.322211 # ok 246 /ocp/target-module@53500000
1317 04:24:05.393438 # not ok 247 /ocp/target-module@53500000/aes@0
1318 04:24:05.413369 # ok 248 /ocp/target-module@56000000
1319 04:24:05.518561 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1320 04:24:05.584716 # ok 250 /opp-table # SKIP
1321 04:24:05.651189 # ok 251 /soc # SKIP
1322 04:24:05.668890 # ok 252 /sound
1323 04:24:05.692890 # ok 253 /target-module@4b000000
1324 04:24:05.717420 # ok 254 /target-module@4b000000/target-module@140000
1325 04:24:05.737568 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1326 04:24:05.745502 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1327 04:24:05.751485 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1328 04:24:07.901967 dt_test_unprobed_devices_sh_ skip
1329 04:24:07.907370 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1330 04:24:07.912952 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1331 04:24:07.913405 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1332 04:24:07.918581 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1333 04:24:07.924174 dt_test_unprobed_devices_sh_fixedregulator0 pass
1334 04:24:07.929795 dt_test_unprobed_devices_sh_leds pass
1335 04:24:07.930256 dt_test_unprobed_devices_sh_ocp pass
1336 04:24:07.935415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1337 04:24:07.941100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1338 04:24:07.946678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1339 04:24:07.957996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1340 04:24:07.963631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1341 04:24:07.969130 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1342 04:24:07.980374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1343 04:24:07.986027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1344 04:24:07.997230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1345 04:24:08.008408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1346 04:24:08.019582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1347 04:24:08.025200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1348 04:24:08.036438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1349 04:24:08.047696 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1350 04:24:08.058873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1351 04:24:08.070018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1352 04:24:08.075678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1353 04:24:08.087039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1354 04:24:08.098244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1355 04:24:08.109344 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1356 04:24:08.120714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1357 04:24:08.126272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1358 04:24:08.137312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1359 04:24:08.148517 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1360 04:24:08.159731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1361 04:24:08.165316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1362 04:24:08.176448 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1363 04:24:08.187737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1364 04:24:08.198832 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1365 04:24:08.210016 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1366 04:24:08.215624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1367 04:24:08.226948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1368 04:24:08.238041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1369 04:24:08.249202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1370 04:24:08.260422 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1371 04:24:08.271628 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1372 04:24:08.282867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1373 04:24:08.294111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1374 04:24:08.305233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1375 04:24:08.316400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1376 04:24:08.327688 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1377 04:24:08.338797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1378 04:24:08.349995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1379 04:24:08.361310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1380 04:24:08.372378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1381 04:24:08.383528 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1382 04:24:08.394735 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1383 04:24:08.405901 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1384 04:24:08.417140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1385 04:24:08.428367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1386 04:24:08.439533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1387 04:24:08.450662 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1388 04:24:08.461879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1389 04:24:08.473026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1390 04:24:08.484222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1391 04:24:08.495447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1392 04:24:08.501051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1393 04:24:08.512245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1394 04:24:08.523430 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1395 04:24:08.534584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1396 04:24:08.545807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1397 04:24:08.556965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1398 04:24:08.568271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1399 04:24:08.579360 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1400 04:24:08.590570 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1401 04:24:08.601766 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1402 04:24:08.612967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1403 04:24:08.624351 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1404 04:24:08.635366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1405 04:24:08.646538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1406 04:24:08.657706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1407 04:24:08.668916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1408 04:24:08.680167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1409 04:24:08.691319 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1410 04:24:08.696923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1411 04:24:08.708079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1412 04:24:08.719314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1413 04:24:08.730544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1414 04:24:08.741669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1415 04:24:08.747318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1416 04:24:08.764053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1417 04:24:08.775294 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1418 04:24:08.780789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1419 04:24:08.797571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1420 04:24:08.808754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1421 04:24:08.819944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1422 04:24:08.825553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1423 04:24:08.836728 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1424 04:24:08.847824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1425 04:24:08.853458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1426 04:24:08.864611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1427 04:24:08.875976 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1428 04:24:08.881429 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1429 04:24:08.892629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1430 04:24:08.898269 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1431 04:24:08.909418 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1432 04:24:08.920668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1433 04:24:08.931922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1434 04:24:08.943059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1435 04:24:08.954316 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1436 04:24:08.965447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1437 04:24:08.976666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1438 04:24:08.987813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1439 04:24:08.999053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1440 04:24:09.010368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1441 04:24:09.021415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1442 04:24:09.032762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1443 04:24:09.049414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1444 04:24:09.060595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1445 04:24:09.071777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1446 04:24:09.082973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1447 04:24:09.094217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1448 04:24:09.111624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1449 04:24:09.122213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1450 04:24:09.133434 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1451 04:24:09.144538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1452 04:24:09.150158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1453 04:24:09.161380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1454 04:24:09.172527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1455 04:24:09.178116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1456 04:24:09.189399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1457 04:24:09.194964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1458 04:24:09.206131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1459 04:24:09.501454 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1460 04:24:09.502713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1461 04:24:09.502963 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1462 04:24:09.503178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1463 04:24:09.503387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1464 04:24:09.503592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1465 04:24:09.503797 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1466 04:24:09.504061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1467 04:24:09.504276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1468 04:24:09.504480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1469 04:24:09.504762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1470 04:24:09.504973 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1471 04:24:09.505178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1472 04:24:09.505380 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1473 04:24:09.505580 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1474 04:24:09.505778 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1475 04:24:09.505976 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1476 04:24:09.506174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1477 04:24:09.506371 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1478 04:24:09.506569 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1479 04:24:09.506765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1480 04:24:09.506959 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1481 04:24:09.507154 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1482 04:24:09.507350 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1483 04:24:09.507647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1484 04:24:09.507872 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1485 04:24:09.508101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1486 04:24:09.508308 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1487 04:24:09.508576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1488 04:24:09.508786 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1489 04:24:09.509042 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1490 04:24:09.509246 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1491 04:24:09.509448 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1492 04:24:09.509647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1493 04:24:09.509845 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1494 04:24:09.510042 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1495 04:24:09.510236 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1496 04:24:09.519148 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1497 04:24:09.524777 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1498 04:24:09.536011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1499 04:24:09.541623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1500 04:24:09.547182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1501 04:24:09.558356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1502 04:24:09.563971 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1503 04:24:09.575115 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1504 04:24:09.580757 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1505 04:24:09.591903 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1506 04:24:09.597539 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1507 04:24:09.608730 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1508 04:24:09.620053 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1509 04:24:09.631157 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1510 04:24:09.642430 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1511 04:24:09.648089 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1512 04:24:09.653639 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1513 04:24:09.664769 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1514 04:24:09.670446 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1515 04:24:09.681556 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1516 04:24:09.692791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1517 04:24:09.698466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1518 04:24:09.709594 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1519 04:24:09.717428 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1520 04:24:09.726333 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1521 04:24:09.731960 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1522 04:24:09.743132 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1523 04:24:09.748789 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1524 04:24:09.754360 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1525 04:24:09.765662 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1526 04:24:09.771173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1527 04:24:09.776748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1528 04:24:09.787887 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1529 04:24:09.793541 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1530 04:24:09.804657 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1531 04:24:09.810279 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1532 04:24:09.821420 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1533 04:24:09.827129 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1534 04:24:09.832703 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1535 04:24:09.838363 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1536 04:24:09.849423 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1537 04:24:09.855069 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1538 04:24:09.866255 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1539 04:24:09.877580 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1540 04:24:09.883123 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1541 04:24:09.894214 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1542 04:24:09.905461 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1543 04:24:09.916574 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1544 04:24:09.922239 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1545 04:24:09.934347 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1546 04:24:09.941786 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1547 04:24:09.946956 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1548 04:24:09.951052 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1549 04:24:09.958082 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1550 04:24:09.963519 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1551 04:24:09.971290 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1552 04:24:09.978195 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1553 04:24:09.985631 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1554 04:24:09.989735 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1555 04:24:10.001161 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1556 04:24:10.001759 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1557 04:24:10.006284 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1558 04:24:10.014789 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1559 04:24:10.017390 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1560 04:24:10.023751 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1561 04:24:10.028594 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1562 04:24:10.034148 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1563 04:24:10.039836 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1564 04:24:10.045485 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1565 04:24:10.050992 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1566 04:24:10.056576 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1567 04:24:10.062178 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1568 04:24:10.067743 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1569 04:24:10.073403 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1570 04:24:10.078963 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1571 04:24:10.084556 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1572 04:24:10.090124 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1573 04:24:10.095732 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1574 04:24:10.101329 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1575 04:24:10.106920 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1576 04:24:10.112556 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1577 04:24:10.118132 dt_test_unprobed_devices_sh_opp-table skip
1578 04:24:10.123784 dt_test_unprobed_devices_sh_soc skip
1579 04:24:10.124286 dt_test_unprobed_devices_sh_sound pass
1580 04:24:10.129344 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1581 04:24:10.134959 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1582 04:24:10.146115 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1583 04:24:10.146642 dt_test_unprobed_devices_sh fail
1584 04:24:10.151759 + ../../utils/send-to-lava.sh ./output/result.txt
1585 04:24:10.157350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1586 04:24:10.158270 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1588 04:24:10.164288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1589 04:24:10.165040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1591 04:24:10.251636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1592 04:24:10.252469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1594 04:24:10.333572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1595 04:24:10.334339 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1597 04:24:10.419960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1598 04:24:10.420830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1600 04:24:10.502026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1601 04:24:10.502830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1603 04:24:10.583289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1604 04:24:10.584097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1606 04:24:10.669599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1607 04:24:10.670440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1609 04:24:10.752093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1610 04:24:10.752901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1612 04:24:10.845971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1613 04:24:10.846765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1615 04:24:10.933962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1616 04:24:10.934793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1618 04:24:11.021230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1619 04:24:11.022043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1621 04:24:11.113452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1622 04:24:11.114290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1624 04:24:11.200264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1625 04:24:11.201088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1627 04:24:11.286338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1628 04:24:11.287170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1630 04:24:11.377518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1631 04:24:11.378332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1633 04:24:11.466052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1634 04:24:11.466881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1636 04:24:11.546593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1637 04:24:11.547421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1639 04:24:11.628262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1640 04:24:11.629080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1642 04:24:11.716625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1643 04:24:11.717456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1645 04:24:11.799654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1646 04:24:11.800527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1648 04:24:11.879468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1649 04:24:11.880302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1651 04:24:11.961945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1652 04:24:11.962791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1654 04:24:12.053621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1655 04:24:12.054439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1657 04:24:12.143376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1658 04:24:12.144175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1660 04:24:12.229225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1661 04:24:12.230071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1663 04:24:12.315529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1664 04:24:12.316420 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1666 04:24:12.398858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1667 04:24:12.399666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1669 04:24:12.480093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1670 04:24:12.480897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1672 04:24:12.560795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1673 04:24:12.561649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1675 04:24:12.647604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1676 04:24:12.648377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1678 04:24:12.728356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1679 04:24:12.729017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1681 04:24:12.814180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1682 04:24:12.814826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1684 04:24:12.894810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1685 04:24:12.895436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1687 04:24:12.975502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1688 04:24:12.976236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1690 04:24:13.057911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1691 04:24:13.058540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1693 04:24:13.144097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1694 04:24:13.144725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1696 04:24:13.225301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1697 04:24:13.225964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1699 04:24:13.307568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1700 04:24:13.308287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1702 04:24:13.421083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1703 04:24:13.421879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1705 04:24:13.512221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1706 04:24:13.512843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1708 04:24:13.600062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1709 04:24:13.600657 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1711 04:24:13.689438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1712 04:24:13.690032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1714 04:24:13.777313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1715 04:24:13.777904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1717 04:24:13.859100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1718 04:24:13.859688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1720 04:24:13.941168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1721 04:24:13.941779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1723 04:24:14.029518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1724 04:24:14.030203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1726 04:24:14.112290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1727 04:24:14.112936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1729 04:24:14.200155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1730 04:24:14.200772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1732 04:24:14.289015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1733 04:24:14.289630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1735 04:24:14.378860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1736 04:24:14.379482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1738 04:24:14.461479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1739 04:24:14.462102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1741 04:24:14.543476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1742 04:24:14.544077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1744 04:24:14.632873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1745 04:24:14.633468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1747 04:24:14.722022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1748 04:24:14.722647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1750 04:24:14.802793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1751 04:24:14.803418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1753 04:24:14.883790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1754 04:24:14.884404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1756 04:24:14.971316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1757 04:24:14.971878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1759 04:24:15.051949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1760 04:24:15.052543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1762 04:24:15.140555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1763 04:24:15.141192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1765 04:24:15.230273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1766 04:24:15.230913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1768 04:24:15.325844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1769 04:24:15.326466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1771 04:24:15.414520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1772 04:24:15.415133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1774 04:24:15.497704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1775 04:24:15.498303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1777 04:24:15.587308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1778 04:24:15.587882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1780 04:24:15.669620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1781 04:24:15.670222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1783 04:24:15.753787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1784 04:24:15.754344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1786 04:24:15.843248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1787 04:24:15.843857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1789 04:24:15.930866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1790 04:24:15.931464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1792 04:24:16.019909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1793 04:24:16.020627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1795 04:24:16.110114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1796 04:24:16.110798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1798 04:24:16.192563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1799 04:24:16.193200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1801 04:24:16.280522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1802 04:24:16.281155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1804 04:24:16.362766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1805 04:24:16.363409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1807 04:24:16.449466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1808 04:24:16.450096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1810 04:24:16.538412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1811 04:24:16.539034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1813 04:24:16.625751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1814 04:24:16.626330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1816 04:24:16.709415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1817 04:24:16.710011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1819 04:24:16.791436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1820 04:24:16.792049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1822 04:24:16.878427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1823 04:24:16.879016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1825 04:24:16.960733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1826 04:24:16.961413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1828 04:24:17.042200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1829 04:24:17.042785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1831 04:24:17.131758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1832 04:24:17.132342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1834 04:24:17.218717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1835 04:24:17.219293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1837 04:24:17.305706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1838 04:24:17.306278 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1840 04:24:17.388510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1841 04:24:17.389091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1843 04:24:17.477040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1844 04:24:17.477587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1846 04:24:17.562532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1847 04:24:17.563274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1849 04:24:17.648348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1850 04:24:17.649010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1852 04:24:17.739166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1853 04:24:17.739833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1855 04:24:17.832588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1856 04:24:17.833266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1858 04:24:17.912177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1859 04:24:17.913094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1861 04:24:18.001674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1862 04:24:18.002508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1864 04:24:18.083018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1865 04:24:18.083840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1867 04:24:18.171814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1868 04:24:18.172752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1870 04:24:18.258160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1871 04:24:18.258994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1873 04:24:18.346459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1874 04:24:18.347337 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1876 04:24:18.430041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1877 04:24:18.430821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1879 04:24:18.521683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1881 04:24:18.524552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1882 04:24:18.612224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1883 04:24:18.613089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1885 04:24:18.699674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1886 04:24:18.700600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1888 04:24:18.782569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1889 04:24:18.783465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1891 04:24:18.869023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1892 04:24:18.869905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1894 04:24:18.952642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1895 04:24:18.953746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1897 04:24:19.042158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1898 04:24:19.043066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1900 04:24:19.131066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1901 04:24:19.131932 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1903 04:24:19.218079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1904 04:24:19.218905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1906 04:24:19.301327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1907 04:24:19.302141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1909 04:24:19.391159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1910 04:24:19.391974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1912 04:24:19.480359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1913 04:24:19.481153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1915 04:24:19.570204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1916 04:24:19.571007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1918 04:24:19.652897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1919 04:24:19.653685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1921 04:24:19.735462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1922 04:24:19.736285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1924 04:24:19.817700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1925 04:24:19.818513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1927 04:24:19.896665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1928 04:24:19.897446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1930 04:24:19.978449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1931 04:24:19.979323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1933 04:24:20.064261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1934 04:24:20.065095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1936 04:24:20.146660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1937 04:24:20.147488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1939 04:24:20.233407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1940 04:24:20.234258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1942 04:24:20.320010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1943 04:24:20.320840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1945 04:24:20.400041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1947 04:24:20.403106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1948 04:24:20.481963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1950 04:24:20.485012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1951 04:24:20.563605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1953 04:24:20.566644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1954 04:24:20.652355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1955 04:24:20.653143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1957 04:24:20.739396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1958 04:24:20.740224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1960 04:24:20.824387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1961 04:24:20.825155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1963 04:24:20.907477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1964 04:24:20.908358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1966 04:24:20.994280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1967 04:24:20.995114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1969 04:24:21.075400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1970 04:24:21.076203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1972 04:24:21.156530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1973 04:24:21.157366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1975 04:24:21.243774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1976 04:24:21.244820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1978 04:24:21.324808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1979 04:24:21.325686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1981 04:24:21.407607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1982 04:24:21.408543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1984 04:24:21.510491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1985 04:24:21.511154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1987 04:24:21.597577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1988 04:24:21.598454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1990 04:24:21.684110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1991 04:24:21.684983 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1993 04:24:21.765452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1994 04:24:21.766274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1996 04:24:21.849364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1997 04:24:21.850330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1999 04:24:21.936524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2000 04:24:21.937565 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2002 04:24:22.018583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2003 04:24:22.019481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2005 04:24:22.101255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2006 04:24:22.102128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2008 04:24:22.188994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2009 04:24:22.189851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2011 04:24:22.267595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2012 04:24:22.268465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2014 04:24:22.350665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2015 04:24:22.351521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2017 04:24:22.432439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2018 04:24:22.433378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2020 04:24:22.514878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2021 04:24:22.515709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2023 04:24:22.598250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2024 04:24:22.599074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2026 04:24:22.686207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2027 04:24:22.687041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2029 04:24:22.773387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2030 04:24:22.774183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2032 04:24:22.862205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2033 04:24:22.863039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2035 04:24:22.948346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2036 04:24:22.949167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2038 04:24:23.035759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2039 04:24:23.036627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2041 04:24:23.122764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2042 04:24:23.123638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2044 04:24:23.204261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2045 04:24:23.205096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2047 04:24:23.287450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2048 04:24:23.288436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2050 04:24:23.368404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2051 04:24:23.369179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2053 04:24:23.451810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2054 04:24:23.452641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2056 04:24:23.537669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2057 04:24:23.538495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2059 04:24:23.626019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2060 04:24:23.627112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2062 04:24:23.707534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2063 04:24:23.708387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2065 04:24:23.789797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2066 04:24:23.790635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2068 04:24:23.880508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2069 04:24:23.881287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2071 04:24:23.967354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2072 04:24:23.968161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2074 04:24:24.055067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2075 04:24:24.055899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2077 04:24:24.144448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2078 04:24:24.145311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2080 04:24:24.234197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2081 04:24:24.235007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2083 04:24:24.321211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2084 04:24:24.322010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2086 04:24:24.409576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2087 04:24:24.410396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2089 04:24:24.496250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2090 04:24:24.497041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2092 04:24:24.586958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2093 04:24:24.587743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2095 04:24:24.674282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2096 04:24:24.675080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2098 04:24:24.756783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2099 04:24:24.757577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2101 04:24:24.837000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2102 04:24:24.837774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2104 04:24:24.919776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2105 04:24:24.920569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2107 04:24:25.008860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2108 04:24:25.009667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2110 04:24:25.097074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2111 04:24:25.097904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2113 04:24:25.187352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2114 04:24:25.188178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2116 04:24:25.272576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2117 04:24:25.273419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2119 04:24:25.357141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2120 04:24:25.357938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2122 04:24:25.445639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2123 04:24:25.446452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2125 04:24:25.529634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2126 04:24:25.530417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2128 04:24:25.614743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2129 04:24:25.615525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2131 04:24:25.700781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2132 04:24:25.701548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2134 04:24:25.783081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2135 04:24:25.783977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2137 04:24:25.868107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2138 04:24:25.868881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2140 04:24:25.949187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2141 04:24:25.949941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2143 04:24:26.037037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2144 04:24:26.037797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2146 04:24:26.124294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2147 04:24:26.125093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2149 04:24:26.211864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2150 04:24:26.212765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2152 04:24:26.295788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2153 04:24:26.296607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2155 04:24:26.376199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2156 04:24:26.376965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2158 04:24:26.465939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2159 04:24:26.466747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2161 04:24:26.547723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2162 04:24:26.548531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2164 04:24:26.638894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2165 04:24:26.639796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2167 04:24:26.737195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2168 04:24:26.738153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2170 04:24:26.834214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2171 04:24:26.835095 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2173 04:24:26.919222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2174 04:24:26.919910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2176 04:24:27.010116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2177 04:24:27.010944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2179 04:24:27.097645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2180 04:24:27.098453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2182 04:24:27.183295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2183 04:24:27.184109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2185 04:24:27.273382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2186 04:24:27.274180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2188 04:24:27.356278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2189 04:24:27.357082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2191 04:24:27.438916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2192 04:24:27.439713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2194 04:24:27.520837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2195 04:24:27.521653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2197 04:24:27.602823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2198 04:24:27.603656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2200 04:24:27.684478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2201 04:24:27.685297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2203 04:24:27.768486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2204 04:24:27.769369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2206 04:24:27.846448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2207 04:24:27.847032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2209 04:24:28.004660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2210 04:24:28.005231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2212 04:24:28.101431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2213 04:24:28.102241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2215 04:24:28.191011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2216 04:24:28.191827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2218 04:24:28.279454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2219 04:24:28.280331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2221 04:24:28.365002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2222 04:24:28.365862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2224 04:24:28.447041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2225 04:24:28.447876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2227 04:24:28.536097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2228 04:24:28.536917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2230 04:24:28.619060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2231 04:24:28.619877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2233 04:24:28.700621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2234 04:24:28.701473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2236 04:24:28.789367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2237 04:24:28.790349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2239 04:24:28.877252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2240 04:24:28.878196 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2242 04:24:28.963410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2243 04:24:28.964314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2245 04:24:29.047342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2246 04:24:29.048211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2248 04:24:29.135347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2249 04:24:29.136185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2251 04:24:29.222687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2252 04:24:29.223535 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2254 04:24:29.312476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2255 04:24:29.313349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2257 04:24:29.402158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2258 04:24:29.402994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2260 04:24:29.489127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2262 04:24:29.491061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2263 04:24:29.572591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2264 04:24:29.573457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2266 04:24:29.662813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2267 04:24:29.663673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2269 04:24:29.745476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2270 04:24:29.746487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2272 04:24:29.829119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2273 04:24:29.830006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2275 04:24:29.917239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2276 04:24:29.918059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2278 04:24:30.006162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2279 04:24:30.007000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2281 04:24:30.094315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2282 04:24:30.095203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2284 04:24:30.183305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2285 04:24:30.184159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2287 04:24:30.266693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2288 04:24:30.267539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2290 04:24:30.356590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2291 04:24:30.357443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2293 04:24:30.444654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2294 04:24:30.445614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2296 04:24:30.533602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2297 04:24:30.534448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2299 04:24:30.623078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2300 04:24:30.623949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2302 04:24:30.712859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2303 04:24:30.713820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2305 04:24:30.801949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2306 04:24:30.802839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2308 04:24:30.884351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2309 04:24:30.885399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2311 04:24:30.968929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2312 04:24:30.969809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2314 04:24:31.055124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2315 04:24:31.056028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2317 04:24:31.144160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2318 04:24:31.145028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2320 04:24:31.232889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2321 04:24:31.233748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2323 04:24:31.320486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2324 04:24:31.321449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2326 04:24:31.411522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2327 04:24:31.412525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2329 04:24:31.499587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2330 04:24:31.500681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2332 04:24:31.583233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2333 04:24:31.584092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2335 04:24:31.668737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2336 04:24:31.669577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2338 04:24:31.750269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2339 04:24:31.751144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2341 04:24:31.839424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2342 04:24:31.840313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2344 04:24:31.928540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2345 04:24:31.929408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2347 04:24:32.029166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2348 04:24:32.030473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2350 04:24:32.123977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2351 04:24:32.124720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2353 04:24:32.209867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2354 04:24:32.210513 + set +x
2355 04:24:32.211265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2357 04:24:32.214005 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 689530_1.6.2.4.5>
2358 04:24:32.214751 Received signal: <ENDRUN> 1_kselftest-dt 689530_1.6.2.4.5
2359 04:24:32.215244 Ending use of test pattern.
2360 04:24:32.215707 Ending test lava.1_kselftest-dt (689530_1.6.2.4.5), duration 66.22
2362 04:24:32.219202 <LAVA_TEST_RUNNER EXIT>
2363 04:24:32.219927 ok: lava_test_shell seems to have completed
2364 04:24:32.231425 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2365 04:24:32.233610 end: 3.1 lava-test-shell (duration 00:01:08) [common]
2366 04:24:32.234232 end: 3 lava-test-retry (duration 00:01:08) [common]
2367 04:24:32.234831 start: 4 finalize (timeout 00:05:42) [common]
2368 04:24:32.235477 start: 4.1 power-off (timeout 00:00:30) [common]
2369 04:24:32.236645 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2370 04:24:32.271234 >> OK - accepted request
2371 04:24:32.273077 Returned 0 in 0 seconds
2372 04:24:32.374115 end: 4.1 power-off (duration 00:00:00) [common]
2374 04:24:32.376060 start: 4.2 read-feedback (timeout 00:05:42) [common]
2375 04:24:32.377295 Listened to connection for namespace 'common' for up to 1s
2376 04:24:32.378240 Listened to connection for namespace 'common' for up to 1s
2377 04:24:33.377388 Finalising connection for namespace 'common'
2378 04:24:33.378183 Disconnecting from shell: Finalise
2379 04:24:33.378776 / #
2380 04:24:33.479907 end: 4.2 read-feedback (duration 00:00:01) [common]
2381 04:24:33.480750 end: 4 finalize (duration 00:00:01) [common]
2382 04:24:33.481471 Cleaning after the job
2383 04:24:33.482206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/ramdisk
2384 04:24:33.485108 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/kernel
2385 04:24:33.487171 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/dtb
2386 04:24:33.488474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/nfsrootfs
2387 04:24:33.528661 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/689530/tftp-deploy-xsdkrgyu/modules
2388 04:24:33.533024 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/689530
2389 04:24:36.413057 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/689530
2390 04:24:36.413732 Job finished correctly