Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 06:36:45.274876 lava-dispatcher, installed at version: 2023.08
2 06:36:45.275163 start: 0 validate
3 06:36:45.275346 Start time: 2024-09-02 06:36:45.275335+00:00 (UTC)
4 06:36:45.275565 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 06:36:45.526927 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 06:36:45.641385 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 06:36:45.755551 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 06:36:45.869407 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 06:36:45.988135 validate duration: 0.71
11 06:36:45.988920 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 06:36:45.989251 start: 1.1 download-retry (timeout 00:10:00) [common]
13 06:36:45.989560 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 06:36:45.990017 Not decompressing ramdisk as can be used compressed.
15 06:36:45.990310 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 06:36:45.990545 saving as /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/ramdisk/initrd.cpio.gz
17 06:36:45.990782 total size: 4775763 (4 MB)
18 06:36:46.217764 progress 0 % (0 MB)
19 06:36:46.555277 progress 5 % (0 MB)
20 06:36:46.777180 progress 10 % (0 MB)
21 06:36:46.798144 progress 15 % (0 MB)
22 06:36:46.891492 progress 20 % (0 MB)
23 06:36:46.906008 progress 25 % (1 MB)
24 06:36:47.010684 progress 30 % (1 MB)
25 06:36:47.117410 progress 35 % (1 MB)
26 06:36:47.138710 progress 40 % (1 MB)
27 06:36:47.241984 progress 45 % (2 MB)
28 06:36:47.344632 progress 50 % (2 MB)
29 06:36:47.446799 progress 55 % (2 MB)
30 06:36:47.469680 progress 60 % (2 MB)
31 06:36:47.571619 progress 65 % (2 MB)
32 06:36:47.672994 progress 70 % (3 MB)
33 06:36:47.695727 progress 75 % (3 MB)
34 06:36:47.796600 progress 80 % (3 MB)
35 06:36:47.892992 progress 85 % (3 MB)
36 06:36:47.920571 progress 90 % (4 MB)
37 06:36:48.018838 progress 95 % (4 MB)
38 06:36:48.113247 progress 100 % (4 MB)
39 06:36:48.114034 4 MB downloaded in 2.12 s (2.15 MB/s)
40 06:36:48.114519 end: 1.1.1 http-download (duration 00:00:02) [common]
42 06:36:48.115365 end: 1.1 download-retry (duration 00:00:02) [common]
43 06:36:48.115658 start: 1.2 download-retry (timeout 00:09:58) [common]
44 06:36:48.115943 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 06:36:48.116378 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 06:36:48.116610 saving as /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/kernel/zImage
47 06:36:48.116826 total size: 11354624 (10 MB)
48 06:36:48.117044 No compression specified
49 06:36:48.232987 progress 0 % (0 MB)
50 06:36:48.581360 progress 5 % (0 MB)
51 06:36:48.911180 progress 10 % (1 MB)
52 06:36:49.244360 progress 15 % (1 MB)
53 06:36:49.576811 progress 20 % (2 MB)
54 06:36:49.848150 progress 25 % (2 MB)
55 06:36:50.146048 progress 30 % (3 MB)
56 06:36:50.475061 progress 35 % (3 MB)
57 06:36:50.712293 progress 40 % (4 MB)
58 06:36:51.035219 progress 45 % (4 MB)
59 06:36:51.356772 progress 50 % (5 MB)
60 06:36:51.597807 progress 55 % (5 MB)
61 06:36:51.912596 progress 60 % (6 MB)
62 06:36:52.159920 progress 65 % (7 MB)
63 06:36:52.475150 progress 70 % (7 MB)
64 06:36:52.715261 progress 75 % (8 MB)
65 06:36:53.037718 progress 80 % (8 MB)
66 06:36:53.277864 progress 85 % (9 MB)
67 06:36:53.593620 progress 90 % (9 MB)
68 06:36:53.839508 progress 95 % (10 MB)
69 06:36:54.151658 progress 100 % (10 MB)
70 06:36:54.152304 10 MB downloaded in 6.04 s (1.79 MB/s)
71 06:36:54.152752 end: 1.2.1 http-download (duration 00:00:06) [common]
73 06:36:54.153554 end: 1.2 download-retry (duration 00:00:06) [common]
74 06:36:54.153844 start: 1.3 download-retry (timeout 00:09:52) [common]
75 06:36:54.154126 start: 1.3.1 http-download (timeout 00:09:52) [common]
76 06:36:54.154519 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 06:36:54.154744 saving as /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/dtb/am335x-boneblack.dtb
78 06:36:54.154958 total size: 70308 (0 MB)
79 06:36:54.155171 No compression specified
80 06:36:54.271317 progress 46 % (0 MB)
81 06:36:54.274139 progress 93 % (0 MB)
82 06:36:54.275121 progress 100 % (0 MB)
83 06:36:54.275504 0 MB downloaded in 0.12 s (0.56 MB/s)
84 06:36:54.275903 end: 1.3.1 http-download (duration 00:00:00) [common]
86 06:36:54.276713 end: 1.3 download-retry (duration 00:00:00) [common]
87 06:36:54.276991 start: 1.4 download-retry (timeout 00:09:52) [common]
88 06:36:54.277273 start: 1.4.1 http-download (timeout 00:09:52) [common]
89 06:36:54.277627 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 06:36:54.277850 saving as /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/nfsrootfs/full.rootfs.tar
91 06:36:54.278061 total size: 117747780 (112 MB)
92 06:36:54.278279 Using unxz to decompress xz
93 06:36:54.394613 progress 0 % (0 MB)
94 06:36:57.752425 progress 5 % (5 MB)
95 06:37:00.664959 progress 10 % (11 MB)
96 06:37:03.439325 progress 15 % (16 MB)
97 06:37:05.629707 progress 20 % (22 MB)
98 06:37:07.232770 progress 25 % (28 MB)
99 06:37:08.445682 progress 30 % (33 MB)
100 06:37:09.386121 progress 35 % (39 MB)
101 06:37:10.176886 progress 40 % (44 MB)
102 06:37:10.863839 progress 45 % (50 MB)
103 06:37:11.475959 progress 50 % (56 MB)
104 06:37:12.007785 progress 55 % (61 MB)
105 06:37:12.615534 progress 60 % (67 MB)
106 06:37:13.130962 progress 65 % (73 MB)
107 06:37:13.721476 progress 70 % (78 MB)
108 06:37:14.285778 progress 75 % (84 MB)
109 06:37:14.814635 progress 80 % (89 MB)
110 06:37:15.336269 progress 85 % (95 MB)
111 06:37:15.848903 progress 90 % (101 MB)
112 06:37:16.348144 progress 95 % (106 MB)
113 06:37:16.847863 progress 100 % (112 MB)
114 06:37:16.851423 112 MB downloaded in 22.57 s (4.97 MB/s)
115 06:37:16.851749 end: 1.4.1 http-download (duration 00:00:23) [common]
117 06:37:16.852358 end: 1.4 download-retry (duration 00:00:23) [common]
118 06:37:16.852568 start: 1.5 download-retry (timeout 00:09:29) [common]
119 06:37:16.852778 start: 1.5.1 http-download (timeout 00:09:29) [common]
120 06:37:16.853080 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 06:37:16.853244 saving as /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/modules/modules.tar
122 06:37:16.853396 total size: 6607904 (6 MB)
123 06:37:16.853553 Using unxz to decompress xz
124 06:37:16.969408 progress 0 % (0 MB)
125 06:37:17.200784 progress 5 % (0 MB)
126 06:37:17.414829 progress 10 % (0 MB)
127 06:37:17.440689 progress 15 % (0 MB)
128 06:37:17.465269 progress 20 % (1 MB)
129 06:37:17.531545 progress 25 % (1 MB)
130 06:37:17.558320 progress 30 % (1 MB)
131 06:37:17.682910 progress 35 % (2 MB)
132 06:37:17.772240 progress 40 % (2 MB)
133 06:37:17.796320 progress 45 % (2 MB)
134 06:37:17.820542 progress 50 % (3 MB)
135 06:37:17.991741 progress 55 % (3 MB)
136 06:37:18.015973 progress 60 % (3 MB)
137 06:37:18.042475 progress 65 % (4 MB)
138 06:37:18.113756 progress 70 % (4 MB)
139 06:37:18.200419 progress 75 % (4 MB)
140 06:37:18.242714 progress 80 % (5 MB)
141 06:37:18.337721 progress 85 % (5 MB)
142 06:37:18.423936 progress 90 % (5 MB)
143 06:37:18.465337 progress 95 % (6 MB)
144 06:37:18.558854 progress 100 % (6 MB)
145 06:37:18.562448 6 MB downloaded in 1.71 s (3.69 MB/s)
146 06:37:18.562858 end: 1.5.1 http-download (duration 00:00:02) [common]
148 06:37:18.563570 end: 1.5 download-retry (duration 00:00:02) [common]
149 06:37:18.563827 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
150 06:37:18.564082 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
151 06:37:24.091560 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd
152 06:37:24.091848 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 06:37:24.091978 start: 1.6.2 lava-overlay (timeout 00:09:22) [common]
154 06:37:24.092397 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm
155 06:37:24.092566 makedir: /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin
156 06:37:24.092697 makedir: /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/tests
157 06:37:24.092825 makedir: /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/results
158 06:37:24.092965 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-add-keys
159 06:37:24.093167 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-add-sources
160 06:37:24.093337 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-background-process-start
161 06:37:24.093506 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-background-process-stop
162 06:37:24.093688 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-common-functions
163 06:37:24.093857 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-echo-ipv4
164 06:37:24.094024 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-install-packages
165 06:37:24.094188 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-installed-packages
166 06:37:24.094350 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-os-build
167 06:37:24.094512 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-probe-channel
168 06:37:24.094675 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-probe-ip
169 06:37:24.094840 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-target-ip
170 06:37:24.095002 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-target-mac
171 06:37:24.095164 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-target-storage
172 06:37:24.095331 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-test-case
173 06:37:24.095500 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-test-event
174 06:37:24.095660 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-test-feedback
175 06:37:24.095819 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-test-raise
176 06:37:24.095979 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-test-reference
177 06:37:24.096141 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-test-runner
178 06:37:24.096327 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-test-set
179 06:37:24.096488 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-test-shell
180 06:37:24.096651 Updating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-add-keys (debian)
181 06:37:24.096866 Updating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-add-sources (debian)
182 06:37:24.097051 Updating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-install-packages (debian)
183 06:37:24.097235 Updating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-installed-packages (debian)
184 06:37:24.097416 Updating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/bin/lava-os-build (debian)
185 06:37:24.097576 Creating /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/environment
186 06:37:24.097699 LAVA metadata
187 06:37:24.097794 - LAVA_JOB_ID=1187659
188 06:37:24.097884 - LAVA_DISPATCHER_IP=192.168.11.5
189 06:37:24.098020 start: 1.6.2.1 ssh-authorize (timeout 00:09:22) [common]
190 06:37:24.098335 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 06:37:24.098477 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:22) [common]
192 06:37:24.098572 skipped lava-vland-overlay
193 06:37:24.098678 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 06:37:24.098789 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:22) [common]
195 06:37:24.098880 skipped lava-multinode-overlay
196 06:37:24.098985 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 06:37:24.099094 start: 1.6.2.4 test-definition (timeout 00:09:22) [common]
198 06:37:24.099190 Loading test definitions
199 06:37:24.099307 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:22) [common]
200 06:37:24.099401 Using /lava-1187659 at stage 0
201 06:37:24.099784 uuid=1187659_1.6.2.4.1 testdef=None
202 06:37:24.099900 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 06:37:24.100010 start: 1.6.2.4.2 test-overlay (timeout 00:09:22) [common]
204 06:37:24.100767 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 06:37:24.101089 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:22) [common]
207 06:37:24.101886 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 06:37:24.102210 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:22) [common]
210 06:37:24.102981 runner path: /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/0/tests/0_timesync-off test_uuid 1187659_1.6.2.4.1
211 06:37:24.103169 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 06:37:24.103491 start: 1.6.2.4.5 git-repo-action (timeout 00:09:22) [common]
214 06:37:24.103586 Using /lava-1187659 at stage 0
215 06:37:24.103718 Fetching tests from https://github.com/kernelci/test-definitions.git
216 06:37:24.103816 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/0/tests/1_kselftest-dt'
217 06:37:28.842791 Running '/usr/bin/git checkout kernelci.org
218 06:37:29.066343 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 06:37:29.067145 uuid=1187659_1.6.2.4.5 testdef=None
220 06:37:29.067352 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 06:37:29.067805 start: 1.6.2.4.6 test-overlay (timeout 00:09:17) [common]
223 06:37:29.069325 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 06:37:29.069802 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:17) [common]
226 06:37:29.071883 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 06:37:29.072406 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:17) [common]
229 06:37:29.074512 runner path: /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/0/tests/1_kselftest-dt test_uuid 1187659_1.6.2.4.5
230 06:37:29.074682 BOARD='beaglebone-black'
231 06:37:29.074818 BRANCH='mainline'
232 06:37:29.074948 SKIPFILE='/dev/null'
233 06:37:29.075076 SKIP_INSTALL='True'
234 06:37:29.075201 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 06:37:29.075330 TST_CASENAME=''
236 06:37:29.075455 TST_CMDFILES='dt'
237 06:37:29.075736 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 06:37:29.076191 Creating lava-test-runner.conf files
240 06:37:29.076333 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1187659/lava-overlay-fpknuazm/lava-1187659/0 for stage 0
241 06:37:29.076517 - 0_timesync-off
242 06:37:29.076654 - 1_kselftest-dt
243 06:37:29.076850 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 06:37:29.077022 start: 1.6.2.5 compress-overlay (timeout 00:09:17) [common]
245 06:37:37.543217 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 06:37:37.543427 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:08) [common]
247 06:37:37.543570 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 06:37:37.543717 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
249 06:37:37.543861 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:08) [common]
250 06:37:37.670787 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 06:37:37.671080 start: 1.6.4 extract-modules (timeout 00:09:08) [common]
252 06:37:37.671250 extracting modules file /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd
253 06:37:37.968257 extracting modules file /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1187659/extract-overlay-ramdisk-1s2xwscm/ramdisk
254 06:37:38.269412 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 06:37:38.269628 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
256 06:37:38.269760 [common] Applying overlay to NFS
257 06:37:38.269857 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1187659/compress-overlay-0kcmjpr1/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd
258 06:37:39.449643 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 06:37:39.449854 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
260 06:37:39.449997 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
261 06:37:39.450143 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 06:37:39.450278 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 06:37:39.450415 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
264 06:37:39.450547 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 06:37:39.450666 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
266 06:37:39.450768 Building ramdisk /var/lib/lava/dispatcher/tmp/1187659/extract-overlay-ramdisk-1s2xwscm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1187659/extract-overlay-ramdisk-1s2xwscm/ramdisk
267 06:37:39.764775 >> 74799 blocks
268 06:37:41.701971 Adding RAMdisk u-boot header.
269 06:37:41.702244 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1187659/extract-overlay-ramdisk-1s2xwscm/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1187659/extract-overlay-ramdisk-1s2xwscm/ramdisk.cpio.gz.uboot
270 06:37:41.851474 output: Image Name:
271 06:37:41.851831 output: Created: Mon Sep 2 06:37:41 2024
272 06:37:41.852053 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 06:37:41.852299 output: Data Size: 14793277 Bytes = 14446.56 KiB = 14.11 MiB
274 06:37:41.852497 output: Load Address: 00000000
275 06:37:41.852688 output: Entry Point: 00000000
276 06:37:41.852878 output:
277 06:37:41.853185 rename /var/lib/lava/dispatcher/tmp/1187659/extract-overlay-ramdisk-1s2xwscm/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/ramdisk/ramdisk.cpio.gz.uboot
278 06:37:41.853513 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 06:37:41.853780 end: 1.6 prepare-tftp-overlay (duration 00:00:23) [common]
280 06:37:41.854041 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:04) [common]
281 06:37:41.854246 No LXC device requested
282 06:37:41.854491 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 06:37:41.854743 start: 1.8 deploy-device-env (timeout 00:09:04) [common]
284 06:37:41.854988 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 06:37:41.855186 Checking files for TFTP limit of 4294967296 bytes.
286 06:37:41.856425 end: 1 tftp-deploy (duration 00:00:56) [common]
287 06:37:41.856693 start: 2 uboot-action (timeout 00:05:00) [common]
288 06:37:41.856953 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 06:37:41.857199 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 06:37:41.857447 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 06:37:41.857819 substitutions:
292 06:37:41.858019 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 06:37:41.858214 - {DTB_ADDR}: 0x88000000
294 06:37:41.858404 - {DTB}: 1187659/tftp-deploy-dykh51w8/dtb/am335x-boneblack.dtb
295 06:37:41.858594 - {INITRD}: 1187659/tftp-deploy-dykh51w8/ramdisk/ramdisk.cpio.gz.uboot
296 06:37:41.858782 - {KERNEL_ADDR}: 0x82000000
297 06:37:41.858970 - {KERNEL}: 1187659/tftp-deploy-dykh51w8/kernel/zImage
298 06:37:41.859156 - {LAVA_MAC}: None
299 06:37:41.859351 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd
300 06:37:41.859539 - {NFS_SERVER_IP}: 192.168.11.5
301 06:37:41.859722 - {PRESEED_CONFIG}: None
302 06:37:41.859904 - {PRESEED_LOCAL}: None
303 06:37:41.860088 - {RAMDISK_ADDR}: 0x83000000
304 06:37:41.860306 - {RAMDISK}: 1187659/tftp-deploy-dykh51w8/ramdisk/ramdisk.cpio.gz.uboot
305 06:37:41.860493 - {ROOT_PART}: None
306 06:37:41.860674 - {ROOT}: None
307 06:37:41.860853 - {SERVER_IP}: 192.168.11.5
308 06:37:41.861030 - {TEE_ADDR}: 0x83000000
309 06:37:41.861211 - {TEE}: None
310 06:37:41.861391 Parsed boot commands:
311 06:37:41.861567 - setenv autoload no
312 06:37:41.861748 - setenv initrd_high 0xffffffff
313 06:37:41.861928 - setenv fdt_high 0xffffffff
314 06:37:41.862106 - dhcp
315 06:37:41.862284 - setenv serverip 192.168.11.5
316 06:37:41.862463 - tftp 0x82000000 1187659/tftp-deploy-dykh51w8/kernel/zImage
317 06:37:41.862645 - tftp 0x83000000 1187659/tftp-deploy-dykh51w8/ramdisk/ramdisk.cpio.gz.uboot
318 06:37:41.862829 - setenv initrd_size ${filesize}
319 06:37:41.863010 - tftp 0x88000000 1187659/tftp-deploy-dykh51w8/dtb/am335x-boneblack.dtb
320 06:37:41.863189 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 06:37:41.863377 - bootz 0x82000000 0x83000000 0x88000000
322 06:37:41.863613 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 06:37:41.864309 start: 2.3 connect-device (timeout 00:05:00) [common]
325 06:37:41.864412 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 06:37:42.221165 Setting prompt string to ['lava-test: # ']
327 06:37:42.221561 end: 2.3 connect-device (duration 00:00:00) [common]
328 06:37:42.221706 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 06:37:42.221897 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 06:37:42.222123 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 06:37:42.222473 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 06:37:42.587193 Returned 0 in 0 seconds
333 06:37:42.688084 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 06:37:42.688970 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 06:37:42.689284 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 06:37:42.689573 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 06:37:42.689824 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 06:37:42.690559 Trying 127.0.0.1...
340 06:37:42.690789 Connected to 127.0.0.1.
341 06:37:42.691000 Escape character is '^]'.
342 06:37:47.612934
343 06:37:47.616488 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 06:37:47.673168 Trying to boot from MMC2
345 06:37:47.721517 Loading Environment from EXT4... Card did not respond to voltage select!
346 06:37:47.788580
347 06:37:47.788853
348 06:37:47.794167 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 06:37:47.794432
350 06:37:47.799233 CPU : AM335X-GP rev 2.1
351 06:37:47.852996 I2C: ready
352 06:37:47.853270 DRAM: 512 MiB
353 06:37:47.907421 No match for driver 'omap_hsmmc'
354 06:37:47.912906 No match for driver 'omap_hsmmc'
355 06:37:47.913168 Some drivers were not found
356 06:37:47.919256 Reset Source: Power-on reset has occurred.
357 06:37:47.919499 RTC 32KCLK Source: External.
358 06:37:47.926689 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 06:37:47.939977 Loading Environment from EXT4... Card did not respond to voltage select!
360 06:37:48.004574 Board: BeagleBone Black
361 06:37:48.008558 <ethaddr> not set. Validating first E-fuse MAC
362 06:37:48.065081 BeagleBone Black:
363 06:37:48.065351 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 06:37:48.070707 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 06:37:48.076709 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 06:37:48.076975 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 06:37:48.081678 Net: eth0: MII MODE
368 06:37:48.090983 cpsw, usb_ether
369 06:37:48.091248 Press SPACE to abort autoboot in 2 seconds
370 06:37:48.142035 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 06:37:48.142376 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 06:37:48.142635 Setting prompt string to ['=> ']
373 06:37:48.142885 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 06:37:48.146225 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 06:37:48.146527 Sending with 10 millisecond of delay
377 06:37:49.281042 => setenv autoload no
378 06:37:49.291523 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 06:37:49.293899 setenv autoload no
380 06:37:49.294368 Sending with 10 millisecond of delay
382 06:37:51.091331 => setenv initrd_high 0xffffffff
383 06:37:51.101852 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 06:37:51.102332 setenv initrd_high 0xffffffff
385 06:37:51.102778 Sending with 10 millisecond of delay
387 06:37:52.719070 => setenv fdt_high 0xffffffff
388 06:37:52.729572 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 06:37:52.730023 setenv fdt_high 0xffffffff
390 06:37:52.730463 Sending with 10 millisecond of delay
392 06:37:53.021893 => dhcp
393 06:37:53.032294 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 06:37:53.032733 dhcp
395 06:37:53.032956 link up on port 0, speed 100, full duplex
396 06:37:53.033168 BOOTP broadcast 1
397 06:37:53.040719 DHCP client bound to address 192.168.11.7 (4 ms)
398 06:37:53.041197 Sending with 10 millisecond of delay
400 06:37:54.777814 => setenv serverip 192.168.11.5
401 06:37:54.788318 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 06:37:54.788788 setenv serverip 192.168.11.5
403 06:37:54.789232 Sending with 10 millisecond of delay
405 06:37:58.332125 => tftp 0x82000000 1187659/tftp-deploy-dykh51w8/kernel/zImage
406 06:37:58.342610 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 06:37:58.343118 tftp 0x82000000 1187659/tftp-deploy-dykh51w8/kernel/zImage
408 06:37:58.343381 link up on port 0, speed 100, full duplex
409 06:37:58.343627 Using cpsw device
410 06:37:58.346922 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
411 06:37:58.352440 Filename '1187659/tftp-deploy-dykh51w8/kernel/zImage'.
412 06:37:58.359370 Load address: 0x82000000
413 06:37:58.535085 Loading: *#################################################################
414 06:37:58.731722 #################################################################
415 06:37:58.906579 #################################################################
416 06:37:59.077089 #################################################################
417 06:37:59.257466 #################################################################
418 06:37:59.427387 #################################################################
419 06:37:59.600052 #################################################################
420 06:37:59.773936 #################################################################
421 06:37:59.948307 #################################################################
422 06:38:00.188118 #################################################################
423 06:38:00.320315 #################################################################
424 06:38:00.464380 ###########################################################
425 06:38:00.464670 5.1 MiB/s
426 06:38:00.464895 done
427 06:38:00.467894 Bytes transferred = 11354624 (ad4200 hex)
428 06:38:00.468415 Sending with 10 millisecond of delay
430 06:38:04.975055 => tftp 0x83000000 1187659/tftp-deploy-dykh51w8/ramdisk/ramdisk.cpio.gz.uboot
431 06:38:04.985523 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
432 06:38:04.986037 tftp 0x83000000 1187659/tftp-deploy-dykh51w8/ramdisk/ramdisk.cpio.gz.uboot
433 06:38:04.986315 link up on port 0, speed 100, full duplex
434 06:38:04.986563 Using cpsw device
435 06:38:04.989832 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
436 06:38:05.003689 Filename '1187659/tftp-deploy-dykh51w8/ramdisk/ramdisk.cpio.gz.uboot'.
437 06:38:05.003997 Load address: 0x83000000
438 06:38:05.200862 Loading: *#################################################################
439 06:38:05.377689 #################################################################
440 06:38:05.553835 #################################################################
441 06:38:05.722047 #################################################################
442 06:38:05.893562 #################################################################
443 06:38:06.068823 #################################################################
444 06:38:06.261962 #################################################################
445 06:38:06.436656 #################################################################
446 06:38:06.607717 #################################################################
447 06:38:06.780814 #################################################################
448 06:38:06.955939 #################################################################
449 06:38:07.130428 #################################################################
450 06:38:07.305288 #################################################################
451 06:38:07.501915 #################################################################
452 06:38:07.675928 #################################################################
453 06:38:07.752996 #################################
454 06:38:07.753273 5.1 MiB/s
455 06:38:07.753497 done
456 06:38:07.756287 Bytes transferred = 14793341 (e1ba7d hex)
457 06:38:07.756826 Sending with 10 millisecond of delay
459 06:38:09.613893 => setenv initrd_size ${filesize}
460 06:38:09.624371 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
461 06:38:09.624835 setenv initrd_size ${filesize}
462 06:38:09.625280 Sending with 10 millisecond of delay
464 06:38:13.830912 => tftp 0x88000000 1187659/tftp-deploy-dykh51w8/dtb/am335x-boneblack.dtb
465 06:38:13.841406 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
466 06:38:13.841893 tftp 0x88000000 1187659/tftp-deploy-dykh51w8/dtb/am335x-boneblack.dtb
467 06:38:13.842144 link up on port 0, speed 100, full duplex
468 06:38:13.842378 Using cpsw device
469 06:38:13.845638 TFTP from server 192.168.11.5; our IP address is 192.168.11.7
470 06:38:13.851992 Filename '1187659/tftp-deploy-dykh51w8/dtb/am335x-boneblack.dtb'.
471 06:38:13.870925 Load address: 0x88000000
472 06:38:13.871217 Loading: *#####
473 06:38:13.871452 4.8 MiB/s
474 06:38:13.871683 done
475 06:38:13.876997 Bytes transferred = 70308 (112a4 hex)
476 06:38:13.877478 Sending with 10 millisecond of delay
478 06:38:27.176437 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 06:38:27.186922 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
480 06:38:27.187372 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 06:38:27.187824 Sending with 10 millisecond of delay
483 06:38:29.526645 => bootz 0x82000000 0x83000000 0x88000000
484 06:38:29.537120 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
485 06:38:29.537438 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
486 06:38:29.537965 bootz 0x82000000 0x83000000 0x88000000
487 06:38:29.538194 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 06:38:29.538740 Image Name:
489 06:38:29.538961 Created: 2024-09-02 6:37:41 UTC
490 06:38:29.544233 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 06:38:29.549993 Data Size: 14793277 Bytes = 14.1 MiB
492 06:38:29.550264 Load Address: 00000000
493 06:38:29.557193 Entry Point: 00000000
494 06:38:29.694427 Verifying Checksum ... OK
495 06:38:29.694701 ## Flattened Device Tree blob at 88000000
496 06:38:29.700981 Booting using the fdt blob at 0x88000000
497 06:38:29.705779 Using Device Tree in place at 88000000, end 880142a3
498 06:38:29.713587
499 06:38:29.713999 Starting kernel ...
500 06:38:29.714229
501 06:38:29.714803 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 06:38:29.715136 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
503 06:38:29.715402 Setting prompt string to ['Linux version [0-9]']
504 06:38:29.715655 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
505 06:38:29.715911 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
506 06:38:30.545956 [ 0.000000] Booting Linux on physical CPU 0x0
507 06:38:30.551865 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
508 06:38:30.552215 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 06:38:30.552506 Setting prompt string to []
510 06:38:30.552803 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 06:38:30.553099 Using line separator: #'\n'#
512 06:38:30.553351 No login prompt set.
513 06:38:30.553617 Parsing kernel messages
514 06:38:30.553858 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 06:38:30.554306 [login-action] Waiting for messages, (timeout 00:04:11)
516 06:38:30.568727 [ 0.000000] Linux version 6.11.0-rc6 (KernelCI@build-j304715-arm-gcc-12-multi-v7-defconfig-pzkrd) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Sep 2 03:48:51 UTC 2024
517 06:38:30.574454 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 06:38:30.580062 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 06:38:30.591558 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 06:38:30.597307 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 06:38:30.603061 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 06:38:30.603334 [ 0.000000] Memory policy: Data cache writeback
523 06:38:30.609703 [ 0.000000] efi: UEFI not found.
524 06:38:30.615130 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 06:38:30.620951 [ 0.000000] Zone ranges:
526 06:38:30.626590 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 06:38:30.632324 [ 0.000000] Normal empty
528 06:38:30.632596 [ 0.000000] HighMem empty
529 06:38:30.638096 [ 0.000000] Movable zone start for each node
530 06:38:30.638371 [ 0.000000] Early memory node ranges
531 06:38:30.649568 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 06:38:30.654906 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 06:38:30.679661 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 06:38:30.685309 [ 0.000000] AM335X ES2.1 (sgx neon)
535 06:38:30.696961 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
536 06:38:30.714823 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 06:38:30.726219 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 06:38:30.732000 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 06:38:30.737749 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 06:38:30.748088 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 06:38:30.776999 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 06:38:30.782866 <6>[ 0.000000] trace event string verifier disabled
543 06:38:30.783144 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 06:38:30.788615 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 06:38:30.799954 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 06:38:30.805710 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 06:38:30.813011 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 06:38:30.827917 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 06:38:30.845124 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 06:38:30.851972 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 06:38:30.944623 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 06:38:30.956116 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 06:38:30.962747 <6>[ 0.008335] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 06:38:30.975837 <6>[ 0.019157] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 06:38:30.983254 <6>[ 0.033980] Console: colour dummy device 80x30
556 06:38:30.989315 Matched prompt #6: WARNING:
557 06:38:30.989604 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 06:38:30.994750 <3>[ 0.038875] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 06:38:31.000501 <3>[ 0.045946] This ensures that you still see kernel messages. Please
560 06:38:31.003716 <3>[ 0.052673] update your kernel commandline.
561 06:38:31.044369 <6>[ 0.057281] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 06:38:31.050118 <6>[ 0.096161] CPU: Testing write buffer coherency: ok
563 06:38:31.056117 <6>[ 0.101525] CPU0: Spectre v2: using BPIALL workaround
564 06:38:31.056411 <6>[ 0.106990] pid_max: default: 32768 minimum: 301
565 06:38:31.067488 <6>[ 0.112177] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 06:38:31.074368 <6>[ 0.119998] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 06:38:31.081327 <6>[ 0.129293] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 06:38:31.089703 <6>[ 0.136147] Setting up static identity map for 0x80300000 - 0x803000ac
569 06:38:31.095431 <6>[ 0.145734] rcu: Hierarchical SRCU implementation.
570 06:38:31.103142 <6>[ 0.151015] rcu: Max phase no-delay instances is 1000.
571 06:38:31.111456 <6>[ 0.162068] EFI services will not be available.
572 06:38:31.117306 <6>[ 0.167313] smp: Bringing up secondary CPUs ...
573 06:38:31.123054 <6>[ 0.172348] smp: Brought up 1 node, 1 CPU
574 06:38:31.128962 <6>[ 0.176747] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 06:38:31.134682 <6>[ 0.183496] CPU: All CPU(s) started in SVC mode.
576 06:38:31.154977 <6>[ 0.188676] Memory: 407012K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48024K reserved, 65536K cma-reserved, 0K highmem)
577 06:38:31.155262 <6>[ 0.204915] devtmpfs: initialized
578 06:38:31.176948 <6>[ 0.221626] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 06:38:31.188308 <6>[ 0.230197] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 06:38:31.194244 <6>[ 0.240631] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 06:38:31.205149 <6>[ 0.252996] pinctrl core: initialized pinctrl subsystem
582 06:38:31.214472 <6>[ 0.263658] DMI not present or invalid.
583 06:38:31.222680 <6>[ 0.269498] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 06:38:31.232097 <6>[ 0.278345] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 06:38:31.247131 <6>[ 0.289757] thermal_sys: Registered thermal governor 'step_wise'
586 06:38:31.247406 <6>[ 0.289896] cpuidle: using governor menu
587 06:38:31.274344 <6>[ 0.325181] No ATAGs?
588 06:38:31.280501 <6>[ 0.327824] hw-breakpoint: debug architecture 0x4 unsupported.
589 06:38:31.290766 <6>[ 0.339837] Serial: AMBA PL011 UART driver
590 06:38:31.331706 <6>[ 0.382621] iommu: Default domain type: Translated
591 06:38:31.341008 <6>[ 0.387852] iommu: DMA domain TLB invalidation policy: strict mode
592 06:38:31.351392 <5>[ 0.400800] SCSI subsystem initialized
593 06:38:31.375312 <6>[ 0.420477] usbcore: registered new interface driver usbfs
594 06:38:31.382173 <6>[ 0.426431] usbcore: registered new interface driver hub
595 06:38:31.382449 <6>[ 0.432251] usbcore: registered new device driver usb
596 06:38:31.387952 <6>[ 0.438744] pps_core: LinuxPPS API ver. 1 registered
597 06:38:31.399443 <6>[ 0.444173] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 06:38:31.404633 <6>[ 0.453871] PTP clock support registered
599 06:38:31.429579 <6>[ 0.479599] EDAC MC: Ver: 3.0.0
600 06:38:31.448523 <6>[ 0.496781] scmi_core: SCMI protocol bus registered
601 06:38:31.463556 <6>[ 0.514065] vgaarb: loaded
602 06:38:31.476107 <6>[ 0.527002] clocksource: Switched to clocksource dmtimer
603 06:38:31.512371 <6>[ 0.562858] NET: Registered PF_INET protocol family
604 06:38:31.524972 <6>[ 0.568522] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 06:38:31.530717 <6>[ 0.577354] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 06:38:31.542181 <6>[ 0.586243] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 06:38:31.547924 <6>[ 0.594520] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 06:38:31.559617 <6>[ 0.602807] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 06:38:31.565291 <6>[ 0.610525] TCP: Hash tables configured (established 4096 bind 4096)
610 06:38:31.571190 <6>[ 0.617448] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 06:38:31.577062 <6>[ 0.624461] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 06:38:31.584590 <6>[ 0.632077] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 06:38:31.630553 <6>[ 0.675613] RPC: Registered named UNIX socket transport module.
614 06:38:31.630830 <6>[ 0.682053] RPC: Registered udp transport module.
615 06:38:31.636283 <6>[ 0.687185] RPC: Registered tcp transport module.
616 06:38:31.644923 <6>[ 0.692286] RPC: Registered tcp-with-tls transport module.
617 06:38:31.650651 <6>[ 0.698211] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 06:38:31.657940 <6>[ 0.705117] PCI: CLS 0 bytes, default 64
619 06:38:31.664425 <5>[ 0.710884] Initialise system trusted keyrings
620 06:38:31.668708 <6>[ 0.716519] Trying to unpack rootfs image as initramfs...
621 06:38:31.723281 <6>[ 0.767754] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 06:38:31.727992 <6>[ 0.775237] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 06:38:31.766817 <5>[ 0.817576] NFS: Registering the id_resolver key type
624 06:38:31.772614 <5>[ 0.823169] Key type id_resolver registered
625 06:38:31.778405 <5>[ 0.827842] Key type id_legacy registered
626 06:38:31.784151 <6>[ 0.832284] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 06:38:31.793716 <6>[ 0.839488] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 06:38:31.839956 <5>[ 0.890856] Key type asymmetric registered
629 06:38:31.845904 <5>[ 0.895377] Asymmetric key parser 'x509' registered
630 06:38:31.857398 <6>[ 0.900849] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 06:38:31.857676 <6>[ 0.908771] io scheduler mq-deadline registered
632 06:38:31.863146 <6>[ 0.913702] io scheduler kyber registered
633 06:38:31.868733 <6>[ 0.918170] io scheduler bfq registered
634 06:38:32.211711 <6>[ 1.258651] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
635 06:38:32.266660 <6>[ 1.317302] msm_serial: driver initialized
636 06:38:32.272661 <6>[ 1.322091] SuperH (H)SCI(F) driver initialized
637 06:38:32.278496 <6>[ 1.327266] STMicroelectronics ASC driver initialized
638 06:38:32.281674 <6>[ 1.332850] STM32 USART driver initialized
639 06:38:32.399109 <6>[ 1.449271] brd: module loaded
640 06:38:32.430499 <6>[ 1.480624] loop: module loaded
641 06:38:32.464533 <6>[ 1.514432] CAN device driver interface
642 06:38:32.470995 <6>[ 1.519638] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
643 06:38:32.476868 <6>[ 1.526537] e1000e: Intel(R) PRO/1000 Network Driver
644 06:38:32.482623 <6>[ 1.531982] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
645 06:38:32.488390 <6>[ 1.538422] igb: Intel(R) Gigabit Ethernet Network Driver
646 06:38:32.496542 <6>[ 1.544247] igb: Copyright (c) 2007-2014 Intel Corporation.
647 06:38:32.508268 <6>[ 1.553429] pegasus: Pegasus/Pegasus II USB Ethernet driver
648 06:38:32.514129 <6>[ 1.559572] usbcore: registered new interface driver pegasus
649 06:38:32.516864 <6>[ 1.565695] usbcore: registered new interface driver asix
650 06:38:32.522622 <6>[ 1.571595] usbcore: registered new interface driver ax88179_178a
651 06:38:32.528381 <6>[ 1.578186] usbcore: registered new interface driver cdc_ether
652 06:38:32.534280 <6>[ 1.584498] usbcore: registered new interface driver smsc75xx
653 06:38:32.542924 <6>[ 1.590733] usbcore: registered new interface driver smsc95xx
654 06:38:32.548500 <6>[ 1.596942] usbcore: registered new interface driver net1080
655 06:38:32.554294 <6>[ 1.603081] usbcore: registered new interface driver cdc_subset
656 06:38:32.562992 <6>[ 1.609484] usbcore: registered new interface driver zaurus
657 06:38:32.568044 <6>[ 1.615559] usbcore: registered new interface driver cdc_ncm
658 06:38:32.577950 <6>[ 1.625033] usbcore: registered new interface driver usb-storage
659 06:38:32.702854 <6>[ 1.751770] i2c_dev: i2c /dev entries driver
660 06:38:32.761168 <5>[ 1.803868] cpuidle: enable-method property 'ti,am3352' found operations
661 06:38:32.767028 <6>[ 1.813515] sdhci: Secure Digital Host Controller Interface driver
662 06:38:32.774369 <6>[ 1.820282] sdhci: Copyright(c) Pierre Ossman
663 06:38:32.781615 <6>[ 1.826703] Synopsys Designware Multimedia Card Interface Driver
664 06:38:32.787057 <6>[ 1.834648] sdhci-pltfm: SDHCI platform and OF driver helper
665 06:38:32.840686 <6>[ 1.887886] ledtrig-cpu: registered to indicate activity on CPUs
666 06:38:32.885045 <6>[ 1.928520] usbcore: registered new interface driver usbhid
667 06:38:32.885326 <6>[ 1.934554] usbhid: USB HID core driver
668 06:38:32.928949 <6>[ 1.977224] NET: Registered PF_INET6 protocol family
669 06:38:32.977515 <6>[ 2.028408] Segment Routing with IPv6
670 06:38:32.983416 <6>[ 2.032553] In-situ OAM (IOAM) with IPv6
671 06:38:32.990130 <6>[ 2.036944] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 06:38:32.995878 <6>[ 2.044283] NET: Registered PF_PACKET protocol family
673 06:38:33.001769 <6>[ 2.049830] can: controller area network core
674 06:38:33.007483 <6>[ 2.054653] NET: Registered PF_CAN protocol family
675 06:38:33.007754 <6>[ 2.059871] can: raw protocol
676 06:38:33.013231 <6>[ 2.063198] can: broadcast manager protocol
677 06:38:33.019731 <6>[ 2.067791] can: netlink gateway - max_hops=1
678 06:38:33.025857 <5>[ 2.073263] Key type dns_resolver registered
679 06:38:33.032108 <6>[ 2.078328] ThumbEE CPU extension supported.
680 06:38:33.032396 <5>[ 2.083013] Registering SWP/SWPB emulation handler
681 06:38:33.041908 <3>[ 2.088706] omap_voltage_late_init: Voltage driver support not added
682 06:38:33.109366 <5>[ 2.157729] Loading compiled-in X.509 certificates
683 06:38:33.248266 <6>[ 2.286093] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 06:38:33.255407 <6>[ 2.302747] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 06:38:33.281570 <3>[ 2.326299] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 06:38:33.371358 <3>[ 2.416148] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 06:38:33.468887 <6>[ 2.517932] OMAP GPIO hardware version 0.1
688 06:38:33.489317 <6>[ 2.536451] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 06:38:33.562669 <4>[ 2.609537] at24 2-0054: supply vcc not found, using dummy regulator
690 06:38:33.616388 <4>[ 2.663255] at24 2-0055: supply vcc not found, using dummy regulator
691 06:38:33.664078 <4>[ 2.710843] at24 2-0056: supply vcc not found, using dummy regulator
692 06:38:33.703709 <4>[ 2.750466] at24 2-0057: supply vcc not found, using dummy regulator
693 06:38:33.747923 <6>[ 2.795490] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 06:38:33.826077 <3>[ 2.869660] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 06:38:33.850530 <6>[ 2.890515] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 06:38:33.871564 <4>[ 2.916908] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 06:38:33.912441 <4>[ 2.958056] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 06:38:33.960704 <6>[ 3.007677] omap_rng 48310000.rng: Random Number Generator ver. 20
699 06:38:33.983945 <5>[ 3.033674] random: crng init done
700 06:38:34.088929 <6>[ 3.134362] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
701 06:38:34.737254 <6>[ 3.786378] Freeing initrd memory: 14448K
702 06:38:34.774677 <6>[ 3.819463] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 06:38:34.780431 <6>[ 3.829660] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
704 06:38:34.792214 <6>[ 3.836928] cpsw-switch 4a100000.switch: ALE Table size 1024
705 06:38:34.798100 <6>[ 3.843370] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
706 06:38:34.809551 <6>[ 3.851505] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
707 06:38:34.816923 <6>[ 3.863144] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
708 06:38:34.828992 <5>[ 3.872183] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
709 06:38:34.856551 <3>[ 3.901728] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
710 06:38:34.862256 <6>[ 3.910309] edma 49000000.dma: TI EDMA DMA engine driver
711 06:38:34.932985 <3>[ 3.977428] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
712 06:38:34.946435 <6>[ 3.991659] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
713 06:38:34.965287 <3>[ 4.013543] l3-aon-clkctrl:0000:0: failed to disable
714 06:38:35.002804 <6>[ 4.047935] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
715 06:38:35.008443 <6>[ 4.057360] printk: legacy console [ttyS0] enabled
716 06:38:35.014048 <6>[ 4.057360] printk: legacy console [ttyS0] enabled
717 06:38:35.019796 <6>[ 4.067677] printk: legacy bootconsole [omap8250] disabled
718 06:38:35.025616 <6>[ 4.067677] printk: legacy bootconsole [omap8250] disabled
719 06:38:35.083551 <4>[ 4.127729] tps65217-pmic: Failed to locate of_node [id: -1]
720 06:38:35.087182 <4>[ 4.135098] tps65217-bl: Failed to locate of_node [id: -1]
721 06:38:35.103194 <6>[ 4.154300] tps65217 0-0024: TPS65217 ID 0xe version 1.2
722 06:38:35.121545 <6>[ 4.161231] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
723 06:38:35.133188 <6>[ 4.174920] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
724 06:38:35.138861 <6>[ 4.186767] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
725 06:38:35.161295 <6>[ 4.206669] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
726 06:38:35.167167 <6>[ 4.215910] sdhci-omap 48060000.mmc: Got CD GPIO
727 06:38:35.175220 <4>[ 4.221075] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
728 06:38:35.189806 <4>[ 4.234335] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
729 06:38:35.196297 <4>[ 4.243294] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
730 06:38:35.206094 <4>[ 4.251996] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
731 06:38:35.329109 <6>[ 4.375690] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
732 06:38:35.354094 <6>[ 4.399797] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
733 06:38:35.390293 <6>[ 4.434945] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 06:38:35.396977 <6>[ 4.443897] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
735 06:38:35.457635 <6>[ 4.499586] mmc1: new high speed MMC card at address 0001
736 06:38:35.457912 <6>[ 4.506613] mmcblk1: mmc1:0001 M62704 3.56 GiB
737 06:38:35.465847 <6>[ 4.515177] mmcblk1: p1
738 06:38:35.474205 <6>[ 4.519741] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
739 06:38:35.482581 <6>[ 4.527687] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
740 06:38:35.488383 <6>[ 4.535654] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
741 06:38:35.515256 <6>[ 4.558164] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 06:38:38.682732 <6>[ 7.727998] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
743 06:38:38.766134 <5>[ 7.777070] Sending DHCP requests ., OK
744 06:38:38.777399 <6>[ 7.821426] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.7
745 06:38:38.777673 <6>[ 7.829626] IP-Config: Complete:
746 06:38:38.788657 <6>[ 7.833164] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.7, mask=255.255.255.0, gw=192.168.11.1
747 06:38:38.794417 <6>[ 7.843793] host=192.168.11.7, domain=usen.ad.jp, nis-domain=(none)
748 06:38:38.806670 <6>[ 7.850893] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
749 06:38:38.806935 <6>[ 7.850925] nameserver0=192.168.11.1
750 06:38:38.812807 <6>[ 7.863169] clk: Disabling unused clocks
751 06:38:38.819327 <6>[ 7.867913] PM: genpd: Disabling unused power domains
752 06:38:38.838453 <6>[ 7.886070] Freeing unused kernel image (initmem) memory: 2048K
753 06:38:38.845913 <6>[ 7.895707] Run /init as init process
754 06:38:38.868134 Loading, please wait...
755 06:38:38.942525 Starting systemd-udevd version 252.22-1~deb12u1
756 06:38:42.094851 <4>[ 11.138833] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
757 06:38:42.306584 <4>[ 11.350534] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
758 06:38:42.556236 <6>[ 11.607782] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
759 06:38:42.567106 <6>[ 11.613463] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
760 06:38:42.606250 <6>[ 11.655871] tda998x 0-0070: found TDA19988
761 06:38:42.691520 <6>[ 11.741421] hub 1-0:1.0: USB hub found
762 06:38:42.706712 <6>[ 11.756558] hub 1-0:1.0: 1 port detected
763 06:38:45.389050 Begin: Loading essential drivers ... done.
764 06:38:45.396505 Begin: Running /scripts/init-premount ... done.
765 06:38:45.407847 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
766 06:38:45.414290 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
767 06:38:45.422288 Device /sys/class/net/eth0 found
768 06:38:45.422555 done.
769 06:38:45.480560 Begin: Waiting up to 180 secs for any network device to become available ... done.
770 06:38:45.561216 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
771 06:38:45.561494 IP-Config: eth0 guessed broadcast address 192.168.11.255
772 06:38:45.566837 IP-Config: eth0 complete (dhcp from 192.168.11.1):
773 06:38:45.577996 address: 192.168.11.7 broadcast: 192.168.11.255 netmask: 255.255.255.0
774 06:38:45.583592 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
775 06:38:45.589215 domain : usen.ad.jp
776 06:38:45.594141 rootserver: 192.168.11.1 rootpath:
777 06:38:45.594409 filename :
778 06:38:45.666220 done.
779 06:38:45.681723 Begin: Running /scripts/nfs-bottom ... done.
780 06:38:45.756716 Begin: Running /scripts/init-bottom ... done.
781 06:38:46.918931 <30>[ 15.966197] systemd[1]: System time before build time, advancing clock.
782 06:38:47.070472 <30>[ 16.091529] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
783 06:38:47.079859 <30>[ 16.128871] systemd[1]: Detected architecture arm.
784 06:38:47.092108
785 06:38:47.092414 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
786 06:38:47.092641
787 06:38:47.133591 <30>[ 16.181392] systemd[1]: Hostname set to <debian-bookworm-armhf>.
788 06:38:49.366616 <30>[ 18.413369] systemd[1]: Queued start job for default target graphical.target.
789 06:38:49.383716 <30>[ 18.428423] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
790 06:38:49.391235 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
791 06:38:49.426195 <30>[ 18.469987] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
792 06:38:49.433477 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
793 06:38:49.468594 <30>[ 18.512777] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
794 06:38:49.475832 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
795 06:38:49.513305 <30>[ 18.558798] systemd[1]: Created slice user.slice - User and Session Slice.
796 06:38:49.519970 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
797 06:38:49.556418 <30>[ 18.599226] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
798 06:38:49.569364 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
799 06:38:49.603109 <30>[ 18.648203] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
800 06:38:49.611090 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
801 06:38:49.653839 <30>[ 18.688035] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
802 06:38:49.660368 <30>[ 18.708529] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
803 06:38:49.668637 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
804 06:38:49.702115 <30>[ 18.747632] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
805 06:38:49.710326 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
806 06:38:49.742794 <30>[ 18.787932] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
807 06:38:49.751152 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
808 06:38:49.782652 <30>[ 18.827954] systemd[1]: Reached target paths.target - Path Units.
809 06:38:49.787775 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
810 06:38:49.822343 <30>[ 18.867635] systemd[1]: Reached target remote-fs.target - Remote File Systems.
811 06:38:49.829626 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
812 06:38:49.863464 <30>[ 18.908340] systemd[1]: Reached target slices.target - Slice Units.
813 06:38:49.868894 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
814 06:38:49.902338 <30>[ 18.947685] systemd[1]: Reached target swap.target - Swaps.
815 06:38:49.906438 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
816 06:38:49.942842 <30>[ 18.987930] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
817 06:38:49.951782 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
818 06:38:49.983583 <30>[ 19.028666] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
819 06:38:49.991936 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
820 06:38:50.082877 <30>[ 19.123207] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
821 06:38:50.095436 <30>[ 19.140615] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
822 06:38:50.103874 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
823 06:38:50.134702 <30>[ 19.181465] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
824 06:38:50.147200 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
825 06:38:50.185399 <30>[ 19.230078] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
826 06:38:50.193551 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
827 06:38:50.230762 <30>[ 19.274683] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
828 06:38:50.236387 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
829 06:38:50.274026 <30>[ 19.319129] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
830 06:38:50.282561 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
831 06:38:50.319909 <30>[ 19.358829] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
832 06:38:50.336471 <30>[ 19.375582] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
833 06:38:50.373321 <30>[ 19.419443] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
834 06:38:50.392042 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
835 06:38:50.453007 <30>[ 19.498851] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
836 06:38:50.468678 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
837 06:38:50.551665 <30>[ 19.596561] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
838 06:38:50.575410 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
839 06:38:50.624383 <30>[ 19.669782] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
840 06:38:50.642031 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
841 06:38:50.668009 <30>[ 19.713896] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
842 06:38:50.696070 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
843 06:38:50.753901 <30>[ 19.800314] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
844 06:38:50.766517 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
845 06:38:50.825377 <30>[ 19.870593] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
846 06:38:50.840001 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
847 06:38:50.894334 <30>[ 19.940596] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
848 06:38:50.907944 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
849 06:38:50.940073 <30>[ 19.986407] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
850 06:38:50.973044 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
851 06:38:51.009270 <28>[ 20.049128] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
852 06:38:51.017694 <28>[ 20.063159] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
853 06:38:51.053600 <30>[ 20.100360] systemd[1]: Starting systemd-journald.service - Journal Service...
854 06:38:51.082065 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
855 06:38:51.162320 <30>[ 20.208423] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
856 06:38:51.188141 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
857 06:38:51.253887 <30>[ 20.300165] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
858 06:38:51.292076 Starting [0;1;39msystemd-network-g… units from Kernel command line...
859 06:38:51.347962 <30>[ 20.392702] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
860 06:38:51.384413 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
861 06:38:51.454055 <30>[ 20.499616] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
862 06:38:51.489436 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
863 06:38:51.553842 <30>[ 20.600229] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
864 06:38:51.603334 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
865 06:38:51.642924 <30>[ 20.689162] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
866 06:38:51.678924 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
867 06:38:51.705669 <30>[ 20.750889] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
868 06:38:51.734952 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
869 06:38:51.845937 <30>[ 20.892876] systemd[1]: modprobe@configfs.service: Deactivated successfully.
870 06:38:51.891912 <30>[ 20.937718] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
871 06:38:51.921289 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
872 06:38:51.953111 <30>[ 20.998652] systemd[1]: Started systemd-journald.service - Journal Service.
873 06:38:51.959911 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
874 06:38:52.002548 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
875 06:38:52.037555 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
876 06:38:52.076910 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
877 06:38:52.097549 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
878 06:38:52.142031 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
879 06:38:52.175534 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
880 06:38:52.215791 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
881 06:38:52.262167 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
882 06:38:52.296529 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
883 06:38:52.362568 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
884 06:38:52.433680 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
885 06:38:52.483529 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
886 06:38:52.585675 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
887 06:38:52.677921 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
888 06:38:52.785629 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kerne<46>[ 21.826063] systemd-journald[163]: Received client request to flush runtime journal.
889 06:38:52.785902 l Configuration File System.
890 06:38:52.884171 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
891 06:38:53.154167 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
892 06:38:53.817608 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
893 06:38:53.884369 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
894 06:38:54.588973 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
895 06:38:54.754304 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
896 06:38:54.784159 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
897 06:38:54.821625 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
898 06:38:54.902295 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
899 06:38:54.948349 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
900 06:38:55.881782 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
901 06:38:55.989544 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
902 06:38:56.352770 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
903 06:38:56.586523 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
904 06:38:56.687669 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
905 06:38:57.780342 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
906 06:38:58.677048 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
907 06:38:59.202776 <5>[ 28.249425] cfg80211: Loading compiled-in X.509 certificates for regulatory database
908 06:38:59.516839 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
909 06:39:00.420925 <5>[ 29.469645] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
910 06:39:00.475761 <5>[ 29.522989] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
911 06:39:00.487423 <4>[ 29.533899] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
912 06:39:00.493354 <6>[ 29.543037] cfg80211: failed to load regulatory.db
913 06:39:01.544688 <46>[ 30.581370] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
914 06:39:01.570226 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
915 06:39:01.588589 <46>[ 30.628302] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
916 06:39:01.603015 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
917 06:39:09.752091 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
918 06:39:09.787836 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
919 06:39:09.823841 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
920 06:39:09.857452 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
921 06:39:09.957472 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
922 06:39:10.055931 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
923 06:39:10.123539 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
924 06:39:10.155889 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
925 06:39:10.189655 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
926 06:39:10.227735 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
927 06:39:10.267451 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
928 06:39:10.308075 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
929 06:39:10.363191 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
930 06:39:10.409300 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
931 06:39:10.453737 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
932 06:39:10.486458 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
933 06:39:10.538320 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
934 06:39:10.585263 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
935 06:39:10.623731 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
936 06:39:10.651831 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
937 06:39:10.692701 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
938 06:39:10.721854 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
939 06:39:10.754746 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
940 06:39:10.834351 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
941 06:39:10.869990 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
942 06:39:10.977668 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
943 06:39:11.086593 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
944 06:39:11.134629 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
945 06:39:11.185746 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
946 06:39:11.225620 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
947 06:39:11.384267 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
948 06:39:11.462597 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
949 06:39:11.522922 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
950 06:39:11.552774 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
951 06:39:11.564810 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
952 06:39:11.798377 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
953 06:39:12.107114 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
954 06:39:12.163604 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
955 06:39:12.218611 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
956 06:39:12.307274 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
957 06:39:12.473923 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
958 06:39:12.624917
959 06:39:12.625187 Debian GNU/Linux 12worm-armhf login: root (automatic login)
960 06:39:12.628266
961 06:39:12.985665 Linux debian-bookworm-armhf 6.11.0-rc6 #1 SMP Mon Sep 2 03:48:51 UTC 2024 armv7l
962 06:39:12.986014
963 06:39:12.991279 The programs included with the Debian GNU/Linux system are free software;
964 06:39:12.996892 the exact distribution terms for each program are described in the
965 06:39:13.002490 individual files in /usr/share/doc/*/copyright.
966 06:39:13.002757
967 06:39:13.010430 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
968 06:39:13.010698 permitted by applicable law.
969 06:39:17.646040 Unable to match end of the kernel message
971 06:39:17.646823 Setting prompt string to ['/ #']
972 06:39:17.647120 end: 2.4.4.1 login-action (duration 00:00:47) [common]
974 06:39:17.647793 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
975 06:39:17.648079 start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
976 06:39:17.648336 Setting prompt string to ['/ #']
977 06:39:17.648543 Forcing a shell prompt, looking for ['/ #']
979 06:39:17.699067 / #
980 06:39:17.699445 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
981 06:39:17.699700 Waiting using forced prompt support (timeout 00:02:30)
982 06:39:17.703897
983 06:39:17.709609 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
984 06:39:17.709941 start: 2.4.6 export-device-env (timeout 00:03:24) [common]
985 06:39:17.710198 Sending with 10 millisecond of delay
987 06:39:22.758726 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd'
988 06:39:22.769310 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1187659/extract-nfsrootfs-mzzqe6rd'
989 06:39:22.769815 Sending with 10 millisecond of delay
991 06:39:24.928109 / # export NFS_SERVER_IP='192.168.11.5'
992 06:39:24.938755 export NFS_SERVER_IP='192.168.11.5'
993 06:39:24.939371 end: 2.4.6 export-device-env (duration 00:00:07) [common]
994 06:39:24.939720 end: 2.4 uboot-commands (duration 00:01:43) [common]
995 06:39:24.940066 end: 2 uboot-action (duration 00:01:43) [common]
996 06:39:24.940441 start: 3 lava-test-retry (timeout 00:07:21) [common]
997 06:39:24.940792 start: 3.1 lava-test-shell (timeout 00:07:21) [common]
998 06:39:24.941064 Using namespace: common
1000 06:39:25.041822 / # #
1001 06:39:25.042212 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1002 06:39:25.046557 #
1003 06:39:25.052596 Using /lava-1187659
1005 06:39:25.153389 / # export SHELL=/bin/bash
1006 06:39:25.158150 export SHELL=/bin/bash
1008 06:39:25.264698 / # . /lava-1187659/environment
1009 06:39:25.269438 . /lava-1187659/environment
1011 06:39:25.381881 / # /lava-1187659/bin/lava-test-runner /lava-1187659/0
1012 06:39:25.382274 Test shell timeout: 10s (minimum of the action and connection timeout)
1013 06:39:25.386572 /lava-1187659/bin/lava-test-runner /lava-1187659/0
1014 06:39:25.808184 + export TESTRUN_ID=0_timesync-off
1015 06:39:25.816101 + TESTRUN_ID=0_timesync-off
1016 06:39:25.816406 + cd /lava-1187659/0/tests/0_timesync-off
1017 06:39:25.816683 ++ cat uuid
1018 06:39:25.832038 + UUID=1187659_1.6.2.4.1
1019 06:39:25.832363 + set +x
1020 06:39:25.837495 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1187659_1.6.2.4.1>
1021 06:39:25.837967 Received signal: <STARTRUN> 0_timesync-off 1187659_1.6.2.4.1
1022 06:39:25.838221 Starting test lava.0_timesync-off (1187659_1.6.2.4.1)
1023 06:39:25.838565 Skipping test definition patterns.
1024 06:39:25.840675 + systemctl stop systemd-timesyncd
1025 06:39:26.158600 + set +x
1026 06:39:26.159198 Received signal: <ENDRUN> 0_timesync-off 1187659_1.6.2.4.1
1027 06:39:26.159494 Ending use of test pattern.
1028 06:39:26.159739 Ending test lava.0_timesync-off (1187659_1.6.2.4.1), duration 0.32
1030 06:39:26.161680 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1187659_1.6.2.4.1>
1031 06:39:26.363279 + export TESTRUN_ID=1_kselftest-dt
1032 06:39:26.371297 + TESTRUN_ID=1_kselftest-dt
1033 06:39:26.371549 + cd /lava-1187659/0/tests/1_kselftest-dt
1034 06:39:26.371818 ++ cat uuid
1035 06:39:26.387528 + UUID=1187659_1.6.2.4.5
1036 06:39:26.387827 + set +x
1037 06:39:26.393117 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1187659_1.6.2.4.5>
1038 06:39:26.393380 + cd ./automated/linux/kselftest/
1039 06:39:26.393879 Received signal: <STARTRUN> 1_kselftest-dt 1187659_1.6.2.4.5
1040 06:39:26.394135 Starting test lava.1_kselftest-dt (1187659_1.6.2.4.5)
1041 06:39:26.394480 Skipping test definition patterns.
1042 06:39:26.421279 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1043 06:39:26.540604 INFO: install_deps skipped
1044 06:39:27.171964 --2024-09-02 06:39:27-- http://storage.kernelci.org/mainline/master/v6.11-rc6-19-g67784a74e258a/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1045 06:39:27.184637 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1046 06:39:27.299174 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1047 06:39:27.410488 HTTP request sent, awaiting response... 200 OK
1048 06:39:27.410787 Length: 3607880 (3.4M) [application/octet-stream]
1049 06:39:27.416081 Saving to: 'kselftest_armhf.tar.gz'
1050 06:39:27.416354
1051 06:39:28.942938 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 225KB/s kselftest_armhf.tar 5%[> ] 207.85K 468KB/s kselftest_armhf.tar 17%[==> ] 632.54K 868KB/s kselftest_armhf.tar 40%[=======> ] 1.41M 1.51MB/s kselftest_armhf.tar 64%[===========> ] 2.21M 1.88MB/s kselftest_armhf.tar 88%[================> ] 3.05M 2.22MB/s kselftest_armhf.tar 100%[===================>] 3.44M 2.25MB/s in 1.5s
1052 06:39:28.943330
1053 06:39:29.580630 2024-09-02 06:39:28 (2.25 MB/s) - 'kselftest_armhf.tar.gz' saved [3607880/3607880]
1054 06:39:29.580967
1055 06:39:48.784463 skiplist:
1056 06:39:48.784830 ========================================
1057 06:39:48.790111 ========================================
1058 06:39:48.890052 dt:test_unprobed_devices.sh
1059 06:39:48.921758 ============== Tests to run ===============
1060 06:39:48.929625 dt:test_unprobed_devices.sh
1061 06:39:48.933603 ===========End Tests to run ===============
1062 06:39:48.944902 shardfile-dt pass
1063 06:39:49.188358 <12>[ 78.240587] kselftest: Running tests in dt
1064 06:39:49.217777 TAP version 13
1065 06:39:49.241184 1..1
1066 06:39:49.294032 # timeout set to 45
1067 06:39:49.294299 # selftests: dt: test_unprobed_devices.sh
1068 06:39:50.172700 # TAP version 13
1069 06:40:02.065971 # 1..255
1070 06:40:02.236382 # ok 1 / # SKIP
1071 06:40:02.258906 # ok 2 /clk_mcasp0
1072 06:40:02.333489 # ok 3 /clk_mcasp0_fixed # SKIP
1073 06:40:02.397261 # ok 4 /cpus/cpu@0 # SKIP
1074 06:40:02.468626 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1075 06:40:02.493268 # ok 6 /fixedregulator0
1076 06:40:02.509471 # ok 7 /leds
1077 06:40:02.530994 # ok 8 /ocp
1078 06:40:02.555188 # ok 9 /ocp/interconnect@44c00000
1079 06:40:02.578201 # ok 10 /ocp/interconnect@44c00000/segment@0
1080 06:40:02.600544 # ok 11 /ocp/interconnect@44c00000/segment@100000
1081 06:40:02.625935 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1082 06:40:02.697421 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1083 06:40:02.720181 # ok 14 /ocp/interconnect@44c00000/segment@200000
1084 06:40:02.743058 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1085 06:40:02.847918 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1086 06:40:02.916431 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1087 06:40:02.987496 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1088 06:40:03.060905 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1089 06:40:03.129117 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1090 06:40:03.201468 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1091 06:40:03.271278 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1092 06:40:03.339396 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1093 06:40:03.412027 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1094 06:40:03.475398 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1095 06:40:03.551008 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1096 06:40:03.620219 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1097 06:40:03.689233 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1098 06:40:03.765853 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1099 06:40:03.836032 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1100 06:40:03.903212 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1101 06:40:03.974005 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1102 06:40:04.045540 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1103 06:40:04.115096 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1104 06:40:04.186672 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1105 06:40:04.259189 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1106 06:40:04.324642 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1107 06:40:04.396436 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1108 06:40:04.463223 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1109 06:40:04.530926 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1110 06:40:04.606105 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1111 06:40:04.676841 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1112 06:40:04.741090 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1113 06:40:04.817222 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1114 06:40:04.880271 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1115 06:40:04.957953 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1116 06:40:05.026525 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1117 06:40:05.099177 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1118 06:40:05.167153 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1119 06:40:05.239389 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1120 06:40:05.308135 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1121 06:40:05.380651 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1122 06:40:05.443900 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1123 06:40:05.521502 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1124 06:40:05.589341 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1125 06:40:05.658731 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1126 06:40:05.729590 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1127 06:40:05.797808 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1128 06:40:05.868742 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1129 06:40:05.932744 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1130 06:40:06.009581 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1131 06:40:06.078920 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1132 06:40:06.142750 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1133 06:40:06.220022 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1134 06:40:06.288460 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1135 06:40:06.352735 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1136 06:40:06.429601 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1137 06:40:06.493055 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1138 06:40:06.561184 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1139 06:40:06.640382 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1140 06:40:06.707338 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1141 06:40:06.779206 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1142 06:40:06.842443 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1143 06:40:06.919295 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1144 06:40:06.987485 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1145 06:40:07.059584 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1146 06:40:07.123099 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1147 06:40:07.200023 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1148 06:40:07.269091 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1149 06:40:07.338216 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1150 06:40:07.410711 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1151 06:40:07.480817 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1152 06:40:07.542249 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1153 06:40:07.620297 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1154 06:40:07.688175 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1155 06:40:07.759468 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1156 06:40:07.828704 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1157 06:40:07.900970 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1158 06:40:07.973294 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1159 06:40:08.036960 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1160 06:40:08.111797 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1161 06:40:08.177429 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1162 06:40:08.253065 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1163 06:40:08.321062 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1164 06:40:08.346137 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1165 06:40:08.362136 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1166 06:40:08.389813 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1167 06:40:08.412423 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1168 06:40:08.438957 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1169 06:40:08.456113 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1170 06:40:08.484409 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1171 06:40:08.506927 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1172 06:40:08.602882 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1173 06:40:08.628394 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1174 06:40:08.657937 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1175 06:40:08.673433 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1176 06:40:08.781208 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1177 06:40:08.851826 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1178 06:40:08.923593 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1179 06:40:08.993825 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1180 06:40:09.068077 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1181 06:40:09.136088 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1182 06:40:09.208685 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1183 06:40:09.270939 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1184 06:40:09.347965 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1185 06:40:09.418803 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1186 06:40:09.489301 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1187 06:40:09.552804 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1188 06:40:09.627686 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1189 06:40:09.699802 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1190 06:40:09.770704 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1191 06:40:09.838991 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1192 06:40:09.860072 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1193 06:40:09.930162 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1194 06:40:09.988829 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1195 06:40:10.065534 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1196 06:40:10.088853 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1197 06:40:10.151907 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1198 06:40:10.179291 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1199 06:40:10.248169 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1200 06:40:10.267691 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1201 06:40:10.296523 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1202 06:40:10.312407 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1203 06:40:10.337679 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1204 06:40:10.365453 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1205 06:40:10.381349 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1206 06:40:10.409158 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1207 06:40:10.436605 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1208 06:40:10.457267 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1209 06:40:10.523394 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1210 06:40:10.599408 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1211 06:40:10.617236 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1212 06:40:10.684282 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1213 06:40:10.756115 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1214 06:40:10.856154 # not ok 145 /ocp/interconnect@47c00000
1215 06:40:10.921889 # not ok 146 /ocp/interconnect@47c00000/segment@0
1216 06:40:10.944009 # ok 147 /ocp/interconnect@48000000
1217 06:40:10.965886 # ok 148 /ocp/interconnect@48000000/segment@0
1218 06:40:10.994149 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1219 06:40:11.018699 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1220 06:40:11.037400 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1221 06:40:11.062614 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1222 06:40:11.087686 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1223 06:40:11.107522 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1224 06:40:11.131725 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1225 06:40:11.201694 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1226 06:40:11.274326 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1227 06:40:11.295570 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1228 06:40:11.310519 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1229 06:40:11.338176 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1230 06:40:11.360958 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1231 06:40:11.385539 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1232 06:40:11.401896 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1233 06:40:11.425409 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1234 06:40:11.454533 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1235 06:40:11.473096 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1236 06:40:11.493386 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1237 06:40:11.516406 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1238 06:40:11.545376 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1239 06:40:11.560067 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1240 06:40:11.588750 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1241 06:40:11.605192 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1242 06:40:11.634950 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1243 06:40:11.650777 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1244 06:40:11.678147 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1245 06:40:11.696029 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1246 06:40:11.722061 # ok 177 /ocp/interconnect@48000000/segment@100000
1247 06:40:11.747948 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1248 06:40:11.763254 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1249 06:40:11.841360 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1250 06:40:11.909758 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1251 06:40:11.974705 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1252 06:40:12.048543 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1253 06:40:12.068822 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1254 06:40:12.086739 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1255 06:40:12.115762 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1256 06:40:12.131756 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1257 06:40:12.155805 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1258 06:40:12.185401 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1259 06:40:12.207542 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1260 06:40:12.229256 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1261 06:40:12.246581 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1262 06:40:12.274201 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1263 06:40:12.298865 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1264 06:40:12.319407 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1265 06:40:12.339212 # ok 196 /ocp/interconnect@48000000/segment@200000
1266 06:40:12.362520 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1267 06:40:12.435472 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1268 06:40:12.448015 # ok 199 /ocp/interconnect@48000000/segment@300000
1269 06:40:12.471612 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1270 06:40:12.501496 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1271 06:40:12.523503 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1272 06:40:12.545741 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1273 06:40:12.562123 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1274 06:40:12.587237 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1275 06:40:12.655902 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1276 06:40:12.678165 # ok 207 /ocp/interconnect@4a000000
1277 06:40:12.695971 # ok 208 /ocp/interconnect@4a000000/segment@0
1278 06:40:12.725504 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1279 06:40:12.749118 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1280 06:40:12.771128 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1281 06:40:12.795463 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1282 06:40:12.865222 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1283 06:40:12.969490 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1284 06:40:13.040771 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1285 06:40:13.136035 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1286 06:40:13.210473 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1287 06:40:13.280467 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1288 06:40:13.375813 # not ok 219 /ocp/interconnect@4b140000
1289 06:40:13.444947 # not ok 220 /ocp/interconnect@4b140000/segment@0
1290 06:40:13.514554 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1291 06:40:13.541355 # ok 222 /ocp/target-module@40300000
1292 06:40:13.555884 # ok 223 /ocp/target-module@40300000/sram@0
1293 06:40:13.634365 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1294 06:40:13.704706 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1295 06:40:13.725256 # ok 226 /ocp/target-module@47400000
1296 06:40:13.744633 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1297 06:40:13.768246 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1298 06:40:13.785655 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1299 06:40:13.807800 # ok 230 /ocp/target-module@47400000/usb@1400
1300 06:40:13.829648 # ok 231 /ocp/target-module@47400000/usb@1800
1301 06:40:13.852876 # ok 232 /ocp/target-module@47810000
1302 06:40:13.874189 # ok 233 /ocp/target-module@49000000
1303 06:40:13.895220 # ok 234 /ocp/target-module@49000000/dma@0
1304 06:40:13.921494 # ok 235 /ocp/target-module@49800000
1305 06:40:13.944351 # ok 236 /ocp/target-module@49800000/dma@0
1306 06:40:13.963741 # ok 237 /ocp/target-module@49900000
1307 06:40:13.983770 # ok 238 /ocp/target-module@49900000/dma@0
1308 06:40:14.003578 # ok 239 /ocp/target-module@49a00000
1309 06:40:14.030284 # ok 240 /ocp/target-module@49a00000/dma@0
1310 06:40:14.052758 # ok 241 /ocp/target-module@4c000000
1311 06:40:14.121217 # not ok 242 /ocp/target-module@4c000000/emif@0
1312 06:40:14.142593 # ok 243 /ocp/target-module@50000000
1313 06:40:14.163781 # ok 244 /ocp/target-module@53100000
1314 06:40:14.236950 # not ok 245 /ocp/target-module@53100000/sham@0
1315 06:40:14.250859 # ok 246 /ocp/target-module@53500000
1316 06:40:14.322496 # not ok 247 /ocp/target-module@53500000/aes@0
1317 06:40:14.343231 # ok 248 /ocp/target-module@56000000
1318 06:40:14.446520 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1319 06:40:14.516474 # ok 250 /opp-table # SKIP
1320 06:40:14.587368 # ok 251 /soc # SKIP
1321 06:40:14.599634 # ok 252 /sound
1322 06:40:14.628141 # ok 253 /target-module@4b000000
1323 06:40:14.652073 # ok 254 /target-module@4b000000/target-module@140000
1324 06:40:14.668050 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1325 06:40:14.675893 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1326 06:40:14.682715 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1327 06:40:16.801113 dt_test_unprobed_devices_sh_ skip
1328 06:40:16.806681 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1329 06:40:16.812308 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1330 06:40:16.812584 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1331 06:40:16.817930 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1332 06:40:16.823431 dt_test_unprobed_devices_sh_fixedregulator0 pass
1333 06:40:16.829066 dt_test_unprobed_devices_sh_leds pass
1334 06:40:16.829340 dt_test_unprobed_devices_sh_ocp pass
1335 06:40:16.834671 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1336 06:40:16.840296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1337 06:40:16.845932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1338 06:40:16.857172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1339 06:40:16.862677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1340 06:40:16.868312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1341 06:40:16.879549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1342 06:40:16.885174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1343 06:40:16.896450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1344 06:40:16.907554 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1345 06:40:16.918809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1346 06:40:16.924450 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1347 06:40:16.935553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1348 06:40:16.946802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1349 06:40:16.958079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1350 06:40:16.969297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1351 06:40:16.974809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1352 06:40:16.986054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1353 06:40:16.997174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1354 06:40:17.008435 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1355 06:40:17.019549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1356 06:40:17.025178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1357 06:40:17.036311 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1358 06:40:17.047551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1359 06:40:17.058675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1360 06:40:17.064306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1361 06:40:17.075545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1362 06:40:17.086680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1363 06:40:17.098087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1364 06:40:17.109116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1365 06:40:17.114681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1366 06:40:17.125953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1367 06:40:17.137051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1368 06:40:17.148321 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1369 06:40:17.159439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1370 06:40:17.170669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1371 06:40:17.181827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1372 06:40:17.193082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1373 06:40:17.204302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1374 06:40:17.215363 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1375 06:40:17.226484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1376 06:40:17.237800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1377 06:40:17.249004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1378 06:40:17.260245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1379 06:40:17.271405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1380 06:40:17.282530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1381 06:40:17.293678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1382 06:40:17.304879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1383 06:40:17.316102 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1384 06:40:17.327252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1385 06:40:17.338529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1386 06:40:17.349673 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1387 06:40:17.360891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1388 06:40:17.371978 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1389 06:40:17.383285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1390 06:40:17.394441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1391 06:40:17.400034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1392 06:40:17.411286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1393 06:40:17.422413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1394 06:40:17.433681 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1395 06:40:17.444806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1396 06:40:17.456056 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1397 06:40:17.467286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1398 06:40:17.478423 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1399 06:40:17.489519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1400 06:40:17.500798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1401 06:40:17.511910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1402 06:40:17.523170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1403 06:40:17.534278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1404 06:40:17.545532 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1405 06:40:17.556663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1406 06:40:17.567846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1407 06:40:17.579030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1408 06:40:17.590276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1409 06:40:17.595908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1410 06:40:17.607029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1411 06:40:17.618291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1412 06:40:17.629417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1413 06:40:17.640658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1414 06:40:17.646276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1415 06:40:17.663025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1416 06:40:17.674291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1417 06:40:17.679779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1418 06:40:17.696527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1419 06:40:17.707776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1420 06:40:17.719025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1421 06:40:17.724560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1422 06:40:17.735772 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1423 06:40:17.746951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1424 06:40:17.752548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1425 06:40:17.763771 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1426 06:40:17.774893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1427 06:40:17.780530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1428 06:40:17.791643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1429 06:40:17.797273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1430 06:40:17.808525 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1431 06:40:17.819646 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1432 06:40:17.830887 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1433 06:40:17.842018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1434 06:40:17.853270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1435 06:40:17.864405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1436 06:40:17.875640 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1437 06:40:17.886768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1438 06:40:17.898021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1439 06:40:17.909269 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1440 06:40:17.920399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1441 06:40:17.931516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1442 06:40:17.948394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1443 06:40:17.959493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1444 06:40:17.970764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1445 06:40:17.981890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1446 06:40:17.993141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1447 06:40:18.009891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1448 06:40:18.021153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1449 06:40:18.032305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1450 06:40:18.043510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1451 06:40:18.049018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1452 06:40:18.060289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1453 06:40:18.071385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1454 06:40:18.076992 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1455 06:40:18.088286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1456 06:40:18.093761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1457 06:40:18.105125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1458 06:40:18.110645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1459 06:40:18.121773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1460 06:40:18.127398 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1461 06:40:18.138649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1462 06:40:18.144286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1463 06:40:18.155387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1464 06:40:18.166512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1465 06:40:18.177764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1466 06:40:18.183390 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1467 06:40:18.194511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1468 06:40:18.205791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1469 06:40:18.211414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1470 06:40:18.222557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1471 06:40:18.228149 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1472 06:40:18.233809 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1473 06:40:18.239283 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1474 06:40:18.244917 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1475 06:40:18.256098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1476 06:40:18.261666 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1477 06:40:18.267289 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1478 06:40:18.278513 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1479 06:40:18.284014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1480 06:40:18.295257 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1481 06:40:18.300902 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1482 06:40:18.312006 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1483 06:40:18.317639 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1484 06:40:18.323261 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1485 06:40:18.334380 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1486 06:40:18.340008 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1487 06:40:18.351282 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1488 06:40:18.356760 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1489 06:40:18.368004 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1490 06:40:18.373647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1491 06:40:18.384778 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1492 06:40:18.390384 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1493 06:40:18.401506 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1494 06:40:18.407274 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1495 06:40:18.418364 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1496 06:40:18.423886 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1497 06:40:18.435152 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1498 06:40:18.440743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1499 06:40:18.446349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1500 06:40:18.457488 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1501 06:40:18.463113 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1502 06:40:18.474215 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1503 06:40:18.479837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1504 06:40:18.491101 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1505 06:40:18.496636 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1506 06:40:18.507938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1507 06:40:18.519077 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1508 06:40:18.530187 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1509 06:40:18.535878 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1510 06:40:18.546941 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1511 06:40:18.552570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1512 06:40:18.563795 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1513 06:40:18.569367 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1514 06:40:18.580568 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1515 06:40:18.586194 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1516 06:40:18.597318 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1517 06:40:18.608576 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1518 06:40:18.614221 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1519 06:40:18.625345 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1520 06:40:18.630968 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1521 06:40:18.642216 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1522 06:40:18.647715 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1523 06:40:18.653395 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1524 06:40:18.664495 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1525 06:40:18.670217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1526 06:40:18.675717 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1527 06:40:18.686872 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1528 06:40:18.692466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1529 06:40:18.703748 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1530 06:40:18.709369 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1531 06:40:18.720464 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1532 06:40:18.726152 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1533 06:40:18.731719 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1534 06:40:18.737312 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1535 06:40:18.748661 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1536 06:40:18.754111 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1537 06:40:18.765299 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1538 06:40:18.770890 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1539 06:40:18.782113 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1540 06:40:18.793186 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1541 06:40:18.804455 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1542 06:40:18.809948 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1543 06:40:18.821203 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1544 06:40:18.832339 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1545 06:40:18.837932 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1546 06:40:18.843551 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1547 06:40:18.849186 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1548 06:40:18.854742 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1549 06:40:18.860372 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1550 06:40:18.865990 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1551 06:40:18.877222 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1552 06:40:18.882823 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1553 06:40:18.888488 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1554 06:40:18.893937 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1555 06:40:18.899583 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1556 06:40:18.905240 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1557 06:40:18.910836 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1558 06:40:18.916461 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1559 06:40:18.921954 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1560 06:40:18.927559 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1561 06:40:18.933207 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1562 06:40:18.938807 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1563 06:40:18.944335 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1564 06:40:18.949931 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1565 06:40:18.955557 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1566 06:40:18.961204 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1567 06:40:18.966811 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1568 06:40:18.972342 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1569 06:40:18.978029 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1570 06:40:18.983701 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1571 06:40:18.989287 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1572 06:40:18.994882 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1573 06:40:19.000524 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1574 06:40:19.006009 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1575 06:40:19.011634 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1576 06:40:19.017256 dt_test_unprobed_devices_sh_opp-table skip
1577 06:40:19.022885 dt_test_unprobed_devices_sh_soc skip
1578 06:40:19.023161 dt_test_unprobed_devices_sh_sound pass
1579 06:40:19.028511 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1580 06:40:19.034006 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1581 06:40:19.045254 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1582 06:40:19.045532 dt_test_unprobed_devices_sh fail
1583 06:40:19.050878 + ../../utils/send-to-lava.sh ./output/result.txt
1584 06:40:19.056331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1585 06:40:19.056898 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1587 06:40:19.094356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1588 06:40:19.094852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1590 06:40:19.189755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1591 06:40:19.190342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1593 06:40:19.283943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1594 06:40:19.284454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1596 06:40:19.377518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1597 06:40:19.378010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1599 06:40:19.471061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1600 06:40:19.471544 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1602 06:40:19.564088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1603 06:40:19.564628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1605 06:40:19.658447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1606 06:40:19.658937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1608 06:40:19.751853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1609 06:40:19.752336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1611 06:40:19.848296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1612 06:40:19.848780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1614 06:40:19.940445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1615 06:40:19.940928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1617 06:40:20.033822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1618 06:40:20.034305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1620 06:40:20.125496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1621 06:40:20.126061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1623 06:40:20.224948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1624 06:40:20.225430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1626 06:40:20.325593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1627 06:40:20.326076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1629 06:40:20.422003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1630 06:40:20.422484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1632 06:40:20.523429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1633 06:40:20.523912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1635 06:40:20.621801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1636 06:40:20.622286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1638 06:40:20.714426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1639 06:40:20.714908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1641 06:40:20.811042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1642 06:40:20.811530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1644 06:40:20.905547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1645 06:40:20.906034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1647 06:40:20.999910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1648 06:40:21.000433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1650 06:40:21.090661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1651 06:40:21.091146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1653 06:40:21.187372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1654 06:40:21.187925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1656 06:40:21.288392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1657 06:40:21.288874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1659 06:40:21.381271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1660 06:40:21.381753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1662 06:40:21.479894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1663 06:40:21.480378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1665 06:40:21.579027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1666 06:40:21.579514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1668 06:40:21.674367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1669 06:40:21.674851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1671 06:40:21.771343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1672 06:40:21.771829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1674 06:40:21.868127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1675 06:40:21.868644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1677 06:40:21.965088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1678 06:40:21.965573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1680 06:40:22.061593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1681 06:40:22.062079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1683 06:40:22.157801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1684 06:40:22.158359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1686 06:40:22.248906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1687 06:40:22.249386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1689 06:40:22.343254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1690 06:40:22.343726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1692 06:40:22.433282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1693 06:40:22.433750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1695 06:40:22.525445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1696 06:40:22.525923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1698 06:40:22.618149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1699 06:40:22.618628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1701 06:40:22.713050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1702 06:40:22.713525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1704 06:40:22.805225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1705 06:40:22.805716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1707 06:40:22.905292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1708 06:40:22.905767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1710 06:40:22.997458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1711 06:40:22.997935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1713 06:40:23.087664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1714 06:40:23.088186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1716 06:40:23.183467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1717 06:40:23.184075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1719 06:40:23.280153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1720 06:40:23.280651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1722 06:40:23.380153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1723 06:40:23.380660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1725 06:40:23.476544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1726 06:40:23.477027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1728 06:40:23.573027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1729 06:40:23.573522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1731 06:40:23.670232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1732 06:40:23.670714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1734 06:40:23.764159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1735 06:40:23.764671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1737 06:40:23.860731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1738 06:40:23.861213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1740 06:40:23.954448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1741 06:40:23.954939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1743 06:40:24.052213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1744 06:40:24.052701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1746 06:40:24.149781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1747 06:40:24.150357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1749 06:40:24.241075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1750 06:40:24.241558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1752 06:40:24.337095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1753 06:40:24.337590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1755 06:40:24.430432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1756 06:40:24.430909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1758 06:40:24.525049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1759 06:40:24.525529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1761 06:40:24.620455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1762 06:40:24.620961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1764 06:40:24.718931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1765 06:40:24.719432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1767 06:40:24.815083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1768 06:40:24.815575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1770 06:40:24.910802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1771 06:40:24.911303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1773 06:40:25.009798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1774 06:40:25.010275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1776 06:40:25.109718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1777 06:40:25.110207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1779 06:40:25.206555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1780 06:40:25.207127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1782 06:40:25.302574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1783 06:40:25.303084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1785 06:40:25.401671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1786 06:40:25.402163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1788 06:40:25.496788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1789 06:40:25.497252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1791 06:40:25.594710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1792 06:40:25.595197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1794 06:40:25.691778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1795 06:40:25.692262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1797 06:40:25.788590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1798 06:40:25.789089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1800 06:40:25.886263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1801 06:40:25.886749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1803 06:40:25.984179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1804 06:40:25.984709 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1806 06:40:26.080229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1807 06:40:26.080707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1809 06:40:26.171683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1810 06:40:26.172258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1812 06:40:26.267551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1813 06:40:26.268028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1815 06:40:26.360374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1816 06:40:26.360852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1818 06:40:26.454200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1819 06:40:26.454672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1821 06:40:26.550412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1822 06:40:26.550888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1824 06:40:26.645691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1825 06:40:26.646176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1827 06:40:26.741686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1828 06:40:26.742162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1830 06:40:26.837816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1831 06:40:26.838294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1833 06:40:26.932366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1834 06:40:26.932852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1836 06:40:27.029176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1837 06:40:27.029671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1839 06:40:27.122221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1840 06:40:27.122705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1842 06:40:27.218334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1843 06:40:27.218911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1845 06:40:27.314386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1846 06:40:27.314871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1848 06:40:27.408075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1849 06:40:27.408590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1851 06:40:27.506196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1852 06:40:27.506678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1854 06:40:27.600255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1855 06:40:27.600734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1857 06:40:27.694999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1858 06:40:27.695470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1860 06:40:27.791182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1861 06:40:27.791672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1863 06:40:27.886746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1864 06:40:27.887223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1866 06:40:27.982757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1867 06:40:27.983233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1869 06:40:28.075805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1870 06:40:28.076261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1872 06:40:28.172347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1873 06:40:28.172903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1875 06:40:28.266530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1876 06:40:28.267014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1878 06:40:28.360402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1879 06:40:28.360887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1881 06:40:28.457164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1882 06:40:28.457650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1884 06:40:28.549414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1885 06:40:28.549908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1887 06:40:28.644049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1888 06:40:28.644574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1890 06:40:28.737963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1891 06:40:28.738441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1893 06:40:28.833459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1894 06:40:28.833944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1896 06:40:28.928832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1897 06:40:28.929306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1899 06:40:29.024881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1900 06:40:29.025367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1902 06:40:29.119077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1903 06:40:29.119563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1905 06:40:29.214236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1906 06:40:29.214798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1908 06:40:29.315325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1909 06:40:29.315811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1911 06:40:29.409068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1912 06:40:29.409555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1914 06:40:29.501692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1915 06:40:29.502178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1917 06:40:29.598330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1918 06:40:29.598821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1920 06:40:29.691058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1921 06:40:29.691545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1923 06:40:29.785056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1924 06:40:29.785545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1926 06:40:29.879305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1927 06:40:29.879794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1929 06:40:29.976174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1930 06:40:29.976688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1932 06:40:30.071554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1933 06:40:30.072080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1935 06:40:30.169932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1936 06:40:30.170504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1938 06:40:30.265413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1939 06:40:30.265900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1941 06:40:30.362413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1942 06:40:30.362925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1944 06:40:30.458073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1946 06:40:30.461004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1947 06:40:30.554286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1949 06:40:30.557317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1950 06:40:30.656441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1952 06:40:30.659416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1953 06:40:30.751390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1954 06:40:30.751896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1956 06:40:30.845610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1957 06:40:30.846093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1959 06:40:30.938385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1960 06:40:30.938872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1962 06:40:31.038026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1963 06:40:31.038553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1965 06:40:31.136061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1966 06:40:31.136579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1968 06:40:31.229878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1969 06:40:31.230444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1971 06:40:31.326617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1972 06:40:31.327102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1974 06:40:31.419889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1975 06:40:31.420374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1977 06:40:31.518128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1978 06:40:31.518613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1980 06:40:31.614106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1981 06:40:31.614619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1983 06:40:31.708873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1984 06:40:31.709359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1986 06:40:31.806855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1987 06:40:31.807357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1989 06:40:31.899348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1990 06:40:31.899838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1992 06:40:31.995867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1993 06:40:31.996352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1995 06:40:32.093594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1996 06:40:32.094101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1998 06:40:32.189097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1999 06:40:32.189687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2001 06:40:32.286960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2002 06:40:32.287446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2004 06:40:32.380460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2005 06:40:32.380959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2007 06:40:32.477089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2008 06:40:32.477570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2010 06:40:32.570320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2011 06:40:32.570805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2013 06:40:32.667828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2014 06:40:32.668306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2016 06:40:32.765570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2017 06:40:32.766080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2019 06:40:32.853841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2020 06:40:32.854323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2022 06:40:32.950211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2023 06:40:32.950700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2025 06:40:33.044347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2026 06:40:33.044832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2028 06:40:33.141996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2029 06:40:33.142478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2031 06:40:33.239834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2032 06:40:33.240432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2034 06:40:33.334199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2035 06:40:33.334708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2037 06:40:33.430820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2038 06:40:33.431322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2040 06:40:33.524919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2041 06:40:33.525404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2043 06:40:33.618935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2044 06:40:33.619426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2046 06:40:33.714537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2047 06:40:33.715039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2049 06:40:33.807558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2050 06:40:33.808042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2052 06:40:33.902427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2053 06:40:33.902913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2055 06:40:33.999285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2056 06:40:33.999767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2058 06:40:34.095044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2059 06:40:34.095528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2061 06:40:34.193027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2062 06:40:34.193593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2064 06:40:34.287560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2065 06:40:34.288043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2067 06:40:34.383264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2068 06:40:34.383746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2070 06:40:34.478161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2071 06:40:34.478646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2073 06:40:34.572681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2074 06:40:34.573167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2076 06:40:34.668020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2077 06:40:34.668527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2079 06:40:34.764872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2080 06:40:34.765367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2082 06:40:34.861398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2083 06:40:34.861896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2085 06:40:34.957888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2086 06:40:34.958397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2088 06:40:35.057162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2089 06:40:35.057652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2091 06:40:35.160532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2092 06:40:35.161167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2094 06:40:35.255641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2095 06:40:35.256191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2097 06:40:35.350754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2098 06:40:35.351235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2100 06:40:35.445757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2101 06:40:35.446243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2103 06:40:35.538873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2104 06:40:35.539356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2106 06:40:35.639200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2107 06:40:35.639685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2109 06:40:35.733862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2110 06:40:35.734358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2112 06:40:35.833340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2113 06:40:35.833834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2115 06:40:35.926970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2116 06:40:35.927452 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2118 06:40:36.023730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2119 06:40:36.024239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2121 06:40:36.119473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2122 06:40:36.119956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2124 06:40:36.217211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2125 06:40:36.217787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2127 06:40:36.311050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2128 06:40:36.311531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2130 06:40:36.410833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2131 06:40:36.411321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2133 06:40:36.505721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2134 06:40:36.506220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2136 06:40:36.597123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2137 06:40:36.597625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2139 06:40:36.689786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2140 06:40:36.690273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2142 06:40:36.786693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2143 06:40:36.787192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2145 06:40:36.881881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2146 06:40:36.882366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2148 06:40:36.976999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2149 06:40:36.977485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2151 06:40:37.073235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2152 06:40:37.073718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2154 06:40:37.169107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2155 06:40:37.169736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2157 06:40:37.266590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2158 06:40:37.267097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2160 06:40:37.364072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2161 06:40:37.364602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2163 06:40:37.458675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2164 06:40:37.459152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2166 06:40:37.551051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2167 06:40:37.551527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2169 06:40:37.646173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2170 06:40:37.646649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2172 06:40:37.735919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2173 06:40:37.736394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2175 06:40:37.829366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2176 06:40:37.829863 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2178 06:40:37.926414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2179 06:40:37.926923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2181 06:40:38.018272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2182 06:40:38.018758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2184 06:40:38.116968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2185 06:40:38.117449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2187 06:40:38.216158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2188 06:40:38.216728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2190 06:40:38.310020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2191 06:40:38.310481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2193 06:40:38.406413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2194 06:40:38.406871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2196 06:40:38.514227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2197 06:40:38.514712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2199 06:40:38.623215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2200 06:40:38.623704 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2202 06:40:38.717553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2203 06:40:38.718105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2205 06:40:38.803911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2206 06:40:38.804395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2208 06:40:38.898295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2209 06:40:38.898801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2211 06:40:38.994170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2212 06:40:38.994673 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2214 06:40:39.088279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2215 06:40:39.088806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2217 06:40:39.181851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2218 06:40:39.182431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2220 06:40:39.273836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2221 06:40:39.274310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2223 06:40:39.365129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2224 06:40:39.365611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2226 06:40:39.458399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2227 06:40:39.458887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2229 06:40:39.550066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2230 06:40:39.550559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2232 06:40:39.639800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2233 06:40:39.640269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2235 06:40:39.733871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2236 06:40:39.734358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2238 06:40:39.824708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2239 06:40:39.825183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2241 06:40:39.911337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2242 06:40:39.911811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2244 06:40:40.005266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2245 06:40:40.005749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2247 06:40:40.100080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2248 06:40:40.100590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2250 06:40:40.193591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2251 06:40:40.194185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2253 06:40:40.291230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2254 06:40:40.291716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2256 06:40:40.387319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2257 06:40:40.387803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2259 06:40:40.477715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2261 06:40:40.480709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2262 06:40:40.569990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2263 06:40:40.570477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2265 06:40:40.663829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2266 06:40:40.664314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2268 06:40:40.753824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2269 06:40:40.754310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2271 06:40:40.847553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2272 06:40:40.848038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2274 06:40:40.938839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2275 06:40:40.939331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2277 06:40:41.031708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2278 06:40:41.032211 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2280 06:40:41.121750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2281 06:40:41.122227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2283 06:40:41.217670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2284 06:40:41.218233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2286 06:40:41.311783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2287 06:40:41.312266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2289 06:40:41.410052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2290 06:40:41.410541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2292 06:40:41.506150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2293 06:40:41.506637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2295 06:40:41.600771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2296 06:40:41.601260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2298 06:40:41.696074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2299 06:40:41.696587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2301 06:40:41.791190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2302 06:40:41.791675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2304 06:40:41.890441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2305 06:40:41.890926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2307 06:40:41.987013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2308 06:40:41.987499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2310 06:40:42.082257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2311 06:40:42.082730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2313 06:40:42.179539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2314 06:40:42.180012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2316 06:40:42.275683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2317 06:40:42.276262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2319 06:40:42.371533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2320 06:40:42.372006 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2322 06:40:42.466325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2323 06:40:42.466816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2325 06:40:42.563057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2326 06:40:42.563538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2328 06:40:42.658675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2329 06:40:42.659164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2331 06:40:42.755428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2332 06:40:42.755906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2334 06:40:42.848950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2335 06:40:42.849445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2337 06:40:42.943282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2338 06:40:42.943769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2340 06:40:43.040385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2341 06:40:43.040855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2343 06:40:43.136749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2344 06:40:43.137223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2346 06:40:43.237007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2347 06:40:43.237569 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2349 06:40:43.332776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2350 06:40:43.333258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2352 06:40:43.424668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2353 06:40:43.424987 + set +x
2354 06:40:43.425451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2356 06:40:43.429024 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1187659_1.6.2.4.5>
2357 06:40:43.429505 Received signal: <ENDRUN> 1_kselftest-dt 1187659_1.6.2.4.5
2358 06:40:43.429752 Ending use of test pattern.
2359 06:40:43.429984 Ending test lava.1_kselftest-dt (1187659_1.6.2.4.5), duration 77.04
2361 06:40:43.436647 <LAVA_TEST_RUNNER EXIT>
2362 06:40:43.437128 ok: lava_test_shell seems to have completed
2363 06:40:43.442883 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2364 06:40:43.443940 end: 3.1 lava-test-shell (duration 00:01:19) [common]
2365 06:40:43.444249 end: 3 lava-test-retry (duration 00:01:19) [common]
2366 06:40:43.444546 start: 4 finalize (timeout 00:06:03) [common]
2367 06:40:43.444846 start: 4.1 power-off (timeout 00:00:30) [common]
2368 06:40:43.445226 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2369 06:40:43.809733 Returned 0 in 0 seconds
2370 06:40:43.910659 end: 4.1 power-off (duration 00:00:00) [common]
2372 06:40:43.911647 start: 4.2 read-feedback (timeout 00:06:02) [common]
2373 06:40:43.912300 Listened to connection for namespace 'common' for up to 1s
2374 06:40:43.912883 Listened to connection for namespace 'common' for up to 1s
2375 06:40:44.912366 Finalising connection for namespace 'common'
2376 06:40:44.912812 Disconnecting from shell: Finalise
2377 06:40:44.913126 / #
2378 06:40:45.013740 end: 4.2 read-feedback (duration 00:00:01) [common]
2379 06:40:45.014147 end: 4 finalize (duration 00:00:02) [common]
2380 06:40:45.014544 Cleaning after the job
2381 06:40:45.014887 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/ramdisk
2382 06:40:45.018591 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/kernel
2383 06:40:45.021096 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/dtb
2384 06:40:45.021408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/nfsrootfs
2385 06:40:45.074686 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1187659/tftp-deploy-dykh51w8/modules
2386 06:40:45.078150 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1187659
2387 06:40:45.717942 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1187659
2388 06:40:45.718225 Job finished correctly