Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:43:47.724975 lava-dispatcher, installed at version: 2024.01
2 21:43:47.725792 start: 0 validate
3 21:43:47.726286 Start time: 2024-09-03 21:43:47.726254+00:00 (UTC)
4 21:43:47.726853 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:43:47.727403 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:43:47.766598 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:43:47.767132 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-26-g88fac17500f4%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 21:43:47.798225 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:43:47.798849 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-26-g88fac17500f4%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:43:48.855279 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:43:48.855798 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-26-g88fac17500f4%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 21:43:48.896518 validate duration: 1.17
14 21:43:48.897370 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:43:48.897706 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:43:48.898003 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:43:48.898570 Not decompressing ramdisk as can be used compressed.
18 21:43:48.898997 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:43:48.899242 saving as /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/ramdisk/rootfs.cpio.gz
20 21:43:48.899494 total size: 8181887 (7 MB)
21 21:43:48.934273 progress 0 % (0 MB)
22 21:43:48.946438 progress 5 % (0 MB)
23 21:43:48.957694 progress 10 % (0 MB)
24 21:43:48.966688 progress 15 % (1 MB)
25 21:43:48.972019 progress 20 % (1 MB)
26 21:43:48.977765 progress 25 % (1 MB)
27 21:43:48.982887 progress 30 % (2 MB)
28 21:43:48.988590 progress 35 % (2 MB)
29 21:43:48.994013 progress 40 % (3 MB)
30 21:43:48.999589 progress 45 % (3 MB)
31 21:43:49.004756 progress 50 % (3 MB)
32 21:43:49.010297 progress 55 % (4 MB)
33 21:43:49.015528 progress 60 % (4 MB)
34 21:43:49.021081 progress 65 % (5 MB)
35 21:43:49.026224 progress 70 % (5 MB)
36 21:43:49.031680 progress 75 % (5 MB)
37 21:43:49.036675 progress 80 % (6 MB)
38 21:43:49.042073 progress 85 % (6 MB)
39 21:43:49.046872 progress 90 % (7 MB)
40 21:43:49.051914 progress 95 % (7 MB)
41 21:43:49.056672 progress 100 % (7 MB)
42 21:43:49.057303 7 MB downloaded in 0.16 s (49.45 MB/s)
43 21:43:49.057843 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:43:49.058720 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:43:49.059006 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:43:49.059273 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:43:49.059732 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-26-g88fac17500f4/arm64/defconfig+debug/gcc-12/kernel/Image
49 21:43:49.059972 saving as /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/kernel/Image
50 21:43:49.060202 total size: 167969280 (160 MB)
51 21:43:49.060416 No compression specified
52 21:43:49.097976 progress 0 % (0 MB)
53 21:43:49.198426 progress 5 % (8 MB)
54 21:43:49.298939 progress 10 % (16 MB)
55 21:43:49.399092 progress 15 % (24 MB)
56 21:43:49.498174 progress 20 % (32 MB)
57 21:43:49.596641 progress 25 % (40 MB)
58 21:43:49.694696 progress 30 % (48 MB)
59 21:43:49.795142 progress 35 % (56 MB)
60 21:43:49.895921 progress 40 % (64 MB)
61 21:43:49.996979 progress 45 % (72 MB)
62 21:43:50.096661 progress 50 % (80 MB)
63 21:43:50.195184 progress 55 % (88 MB)
64 21:43:50.295408 progress 60 % (96 MB)
65 21:43:50.395381 progress 65 % (104 MB)
66 21:43:50.494832 progress 70 % (112 MB)
67 21:43:50.593609 progress 75 % (120 MB)
68 21:43:50.693983 progress 80 % (128 MB)
69 21:43:50.794765 progress 85 % (136 MB)
70 21:43:50.895222 progress 90 % (144 MB)
71 21:43:50.995809 progress 95 % (152 MB)
72 21:43:51.095568 progress 100 % (160 MB)
73 21:43:51.096163 160 MB downloaded in 2.04 s (78.68 MB/s)
74 21:43:51.096677 end: 1.2.1 http-download (duration 00:00:02) [common]
76 21:43:51.097528 end: 1.2 download-retry (duration 00:00:02) [common]
77 21:43:51.097820 start: 1.3 download-retry (timeout 00:09:58) [common]
78 21:43:51.098121 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 21:43:51.098648 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-26-g88fac17500f4/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:43:51.099003 saving as /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:43:51.099226 total size: 54667 (0 MB)
82 21:43:51.099443 No compression specified
83 21:43:51.148838 progress 59 % (0 MB)
84 21:43:51.149684 progress 100 % (0 MB)
85 21:43:51.150230 0 MB downloaded in 0.05 s (1.02 MB/s)
86 21:43:51.150697 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:43:51.151520 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:43:51.151782 start: 1.4 download-retry (timeout 00:09:58) [common]
90 21:43:51.152073 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 21:43:51.152563 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-26-g88fac17500f4/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 21:43:51.152809 saving as /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/modules/modules.tar
93 21:43:51.153017 total size: 27444600 (26 MB)
94 21:43:51.153228 Using unxz to decompress xz
95 21:43:51.189406 progress 0 % (0 MB)
96 21:43:51.378057 progress 5 % (1 MB)
97 21:43:51.585356 progress 10 % (2 MB)
98 21:43:51.788178 progress 15 % (3 MB)
99 21:43:52.001959 progress 20 % (5 MB)
100 21:43:52.203899 progress 25 % (6 MB)
101 21:43:52.410651 progress 30 % (7 MB)
102 21:43:52.598771 progress 35 % (9 MB)
103 21:43:52.806485 progress 40 % (10 MB)
104 21:43:53.002352 progress 45 % (11 MB)
105 21:43:53.205723 progress 50 % (13 MB)
106 21:43:53.412909 progress 55 % (14 MB)
107 21:43:53.619931 progress 60 % (15 MB)
108 21:43:53.820493 progress 65 % (17 MB)
109 21:43:54.035961 progress 70 % (18 MB)
110 21:43:54.236314 progress 75 % (19 MB)
111 21:43:54.476286 progress 80 % (20 MB)
112 21:43:54.667770 progress 85 % (22 MB)
113 21:43:54.881264 progress 90 % (23 MB)
114 21:43:55.076482 progress 95 % (24 MB)
115 21:43:55.274138 progress 100 % (26 MB)
116 21:43:55.289410 26 MB downloaded in 4.14 s (6.33 MB/s)
117 21:43:55.290018 end: 1.4.1 http-download (duration 00:00:04) [common]
119 21:43:55.290846 end: 1.4 download-retry (duration 00:00:04) [common]
120 21:43:55.291118 start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
121 21:43:55.291387 start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
122 21:43:55.291636 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:43:55.291891 start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
124 21:43:55.292914 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e
125 21:43:55.293815 makedir: /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin
126 21:43:55.294472 makedir: /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/tests
127 21:43:55.295100 makedir: /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/results
128 21:43:55.295699 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-add-keys
129 21:43:55.296786 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-add-sources
130 21:43:55.297742 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-background-process-start
131 21:43:55.298721 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-background-process-stop
132 21:43:55.299724 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-common-functions
133 21:43:55.300696 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-echo-ipv4
134 21:43:55.301619 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-install-packages
135 21:43:55.302519 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-installed-packages
136 21:43:55.303446 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-os-build
137 21:43:55.304424 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-probe-channel
138 21:43:55.305320 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-probe-ip
139 21:43:55.306216 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-target-ip
140 21:43:55.307109 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-target-mac
141 21:43:55.308016 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-target-storage
142 21:43:55.308963 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-test-case
143 21:43:55.309886 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-test-event
144 21:43:55.310789 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-test-feedback
145 21:43:55.311690 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-test-raise
146 21:43:55.312798 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-test-reference
147 21:43:55.313740 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-test-runner
148 21:43:55.314624 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-test-set
149 21:43:55.315495 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-test-shell
150 21:43:55.316438 Updating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-install-packages (oe)
151 21:43:55.317435 Updating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/bin/lava-installed-packages (oe)
152 21:43:55.318263 Creating /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/environment
153 21:43:55.318967 LAVA metadata
154 21:43:55.319452 - LAVA_JOB_ID=699433
155 21:43:55.319879 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:43:55.320586 start: 1.5.2.1 ssh-authorize (timeout 00:09:54) [common]
157 21:43:55.322381 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:43:55.322973 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:54) [common]
159 21:43:55.323385 skipped lava-vland-overlay
160 21:43:55.323870 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:43:55.324421 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:54) [common]
162 21:43:55.324850 skipped lava-multinode-overlay
163 21:43:55.325336 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:43:55.325834 start: 1.5.2.4 test-definition (timeout 00:09:54) [common]
165 21:43:55.326310 Loading test definitions
166 21:43:55.326853 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:54) [common]
167 21:43:55.327294 Using /lava-699433 at stage 0
168 21:43:55.329518 uuid=699433_1.5.2.4.1 testdef=None
169 21:43:55.330097 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:43:55.330620 start: 1.5.2.4.2 test-overlay (timeout 00:09:54) [common]
171 21:43:55.333199 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:43:55.334027 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:54) [common]
174 21:43:55.336503 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:43:55.337404 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:54) [common]
177 21:43:55.339681 runner path: /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/0/tests/0_dmesg test_uuid 699433_1.5.2.4.1
178 21:43:55.340312 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:43:55.341123 Creating lava-test-runner.conf files
181 21:43:55.341329 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/699433/lava-overlay-uucfi93e/lava-699433/0 for stage 0
182 21:43:55.341683 - 0_dmesg
183 21:43:55.342048 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:43:55.342335 start: 1.5.2.5 compress-overlay (timeout 00:09:54) [common]
185 21:43:55.366724 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:43:55.367153 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:54) [common]
187 21:43:55.367421 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:43:55.367691 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:43:55.367958 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
190 21:43:56.282768 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:43:56.283213 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
192 21:43:56.283458 extracting modules file /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/699433/extract-overlay-ramdisk-bukgteii/ramdisk
193 21:43:58.013845 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 21:43:58.014318 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 21:43:58.014598 [common] Applying overlay /var/lib/lava/dispatcher/tmp/699433/compress-overlay-hrp4k1e9/overlay-1.5.2.5.tar.gz to ramdisk
196 21:43:58.014813 [common] Applying overlay /var/lib/lava/dispatcher/tmp/699433/compress-overlay-hrp4k1e9/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/699433/extract-overlay-ramdisk-bukgteii/ramdisk
197 21:43:58.045233 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:43:58.045668 start: 1.5.6 prepare-kernel (timeout 00:09:51) [common]
199 21:43:58.045941 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:51) [common]
200 21:43:58.046177 Converting downloaded kernel to a uImage
201 21:43:58.046499 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/kernel/Image /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/kernel/uImage
202 21:43:59.767464 output: Image Name:
203 21:43:59.767886 output: Created: Tue Sep 3 21:43:58 2024
204 21:43:59.768144 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:43:59.768355 output: Data Size: 167969280 Bytes = 164032.50 KiB = 160.19 MiB
206 21:43:59.768558 output: Load Address: 01080000
207 21:43:59.768758 output: Entry Point: 01080000
208 21:43:59.768956 output:
209 21:43:59.769294 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 21:43:59.769560 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 21:43:59.769831 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 21:43:59.770084 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:43:59.770340 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 21:43:59.770593 Building ramdisk /var/lib/lava/dispatcher/tmp/699433/extract-overlay-ramdisk-bukgteii/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/699433/extract-overlay-ramdisk-bukgteii/ramdisk
215 21:44:05.376339 >> 436302 blocks
216 21:44:23.888752 Adding RAMdisk u-boot header.
217 21:44:23.889714 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/699433/extract-overlay-ramdisk-bukgteii/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/699433/extract-overlay-ramdisk-bukgteii/ramdisk.cpio.gz.uboot
218 21:44:24.525633 output: Image Name:
219 21:44:24.526055 output: Created: Tue Sep 3 21:44:23 2024
220 21:44:24.526264 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:44:24.526468 output: Data Size: 53175022 Bytes = 51928.73 KiB = 50.71 MiB
222 21:44:24.526668 output: Load Address: 00000000
223 21:44:24.526868 output: Entry Point: 00000000
224 21:44:24.527063 output:
225 21:44:24.527664 rename /var/lib/lava/dispatcher/tmp/699433/extract-overlay-ramdisk-bukgteii/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/ramdisk/ramdisk.cpio.gz.uboot
226 21:44:24.528159 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 21:44:24.528715 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
228 21:44:24.529237 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 21:44:24.529684 No LXC device requested
230 21:44:24.530174 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:44:24.530677 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 21:44:24.531160 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:44:24.531568 Checking files for TFTP limit of 4294967296 bytes.
234 21:44:24.534255 end: 1 tftp-deploy (duration 00:00:36) [common]
235 21:44:24.534821 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:44:24.535335 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:44:24.535821 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:44:24.536352 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:44:24.536877 Using kernel file from prepare-kernel: 699433/tftp-deploy-0u_jd6gr/kernel/uImage
240 21:44:24.537499 substitutions:
241 21:44:24.537909 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:44:24.538309 - {DTB_ADDR}: 0x01070000
243 21:44:24.538702 - {DTB}: 699433/tftp-deploy-0u_jd6gr/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:44:24.539099 - {INITRD}: 699433/tftp-deploy-0u_jd6gr/ramdisk/ramdisk.cpio.gz.uboot
245 21:44:24.539494 - {KERNEL_ADDR}: 0x01080000
246 21:44:24.539881 - {KERNEL}: 699433/tftp-deploy-0u_jd6gr/kernel/uImage
247 21:44:24.540308 - {LAVA_MAC}: None
248 21:44:24.540738 - {PRESEED_CONFIG}: None
249 21:44:24.541133 - {PRESEED_LOCAL}: None
250 21:44:24.541520 - {RAMDISK_ADDR}: 0x08000000
251 21:44:24.541906 - {RAMDISK}: 699433/tftp-deploy-0u_jd6gr/ramdisk/ramdisk.cpio.gz.uboot
252 21:44:24.542297 - {ROOT_PART}: None
253 21:44:24.542685 - {ROOT}: None
254 21:44:24.543070 - {SERVER_IP}: 192.168.6.2
255 21:44:24.543461 - {TEE_ADDR}: 0x83000000
256 21:44:24.543845 - {TEE}: None
257 21:44:24.544259 Parsed boot commands:
258 21:44:24.544637 - setenv autoload no
259 21:44:24.545023 - setenv initrd_high 0xffffffff
260 21:44:24.545407 - setenv fdt_high 0xffffffff
261 21:44:24.545791 - dhcp
262 21:44:24.546176 - setenv serverip 192.168.6.2
263 21:44:24.546559 - tftpboot 0x01080000 699433/tftp-deploy-0u_jd6gr/kernel/uImage
264 21:44:24.546945 - tftpboot 0x08000000 699433/tftp-deploy-0u_jd6gr/ramdisk/ramdisk.cpio.gz.uboot
265 21:44:24.547331 - tftpboot 0x01070000 699433/tftp-deploy-0u_jd6gr/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:44:24.547713 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:44:24.548132 - bootm 0x01080000 0x08000000 0x01070000
268 21:44:24.548622 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:44:24.550091 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:44:24.550525 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:44:24.566957 Setting prompt string to ['lava-test: # ']
273 21:44:24.568444 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:44:24.569028 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:44:24.569555 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:44:24.570074 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:44:24.571338 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:44:24.608754 >> OK - accepted request
279 21:44:24.610873 Returned 0 in 0 seconds
280 21:44:24.712024 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:44:24.713656 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:44:24.714223 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:44:24.714723 Setting prompt string to ['Hit any key to stop autoboot']
285 21:44:24.715180 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:44:24.716822 Trying 192.168.56.21...
287 21:44:24.717304 Connected to conserv1.
288 21:44:24.717729 Escape character is '^]'.
289 21:44:24.718157
290 21:44:24.718577 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 21:44:24.719006
292 21:44:35.982258 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 21:44:35.982876 bl2_stage_init 0x01
294 21:44:35.983304 bl2_stage_init 0x81
295 21:44:35.987822 hw id: 0x0000 - pwm id 0x01
296 21:44:35.988348 bl2_stage_init 0xc1
297 21:44:35.988753 bl2_stage_init 0x02
298 21:44:35.989157
299 21:44:35.993397 L0:00000000
300 21:44:35.993842 L1:20000703
301 21:44:35.994235 L2:00008067
302 21:44:35.994622 L3:14000000
303 21:44:35.996336 B2:00402000
304 21:44:35.996758 B1:e0f83180
305 21:44:35.997149
306 21:44:35.997540 TE: 58124
307 21:44:35.997929
308 21:44:36.007527 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 21:44:36.007950
310 21:44:36.008376 Board ID = 1
311 21:44:36.008767 Set A53 clk to 24M
312 21:44:36.009153 Set A73 clk to 24M
313 21:44:36.013175 Set clk81 to 24M
314 21:44:36.013593 A53 clk: 1200 MHz
315 21:44:36.013980 A73 clk: 1200 MHz
316 21:44:36.016445 CLK81: 166.6M
317 21:44:36.016870 smccc: 00012a92
318 21:44:36.022206 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 21:44:36.027685 board id: 1
320 21:44:36.031908 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:44:36.043555 fw parse done
322 21:44:36.048585 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:44:36.091263 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:44:36.103219 PIEI prepare done
325 21:44:36.103665 fastboot data load
326 21:44:36.104101 fastboot data verify
327 21:44:36.108662 verify result: 266
328 21:44:36.114297 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 21:44:36.114764 LPDDR4 probe
330 21:44:36.115156 ddr clk to 1584MHz
331 21:44:36.121356 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:44:36.158648
333 21:44:36.159114 dmc_version 0001
334 21:44:36.165400 Check phy result
335 21:44:36.172215 INFO : End of CA training
336 21:44:36.172675 INFO : End of initialization
337 21:44:36.177643 INFO : Training has run successfully!
338 21:44:36.178076 Check phy result
339 21:44:36.183247 INFO : End of initialization
340 21:44:36.183671 INFO : End of read enable training
341 21:44:36.186583 INFO : End of fine write leveling
342 21:44:36.192211 INFO : End of Write leveling coarse delay
343 21:44:36.197861 INFO : Training has run successfully!
344 21:44:36.198319 Check phy result
345 21:44:36.198733 INFO : End of initialization
346 21:44:36.203368 INFO : End of read dq deskew training
347 21:44:36.206693 INFO : End of MPR read delay center optimization
348 21:44:36.212269 INFO : End of write delay center optimization
349 21:44:36.217857 INFO : End of read delay center optimization
350 21:44:36.218286 INFO : End of max read latency training
351 21:44:36.223423 INFO : Training has run successfully!
352 21:44:36.223850 1D training succeed
353 21:44:36.231295 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:44:36.279472 Check phy result
355 21:44:36.280044 INFO : End of initialization
356 21:44:36.300213 INFO : End of 2D read delay Voltage center optimization
357 21:44:36.321344 INFO : End of 2D read delay Voltage center optimization
358 21:44:36.372488 INFO : End of 2D write delay Voltage center optimization
359 21:44:36.422700 INFO : End of 2D write delay Voltage center optimization
360 21:44:36.428248 INFO : Training has run successfully!
361 21:44:36.428691
362 21:44:36.429106 channel==0
363 21:44:36.433824 RxClkDly_Margin_A0==88 ps 9
364 21:44:36.434262 TxDqDly_Margin_A0==98 ps 10
365 21:44:36.439505 RxClkDly_Margin_A1==88 ps 9
366 21:44:36.439947 TxDqDly_Margin_A1==88 ps 9
367 21:44:36.440410 TrainedVREFDQ_A0==74
368 21:44:36.445025 TrainedVREFDQ_A1==74
369 21:44:36.445458 VrefDac_Margin_A0==25
370 21:44:36.445868 DeviceVref_Margin_A0==40
371 21:44:36.450685 VrefDac_Margin_A1==25
372 21:44:36.451164 DeviceVref_Margin_A1==40
373 21:44:36.451588
374 21:44:36.452027
375 21:44:36.452442 channel==1
376 21:44:36.456258 RxClkDly_Margin_A0==98 ps 10
377 21:44:36.456692 TxDqDly_Margin_A0==98 ps 10
378 21:44:36.461836 RxClkDly_Margin_A1==88 ps 9
379 21:44:36.462269 TxDqDly_Margin_A1==98 ps 10
380 21:44:36.467459 TrainedVREFDQ_A0==77
381 21:44:36.467923 TrainedVREFDQ_A1==77
382 21:44:36.468375 VrefDac_Margin_A0==22
383 21:44:36.473068 DeviceVref_Margin_A0==37
384 21:44:36.473501 VrefDac_Margin_A1==24
385 21:44:36.478774 DeviceVref_Margin_A1==37
386 21:44:36.479204
387 21:44:36.479617 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:44:36.480053
389 21:44:36.512349 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
390 21:44:36.512848 2D training succeed
391 21:44:36.517861 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:44:36.523445 auto size-- 65535DDR cs0 size: 2048MB
393 21:44:36.523879 DDR cs1 size: 2048MB
394 21:44:36.529047 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:44:36.529478 cs0 DataBus test pass
396 21:44:36.534731 cs1 DataBus test pass
397 21:44:36.535186 cs0 AddrBus test pass
398 21:44:36.535595 cs1 AddrBus test pass
399 21:44:36.536028
400 21:44:36.540321 100bdlr_step_size ps== 420
401 21:44:36.540766 result report
402 21:44:36.545883 boot times 0Enable ddr reg access
403 21:44:36.550366 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:44:36.564721 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 21:44:37.138533 0.0;M3 CHK:0;cm4_sp_mode 0
406 21:44:37.139119 MVN_1=0x00000000
407 21:44:37.143918 MVN_2=0x00000000
408 21:44:37.149688 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 21:44:37.150163 OPS=0x10
410 21:44:37.150577 ring efuse init
411 21:44:37.150978 chipver efuse init
412 21:44:37.158010 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 21:44:37.158475 [0.018961 Inits done]
414 21:44:37.158885 secure task start!
415 21:44:37.164608 high task start!
416 21:44:37.165102 low task start!
417 21:44:37.165549 run into bl31
418 21:44:37.172094 NOTICE: BL31: v1.3(release):4fc40b1
419 21:44:37.179900 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 21:44:37.180389 NOTICE: BL31: G12A normal boot!
421 21:44:37.205269 NOTICE: BL31: BL33 decompress pass
422 21:44:37.210945 ERROR: Error initializing runtime service opteed_fast
423 21:44:38.443672
424 21:44:38.444298
425 21:44:38.452128 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 21:44:38.452580
427 21:44:38.452994 Model: Libre Computer AML-A311D-CC Alta
428 21:44:38.660755 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 21:44:38.683957 DRAM: 2 GiB (effective 3.8 GiB)
430 21:44:38.826926 Core: 408 devices, 31 uclasses, devicetree: separate
431 21:44:38.832793 WDT: Not starting watchdog@f0d0
432 21:44:38.865082 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 21:44:38.877581 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 21:44:40.114341 ** Bad device specification mmc 0 *~ G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
435 21:44:40.114975 bl2_stage_init 0x01
436 21:44:40.115443 bl2_stage_init 0x81
437 21:44:40.119946 hw id: 0x0000 - pwm id 0x01
438 21:44:40.120449 bl2_stage_init 0xc1
439 21:44:40.120867 bl2_stage_init 0x02
440 21:44:40.121268
441 21:44:40.125425 L0:00000000
442 21:44:40.125878 L1:20000703
443 21:44:40.126291 L2:00008067
444 21:44:40.126690 L3:14000000
445 21:44:40.131082 B2:00402000
446 21:44:40.131565 B1:e0f83180
447 21:44:40.132046
448 21:44:40.132471 TE: 58159
449 21:44:40.132881
450 21:44:40.136667 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
451 21:44:40.137115
452 21:44:40.137526 Board ID = 1
453 21:44:40.142272 Set A53 clk to 24M
454 21:44:40.142729 Set A73 clk to 24M
455 21:44:40.143136 Set clk81 to 24M
456 21:44:40.147935 A53 clk: 1200 MHz
457 21:44:40.148406 A73 clk: 1200 MHz
458 21:44:40.148810 CLK81: 166.6M
459 21:44:40.149212 smccc: 00012ab5
460 21:44:40.153544 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
461 21:44:40.159118 board id: 1
462 21:44:40.165018 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
463 21:44:40.175613 fw parse done
464 21:44:40.181551 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
465 21:44:40.224060 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
466 21:44:40.234900 PIEI prepare done
467 21:44:40.235354 fastboot data load
468 21:44:40.235764 fastboot data verify
469 21:44:40.240518 verify result: 266
470 21:44:40.246134 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
471 21:44:40.246590 LPDDR4 probe
472 21:44:40.246996 ddr clk to 1584MHz
473 21:44:40.254104 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
474 21:44:40.291394
475 21:44:40.291856 dmc_version 0001
476 21:44:40.298000 Check phy result
477 21:44:40.303928 INFO : End of CA training
478 21:44:40.304380 INFO : End of initialization
479 21:44:40.309578 INFO : Training has run successfully!
480 21:44:40.310043 Check phy result
481 21:44:40.315098 INFO : End of initialization
482 21:44:40.315530 INFO : End of read enable training
483 21:44:40.320785 INFO : End of fine write leveling
484 21:44:40.326296 INFO : End of Write leveling coarse delay
485 21:44:40.326723 INFO : Training has run successfully!
486 21:44:40.327132 Check phy result
487 21:44:40.331889 INFO : End of initialization
488 21:44:40.332356 INFO : End of read dq deskew training
489 21:44:40.337553 INFO : End of MPR read delay center optimization
490 21:44:40.343073 INFO : End of write delay center optimization
491 21:44:40.348772 INFO : End of read delay center optimization
492 21:44:40.349203 INFO : End of max read latency training
493 21:44:40.354296 INFO : Training has run successfully!
494 21:44:40.354741 1D training succeed
495 21:44:40.363507 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
496 21:44:40.411055 Check phy result
497 21:44:40.411514 INFO : End of initialization
498 21:44:40.432691 INFO : End of 2D read delay Voltage center optimization
499 21:44:40.452872 INFO : End of 2D read delay Voltage center optimization
500 21:44:40.503781 INFO : End of 2D write delay Voltage center optimization
501 21:44:40.553902 INFO : End of 2D write delay Voltage center optimization
502 21:44:40.559582 INFO : Training has run successfully!
503 21:44:40.560045
504 21:44:40.560466 channel==0
505 21:44:40.565068 RxClkDly_Margin_A0==88 ps 9
506 21:44:40.565492 TxDqDly_Margin_A0==98 ps 10
507 21:44:40.570787 RxClkDly_Margin_A1==88 ps 9
508 21:44:40.571212 TxDqDly_Margin_A1==98 ps 10
509 21:44:40.571622 TrainedVREFDQ_A0==74
510 21:44:40.576302 TrainedVREFDQ_A1==74
511 21:44:40.576738 VrefDac_Margin_A0==25
512 21:44:40.577143 DeviceVref_Margin_A0==40
513 21:44:40.581866 VrefDac_Margin_A1==25
514 21:44:40.582318 DeviceVref_Margin_A1==40
515 21:44:40.582723
516 21:44:40.583128
517 21:44:40.587550 channel==1
518 21:44:40.587976 RxClkDly_Margin_A0==98 ps 10
519 21:44:40.588411 TxDqDly_Margin_A0==98 ps 10
520 21:44:40.593078 RxClkDly_Margin_A1==98 ps 10
521 21:44:40.593512 TxDqDly_Margin_A1==88 ps 9
522 21:44:40.598719 TrainedVREFDQ_A0==77
523 21:44:40.599146 TrainedVREFDQ_A1==77
524 21:44:40.599547 VrefDac_Margin_A0==22
525 21:44:40.604346 DeviceVref_Margin_A0==37
526 21:44:40.604777 VrefDac_Margin_A1==22
527 21:44:40.610007 DeviceVref_Margin_A1==37
528 21:44:40.610452
529 21:44:40.610859 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
530 21:44:40.615483
531 21:44:40.643534 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
532 21:44:40.644059 2D training succeed
533 21:44:40.649125 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
534 21:44:40.654815 auto size-- 65535DDR cs0 size: 2048MB
535 21:44:40.655249 DDR cs1 size: 2048MB
536 21:44:40.660253 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
537 21:44:40.660689 cs0 DataBus test pass
538 21:44:40.665878 cs1 DataBus test pass
539 21:44:40.666307 cs0 AddrBus test pass
540 21:44:40.666712 cs1 AddrBus test pass
541 21:44:40.667114
542 21:44:40.671488 100bdlr_step_size ps== 420
543 21:44:40.671939 result report
544 21:44:40.677073 boot times 0Enable ddr reg access
545 21:44:40.682527 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
546 21:44:40.696035 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
547 21:44:41.268116 0.0;M3 CHK:0;cm4_sp_mode 0
548 21:44:41.268703 MVN_1=0x00000000
549 21:44:41.273517 MVN_2=0x00000000
550 21:44:41.279252 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
551 21:44:41.279750 OPS=0x10
552 21:44:41.280231 ring efuse init
553 21:44:41.280659 chipver efuse init
554 21:44:41.287468 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
555 21:44:41.287917 [0.018961 Inits done]
556 21:44:41.295019 secure task start!
557 21:44:41.295436 high task start!
558 21:44:41.295823 low task start!
559 21:44:41.296241 run into bl31
560 21:44:41.301646 NOTICE: BL31: v1.3(release):4fc40b1
561 21:44:41.309476 NOTICE: BL31: Built : 15:58:17, May 22 2019
562 21:44:41.309911 NOTICE: BL31: G12A normal boot!
563 21:44:41.334954 NOTICE: BL31: BL33 decompress pass
564 21:44:41.339545 ERROR: Error initializing runtime service opteed_fast
565 21:44:42.573462
566 21:44:42.574072
567 21:44:42.581798 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
568 21:44:42.582280
569 21:44:42.582696 Model: Libre Computer AML-A311D-CC Alta
570 21:44:42.790286 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
571 21:44:42.812716 DRAM: 2 GiB (effective 3.8 GiB)
572 21:44:42.956622 Core: 408 devices, 31 uclasses, devicetree: separate
573 21:44:42.962462 WDT: Not starting watchdog@f0d0
574 21:44:42.994698 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
575 21:44:43.007171 Loading Environment from FAT... Card did not respond to voltage select! : -110
576 21:44:43.012166 ** Bad device specification mmc 0 **
577 21:44:43.022488 Card did not respond to voltage select! : -110
578 21:44:43.030192 ** Bad device specification mmc 0 **
579 21:44:43.030667 Couldn't find partition mmc 0
580 21:44:43.038463 Card did not respond to voltage select! : -110
581 21:44:43.044175 ** Bad device specification mmc 0 **
582 21:44:43.044674 Couldn't find partition mmc 0
583 21:44:43.049058 Error: could not access storage.
584 21:44:43.391595 Net: eth0: ethernet@ff3f0000
585 21:44:43.392230 starting USB...
586 21:44:43.643382 Bus usb@ff500000: Register 3000140 NbrPorts 3
587 21:44:43.643973 Starting the controller
588 21:44:43.649370 USB XHCI 1.10
589 21:44:45.362761 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
590 21:44:45.363364 bl2_stage_init 0x01
591 21:44:45.363792 bl2_stage_init 0x81
592 21:44:45.368288 hw id: 0x0000 - pwm id 0x01
593 21:44:45.368737 bl2_stage_init 0xc1
594 21:44:45.369149 bl2_stage_init 0x02
595 21:44:45.369553
596 21:44:45.373937 L0:00000000
597 21:44:45.374379 L1:20000703
598 21:44:45.374788 L2:00008067
599 21:44:45.375191 L3:14000000
600 21:44:45.376832 B2:00402000
601 21:44:45.377269 B1:e0f83180
602 21:44:45.377676
603 21:44:45.378081 TE: 58167
604 21:44:45.378482
605 21:44:45.388067 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
606 21:44:45.388548
607 21:44:45.388967 Board ID = 1
608 21:44:45.389365 Set A53 clk to 24M
609 21:44:45.389758 Set A73 clk to 24M
610 21:44:45.393614 Set clk81 to 24M
611 21:44:45.394054 A53 clk: 1200 MHz
612 21:44:45.394462 A73 clk: 1200 MHz
613 21:44:45.399230 CLK81: 166.6M
614 21:44:45.399665 smccc: 00012abc
615 21:44:45.404769 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
616 21:44:45.405209 board id: 1
617 21:44:45.413232 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
618 21:44:45.424037 fw parse done
619 21:44:45.430129 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
620 21:44:45.472211 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
621 21:44:45.483541 PIEI prepare done
622 21:44:45.483970 fastboot data load
623 21:44:45.484418 fastboot data verify
624 21:44:45.489166 verify result: 266
625 21:44:45.494770 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
626 21:44:45.495258 LPDDR4 probe
627 21:44:45.495674 ddr clk to 1584MHz
628 21:44:45.501808 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
629 21:44:45.540016
630 21:44:45.540499 dmc_version 0001
631 21:44:45.546671 Check phy result
632 21:44:45.552563 INFO : End of CA training
633 21:44:45.553011 INFO : End of initialization
634 21:44:45.558127 INFO : Training has run successfully!
635 21:44:45.558562 Check phy result
636 21:44:45.563766 INFO : End of initialization
637 21:44:45.564225 INFO : End of read enable training
638 21:44:45.569333 INFO : End of fine write leveling
639 21:44:45.574954 INFO : End of Write leveling coarse delay
640 21:44:45.575422 INFO : Training has run successfully!
641 21:44:45.575833 Check phy result
642 21:44:45.580465 INFO : End of initialization
643 21:44:45.580898 INFO : End of read dq deskew training
644 21:44:45.586162 INFO : End of MPR read delay center optimization
645 21:44:45.591811 INFO : End of write delay center optimization
646 21:44:45.597328 INFO : End of read delay center optimization
647 21:44:45.597768 INFO : End of max read latency training
648 21:44:45.602905 INFO : Training has run successfully!
649 21:44:45.603334 1D training succeed
650 21:44:45.611295 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
651 21:44:45.658902 Check phy result
652 21:44:45.659400 INFO : End of initialization
653 21:44:45.681425 INFO : End of 2D read delay Voltage center optimization
654 21:44:45.701722 INFO : End of 2D read delay Voltage center optimization
655 21:44:45.753758 INFO : End of 2D write delay Voltage center optimization
656 21:44:45.803208 INFO : End of 2D write delay Voltage center optimization
657 21:44:45.808695 INFO : Training has run successfully!
658 21:44:45.809155
659 21:44:45.809570 channel==0
660 21:44:45.814357 RxClkDly_Margin_A0==88 ps 9
661 21:44:45.814804 TxDqDly_Margin_A0==98 ps 10
662 21:44:45.817675 RxClkDly_Margin_A1==88 ps 9
663 21:44:45.818117 TxDqDly_Margin_A1==88 ps 9
664 21:44:45.823409 TrainedVREFDQ_A0==74
665 21:44:45.823843 TrainedVREFDQ_A1==74
666 21:44:45.824281 VrefDac_Margin_A0==25
667 21:44:45.829225 DeviceVref_Margin_A0==40
668 21:44:45.829700 VrefDac_Margin_A1==25
669 21:44:45.834508 DeviceVref_Margin_A1==40
670 21:44:45.834940
671 21:44:45.835348
672 21:44:45.835753 channel==1
673 21:44:45.836190 RxClkDly_Margin_A0==98 ps 10
674 21:44:45.840463 TxDqDly_Margin_A0==88 ps 9
675 21:44:45.840900 RxClkDly_Margin_A1==98 ps 10
676 21:44:45.845610 TxDqDly_Margin_A1==98 ps 10
677 21:44:45.846079 TrainedVREFDQ_A0==77
678 21:44:45.846494 TrainedVREFDQ_A1==78
679 21:44:45.851142 VrefDac_Margin_A0==22
680 21:44:45.851577 DeviceVref_Margin_A0==37
681 21:44:45.856776 VrefDac_Margin_A1==24
682 21:44:45.857214 DeviceVref_Margin_A1==36
683 21:44:45.857619
684 21:44:45.862555 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
685 21:44:45.862991
686 21:44:45.890429 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
687 21:44:45.895940 2D training succeed
688 21:44:45.901515 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
689 21:44:45.901964 auto size-- 65535DDR cs0 size: 2048MB
690 21:44:45.907169 DDR cs1 size: 2048MB
691 21:44:45.907637 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
692 21:44:45.912716 cs0 DataBus test pass
693 21:44:45.913157 cs1 DataBus test pass
694 21:44:45.913562 cs0 AddrBus test pass
695 21:44:45.918309 cs1 AddrBus test pass
696 21:44:45.918741
697 21:44:45.919144 100bdlr_step_size ps== 420
698 21:44:45.919553 result report
699 21:44:45.923938 boot times 0Enable ddr reg access
700 21:44:45.931558 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
701 21:44:45.945040 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
702 21:44:46.518779 0.0;M3 CHK:0;cm4_sp_mode 0
703 21:44:46.519364 MVN_1=0x00000000
704 21:44:46.524264 MVN_2=0x00000000
705 21:44:46.530063 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
706 21:44:46.530575 OPS=0x10
707 21:44:46.531007 ring efuse init
708 21:44:46.531429 chipver efuse init
709 21:44:46.538189 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
710 21:44:46.538666 [0.018961 Inits done]
711 21:44:46.544849 secure task start!
712 21:44:46.545278 high task start!
713 21:44:46.545675 low task start!
714 21:44:46.546067 run into bl31
715 21:44:46.552564 NOTICE: BL31: v1.3(release):4fc40b1
716 21:44:46.559528 NOTICE: BL31: Built : 15:58:17, May 22 2019
717 21:44:46.560044 NOTICE: BL31: G12A normal boot!
718 21:44:46.585817 NOTICE: BL31: BL33 decompress pass
719 21:44:46.590434 ERROR: Error initializing runtime service opteed_fast
720 21:44:47.824248
721 21:44:47.824820
722 21:44:47.832656 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
723 21:44:47.833115
724 21:44:47.833536 Model: Libre Computer AML-A311D-CC Alta
725 21:44:48.041080 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
726 21:44:48.064515 DRAM: 2 GiB (effective 3.8 GiB)
727 21:44:48.207480 Core: 408 devices, 31 uclasses, devicetree: separate
728 21:44:48.213341 WDT: Not starting watchdog@f0d0
729 21:44:48.245617 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
730 21:44:48.258096 Loading Environment from FAT... Card did not respond to voltage select! : -110
731 21:44:48.263009 ** Bad device specification mmc 0 **
732 21:44:48.273303 Card did not respond to voltage select! : -110
733 21:44:48.281013 ** Bad device specification mmc 0 **
734 21:44:48.281459 Couldn't find partition mmc 0
735 21:44:48.289348 Card did not respond to voltage select! : -110
736 21:44:48.294868 ** Bad device specification mmc 0 **
737 21:44:48.295340 Couldn't find partition mmc 0
738 21:44:48.299961 Error: could not access storage.
739 21:44:48.642387 Net: eth0: ethernet@ff3f0000
740 21:44:48.642952 starting USB...
741 21:44:48.894149 Bus usb@ff500000: Register 3000140 NbrPorts 3
742 21:44:48.894720 Starting the controller
743 21:44:48.900738 USB XHCI 1.10
744 21:44:51.062968 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
745 21:44:51.063599 bl2_stage_init 0x81
746 21:44:51.068493 hw id: 0x0000 - pwm id 0x01
747 21:44:51.068950 bl2_stage_init 0xc1
748 21:44:51.069370 bl2_stage_init 0x02
749 21:44:51.069779
750 21:44:51.074122 L0:00000000
751 21:44:51.074567 L1:20000703
752 21:44:51.074980 L2:00008067
753 21:44:51.075384 L3:14000000
754 21:44:51.075787 B2:00402000
755 21:44:51.079689 B1:e0f83180
756 21:44:51.080161
757 21:44:51.080582 TE: 58150
758 21:44:51.080992
759 21:44:51.085369 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
760 21:44:51.085809
761 21:44:51.086219 Board ID = 1
762 21:44:51.090867 Set A53 clk to 24M
763 21:44:51.091302 Set A73 clk to 24M
764 21:44:51.091702 Set clk81 to 24M
765 21:44:51.096440 A53 clk: 1200 MHz
766 21:44:51.096886 A73 clk: 1200 MHz
767 21:44:51.097295 CLK81: 166.6M
768 21:44:51.097698 smccc: 00012aac
769 21:44:51.102065 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
770 21:44:51.107589 board id: 1
771 21:44:51.113410 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
772 21:44:51.124060 fw parse done
773 21:44:51.129367 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
774 21:44:51.171799 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
775 21:44:51.183631 PIEI prepare done
776 21:44:51.184098 fastboot data load
777 21:44:51.184513 fastboot data verify
778 21:44:51.189454 verify result: 266
779 21:44:51.194933 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
780 21:44:51.195369 LPDDR4 probe
781 21:44:51.195777 ddr clk to 1584MHz
782 21:44:51.202895 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 21:44:51.240080
784 21:44:51.240566 dmc_version 0001
785 21:44:51.246731 Check phy result
786 21:44:51.252603 INFO : End of CA training
787 21:44:51.253071 INFO : End of initialization
788 21:44:51.258179 INFO : Training has run successfully!
789 21:44:51.258619 Check phy result
790 21:44:51.263745 INFO : End of initialization
791 21:44:51.264224 INFO : End of read enable training
792 21:44:51.269398 INFO : End of fine write leveling
793 21:44:51.274998 INFO : End of Write leveling coarse delay
794 21:44:51.275430 INFO : Training has run successfully!
795 21:44:51.275839 Check phy result
796 21:44:51.280664 INFO : End of initialization
797 21:44:51.281104 INFO : End of read dq deskew training
798 21:44:51.286185 INFO : End of MPR read delay center optimization
799 21:44:51.291806 INFO : End of write delay center optimization
800 21:44:51.297400 INFO : End of read delay center optimization
801 21:44:51.297833 INFO : End of max read latency training
802 21:44:51.302986 INFO : Training has run successfully!
803 21:44:51.303417 1D training succeed
804 21:44:51.312215 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
805 21:44:51.358896 Check phy result
806 21:44:51.359388 INFO : End of initialization
807 21:44:51.380589 INFO : End of 2D read delay Voltage center optimization
808 21:44:51.401806 INFO : End of 2D read delay Voltage center optimization
809 21:44:51.453788 INFO : End of 2D write delay Voltage center optimization
810 21:44:51.503171 INFO : End of 2D write delay Voltage center optimization
811 21:44:51.508727 INFO : Training has run successfully!
812 21:44:51.509164
813 21:44:51.509575 channel==0
814 21:44:51.514394 RxClkDly_Margin_A0==88 ps 9
815 21:44:51.514822 TxDqDly_Margin_A0==98 ps 10
816 21:44:51.517726 RxClkDly_Margin_A1==88 ps 9
817 21:44:51.518158 TxDqDly_Margin_A1==98 ps 10
818 21:44:51.523209 TrainedVREFDQ_A0==74
819 21:44:51.523658 TrainedVREFDQ_A1==74
820 21:44:51.528839 VrefDac_Margin_A0==25
821 21:44:51.529313 DeviceVref_Margin_A0==40
822 21:44:51.529728 VrefDac_Margin_A1==25
823 21:44:51.534413 DeviceVref_Margin_A1==40
824 21:44:51.534866
825 21:44:51.535264
826 21:44:51.535652 channel==1
827 21:44:51.536073 RxClkDly_Margin_A0==98 ps 10
828 21:44:51.539964 TxDqDly_Margin_A0==88 ps 9
829 21:44:51.540419 RxClkDly_Margin_A1==98 ps 10
830 21:44:51.545725 TxDqDly_Margin_A1==88 ps 9
831 21:44:51.546147 TrainedVREFDQ_A0==77
832 21:44:51.546539 TrainedVREFDQ_A1==77
833 21:44:51.551266 VrefDac_Margin_A0==22
834 21:44:51.551685 DeviceVref_Margin_A0==37
835 21:44:51.556929 VrefDac_Margin_A1==22
836 21:44:51.557351 DeviceVref_Margin_A1==37
837 21:44:51.557739
838 21:44:51.562577 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
839 21:44:51.562992
840 21:44:51.590419 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
841 21:44:51.595946 2D training succeed
842 21:44:51.601550 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
843 21:44:51.601989 auto size-- 65535DDR cs0 size: 2048MB
844 21:44:51.607111 DDR cs1 size: 2048MB
845 21:44:51.607529 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
846 21:44:51.612716 cs0 DataBus test pass
847 21:44:51.613125 cs1 DataBus test pass
848 21:44:51.613512 cs0 AddrBus test pass
849 21:44:51.618427 cs1 AddrBus test pass
850 21:44:51.618840
851 21:44:51.619235 100bdlr_step_size ps== 420
852 21:44:51.619629 result report
853 21:44:51.623964 boot times 0Enable ddr reg access
854 21:44:51.630727 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
855 21:44:51.644222 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
856 21:44:52.218830 0.0;M3 CHK:0;cm4_sp_mode 0
857 21:44:52.219431 MVN_1=0x00000000
858 21:44:52.224466 MVN_2=0x00000000
859 21:44:52.230033 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
860 21:44:52.230478 OPS=0x10
861 21:44:52.230895 ring efuse init
862 21:44:52.231296 chipver efuse init
863 21:44:52.235628 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
864 21:44:52.241218 [0.018961 Inits done]
865 21:44:52.241689 secure task start!
866 21:44:52.242104 high task start!
867 21:44:52.245825 low task start!
868 21:44:52.246310 run into bl31
869 21:44:52.252477 NOTICE: BL31: v1.3(release):4fc40b1
870 21:44:52.259358 NOTICE: BL31: Built : 15:58:17, May 22 2019
871 21:44:52.259815 NOTICE: BL31: G12A normal boot!
872 21:44:52.285661 NOTICE: BL31: BL33 decompress pass
873 21:44:52.290397 ERROR: Error initializing runtime service opteed_fast
874 21:44:53.524318
875 21:44:53.524910
876 21:44:53.531652 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
877 21:44:53.532141
878 21:44:53.532568 Model: Libre Computer AML-A311D-CC Alta
879 21:44:53.740098 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
880 21:44:53.763494 DRAM: 2 GiB (effective 3.8 GiB)
881 21:44:53.907373 Core: 408 devices, 31 uclasses, devicetree: separate
882 21:44:53.912371 WDT: Not starting watchdog@f0d0
883 21:44:53.945451 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
884 21:44:53.957955 Loading Environment from FAT... Card did not respond to voltage select! : -110
885 21:44:53.961999 ** Bad device specification mmc 0 **
886 21:44:53.973300 Card did not respond to voltage select! : -110
887 21:44:53.980023 ** Bad device specification mmc 0 **
888 21:44:53.980467 Couldn't find partition mmc 0
889 21:44:53.989257 Card did not respond to voltage select! : -110
890 21:44:53.994777 ** Bad device specification mmc 0 **
891 21:44:53.995219 Couldn't find partition mmc 0
892 21:44:53.998942 Error: could not access storage.
893 21:44:54.341366 Net: eth0: ethernet@ff3f0000
894 21:44:54.341886 starting USB...
895 21:44:54.594091 Bus usb@ff500000: Register 3000140 NbrPorts 3
896 21:44:54.594673 Starting the controller
897 21:44:54.601041 USB XHCI 1.10
898 21:44:56.462672 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
899 21:44:56.463262 bl2_stage_init 0x01
900 21:44:56.463690 bl2_stage_init 0x81
901 21:44:56.468254 hw id: 0x0000 - pwm id 0x01
902 21:44:56.468708 bl2_stage_init 0xc1
903 21:44:56.469122 bl2_stage_init 0x02
904 21:44:56.469524
905 21:44:56.473761 L0:00000000
906 21:44:56.474198 L1:20000703
907 21:44:56.474605 L2:00008067
908 21:44:56.475010 L3:14000000
909 21:44:56.479345 B2:00402000
910 21:44:56.479781 B1:e0f83180
911 21:44:56.480224
912 21:44:56.480635 TE: 58124
913 21:44:56.481041
914 21:44:56.485035 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
915 21:44:56.485476
916 21:44:56.485888 Board ID = 1
917 21:44:56.490670 Set A53 clk to 24M
918 21:44:56.491135 Set A73 clk to 24M
919 21:44:56.491550 Set clk81 to 24M
920 21:44:56.496196 A53 clk: 1200 MHz
921 21:44:56.496636 A73 clk: 1200 MHz
922 21:44:56.497040 CLK81: 166.6M
923 21:44:56.497599 smccc: 00012a92
924 21:44:56.501824 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
925 21:44:56.507353 board id: 1
926 21:44:56.512271 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
927 21:44:56.523872 fw parse done
928 21:44:56.529863 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
929 21:44:56.572515 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
930 21:44:56.583477 PIEI prepare done
931 21:44:56.584248 fastboot data load
932 21:44:56.584663 fastboot data verify
933 21:44:56.589110 verify result: 266
934 21:44:56.594657 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
935 21:44:56.595079 LPDDR4 probe
936 21:44:56.595470 ddr clk to 1584MHz
937 21:44:56.601772 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 21:44:56.638960
939 21:44:56.639427 dmc_version 0001
940 21:44:56.645704 Check phy result
941 21:44:56.652481 INFO : End of CA training
942 21:44:56.652899 INFO : End of initialization
943 21:44:56.658115 INFO : Training has run successfully!
944 21:44:56.658718 Check phy result
945 21:44:56.663724 INFO : End of initialization
946 21:44:56.664217 INFO : End of read enable training
947 21:44:56.669262 INFO : End of fine write leveling
948 21:44:56.674900 INFO : End of Write leveling coarse delay
949 21:44:56.675369 INFO : Training has run successfully!
950 21:44:56.675780 Check phy result
951 21:44:56.680582 INFO : End of initialization
952 21:44:56.681024 INFO : End of read dq deskew training
953 21:44:56.686177 INFO : End of MPR read delay center optimization
954 21:44:56.691559 INFO : End of write delay center optimization
955 21:44:56.697174 INFO : End of read delay center optimization
956 21:44:56.697608 INFO : End of max read latency training
957 21:44:56.702845 INFO : Training has run successfully!
958 21:44:56.703283 1D training succeed
959 21:44:56.711957 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
960 21:44:56.759616 Check phy result
961 21:44:56.760124 INFO : End of initialization
962 21:44:56.780330 INFO : End of 2D read delay Voltage center optimization
963 21:44:56.800460 INFO : End of 2D read delay Voltage center optimization
964 21:44:56.853213 INFO : End of 2D write delay Voltage center optimization
965 21:44:56.902471 INFO : End of 2D write delay Voltage center optimization
966 21:44:56.907950 INFO : Training has run successfully!
967 21:44:56.908433
968 21:44:56.908850 channel==0
969 21:44:56.913556 RxClkDly_Margin_A0==88 ps 9
970 21:44:56.913987 TxDqDly_Margin_A0==98 ps 10
971 21:44:56.916854 RxClkDly_Margin_A1==88 ps 9
972 21:44:56.917286 TxDqDly_Margin_A1==98 ps 10
973 21:44:56.922368 TrainedVREFDQ_A0==74
974 21:44:56.922797 TrainedVREFDQ_A1==74
975 21:44:56.928074 VrefDac_Margin_A0==25
976 21:44:56.928504 DeviceVref_Margin_A0==40
977 21:44:56.928909 VrefDac_Margin_A1==25
978 21:44:56.933636 DeviceVref_Margin_A1==40
979 21:44:56.934093
980 21:44:56.934504
981 21:44:56.934903 channel==1
982 21:44:56.935302 RxClkDly_Margin_A0==98 ps 10
983 21:44:56.939164 TxDqDly_Margin_A0==98 ps 10
984 21:44:56.939596 RxClkDly_Margin_A1==88 ps 9
985 21:44:56.944829 TxDqDly_Margin_A1==88 ps 9
986 21:44:56.945408 TrainedVREFDQ_A0==77
987 21:44:56.945839 TrainedVREFDQ_A1==77
988 21:44:56.950382 VrefDac_Margin_A0==22
989 21:44:56.950819 DeviceVref_Margin_A0==37
990 21:44:56.956109 VrefDac_Margin_A1==24
991 21:44:56.956539 DeviceVref_Margin_A1==37
992 21:44:56.956941
993 21:44:56.961674 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
994 21:44:56.962102
995 21:44:56.989646 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
996 21:44:56.995177 2D training succeed
997 21:44:57.000876 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
998 21:44:57.001314 auto size-- 65535DDR cs0 size: 2048MB
999 21:44:57.006375 DDR cs1 size: 2048MB
1000 21:44:57.006805 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1001 21:44:57.012101 cs0 DataBus test pass
1002 21:44:57.012525 cs1 DataBus test pass
1003 21:44:57.012929 cs0 AddrBus test pass
1004 21:44:57.017577 cs1 AddrBus test pass
1005 21:44:57.018003
1006 21:44:57.018406 100bdlr_step_size ps== 420
1007 21:44:57.018811 result report
1008 21:44:57.023170 boot times 0Enable ddr reg access
1009 21:44:57.030027 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1010 21:44:57.043431 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1011 21:44:57.616407 0.0;M3 CHK:0;cm4_sp_mode 0
1012 21:44:57.616979 MVN_1=0x00000000
1013 21:44:57.621993 MVN_2=0x00000000
1014 21:44:57.627747 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1015 21:44:57.628244 OPS=0x10
1016 21:44:57.628661 ring efuse init
1017 21:44:57.629067 chipver efuse init
1018 21:44:57.633276 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1019 21:44:57.638945 [0.018961 Inits done]
1020 21:44:57.639384 secure task start!
1021 21:44:57.639800 high task start!
1022 21:44:57.642431 low task start!
1023 21:44:57.642860 run into bl31
1024 21:44:57.650200 NOTICE: BL31: v1.3(release):4fc40b1
1025 21:44:57.656941 NOTICE: BL31: Built : 15:58:17, May 22 2019
1026 21:44:57.657398 NOTICE: BL31: G12A normal boot!
1027 21:44:57.683199 NOTICE: BL31: BL33 decompress pass
1028 21:44:57.688662 ERROR: Error initializing runtime service opteed_fast
1029 21:44:58.921785
1030 21:44:58.922378
1031 21:44:58.930190 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1032 21:44:58.930648
1033 21:44:58.931060 Model: Libre Computer AML-A311D-CC Alta
1034 21:44:59.138550 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1035 21:44:59.161654 DRAM: 2 GiB (effective 3.8 GiB)
1036 21:44:59.304955 Core: 408 devices, 31 uclasses, devicetree: separate
1037 21:44:59.310799 WDT: Not starting watchdog@f0d0
1038 21:44:59.343078 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1039 21:44:59.355539 Loading Environment from FAT... Card did not respond to voltage select! : -110
1040 21:44:59.360527 ** Bad device specification mmc 0 **
1041 21:44:59.370835 Card did not respond to voltage select! : -110
1042 21:44:59.378478 ** Bad device specification mmc 0 **
1043 21:44:59.378911 Couldn't find partition mmc 0
1044 21:44:59.386815 Card did not respond to voltage select! : -110
1045 21:44:59.392404 ** Bad device specification mmc 0 **
1046 21:44:59.392834 Couldn't find partition mmc 0
1047 21:44:59.397483 Error: could not access storage.
1048 21:44:59.739835 Net: eth0: ethernet@ff3f0000
1049 21:44:59.740353 starting USB...
1050 21:44:59.991609 Bus usb@ff500000: Register 3000140 NbrPorts 3
1051 21:44:59.992119 Starting the controller
1052 21:44:59.998625 USB XHCI 1.10
1053 21:45:01.554920 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1054 21:45:01.562250 scanning usb for storage devices... 0 Storage Device(s) found
1056 21:45:01.613941 Hit any key to stop autoboot: 1
1057 21:45:01.614716 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1058 21:45:01.615598 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1059 21:45:01.616165 Setting prompt string to ['=>']
1060 21:45:01.616647 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1061 21:45:01.620572 0
1062 21:45:01.621425 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 21:45:01.621898 Sending with 10 millisecond of delay
1065 21:45:02.756457 => setenv autoload no
1066 21:45:02.767243 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1067 21:45:02.772191 setenv autoload no
1068 21:45:02.772944 Sending with 10 millisecond of delay
1070 21:45:04.569813 => setenv initrd_high 0xffffffff
1071 21:45:04.580556 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1072 21:45:04.581385 setenv initrd_high 0xffffffff
1073 21:45:04.582094 Sending with 10 millisecond of delay
1075 21:45:06.198016 => setenv fdt_high 0xffffffff
1076 21:45:06.208753 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1077 21:45:06.209555 setenv fdt_high 0xffffffff
1078 21:45:06.210260 Sending with 10 millisecond of delay
1080 21:45:06.502037 => dhcp
1081 21:45:06.512763 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1082 21:45:06.513597 dhcp
1083 21:45:06.514030 Speed: 1000, full duplex
1084 21:45:06.514439 BOOTP broadcast 1
1085 21:45:06.760195 BOOTP broadcast 2
1086 21:45:06.919396 DHCP client bound to address 192.168.6.33 (407 ms)
1087 21:45:06.920308 Sending with 10 millisecond of delay
1089 21:45:08.601456 => setenv serverip 192.168.6.2
1090 21:45:08.612585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1091 21:45:08.613528 setenv serverip 192.168.6.2
1092 21:45:08.614277 Sending with 10 millisecond of delay
1094 21:45:12.339317 => tftpboot 0x01080000 699433/tftp-deploy-0u_jd6gr/kernel/uImage
1095 21:45:12.350108 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1096 21:45:12.351040 tftpboot 0x01080000 699433/tftp-deploy-0u_jd6gr/kernel/uImage
1097 21:45:12.351512 Speed: 1000, full duplex
1098 21:45:12.351913 Using ethernet@ff3f0000 device
1099 21:45:12.352935 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1100 21:45:12.358649 Filename '699433/tftp-deploy-0u_jd6gr/kernel/uImage'.
1101 21:45:12.362356 Load address: 0x1080000
1102 21:45:12.582060 Loading: * UDP wrong checksum 000000ff 000022f9
1103 21:45:12.616273 # UDP wrong checksum 000000ff 0000a9eb
1104 21:45:16.013577 ############## UDP wrong checksum 000000ff 0000959f
1105 21:45:16.030884 UDP wrong checksum 000000ff 00003292
1106 21:45:17.030592 ####
1107 21:45:17.031220 TFTP error: trying to overwrite reserved memory...
1109 21:45:17.032786 end: 2.4.3 bootloader-commands (duration 00:00:15) [common]
1112 21:45:17.034781 end: 2.4 uboot-commands (duration 00:00:52) [common]
1114 21:45:17.036304 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1116 21:45:17.037465 end: 2 uboot-action (duration 00:00:53) [common]
1118 21:45:17.039147 Cleaning after the job
1119 21:45:17.039770 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/ramdisk
1120 21:45:17.072621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/kernel
1121 21:45:17.129626 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/dtb
1122 21:45:17.130491 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/699433/tftp-deploy-0u_jd6gr/modules
1123 21:45:17.188702 start: 4.1 power-off (timeout 00:00:30) [common]
1124 21:45:17.189385 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1125 21:45:17.222775 >> OK - accepted request
1126 21:45:17.224799 Returned 0 in 0 seconds
1127 21:45:17.325591 end: 4.1 power-off (duration 00:00:00) [common]
1129 21:45:17.326605 start: 4.2 read-feedback (timeout 00:10:00) [common]
1130 21:45:17.327264 Listened to connection for namespace 'common' for up to 1s
1131 21:45:18.328192 Finalising connection for namespace 'common'
1132 21:45:18.328642 Disconnecting from shell: Finalise
1133 21:45:18.328901 =>
1134 21:45:18.429637 end: 4.2 read-feedback (duration 00:00:01) [common]
1135 21:45:18.430354 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/699433
1136 21:45:18.794080 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/699433
1137 21:45:18.794716 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.