Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:20:07.215420 lava-dispatcher, installed at version: 2024.01
2 21:20:07.216529 start: 0 validate
3 21:20:07.217285 Start time: 2024-09-03 21:20:07.217252+00:00 (UTC)
4 21:20:07.218119 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:20:07.218883 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:20:07.256502 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:20:07.257095 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-26-g88fac17500f4%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 21:20:08.294948 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:20:08.295642 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-26-g88fac17500f4%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 21:20:33.446041 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:20:33.446541 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-26-g88fac17500f4%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 21:20:34.492375 validate duration: 27.28
14 21:20:34.493304 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:20:34.493669 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:20:34.493998 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:20:34.494668 Not decompressing ramdisk as can be used compressed.
18 21:20:34.495158 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:20:34.495462 saving as /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/ramdisk/rootfs.cpio.gz
20 21:20:34.495774 total size: 8181887 (7 MB)
21 21:20:34.543957 progress 0 % (0 MB)
22 21:20:34.557023 progress 5 % (0 MB)
23 21:20:34.568851 progress 10 % (0 MB)
24 21:20:34.578553 progress 15 % (1 MB)
25 21:20:34.584312 progress 20 % (1 MB)
26 21:20:34.590334 progress 25 % (1 MB)
27 21:20:34.596194 progress 30 % (2 MB)
28 21:20:34.602065 progress 35 % (2 MB)
29 21:20:34.607519 progress 40 % (3 MB)
30 21:20:34.613601 progress 45 % (3 MB)
31 21:20:34.619031 progress 50 % (3 MB)
32 21:20:34.625030 progress 55 % (4 MB)
33 21:20:34.630702 progress 60 % (4 MB)
34 21:20:34.636771 progress 65 % (5 MB)
35 21:20:34.642238 progress 70 % (5 MB)
36 21:20:34.648278 progress 75 % (5 MB)
37 21:20:34.653715 progress 80 % (6 MB)
38 21:20:34.659546 progress 85 % (6 MB)
39 21:20:34.665212 progress 90 % (7 MB)
40 21:20:34.671057 progress 95 % (7 MB)
41 21:20:34.676146 progress 100 % (7 MB)
42 21:20:34.676860 7 MB downloaded in 0.18 s (43.09 MB/s)
43 21:20:34.677411 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:20:34.678304 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:20:34.678600 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:20:34.678868 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:20:34.679396 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-26-g88fac17500f4/arm64/defconfig+debug/gcc-12/kernel/Image
49 21:20:34.679680 saving as /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/kernel/Image
50 21:20:34.679918 total size: 167969280 (160 MB)
51 21:20:34.680174 No compression specified
52 21:20:34.714869 progress 0 % (0 MB)
53 21:20:34.824598 progress 5 % (8 MB)
54 21:20:34.935863 progress 10 % (16 MB)
55 21:20:35.043634 progress 15 % (24 MB)
56 21:20:35.152458 progress 20 % (32 MB)
57 21:20:35.259340 progress 25 % (40 MB)
58 21:20:35.365136 progress 30 % (48 MB)
59 21:20:35.469935 progress 35 % (56 MB)
60 21:20:35.576156 progress 40 % (64 MB)
61 21:20:35.682815 progress 45 % (72 MB)
62 21:20:35.790635 progress 50 % (80 MB)
63 21:20:35.897558 progress 55 % (88 MB)
64 21:20:36.004873 progress 60 % (96 MB)
65 21:20:36.120211 progress 65 % (104 MB)
66 21:20:36.236035 progress 70 % (112 MB)
67 21:20:36.353511 progress 75 % (120 MB)
68 21:20:36.470729 progress 80 % (128 MB)
69 21:20:36.594220 progress 85 % (136 MB)
70 21:20:36.712940 progress 90 % (144 MB)
71 21:20:36.824090 progress 95 % (152 MB)
72 21:20:36.937320 progress 100 % (160 MB)
73 21:20:36.937933 160 MB downloaded in 2.26 s (70.94 MB/s)
74 21:20:36.938413 end: 1.2.1 http-download (duration 00:00:02) [common]
76 21:20:36.939225 end: 1.2 download-retry (duration 00:00:02) [common]
77 21:20:36.939501 start: 1.3 download-retry (timeout 00:09:58) [common]
78 21:20:36.939767 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 21:20:36.940300 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-26-g88fac17500f4/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 21:20:36.940597 saving as /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 21:20:36.940808 total size: 53173 (0 MB)
82 21:20:36.941019 No compression specified
83 21:20:36.987136 progress 61 % (0 MB)
84 21:20:36.988304 progress 100 % (0 MB)
85 21:20:36.989030 0 MB downloaded in 0.05 s (1.05 MB/s)
86 21:20:36.989647 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:20:36.990659 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:20:36.990989 start: 1.4 download-retry (timeout 00:09:58) [common]
90 21:20:36.991313 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 21:20:36.992857 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-26-g88fac17500f4/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 21:20:36.993349 saving as /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/modules/modules.tar
93 21:20:36.993647 total size: 27444600 (26 MB)
94 21:20:36.994072 Using unxz to decompress xz
95 21:20:37.057340 progress 0 % (0 MB)
96 21:20:37.272099 progress 5 % (1 MB)
97 21:20:37.492379 progress 10 % (2 MB)
98 21:20:37.710750 progress 15 % (3 MB)
99 21:20:37.928813 progress 20 % (5 MB)
100 21:20:38.146251 progress 25 % (6 MB)
101 21:20:38.368698 progress 30 % (7 MB)
102 21:20:38.562186 progress 35 % (9 MB)
103 21:20:38.780737 progress 40 % (10 MB)
104 21:20:38.988891 progress 45 % (11 MB)
105 21:20:39.198464 progress 50 % (13 MB)
106 21:20:39.417348 progress 55 % (14 MB)
107 21:20:39.643139 progress 60 % (15 MB)
108 21:20:39.855112 progress 65 % (17 MB)
109 21:20:40.075248 progress 70 % (18 MB)
110 21:20:40.299361 progress 75 % (19 MB)
111 21:20:40.558647 progress 80 % (20 MB)
112 21:20:40.768193 progress 85 % (22 MB)
113 21:20:40.994340 progress 90 % (23 MB)
114 21:20:41.196768 progress 95 % (24 MB)
115 21:20:41.402541 progress 100 % (26 MB)
116 21:20:41.417997 26 MB downloaded in 4.42 s (5.92 MB/s)
117 21:20:41.418624 end: 1.4.1 http-download (duration 00:00:04) [common]
119 21:20:41.419548 end: 1.4 download-retry (duration 00:00:04) [common]
120 21:20:41.419887 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 21:20:41.420258 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 21:20:41.420580 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:20:41.420894 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 21:20:41.421511 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc
125 21:20:41.422029 makedir: /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin
126 21:20:41.422448 makedir: /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/tests
127 21:20:41.422847 makedir: /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/results
128 21:20:41.423223 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-add-keys
129 21:20:41.423812 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-add-sources
130 21:20:41.424449 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-background-process-start
131 21:20:41.425061 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-background-process-stop
132 21:20:41.426076 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-common-functions
133 21:20:41.426712 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-echo-ipv4
134 21:20:41.427296 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-install-packages
135 21:20:41.427870 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-installed-packages
136 21:20:41.428602 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-os-build
137 21:20:41.429465 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-probe-channel
138 21:20:41.430100 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-probe-ip
139 21:20:41.430672 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-target-ip
140 21:20:41.431256 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-target-mac
141 21:20:41.431813 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-target-storage
142 21:20:41.432757 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-test-case
143 21:20:41.433372 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-test-event
144 21:20:41.433923 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-test-feedback
145 21:20:41.434475 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-test-raise
146 21:20:41.435014 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-test-reference
147 21:20:41.435555 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-test-runner
148 21:20:41.436183 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-test-set
149 21:20:41.436766 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-test-shell
150 21:20:41.437352 Updating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-install-packages (oe)
151 21:20:41.437952 Updating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/bin/lava-installed-packages (oe)
152 21:20:41.438439 Creating /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/environment
153 21:20:41.438892 LAVA metadata
154 21:20:41.439193 - LAVA_JOB_ID=699413
155 21:20:41.439439 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:20:41.439852 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 21:20:41.441609 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:20:41.441959 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 21:20:41.442183 skipped lava-vland-overlay
160 21:20:41.442463 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:20:41.442786 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 21:20:41.443054 skipped lava-multinode-overlay
163 21:20:41.443346 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:20:41.443657 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 21:20:41.443967 Loading test definitions
166 21:20:41.444359 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 21:20:41.444637 Using /lava-699413 at stage 0
168 21:20:41.446003 uuid=699413_1.5.2.4.1 testdef=None
169 21:20:41.446390 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:20:41.446715 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 21:20:41.448828 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:20:41.449753 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 21:20:41.452424 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:20:41.453392 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 21:20:41.455876 runner path: /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/0/tests/0_dmesg test_uuid 699413_1.5.2.4.1
178 21:20:41.456593 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:20:41.457448 Creating lava-test-runner.conf files
181 21:20:41.457687 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/699413/lava-overlay-rgxvkhgc/lava-699413/0 for stage 0
182 21:20:41.458396 - 0_dmesg
183 21:20:41.458835 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:20:41.459176 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 21:20:41.485693 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:20:41.486167 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 21:20:41.486439 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:20:41.486714 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:20:41.486983 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 21:20:42.454228 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:20:42.454694 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 21:20:42.454941 extracting modules file /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/699413/extract-overlay-ramdisk-2gjqc404/ramdisk
193 21:20:44.201565 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 21:20:44.202055 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
195 21:20:44.202363 [common] Applying overlay /var/lib/lava/dispatcher/tmp/699413/compress-overlay-sh4hexx0/overlay-1.5.2.5.tar.gz to ramdisk
196 21:20:44.202613 [common] Applying overlay /var/lib/lava/dispatcher/tmp/699413/compress-overlay-sh4hexx0/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/699413/extract-overlay-ramdisk-2gjqc404/ramdisk
197 21:20:44.235050 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:20:44.235509 start: 1.5.6 prepare-kernel (timeout 00:09:50) [common]
199 21:20:44.235784 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:50) [common]
200 21:20:44.236037 Converting downloaded kernel to a uImage
201 21:20:44.236357 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/kernel/Image /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/kernel/uImage
202 21:20:45.974669 output: Image Name:
203 21:20:45.975091 output: Created: Tue Sep 3 21:20:44 2024
204 21:20:45.975321 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:20:45.975539 output: Data Size: 167969280 Bytes = 164032.50 KiB = 160.19 MiB
206 21:20:45.975753 output: Load Address: 01080000
207 21:20:45.975964 output: Entry Point: 01080000
208 21:20:45.976220 output:
209 21:20:45.976569 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 21:20:45.976860 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 21:20:45.977152 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 21:20:45.977427 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:20:45.977704 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 21:20:45.977985 Building ramdisk /var/lib/lava/dispatcher/tmp/699413/extract-overlay-ramdisk-2gjqc404/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/699413/extract-overlay-ramdisk-2gjqc404/ramdisk
215 21:20:52.644493 >> 436302 blocks
216 21:21:11.574338 Adding RAMdisk u-boot header.
217 21:21:11.574852 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/699413/extract-overlay-ramdisk-2gjqc404/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/699413/extract-overlay-ramdisk-2gjqc404/ramdisk.cpio.gz.uboot
218 21:21:12.165397 output: Image Name:
219 21:21:12.166046 output: Created: Tue Sep 3 21:21:11 2024
220 21:21:12.166500 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:21:12.167004 output: Data Size: 53177846 Bytes = 51931.49 KiB = 50.71 MiB
222 21:21:12.167463 output: Load Address: 00000000
223 21:21:12.167886 output: Entry Point: 00000000
224 21:21:12.168407 output:
225 21:21:12.172135 rename /var/lib/lava/dispatcher/tmp/699413/extract-overlay-ramdisk-2gjqc404/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/ramdisk/ramdisk.cpio.gz.uboot
226 21:21:12.172717 end: 1.5.8 compress-ramdisk (duration 00:00:26) [common]
227 21:21:12.173117 end: 1.5 prepare-tftp-overlay (duration 00:00:31) [common]
228 21:21:12.173655 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:22) [common]
229 21:21:12.174126 No LXC device requested
230 21:21:12.174680 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:21:12.175242 start: 1.7 deploy-device-env (timeout 00:09:22) [common]
232 21:21:12.175796 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:21:12.176348 Checking files for TFTP limit of 4294967296 bytes.
234 21:21:12.179840 end: 1 tftp-deploy (duration 00:00:38) [common]
235 21:21:12.180599 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:21:12.181153 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:21:12.181670 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:21:12.182176 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:21:12.182744 Using kernel file from prepare-kernel: 699413/tftp-deploy-bmaeeak2/kernel/uImage
240 21:21:12.183377 substitutions:
241 21:21:12.183814 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:21:12.184277 - {DTB_ADDR}: 0x01070000
243 21:21:12.184682 - {DTB}: 699413/tftp-deploy-bmaeeak2/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 21:21:12.185085 - {INITRD}: 699413/tftp-deploy-bmaeeak2/ramdisk/ramdisk.cpio.gz.uboot
245 21:21:12.185482 - {KERNEL_ADDR}: 0x01080000
246 21:21:12.185877 - {KERNEL}: 699413/tftp-deploy-bmaeeak2/kernel/uImage
247 21:21:12.186271 - {LAVA_MAC}: None
248 21:21:12.186701 - {PRESEED_CONFIG}: None
249 21:21:12.187095 - {PRESEED_LOCAL}: None
250 21:21:12.187483 - {RAMDISK_ADDR}: 0x08000000
251 21:21:12.187869 - {RAMDISK}: 699413/tftp-deploy-bmaeeak2/ramdisk/ramdisk.cpio.gz.uboot
252 21:21:12.188303 - {ROOT_PART}: None
253 21:21:12.188696 - {ROOT}: None
254 21:21:12.189086 - {SERVER_IP}: 192.168.6.2
255 21:21:12.189482 - {TEE_ADDR}: 0x83000000
256 21:21:12.189871 - {TEE}: None
257 21:21:12.190258 Parsed boot commands:
258 21:21:12.190634 - setenv autoload no
259 21:21:12.191018 - setenv initrd_high 0xffffffff
260 21:21:12.191410 - setenv fdt_high 0xffffffff
261 21:21:12.191798 - dhcp
262 21:21:12.192226 - setenv serverip 192.168.6.2
263 21:21:12.192616 - tftpboot 0x01080000 699413/tftp-deploy-bmaeeak2/kernel/uImage
264 21:21:12.193004 - tftpboot 0x08000000 699413/tftp-deploy-bmaeeak2/ramdisk/ramdisk.cpio.gz.uboot
265 21:21:12.193396 - tftpboot 0x01070000 699413/tftp-deploy-bmaeeak2/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 21:21:12.193784 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:21:12.194183 - bootm 0x01080000 0x08000000 0x01070000
268 21:21:12.194702 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:21:12.196222 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:21:12.196678 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 21:21:12.211913 Setting prompt string to ['lava-test: # ']
273 21:21:12.213514 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:21:12.214122 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:21:12.214657 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:21:12.215176 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:21:12.216412 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 21:21:12.260446 >> OK - accepted request
279 21:21:12.263211 Returned 0 in 0 seconds
280 21:21:12.364432 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:21:12.366138 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:21:12.366724 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:21:12.367240 Setting prompt string to ['Hit any key to stop autoboot']
285 21:21:12.367695 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:21:12.369315 Trying 192.168.56.21...
287 21:21:12.369800 Connected to conserv1.
288 21:21:12.370232 Escape character is '^]'.
289 21:21:12.370667
290 21:21:12.371096 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 21:21:12.371541
292 21:21:19.908033 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 21:21:19.908467 bl2_stage_init 0x01
294 21:21:19.908703 bl2_stage_init 0x81
295 21:21:19.913392 hw id: 0x0000 - pwm id 0x01
296 21:21:19.913810 bl2_stage_init 0xc1
297 21:21:19.918133 bl2_stage_init 0x02
298 21:21:19.918596
299 21:21:19.918930 L0:00000000
300 21:21:19.919242 L1:00000703
301 21:21:19.919465 L2:00008067
302 21:21:19.923540 L3:15000000
303 21:21:19.923834 S1:00000000
304 21:21:19.924066 B2:20282000
305 21:21:19.924293 B1:a0f83180
306 21:21:19.924495
307 21:21:19.924695 TE: 68067
308 21:21:19.924896
309 21:21:19.934898 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 21:21:19.935201
311 21:21:19.935410 Board ID = 1
312 21:21:19.935610 Set cpu clk to 24M
313 21:21:19.935808 Set clk81 to 24M
314 21:21:19.940433 Use GP1_pll as DSU clk.
315 21:21:19.940713 DSU clk: 1200 Mhz
316 21:21:19.940920 CPU clk: 1200 MHz
317 21:21:19.946105 Set clk81 to 166.6M
318 21:21:19.951442 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 21:21:19.951753 board id: 1
320 21:21:19.959722 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:21:19.970415 fw parse done
322 21:21:19.976331 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:21:20.018977 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:21:20.029997 PIEI prepare done
325 21:21:20.030339 fastboot data load
326 21:21:20.030553 fastboot data verify
327 21:21:20.035500 verify result: 266
328 21:21:20.041080 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 21:21:20.041382 LPDDR4 probe
330 21:21:20.041607 ddr clk to 1584MHz
331 21:21:20.049125 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:21:20.086451
333 21:21:20.086841 dmc_version 0001
334 21:21:20.093113 Check phy result
335 21:21:20.098965 INFO : End of CA training
336 21:21:20.099283 INFO : End of initialization
337 21:21:20.104531 INFO : Training has run successfully!
338 21:21:20.104822 Check phy result
339 21:21:20.110226 INFO : End of initialization
340 21:21:20.110677 INFO : End of read enable training
341 21:21:20.113450 INFO : End of fine write leveling
342 21:21:20.119100 INFO : End of Write leveling coarse delay
343 21:21:20.124740 INFO : Training has run successfully!
344 21:21:20.125043 Check phy result
345 21:21:20.125255 INFO : End of initialization
346 21:21:20.130244 INFO : End of read dq deskew training
347 21:21:20.135878 INFO : End of MPR read delay center optimization
348 21:21:20.136217 INFO : End of write delay center optimization
349 21:21:20.141504 INFO : End of read delay center optimization
350 21:21:20.147133 INFO : End of max read latency training
351 21:21:20.147464 INFO : Training has run successfully!
352 21:21:20.152731 1D training succeed
353 21:21:20.158537 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:21:20.206228 Check phy result
355 21:21:20.206652 INFO : End of initialization
356 21:21:20.228568 INFO : End of 2D read delay Voltage center optimization
357 21:21:20.247718 INFO : End of 2D read delay Voltage center optimization
358 21:21:20.299525 INFO : End of 2D write delay Voltage center optimization
359 21:21:20.348886 INFO : End of 2D write delay Voltage center optimization
360 21:21:20.354444 INFO : Training has run successfully!
361 21:21:20.354773
362 21:21:20.354986 channel==0
363 21:21:20.359889 RxClkDly_Margin_A0==78 ps 8
364 21:21:20.360254 TxDqDly_Margin_A0==88 ps 9
365 21:21:20.365565 RxClkDly_Margin_A1==88 ps 9
366 21:21:20.365917 TxDqDly_Margin_A1==98 ps 10
367 21:21:20.366132 TrainedVREFDQ_A0==74
368 21:21:20.371050 TrainedVREFDQ_A1==75
369 21:21:20.371420 VrefDac_Margin_A0==24
370 21:21:20.371639 DeviceVref_Margin_A0==40
371 21:21:20.376783 VrefDac_Margin_A1==23
372 21:21:20.377091 DeviceVref_Margin_A1==39
373 21:21:20.377298
374 21:21:20.377503
375 21:21:20.377707 channel==1
376 21:21:20.382204 RxClkDly_Margin_A0==78 ps 8
377 21:21:20.382475 TxDqDly_Margin_A0==98 ps 10
378 21:21:20.388491 RxClkDly_Margin_A1==88 ps 9
379 21:21:20.388765 TxDqDly_Margin_A1==88 ps 9
380 21:21:20.393499 TrainedVREFDQ_A0==78
381 21:21:20.393760 TrainedVREFDQ_A1==77
382 21:21:20.393966 VrefDac_Margin_A0==22
383 21:21:20.399016 DeviceVref_Margin_A0==36
384 21:21:20.399279 VrefDac_Margin_A1==22
385 21:21:20.404733 DeviceVref_Margin_A1==37
386 21:21:20.404995
387 21:21:20.405205 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:21:20.405408
389 21:21:20.438300 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000018 00000016 00000018 00000016 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 21:21:20.438705 2D training succeed
391 21:21:20.443882 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:21:20.449436 auto size-- 65535DDR cs0 size: 2048MB
393 21:21:20.449729 DDR cs1 size: 2048MB
394 21:21:20.455046 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:21:20.455328 cs0 DataBus test pass
396 21:21:20.460804 cs1 DataBus test pass
397 21:21:20.461160 cs0 AddrBus test pass
398 21:21:20.461373 cs1 AddrBus test pass
399 21:21:20.461579
400 21:21:20.466754 100bdlr_step_size ps== 478
401 21:21:20.467062 result report
402 21:21:20.472363 boot times 0Enable ddr reg access
403 21:21:20.477007 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:21:20.490802 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 21:21:21.144802 bl2z: ptr: 05129330, size: 00001e40
406 21:21:21.151938 0.0;M3 CHK:0;cm4_sp_mode 0
407 21:21:21.152309 MVN_1=0x00000000
408 21:21:21.152521 MVN_2=0x00000000
409 21:21:21.163449 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 21:21:21.163773 OPS=0x04
411 21:21:21.164006 ring efuse init
412 21:21:21.169133 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 21:21:21.169870 [0.017320 Inits done]
414 21:21:21.170429 secure task start!
415 21:21:21.176993 high task start!
416 21:21:21.177640 low task start!
417 21:21:21.178186 run into bl31
418 21:21:21.185644 NOTICE: BL31: v1.3(release):4fc40b1
419 21:21:21.193473 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 21:21:21.194215 NOTICE: BL31: G12A normal boot!
421 21:21:21.208951 NOTICE: BL31: BL33 decompress pass
422 21:21:21.214570 ERROR: Error initializing runtime service opteed_fast
423 21:21:22.460308 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 21:21:22.460992 bl2_stage_init 0x01
425 21:21:22.461442 bl2_stage_init 0x81
426 21:21:22.465813 hw id: 0x0000 - pwm id 0x01
427 21:21:22.466325 bl2_stage_init 0xc1
428 21:21:22.471970 bl2_stage_init 0x02
429 21:21:22.472494
430 21:21:22.472936 L0:00000000
431 21:21:22.473364 L1:00000703
432 21:21:22.473792 L2:00008067
433 21:21:22.476467 L3:15000000
434 21:21:22.476931 S1:00000000
435 21:21:22.477359 B2:20282000
436 21:21:22.477785 B1:a0f83180
437 21:21:22.478208
438 21:21:22.478634 TE: 70347
439 21:21:22.479059
440 21:21:22.488114 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 21:21:22.488506
442 21:21:22.488712 Board ID = 1
443 21:21:22.488912 Set cpu clk to 24M
444 21:21:22.489109 Set clk81 to 24M
445 21:21:22.492552 Use GP1_pll as DSU clk.
446 21:21:22.492813 DSU clk: 1200 Mhz
447 21:21:22.493015 CPU clk: 1200 MHz
448 21:21:22.498097 Set clk81 to 166.6M
449 21:21:22.503724 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 21:21:22.504126 board id: 1
451 21:21:22.511207 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 21:21:22.522880 fw parse done
453 21:21:22.527861 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 21:21:22.571323 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 21:21:22.582645 PIEI prepare done
456 21:21:22.582966 fastboot data load
457 21:21:22.583178 fastboot data verify
458 21:21:22.588069 verify result: 266
459 21:21:22.593419 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 21:21:22.593683 LPDDR4 probe
461 21:21:22.593886 ddr clk to 1584MHz
462 21:21:23.961264 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 21:21:23.961690 bl2_stage_init 0x01
464 21:21:23.961916 bl2_stage_init 0x81
465 21:21:23.966639 hw id: 0x0000 - pwm id 0x01
466 21:21:23.966939 bl2_stage_init 0xc1
467 21:21:23.972525 bl2_stage_init 0x02
468 21:21:23.972859
469 21:21:23.973094 L0:00000000
470 21:21:23.973315 L1:00000703
471 21:21:23.973536 L2:00008067
472 21:21:23.973753 L3:15000000
473 21:21:23.979261 S1:00000000
474 21:21:23.979590 B2:20282000
475 21:21:23.979829 B1:a0f83180
476 21:21:23.980079
477 21:21:23.980311 TE: 70276
478 21:21:23.980531
479 21:21:23.983441 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 21:21:23.983748
481 21:21:23.989345 Board ID = 1
482 21:21:23.989699 Set cpu clk to 24M
483 21:21:23.989944 Set clk81 to 24M
484 21:21:23.994691 Use GP1_pll as DSU clk.
485 21:21:23.995039 DSU clk: 1200 Mhz
486 21:21:23.995278 CPU clk: 1200 MHz
487 21:21:24.000222 Set clk81 to 166.6M
488 21:21:24.005935 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 21:21:24.006301 board id: 1
490 21:21:24.013057 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 21:21:24.023753 fw parse done
492 21:21:24.028740 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 21:21:24.072322 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 21:21:24.083354 PIEI prepare done
495 21:21:24.083729 fastboot data load
496 21:21:24.083965 fastboot data verify
497 21:21:24.088872 verify result: 266
498 21:21:24.094631 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 21:21:24.094979 LPDDR4 probe
500 21:21:24.095220 ddr clk to 1584MHz
501 21:21:24.102602 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 21:21:24.139766
503 21:21:24.140201 dmc_version 0001
504 21:21:24.146398 Check phy result
505 21:21:24.152448 INFO : End of CA training
506 21:21:24.152814 INFO : End of initialization
507 21:21:24.157966 INFO : Training has run successfully!
508 21:21:24.158307 Check phy result
509 21:21:24.163607 INFO : End of initialization
510 21:21:24.164217 INFO : End of read enable training
511 21:21:24.169228 INFO : End of fine write leveling
512 21:21:24.174786 INFO : End of Write leveling coarse delay
513 21:21:24.175358 INFO : Training has run successfully!
514 21:21:24.175757 Check phy result
515 21:21:24.180427 INFO : End of initialization
516 21:21:24.180765 INFO : End of read dq deskew training
517 21:21:24.185891 INFO : End of MPR read delay center optimization
518 21:21:24.191649 INFO : End of write delay center optimization
519 21:21:24.197196 INFO : End of read delay center optimization
520 21:21:24.197755 INFO : End of max read latency training
521 21:21:24.202793 INFO : Training has run successfully!
522 21:21:24.203347 1D training succeed
523 21:21:24.211911 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 21:21:24.259580 Check phy result
525 21:21:24.260205 INFO : End of initialization
526 21:21:24.281932 INFO : End of 2D read delay Voltage center optimization
527 21:21:24.301096 INFO : End of 2D read delay Voltage center optimization
528 21:21:24.352931 INFO : End of 2D write delay Voltage center optimization
529 21:21:24.402230 INFO : End of 2D write delay Voltage center optimization
530 21:21:24.407711 INFO : Training has run successfully!
531 21:21:24.408149
532 21:21:24.408440 channel==0
533 21:21:24.413406 RxClkDly_Margin_A0==78 ps 8
534 21:21:24.413781 TxDqDly_Margin_A0==98 ps 10
535 21:21:24.418730 RxClkDly_Margin_A1==88 ps 9
536 21:21:24.419100 TxDqDly_Margin_A1==98 ps 10
537 21:21:24.419373 TrainedVREFDQ_A0==74
538 21:21:24.424447 TrainedVREFDQ_A1==74
539 21:21:24.424831 VrefDac_Margin_A0==25
540 21:21:24.425128 DeviceVref_Margin_A0==40
541 21:21:24.430150 VrefDac_Margin_A1==23
542 21:21:24.430530 DeviceVref_Margin_A1==40
543 21:21:24.430810
544 21:21:24.431073
545 21:21:24.435643 channel==1
546 21:21:24.436052 RxClkDly_Margin_A0==88 ps 9
547 21:21:24.436355 TxDqDly_Margin_A0==98 ps 10
548 21:21:24.441334 RxClkDly_Margin_A1==78 ps 8
549 21:21:24.441706 TxDqDly_Margin_A1==88 ps 9
550 21:21:24.446826 TrainedVREFDQ_A0==78
551 21:21:24.447207 TrainedVREFDQ_A1==75
552 21:21:24.447474 VrefDac_Margin_A0==23
553 21:21:24.452455 DeviceVref_Margin_A0==36
554 21:21:24.452848 VrefDac_Margin_A1==22
555 21:21:24.458088 DeviceVref_Margin_A1==39
556 21:21:24.458457
557 21:21:24.458755 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 21:21:24.459019
559 21:21:24.491673 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
560 21:21:24.492385 2D training succeed
561 21:21:24.497449 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 21:21:24.502881 auto size-- 65535DDR cs0 size: 2048MB
563 21:21:24.503474 DDR cs1 size: 2048MB
564 21:21:24.508551 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 21:21:24.508877 cs0 DataBus test pass
566 21:21:24.514072 cs1 DataBus test pass
567 21:21:24.514396 cs0 AddrBus test pass
568 21:21:24.514838 cs1 AddrBus test pass
569 21:21:24.515304
570 21:21:24.519725 100bdlr_step_size ps== 478
571 21:21:24.520061 result report
572 21:21:24.525470 boot times 0Enable ddr reg access
573 21:21:24.530629 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 21:21:24.544504 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 21:21:25.201389 bl2z: ptr: 05129330, size: 00001e40
576 21:21:25.206839 0.0;M3 CHK:0;cm4_sp_mode 0
577 21:21:25.207327 MVN_1=0x00000000
578 21:21:25.207564 MVN_2=0x00000000
579 21:21:25.218832 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 21:21:25.219229 OPS=0x04
581 21:21:25.219452 ring efuse init
582 21:21:25.222795 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 21:21:25.226389 [0.017319 Inits done]
584 21:21:25.226859 secure task start!
585 21:21:25.227184 high task start!
586 21:21:25.231770 low task start!
587 21:21:25.232161 run into bl31
588 21:21:25.242495 NOTICE: BL31: v1.3(release):4fc40b1
589 21:21:25.247871 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 21:21:25.248284 NOTICE: BL31: G12A normal boot!
591 21:21:25.263442 NOTICE: BL31: BL33 decompress pass
592 21:21:25.269131 ERROR: Error initializing runtime service opteed_fast
593 21:21:26.513782 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 21:21:26.514207 bl2_stage_init 0x01
595 21:21:26.514432 bl2_stage_init 0x81
596 21:21:26.519337 hw id: 0x0000 - pwm id 0x01
597 21:21:26.519781 bl2_stage_init 0xc1
598 21:21:26.520141 bl2_stage_init 0x02
599 21:21:26.520484
600 21:21:26.524994 L0:00000000
601 21:21:26.525311 L1:00000703
602 21:21:26.525527 L2:00008067
603 21:21:26.525743 L3:15000000
604 21:21:26.525948 S1:00000000
605 21:21:26.530578 B2:20282000
606 21:21:26.530888 B1:a0f83180
607 21:21:26.531101
608 21:21:26.531314 TE: 73171
609 21:21:26.531518
610 21:21:26.536165 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 21:21:26.536476
612 21:21:26.541739 Board ID = 1
613 21:21:26.542341 Set cpu clk to 24M
614 21:21:26.542684 Set clk81 to 24M
615 21:21:26.547376 Use GP1_pll as DSU clk.
616 21:21:26.547682 DSU clk: 1200 Mhz
617 21:21:26.547897 CPU clk: 1200 MHz
618 21:21:26.548127 Set clk81 to 166.6M
619 21:21:26.558607 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 21:21:26.558986 board id: 1
621 21:21:26.565032 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 21:21:26.575711 fw parse done
623 21:21:26.581218 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 21:21:26.624202 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 21:21:26.635172 PIEI prepare done
626 21:21:26.635489 fastboot data load
627 21:21:26.635704 fastboot data verify
628 21:21:26.640764 verify result: 266
629 21:21:26.646341 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 21:21:26.646635 LPDDR4 probe
631 21:21:26.646859 ddr clk to 1584MHz
632 21:21:26.653655 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 21:21:26.691344
634 21:21:26.691704 dmc_version 0001
635 21:21:26.698166 Check phy result
636 21:21:26.704363 INFO : End of CA training
637 21:21:26.704705 INFO : End of initialization
638 21:21:26.709850 INFO : Training has run successfully!
639 21:21:26.710154 Check phy result
640 21:21:26.715400 INFO : End of initialization
641 21:21:26.715697 INFO : End of read enable training
642 21:21:26.720986 INFO : End of fine write leveling
643 21:21:26.726725 INFO : End of Write leveling coarse delay
644 21:21:26.727039 INFO : Training has run successfully!
645 21:21:26.727276 Check phy result
646 21:21:26.732250 INFO : End of initialization
647 21:21:26.732554 INFO : End of read dq deskew training
648 21:21:26.737810 INFO : End of MPR read delay center optimization
649 21:21:26.743414 INFO : End of write delay center optimization
650 21:21:26.749014 INFO : End of read delay center optimization
651 21:21:26.749331 INFO : End of max read latency training
652 21:21:26.754672 INFO : Training has run successfully!
653 21:21:26.754990 1D training succeed
654 21:21:26.763748 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 21:21:26.811413 Check phy result
656 21:21:26.811809 INFO : End of initialization
657 21:21:26.833901 INFO : End of 2D read delay Voltage center optimization
658 21:21:26.852957 INFO : End of 2D read delay Voltage center optimization
659 21:21:26.905006 INFO : End of 2D write delay Voltage center optimization
660 21:21:26.954125 INFO : End of 2D write delay Voltage center optimization
661 21:21:26.959563 INFO : Training has run successfully!
662 21:21:26.959872
663 21:21:26.960129 channel==0
664 21:21:26.965288 RxClkDly_Margin_A0==78 ps 8
665 21:21:26.965596 TxDqDly_Margin_A0==98 ps 10
666 21:21:26.970770 RxClkDly_Margin_A1==88 ps 9
667 21:21:26.971073 TxDqDly_Margin_A1==98 ps 10
668 21:21:26.971312 TrainedVREFDQ_A0==74
669 21:21:26.976375 TrainedVREFDQ_A1==74
670 21:21:26.976681 VrefDac_Margin_A0==24
671 21:21:26.976919 DeviceVref_Margin_A0==40
672 21:21:26.982102 VrefDac_Margin_A1==23
673 21:21:26.982416 DeviceVref_Margin_A1==40
674 21:21:26.982630
675 21:21:26.982860
676 21:21:26.987626 channel==1
677 21:21:26.987923 RxClkDly_Margin_A0==88 ps 9
678 21:21:26.988176 TxDqDly_Margin_A0==98 ps 10
679 21:21:26.993177 RxClkDly_Margin_A1==78 ps 8
680 21:21:26.993629 TxDqDly_Margin_A1==88 ps 9
681 21:21:26.998771 TrainedVREFDQ_A0==78
682 21:21:26.999101 TrainedVREFDQ_A1==75
683 21:21:26.999323 VrefDac_Margin_A0==22
684 21:21:27.004327 DeviceVref_Margin_A0==36
685 21:21:27.004651 VrefDac_Margin_A1==22
686 21:21:27.009933 DeviceVref_Margin_A1==39
687 21:21:27.010277
688 21:21:27.010494 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 21:21:27.010701
690 21:21:27.043535 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
691 21:21:27.043931 2D training succeed
692 21:21:27.049193 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 21:21:27.054746 auto size-- 65535DDR cs0 size: 2048MB
694 21:21:27.055056 DDR cs1 size: 2048MB
695 21:21:27.060293 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 21:21:27.060739 cs0 DataBus test pass
697 21:21:27.065909 cs1 DataBus test pass
698 21:21:27.066213 cs0 AddrBus test pass
699 21:21:27.066424 cs1 AddrBus test pass
700 21:21:27.066642
701 21:21:27.071508 100bdlr_step_size ps== 478
702 21:21:27.071821 result report
703 21:21:27.077126 boot times 0Enable ddr reg access
704 21:21:27.081930 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 21:21:27.095467 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 21:21:27.751124 bl2z: ptr: 05129330, size: 00001e40
707 21:21:27.759896 0.0;M3 CHK:0;cm4_sp_mode 0
708 21:21:27.760233 MVN_1=0x00000000
709 21:21:27.760447 MVN_2=0x00000000
710 21:21:27.771401 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 21:21:27.771735 OPS=0x04
712 21:21:27.771950 ring efuse init
713 21:21:27.776967 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 21:21:27.777231 [0.017319 Inits done]
715 21:21:27.777437 secure task start!
716 21:21:27.783651 high task start!
717 21:21:27.783925 low task start!
718 21:21:27.784157 run into bl31
719 21:21:27.792865 NOTICE: BL31: v1.3(release):4fc40b1
720 21:21:27.799925 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 21:21:27.800360 NOTICE: BL31: G12A normal boot!
722 21:21:27.816332 NOTICE: BL31: BL33 decompress pass
723 21:21:27.821437 ERROR: Error initializing runtime service opteed_fast
724 21:21:28.617403
725 21:21:28.617792
726 21:21:28.622835 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 21:21:28.623124
728 21:21:28.625991 Model: Libre Computer AML-S905D3-CC Solitude
729 21:21:28.773053 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 21:21:28.787969 DRAM: 2 GiB (effective 3.8 GiB)
731 21:21:28.889714 Core: 406 devices, 33 uclasses, devicetree: separate
732 21:21:28.894736 WDT: Not starting watchdog@f0d0
733 21:21:28.920691 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 21:21:28.932828 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 21:21:28.937806 ** Bad device specification mmc 0 **
736 21:21:28.947818 Card did not respond to voltage select! : -110
737 21:21:28.954541 ** Bad device specification mmc 0 **
738 21:21:28.954832 Couldn't find partition mmc 0
739 21:21:28.963965 Card did not respond to voltage select! : -110
740 21:21:28.969398 ** Bad device specification mmc 0 **
741 21:21:28.969785 Couldn't find partition mmc 0
742 21:21:28.973458 Error: could not access storage.
743 21:21:29.270651 Net: eth0: ethernet@ff3f0000
744 21:21:29.271057 starting USB...
745 21:21:29.515533 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 21:21:29.516149 Starting the controller
747 21:21:29.522470 USB XHCI 1.10
748 21:21:31.076605 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 21:21:31.084832 scanning usb for storage devices... 0 Storage Device(s) found
751 21:21:31.135948 Hit any key to stop autoboot: 1
752 21:21:31.136650 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
753 21:21:31.136993 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
754 21:21:31.137245 Setting prompt string to ['=>']
755 21:21:31.137484 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
756 21:21:31.150883 0
757 21:21:31.151478 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 21:21:31.252246 => setenv autoload no
760 21:21:31.252934 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
761 21:21:31.257194 setenv autoload no
763 21:21:31.358216 => setenv initrd_high 0xffffffff
764 21:21:31.358736 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 21:21:31.363101 setenv initrd_high 0xffffffff
767 21:21:31.464082 => setenv fdt_high 0xffffffff
768 21:21:31.464613 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 21:21:31.468232 setenv fdt_high 0xffffffff
771 21:21:31.569199 => dhcp
772 21:21:31.569687 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 21:21:31.573757 dhcp
774 21:21:32.078136 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 21:21:32.078506 Speed: 1000, full duplex
776 21:21:32.078712 BOOTP broadcast 1
777 21:21:32.327302 BOOTP broadcast 2
778 21:21:32.828307 BOOTP broadcast 3
779 21:21:33.829401 BOOTP broadcast 4
780 21:21:35.830387 BOOTP broadcast 5
781 21:21:35.848868 DHCP client bound to address 192.168.6.12 (3769 ms)
783 21:21:35.950000 => setenv serverip 192.168.6.2
784 21:21:35.950523 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
785 21:21:35.955024 setenv serverip 192.168.6.2
787 21:21:36.055914 => tftpboot 0x01080000 699413/tftp-deploy-bmaeeak2/kernel/uImage
788 21:21:36.056372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
789 21:21:36.063126 tftpboot 0x01080000 699413/tftp-deploy-bmaeeak2/kernel/uImage
790 21:21:36.063406 Speed: 1000, full duplex
791 21:21:36.063620 Using ethernet@ff3f0000 device
792 21:21:36.068716 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 21:21:36.074147 Filename '699413/tftp-deploy-bmaeeak2/kernel/uImage'.
794 21:21:36.078308 Load address: 0x1080000
795 21:21:40.341768 Loading: *###################
796 21:21:40.342191 TFTP error: trying to overwrite reserved memory...
798 21:21:40.343064 end: 2.4.3 bootloader-commands (duration 00:00:09) [common]
801 21:21:40.344082 end: 2.4 uboot-commands (duration 00:00:28) [common]
803 21:21:40.344804 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
805 21:21:40.345403 end: 2 uboot-action (duration 00:00:28) [common]
807 21:21:40.346266 Cleaning after the job
808 21:21:40.346592 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/ramdisk
809 21:21:40.363130 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/kernel
810 21:21:40.369584 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/dtb
811 21:21:40.370680 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/699413/tftp-deploy-bmaeeak2/modules
812 21:21:40.378650 start: 4.1 power-off (timeout 00:00:30) [common]
813 21:21:40.379252 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
814 21:21:40.415361 >> OK - accepted request
815 21:21:40.417692 Returned 0 in 0 seconds
816 21:21:40.518473 end: 4.1 power-off (duration 00:00:00) [common]
818 21:21:40.519492 start: 4.2 read-feedback (timeout 00:10:00) [common]
819 21:21:40.520208 Listened to connection for namespace 'common' for up to 1s
820 21:21:41.521086 Finalising connection for namespace 'common'
821 21:21:41.521594 Disconnecting from shell: Finalise
822 21:21:41.521915 =>
823 21:21:41.622603 end: 4.2 read-feedback (duration 00:00:01) [common]
824 21:21:41.623083 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/699413
825 21:21:41.987339 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/699413
826 21:21:41.988483 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.