Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 02:59:29.112932 lava-dispatcher, installed at version: 2024.01
2 02:59:29.113312 start: 0 validate
3 02:59:29.113461 Start time: 2024-09-05 02:59:29.113454+00:00 (UTC)
4 02:59:29.113647 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 02:59:29.401840 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/kernel/zImage exists
6 02:59:29.546368 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb exists
7 02:59:29.690477 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 02:59:29.833993 Validating that http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/modules.tar.xz exists
9 02:59:29.980784 validate duration: 0.87
11 02:59:29.981338 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 02:59:29.981511 start: 1.1 download-retry (timeout 00:10:00) [common]
13 02:59:29.981731 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 02:59:29.982126 Not decompressing ramdisk as can be used compressed.
15 02:59:29.982369 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 02:59:29.982504 saving as /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/ramdisk/initrd.cpio.gz
17 02:59:29.982624 total size: 4775763 (4 MB)
18 02:59:30.267610 progress 0 % (0 MB)
19 02:59:30.694605 progress 5 % (0 MB)
20 02:59:31.003357 progress 10 % (0 MB)
21 02:59:31.007505 progress 15 % (0 MB)
22 02:59:31.010750 progress 20 % (0 MB)
23 02:59:31.143672 progress 25 % (1 MB)
24 02:59:31.165322 progress 30 % (1 MB)
25 02:59:31.308530 progress 35 % (1 MB)
26 02:59:31.440338 progress 40 % (1 MB)
27 02:59:31.462814 progress 45 % (2 MB)
28 02:59:31.604798 progress 50 % (2 MB)
29 02:59:31.727527 progress 55 % (2 MB)
30 02:59:31.755663 progress 60 % (2 MB)
31 02:59:31.893484 progress 65 % (2 MB)
32 02:59:32.008780 progress 70 % (3 MB)
33 02:59:32.048926 progress 75 % (3 MB)
34 02:59:32.171295 progress 80 % (3 MB)
35 02:59:32.204421 progress 85 % (3 MB)
36 02:59:32.341075 progress 90 % (4 MB)
37 02:59:32.434961 progress 95 % (4 MB)
38 02:59:32.488263 progress 100 % (4 MB)
39 02:59:32.488568 4 MB downloaded in 2.51 s (1.82 MB/s)
40 02:59:32.488750 end: 1.1.1 http-download (duration 00:00:03) [common]
42 02:59:32.488982 end: 1.1 download-retry (duration 00:00:03) [common]
43 02:59:32.489060 start: 1.2 download-retry (timeout 00:09:57) [common]
44 02:59:32.489131 start: 1.2.1 http-download (timeout 00:09:57) [common]
45 02:59:32.489320 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/kernel/zImage
46 02:59:32.489384 saving as /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/kernel/zImage
47 02:59:32.489437 total size: 11952640 (11 MB)
48 02:59:32.489492 No compression specified
49 02:59:32.632250 progress 0 % (0 MB)
50 02:59:32.782056 progress 5 % (0 MB)
51 02:59:32.936179 progress 10 % (1 MB)
52 02:59:33.209633 progress 15 % (1 MB)
53 02:59:33.360627 progress 20 % (2 MB)
54 02:59:33.655356 progress 25 % (2 MB)
55 02:59:33.934689 progress 30 % (3 MB)
56 02:59:34.112715 progress 35 % (4 MB)
57 02:59:34.396757 progress 40 % (4 MB)
58 02:59:34.676438 progress 45 % (5 MB)
59 02:59:34.952788 progress 50 % (5 MB)
60 02:59:35.148224 progress 55 % (6 MB)
61 02:59:35.389166 progress 60 % (6 MB)
62 02:59:35.669033 progress 65 % (7 MB)
63 02:59:35.913418 progress 70 % (8 MB)
64 02:59:36.108205 progress 75 % (8 MB)
65 02:59:36.371561 progress 80 % (9 MB)
66 02:59:36.572107 progress 85 % (9 MB)
67 02:59:36.817377 progress 90 % (10 MB)
68 02:59:37.064721 progress 95 % (10 MB)
69 02:59:37.248774 progress 100 % (11 MB)
70 02:59:37.249300 11 MB downloaded in 4.76 s (2.39 MB/s)
71 02:59:37.249606 end: 1.2.1 http-download (duration 00:00:05) [common]
73 02:59:37.250057 end: 1.2 download-retry (duration 00:00:05) [common]
74 02:59:37.250221 start: 1.3 download-retry (timeout 00:09:53) [common]
75 02:59:37.250371 start: 1.3.1 http-download (timeout 00:09:53) [common]
76 02:59:37.250704 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
77 02:59:37.250845 saving as /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/dtb/am335x-boneblack.dtb
78 02:59:37.250955 total size: 70308 (0 MB)
79 02:59:37.251069 No compression specified
80 02:59:37.395337 progress 46 % (0 MB)
81 02:59:37.397038 progress 93 % (0 MB)
82 02:59:37.397673 progress 100 % (0 MB)
83 02:59:37.397932 0 MB downloaded in 0.15 s (0.46 MB/s)
84 02:59:37.398206 end: 1.3.1 http-download (duration 00:00:00) [common]
86 02:59:37.398648 end: 1.3 download-retry (duration 00:00:00) [common]
87 02:59:37.398799 start: 1.4 download-retry (timeout 00:09:53) [common]
88 02:59:37.398954 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 02:59:37.399270 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 02:59:37.399403 saving as /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/nfsrootfs/full.rootfs.tar
91 02:59:37.399511 total size: 117747780 (112 MB)
92 02:59:37.399626 Using unxz to decompress xz
93 02:59:37.543877 progress 0 % (0 MB)
94 02:59:39.748167 progress 5 % (5 MB)
95 02:59:42.004839 progress 10 % (11 MB)
96 02:59:44.015645 progress 15 % (16 MB)
97 02:59:45.700540 progress 20 % (22 MB)
98 02:59:47.040036 progress 25 % (28 MB)
99 02:59:48.143582 progress 30 % (33 MB)
100 02:59:49.101425 progress 35 % (39 MB)
101 02:59:49.853378 progress 40 % (44 MB)
102 02:59:50.558322 progress 45 % (50 MB)
103 02:59:51.176119 progress 50 % (56 MB)
104 02:59:51.721910 progress 55 % (61 MB)
105 02:59:52.242240 progress 60 % (67 MB)
106 02:59:52.693238 progress 65 % (73 MB)
107 02:59:53.126019 progress 70 % (78 MB)
108 02:59:53.542553 progress 75 % (84 MB)
109 02:59:53.916547 progress 80 % (89 MB)
110 02:59:54.285860 progress 85 % (95 MB)
111 02:59:54.660980 progress 90 % (101 MB)
112 02:59:55.027916 progress 95 % (106 MB)
113 02:59:55.419404 progress 100 % (112 MB)
114 02:59:55.425828 112 MB downloaded in 18.03 s (6.23 MB/s)
115 02:59:55.426080 end: 1.4.1 http-download (duration 00:00:18) [common]
117 02:59:55.426302 end: 1.4 download-retry (duration 00:00:18) [common]
118 02:59:55.426381 start: 1.5 download-retry (timeout 00:09:35) [common]
119 02:59:55.426452 start: 1.5.1 http-download (timeout 00:09:35) [common]
120 02:59:55.426642 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/modules.tar.xz
121 02:59:55.426701 saving as /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/modules/modules.tar
122 02:59:55.426759 total size: 6910536 (6 MB)
123 02:59:55.426814 Using unxz to decompress xz
124 02:59:55.569390 progress 0 % (0 MB)
125 02:59:55.589265 progress 5 % (0 MB)
126 02:59:55.612296 progress 10 % (0 MB)
127 02:59:55.633114 progress 15 % (1 MB)
128 02:59:55.659596 progress 20 % (1 MB)
129 02:59:55.681949 progress 25 % (1 MB)
130 02:59:55.706150 progress 30 % (2 MB)
131 02:59:55.727269 progress 35 % (2 MB)
132 02:59:55.750761 progress 40 % (2 MB)
133 02:59:55.771955 progress 45 % (2 MB)
134 02:59:55.795482 progress 50 % (3 MB)
135 02:59:55.816500 progress 55 % (3 MB)
136 02:59:55.840296 progress 60 % (3 MB)
137 02:59:55.864067 progress 65 % (4 MB)
138 02:59:55.886004 progress 70 % (4 MB)
139 02:59:55.909412 progress 75 % (4 MB)
140 02:59:55.931589 progress 80 % (5 MB)
141 02:59:55.955940 progress 85 % (5 MB)
142 02:59:55.977094 progress 90 % (5 MB)
143 02:59:56.004583 progress 95 % (6 MB)
144 02:59:56.025984 progress 100 % (6 MB)
145 02:59:56.033053 6 MB downloaded in 0.61 s (10.87 MB/s)
146 02:59:56.033435 end: 1.5.1 http-download (duration 00:00:01) [common]
148 02:59:56.033914 end: 1.5 download-retry (duration 00:00:01) [common]
149 02:59:56.034066 start: 1.6 prepare-tftp-overlay (timeout 00:09:34) [common]
150 02:59:56.034215 start: 1.6.1 extract-nfsrootfs (timeout 00:09:34) [common]
151 03:00:01.294488 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf
152 03:00:01.294794 end: 1.6.1 extract-nfsrootfs (duration 00:00:05) [common]
153 03:00:01.294882 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
154 03:00:01.295137 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih
155 03:00:01.295278 makedir: /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin
156 03:00:01.295380 makedir: /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/tests
157 03:00:01.295478 makedir: /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/results
158 03:00:01.295592 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-add-keys
159 03:00:01.295762 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-add-sources
160 03:00:01.295899 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-background-process-start
161 03:00:01.296031 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-background-process-stop
162 03:00:01.296172 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-common-functions
163 03:00:01.296304 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-echo-ipv4
164 03:00:01.296434 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-install-packages
165 03:00:01.296571 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-installed-packages
166 03:00:01.296699 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-os-build
167 03:00:01.296830 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-probe-channel
168 03:00:01.296959 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-probe-ip
169 03:00:01.297087 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-target-ip
170 03:00:01.297217 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-target-mac
171 03:00:01.297346 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-target-storage
172 03:00:01.297494 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-test-case
173 03:00:01.297639 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-test-event
174 03:00:01.297769 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-test-feedback
175 03:00:01.297897 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-test-raise
176 03:00:01.298027 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-test-reference
177 03:00:01.298157 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-test-runner
178 03:00:01.298286 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-test-set
179 03:00:01.298415 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-test-shell
180 03:00:01.298551 Updating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-add-keys (debian)
181 03:00:01.298723 Updating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-add-sources (debian)
182 03:00:01.298882 Updating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-install-packages (debian)
183 03:00:01.299042 Updating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-installed-packages (debian)
184 03:00:01.299198 Updating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/bin/lava-os-build (debian)
185 03:00:01.299331 Creating /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/environment
186 03:00:01.299454 LAVA metadata
187 03:00:01.299526 - LAVA_JOB_ID=707117
188 03:00:01.299581 - LAVA_DISPATCHER_IP=192.168.56.193
189 03:00:01.299695 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
190 03:00:01.299987 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 03:00:01.300068 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
192 03:00:01.300127 skipped lava-vland-overlay
193 03:00:01.300191 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 03:00:01.300257 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
195 03:00:01.300310 skipped lava-multinode-overlay
196 03:00:01.300371 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 03:00:01.300436 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
198 03:00:01.300499 Loading test definitions
199 03:00:01.300571 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
200 03:00:01.300628 Using /lava-707117 at stage 0
201 03:00:01.300998 uuid=707117_1.6.2.4.1 testdef=None
202 03:00:01.301078 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 03:00:01.301146 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
204 03:00:01.301599 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 03:00:01.301802 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
207 03:00:01.302470 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 03:00:01.302689 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
210 03:00:01.303232 runner path: /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/0/tests/0_timesync-off test_uuid 707117_1.6.2.4.1
211 03:00:01.303390 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 03:00:01.303589 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
214 03:00:01.303649 Using /lava-707117 at stage 0
215 03:00:01.303741 Fetching tests from https://github.com/kernelci/test-definitions.git
216 03:00:01.303819 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/0/tests/1_kselftest-dt'
217 03:00:03.111692 Running '/usr/bin/git checkout kernelci.org
218 03:00:03.202712 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 03:00:03.203540 uuid=707117_1.6.2.4.5 testdef=None
220 03:00:03.203653 end: 1.6.2.4.5 git-repo-action (duration 00:00:02) [common]
222 03:00:03.203895 start: 1.6.2.4.6 test-overlay (timeout 00:09:27) [common]
223 03:00:03.204726 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 03:00:03.204978 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:27) [common]
226 03:00:03.206066 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 03:00:03.206322 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:27) [common]
229 03:00:03.207323 runner path: /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/0/tests/1_kselftest-dt test_uuid 707117_1.6.2.4.5
230 03:00:03.207410 BOARD='beaglebone-black'
231 03:00:03.207478 BRANCH='mainline'
232 03:00:03.207543 SKIPFILE='/dev/null'
233 03:00:03.207608 SKIP_INSTALL='True'
234 03:00:03.207673 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
235 03:00:03.207738 TST_CASENAME=''
236 03:00:03.207801 TST_CMDFILES='dt'
237 03:00:03.208010 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 03:00:03.208233 Creating lava-test-runner.conf files
240 03:00:03.208301 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/707117/lava-overlay-bn1mh4ih/lava-707117/0 for stage 0
241 03:00:03.208424 - 0_timesync-off
242 03:00:03.208491 - 1_kselftest-dt
243 03:00:03.208610 end: 1.6.2.4 test-definition (duration 00:00:02) [common]
244 03:00:03.208700 start: 1.6.2.5 compress-overlay (timeout 00:09:27) [common]
245 03:00:11.384662 end: 1.6.2.5 compress-overlay (duration 00:00:08) [common]
246 03:00:11.384827 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:19) [common]
247 03:00:11.384924 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 03:00:11.385015 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
249 03:00:11.385102 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:19) [common]
250 03:00:11.511726 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 03:00:11.512057 start: 1.6.4 extract-modules (timeout 00:09:18) [common]
252 03:00:11.512248 extracting modules file /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf
253 03:00:11.812146 extracting modules file /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/707117/extract-overlay-ramdisk-au1jx59e/ramdisk
254 03:00:12.120470 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 03:00:12.120665 start: 1.6.5 apply-overlay-tftp (timeout 00:09:18) [common]
256 03:00:12.120778 [common] Applying overlay to NFS
257 03:00:12.120842 [common] Applying overlay /var/lib/lava/dispatcher/tmp/707117/compress-overlay-fskddgo8/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf
258 03:00:13.124795 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 03:00:13.124963 start: 1.6.6 prepare-kernel (timeout 00:09:17) [common]
260 03:00:13.125068 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:17) [common]
261 03:00:13.125163 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 03:00:13.125242 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 03:00:13.125328 start: 1.6.7 configure-preseed-file (timeout 00:09:17) [common]
264 03:00:13.125408 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 03:00:13.125493 start: 1.6.8 compress-ramdisk (timeout 00:09:17) [common]
266 03:00:13.125563 Building ramdisk /var/lib/lava/dispatcher/tmp/707117/extract-overlay-ramdisk-au1jx59e/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/707117/extract-overlay-ramdisk-au1jx59e/ramdisk
267 03:00:13.436364 >> 78946 blocks
268 03:00:15.394531 Adding RAMdisk u-boot header.
269 03:00:15.394831 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/707117/extract-overlay-ramdisk-au1jx59e/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/707117/extract-overlay-ramdisk-au1jx59e/ramdisk.cpio.gz.uboot
270 03:00:15.502020 output: Image Name:
271 03:00:15.502244 output: Created: Thu Sep 5 03:00:15 2024
272 03:00:15.502372 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 03:00:15.502482 output: Data Size: 15340739 Bytes = 14981.19 KiB = 14.63 MiB
274 03:00:15.502590 output: Load Address: 00000000
275 03:00:15.502694 output: Entry Point: 00000000
276 03:00:15.502800 output:
277 03:00:15.503020 rename /var/lib/lava/dispatcher/tmp/707117/extract-overlay-ramdisk-au1jx59e/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/ramdisk/ramdisk.cpio.gz.uboot
278 03:00:15.503224 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 03:00:15.503384 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
280 03:00:15.503537 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
281 03:00:15.503678 No LXC device requested
282 03:00:15.503817 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 03:00:15.503961 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
284 03:00:15.504099 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 03:00:15.504213 Checking files for TFTP limit of 4294967296 bytes.
286 03:00:15.505149 end: 1 tftp-deploy (duration 00:00:46) [common]
287 03:00:15.505400 start: 2 uboot-action (timeout 00:05:00) [common]
288 03:00:15.505643 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 03:00:15.505857 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 03:00:15.506101 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 03:00:15.506483 substitutions:
292 03:00:15.506683 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 03:00:15.506843 - {DTB_ADDR}: 0x88000000
294 03:00:15.506998 - {DTB}: 707117/tftp-deploy-ustv2ygg/dtb/am335x-boneblack.dtb
295 03:00:15.507152 - {INITRD}: 707117/tftp-deploy-ustv2ygg/ramdisk/ramdisk.cpio.gz.uboot
296 03:00:15.507306 - {KERNEL_ADDR}: 0x82000000
297 03:00:15.507458 - {KERNEL}: 707117/tftp-deploy-ustv2ygg/kernel/zImage
298 03:00:15.507609 - {LAVA_MAC}: None
299 03:00:15.507790 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf
300 03:00:15.507948 - {NFS_SERVER_IP}: 192.168.56.193
301 03:00:15.508078 - {PRESEED_CONFIG}: None
302 03:00:15.508182 - {PRESEED_LOCAL}: None
303 03:00:15.508287 - {RAMDISK_ADDR}: 0x83000000
304 03:00:15.508392 - {RAMDISK}: 707117/tftp-deploy-ustv2ygg/ramdisk/ramdisk.cpio.gz.uboot
305 03:00:15.508497 - {ROOT_PART}: None
306 03:00:15.508602 - {ROOT}: None
307 03:00:15.508706 - {SERVER_IP}: 192.168.56.193
308 03:00:15.508810 - {TEE_ADDR}: 0x83000000
309 03:00:15.508915 - {TEE}: None
310 03:00:15.509020 Parsed boot commands:
311 03:00:15.509123 - setenv autoload no
312 03:00:15.509226 - setenv initrd_high 0xffffffff
313 03:00:15.509330 - setenv fdt_high 0xffffffff
314 03:00:15.509433 - dhcp
315 03:00:15.509536 - setenv serverip 192.168.56.193
316 03:00:15.509657 - tftp 0x82000000 707117/tftp-deploy-ustv2ygg/kernel/zImage
317 03:00:15.509762 - tftp 0x83000000 707117/tftp-deploy-ustv2ygg/ramdisk/ramdisk.cpio.gz.uboot
318 03:00:15.509867 - setenv initrd_size ${filesize}
319 03:00:15.510002 - tftp 0x88000000 707117/tftp-deploy-ustv2ygg/dtb/am335x-boneblack.dtb
320 03:00:15.510141 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 03:00:15.510260 - bootz 0x82000000 0x83000000 0x88000000
322 03:00:15.510419 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 03:00:15.510856 start: 2.3 connect-device (timeout 00:05:00) [common]
325 03:00:15.510985 [common] connect-device Connecting to device using 'telnet conserv3 3002'
326 03:00:15.518858 Setting prompt string to ['lava-test: # ']
327 03:00:15.519585 end: 2.3 connect-device (duration 00:00:00) [common]
328 03:00:15.519794 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 03:00:15.519965 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 03:00:15.520121 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 03:00:15.520517 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
332 03:00:15.540503 >> OK - accepted request
333 03:00:15.542430 Returned 0 in 0 seconds
334 03:00:15.643116 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
336 03:00:15.643933 end: 2.4.1 reset-device (duration 00:00:00) [common]
337 03:00:15.644188 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
338 03:00:15.644426 Setting prompt string to ['Hit any key to stop autoboot']
339 03:00:15.644628 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
340 03:00:15.645413 Trying 192.168.56.22...
341 03:00:15.645561 Connected to conserv3.
342 03:00:15.645692 Escape character is '^]'.
343 03:00:15.645817
344 03:00:15.645934 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
345 03:00:15.646056
346 03:00:24.386100
347 03:00:24.393022 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
348 03:00:24.393289 Trying to boot from MMC1
349 03:00:28.440077
350 03:00:28.446626 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
351 03:00:28.446929 Trying to boot from MMC1
352 03:00:31.137044
353 03:00:31.144074 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
354 03:00:31.144356 Trying to boot from MMC1
355 03:00:31.966798
356 03:00:31.966978
357 03:00:31.967241 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
358 03:00:31.967313
359 03:00:31.967366 CPU : AM335X-GP rev 2.0
360 03:00:31.967432 Model: TI AM335x BeagleBone Black
361 03:00:31.967486 DRAM: 512 MiB
362 03:00:31.967536 Core: 160 devices, 18 uclasses, devicetree: separate
363 03:00:31.969926 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
364 03:00:32.232395 NAND: 0 MiB
365 03:00:32.242563 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
366 03:00:32.357361 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
367 03:00:32.378851 <ethaddr> not set. Validating first E-fuse MAC
368 03:00:32.409281 Net: eth2: ethernet@4a100000, eth3: usb_ether
370 03:00:32.467543 Hit any key to stop autoboot: 2
371 03:00:32.467959 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
372 03:00:32.468100 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
373 03:00:32.468188 Setting prompt string to ['=>']
374 03:00:32.468269 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
375 03:00:32.478155 0
376 03:00:32.478689 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
377 03:00:32.478859 Sending with 10 millisecond of delay
379 03:00:33.612333 => setenv autoload no
380 03:00:33.622642 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
381 03:00:33.623711 setenv autoload no
382 03:00:33.624031 Sending with 10 millisecond of delay
384 03:00:35.420205 => setenv initrd_high 0xffffffff
385 03:00:35.430580 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
386 03:00:35.430946 setenv initrd_high 0xffffffff
387 03:00:35.431291 Sending with 10 millisecond of delay
389 03:00:37.046298 => setenv fdt_high 0xffffffff
390 03:00:37.056588 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
391 03:00:37.056930 setenv fdt_high 0xffffffff
392 03:00:37.057263 Sending with 10 millisecond of delay
394 03:00:37.348221 => dhcp
395 03:00:37.358590 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 03:00:37.358829 dhcp
397 03:00:37.360365 link up on port 0, speed 100, full duplex
398 03:00:37.360520 BOOTP broadcast 1
399 03:00:37.612544 BOOTP broadcast 2
400 03:00:38.114806 BOOTP broadcast 3
401 03:00:39.117440 BOOTP broadcast 4
402 03:00:41.119349 BOOTP broadcast 5
403 03:00:41.152882 *** Unhandled DHCP Option in OFFER/ACK: 42
404 03:00:41.190600 *** Unhandled DHCP Option in OFFER/ACK: 42
405 03:00:41.197033 DHCP client bound to address 192.168.56.6 (3833 ms)
406 03:00:41.197468 Sending with 10 millisecond of delay
408 03:00:43.055400 => setenv serverip 192.168.56.193
409 03:00:43.065907 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
410 03:00:43.066418 setenv serverip 192.168.56.193
411 03:00:43.066812 Sending with 10 millisecond of delay
413 03:00:46.552456 => tftp 0x82000000 707117/tftp-deploy-ustv2ygg/kernel/zImage
414 03:00:46.562915 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
415 03:00:46.563393 tftp 0x82000000 707117/tftp-deploy-ustv2ygg/kernel/zImage
416 03:00:46.563572 link up on port 0, speed 100, full duplex
417 03:00:46.567971 Using ethernet@4a100000 device
418 03:00:46.573758 TFTP from server 192.168.56.193; our IP address is 192.168.56.6
419 03:00:46.580750 Filename '707117/tftp-deploy-ustv2ygg/kernel/zImage'.
420 03:00:46.580922 Load address: 0x82000000
421 03:00:48.442561 Loading: *################################################## 11.4 MiB
422 03:00:48.442732 6.1 MiB/s
423 03:00:48.442789 done
424 03:00:48.447398 Bytes transferred = 11952640 (b66200 hex)
425 03:00:48.447926 Sending with 10 millisecond of delay
427 03:00:52.900806 => tftp 0x83000000 707117/tftp-deploy-ustv2ygg/ramdisk/ramdisk.cpio.gz.uboot
428 03:00:52.911264 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
429 03:00:52.911734 tftp 0x83000000 707117/tftp-deploy-ustv2ygg/ramdisk/ramdisk.cpio.gz.uboot
430 03:00:52.911908 link up on port 0, speed 100, full duplex
431 03:00:52.916596 Using ethernet@4a100000 device
432 03:00:52.922515 TFTP from server 192.168.56.193; our IP address is 192.168.56.6
433 03:00:52.925340 Filename '707117/tftp-deploy-ustv2ygg/ramdisk/ramdisk.cpio.gz.uboot'.
434 03:00:52.929619 Load address: 0x83000000
435 03:00:55.439011 Loading: *################################################## 14.6 MiB
436 03:00:55.439333 5.8 MiB/s
437 03:00:55.439497 done
438 03:00:55.443461 Bytes transferred = 15340803 (ea1503 hex)
439 03:00:55.443939 Sending with 10 millisecond of delay
441 03:00:57.309873 => setenv initrd_size ${filesize}
442 03:00:57.320336 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
443 03:00:57.320842 setenv initrd_size ${filesize}
444 03:00:57.321225 Sending with 10 millisecond of delay
446 03:01:01.484117 => tftp 0x88000000 707117/tftp-deploy-ustv2ygg/dtb/am335x-boneblack.dtb
447 03:01:01.494693 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
448 03:01:01.495261 tftp 0x88000000 707117/tftp-deploy-ustv2ygg/dtb/am335x-boneblack.dtb
449 03:01:01.495440 link up on port 0, speed 100, full duplex
450 03:01:01.499677 Using ethernet@4a100000 device
451 03:01:01.505360 TFTP from server 192.168.56.193; our IP address is 192.168.56.6
452 03:01:01.512669 Filename '707117/tftp-deploy-ustv2ygg/dtb/am335x-boneblack.dtb'.
453 03:01:01.512991 Load address: 0x88000000
454 03:01:01.527468 Loading: *################################################## 68.7 KiB
455 03:01:01.533094 3.9 MiB/s
456 03:01:01.533303 done
457 03:01:01.536844 Bytes transferred = 70308 (112a4 hex)
458 03:01:01.537365 Sending with 10 millisecond of delay
460 03:01:14.905913 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
461 03:01:14.916313 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
462 03:01:14.916879 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 03:01:14.917318 Sending with 10 millisecond of delay
465 03:01:17.255832 => bootz 0x82000000 0x83000000 0x88000000
466 03:01:17.266246 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
467 03:01:17.266525 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
468 03:01:17.266883 bootz 0x82000000 0x83000000 0x88000000
469 03:01:17.267016 Kernel image @ 0x82000000 [ 0x000000 - 0xb66200 ]
470 03:01:17.268251 ## Loading init Ramdisk from Legacy Image at 83000000 ...
471 03:01:17.274033 Image Name:
472 03:01:17.274246 Created: 2024-09-05 3:00:15 UTC
473 03:01:17.279529 Image Type: ARM Linux RAMDisk Image (uncompressed)
474 03:01:17.285043 Data Size: 15340739 Bytes = 14.6 MiB
475 03:01:17.285252 Load Address: 00000000
476 03:01:17.291175 Entry Point: 00000000
477 03:01:17.465679 Verifying Checksum ... OK
478 03:01:17.465947 ## Flattened Device Tree blob at 88000000
479 03:01:17.472152 Booting using the fdt blob at 0x88000000
480 03:01:17.472390 Working FDT set to 88000000
481 03:01:17.477782 Using Device Tree in place at 88000000, end 880142a3
482 03:01:17.482089 Working FDT set to 88000000
483 03:01:17.495604
484 03:01:17.495842 Starting kernel ...
485 03:01:17.495990
486 03:01:17.496405 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
487 03:01:17.496591 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
488 03:01:17.496732 Setting prompt string to ['Linux version [0-9]']
489 03:01:17.496864 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
490 03:01:17.496996 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
491 03:01:18.462487 [ 0.000000] Booting Linux on physical CPU 0x0
492 03:01:18.462948 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
493 03:01:18.463076 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
494 03:01:18.463156 Setting prompt string to []
495 03:01:18.463244 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
496 03:01:18.463330 Using line separator: #'\n'#
497 03:01:18.463396 No login prompt set.
498 03:01:18.463468 Parsing kernel messages
499 03:01:18.463533 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
500 03:01:18.463674 [login-action] Waiting for messages, (timeout 00:03:57)
501 03:01:18.463751 Waiting using forced prompt support (timeout 00:01:59)
502 03:01:18.464353 [ 0.000000] Linux version 6.11.0-rc6 (KernelCI@build-j308037-arm-clang-16-multi-v7-defconfig-lcbrl) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Thu Sep 5 02:06:34 UTC 2024
503 03:01:18.464443 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
504 03:01:18.464513 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
505 03:01:18.464580 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
506 03:01:18.464646 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
507 03:01:18.464712 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
508 03:01:18.464777 [ 0.000000] Memory policy: Data cache writeback
509 03:01:18.464842 [ 0.000000] efi: UEFI not found.
510 03:01:18.464907 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
511 03:01:18.464977 [ 0.000000] Zone ranges:
512 03:01:18.465039 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
513 03:01:18.465103 [ 0.000000] Normal empty
514 03:01:18.465167 [ 0.000000] HighMem empty
515 03:01:18.465230 [ 0.000000] Movable zone start for each node
516 03:01:18.465294 [ 0.000000] Early memory node ranges
517 03:01:18.465357 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
518 03:01:18.465421 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
519 03:01:18.465484 [ 0.000000] CPU: All CPU(s) started in SVC mode.
520 03:01:18.465548 [ 0.000000] AM335X ES2.0 (sgx neon)
521 03:01:18.465647 [ 0.000000] percpu: Embedded 17 pages/cpu s40268 r8192 d21172 u69632
522 03:01:18.488121 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.56.193:/var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
523 03:01:18.499429 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
524 03:01:18.505324 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
525 03:01:18.511006 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
526 03:01:18.520364 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
527 03:01:18.549363 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
528 03:01:18.555359 <6>[ 0.000000] trace event string verifier disabled
529 03:01:18.555549 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
530 03:01:18.563484 <6>[ 0.000000] rcu: RCU event tracing is enabled.
531 03:01:18.569244 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
532 03:01:18.580637 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
533 03:01:18.585512 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
534 03:01:18.600606 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
535 03:01:18.618130 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
536 03:01:18.624880 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
537 03:01:18.724097 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
538 03:01:18.732653 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
539 03:01:18.745093 <6>[ 0.008342] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
540 03:01:18.753398 <6>[ 0.019190] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
541 03:01:18.762884 <6>[ 0.034155] Console: colour dummy device 80x30
542 03:01:18.768855 Matched prompt #6: WARNING:
543 03:01:18.769123 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
544 03:01:18.774372 <3>[ 0.039056] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
545 03:01:18.777076 <3>[ 0.046131] This ensures that you still see kernel messages. Please
546 03:01:18.783451 <3>[ 0.052857] update your kernel commandline.
547 03:01:18.823863 <6>[ 0.057471] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
548 03:01:18.829636 <6>[ 0.096199] CPU: Testing write buffer coherency: ok
549 03:01:18.835596 <6>[ 0.101569] CPU0: Spectre v2: using BPIALL workaround
550 03:01:18.835851 <6>[ 0.107034] pid_max: default: 32768 minimum: 301
551 03:01:18.847080 <6>[ 0.112220] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
552 03:01:18.853843 <6>[ 0.120043] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
553 03:01:18.860924 <6>[ 0.129361] CPU0: thread -1, cpu 0, socket -1, mpidr 0
554 03:01:18.869384 <6>[ 0.136253] Setting up static identity map for 0x80300000 - 0x803000ac
555 03:01:18.875112 <6>[ 0.145897] rcu: Hierarchical SRCU implementation.
556 03:01:18.882708 <6>[ 0.151179] rcu: Max phase no-delay instances is 1000.
557 03:01:18.891412 <6>[ 0.162458] EFI services will not be available.
558 03:01:18.897285 <6>[ 0.167727] smp: Bringing up secondary CPUs ...
559 03:01:18.902982 <6>[ 0.172771] smp: Brought up 1 node, 1 CPU
560 03:01:18.911096 <6>[ 0.177169] SMP: Total of 1 processors activated (996.14 BogoMIPS).
561 03:01:18.917101 <6>[ 0.183920] CPU: All CPU(s) started in SVC mode.
562 03:01:18.929342 <6>[ 0.189102] Memory: 405452K/522240K available (17408K kernel code, 2536K rwdata, 6644K rodata, 2048K init, 432K bss, 49584K reserved, 65536K cma-reserved, 0K highmem)
563 03:01:18.935120 <6>[ 0.205375] devtmpfs: initialized
564 03:01:18.957740 <6>[ 0.222884] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
565 03:01:18.969226 <6>[ 0.231493] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
566 03:01:18.975321 <6>[ 0.241934] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
567 03:01:18.985751 <6>[ 0.254219] pinctrl core: initialized pinctrl subsystem
568 03:01:18.995293 <6>[ 0.265047] DMI not present or invalid.
569 03:01:19.003700 <6>[ 0.270906] NET: Registered PF_NETLINK/PF_ROUTE protocol family
570 03:01:19.013179 <6>[ 0.279851] DMA: preallocated 256 KiB pool for atomic coherent allocations
571 03:01:19.028499 <6>[ 0.291310] thermal_sys: Registered thermal governor 'step_wise'
572 03:01:19.028757 <6>[ 0.291465] cpuidle: using governor menu
573 03:01:19.055595 <6>[ 0.326721] No ATAGs?
574 03:01:19.061498 <6>[ 0.329364] hw-breakpoint: debug architecture 0x4 unsupported.
575 03:01:19.072088 <6>[ 0.341636] Serial: AMBA PL011 UART driver
576 03:01:19.113649 <6>[ 0.384965] iommu: Default domain type: Translated
577 03:01:19.122741 <6>[ 0.390313] iommu: DMA domain TLB invalidation policy: strict mode
578 03:01:19.139773 <5>[ 0.410499] SCSI subsystem initialized
579 03:01:19.145599 <6>[ 0.415383] usbcore: registered new interface driver usbfs
580 03:01:19.151554 <6>[ 0.421438] usbcore: registered new interface driver hub
581 03:01:19.158277 <6>[ 0.427225] usbcore: registered new device driver usb
582 03:01:19.164023 <6>[ 0.433807] pps_core: LinuxPPS API ver. 1 registered
583 03:01:19.175524 <6>[ 0.439194] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
584 03:01:19.178833 <6>[ 0.448925] PTP clock support registered
585 03:01:19.219082 <6>[ 0.489751] EDAC MC: Ver: 3.0.0
586 03:01:19.225249 <6>[ 0.493963] scmi_core: SCMI protocol bus registered
587 03:01:19.242915 <6>[ 0.514046] vgaarb: loaded
588 03:01:19.255445 <6>[ 0.526882] clocksource: Switched to clocksource dmtimer
589 03:01:19.294104 <6>[ 0.565105] NET: Registered PF_INET protocol family
590 03:01:19.306760 <6>[ 0.570809] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
591 03:01:19.312586 <6>[ 0.579799] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
592 03:01:19.324112 <6>[ 0.588721] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
593 03:01:19.329809 <6>[ 0.596981] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
594 03:01:19.341331 <6>[ 0.605249] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
595 03:01:19.347340 <6>[ 0.612967] TCP: Hash tables configured (established 4096 bind 4096)
596 03:01:19.352981 <6>[ 0.619889] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
597 03:01:19.358831 <6>[ 0.626931] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
598 03:01:19.366429 <6>[ 0.634511] NET: Registered PF_UNIX/PF_LOCAL protocol family
599 03:01:19.400979 <6>[ 0.666673] RPC: Registered named UNIX socket transport module.
600 03:01:19.401241 <6>[ 0.673110] RPC: Registered udp transport module.
601 03:01:19.406744 <6>[ 0.678246] RPC: Registered tcp transport module.
602 03:01:19.412564 <6>[ 0.683350] RPC: Registered tcp-with-tls transport module.
603 03:01:19.425585 <6>[ 0.689279] RPC: Registered tcp NFSv4.1 backchannel transport module.
604 03:01:19.425867 <6>[ 0.696188] PCI: CLS 0 bytes, default 64
605 03:01:19.432843 <5>[ 0.702040] Initialise system trusted keyrings
606 03:01:19.453130 <6>[ 0.721295] Trying to unpack rootfs image as initramfs...
607 03:01:19.472917 <6>[ 0.737895] workingset: timestamp_bits=30 max_order=17 bucket_order=0
608 03:01:19.477454 <6>[ 0.745371] squashfs: version 4.0 (2009/01/31) Phillip Lougher
609 03:01:19.536187 <5>[ 0.807556] NFS: Registering the id_resolver key type
610 03:01:19.542081 <5>[ 0.813144] Key type id_resolver registered
611 03:01:19.547757 <5>[ 0.817844] Key type id_legacy registered
612 03:01:19.553627 <6>[ 0.822286] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
613 03:01:19.563119 <6>[ 0.829496] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
614 03:01:19.596392 <5>[ 0.867742] Key type asymmetric registered
615 03:01:19.602400 <5>[ 0.872268] Asymmetric key parser 'x509' registered
616 03:01:19.610650 <6>[ 0.877794] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
617 03:01:19.616426 <6>[ 0.885679] io scheduler mq-deadline registered
618 03:01:19.625132 <6>[ 0.890647] io scheduler kyber registered
619 03:01:19.625337 <6>[ 0.895099] io scheduler bfq registered
620 03:01:19.983954 <6>[ 1.251420] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
621 03:01:20.041619 <6>[ 1.312532] msm_serial: driver initialized
622 03:01:20.047640 <6>[ 1.317575] SuperH (H)SCI(F) driver initialized
623 03:01:20.053427 <6>[ 1.322706] STMicroelectronics ASC driver initialized
624 03:01:20.058698 <6>[ 1.328389] STM32 USART driver initialized
625 03:01:20.160735 <6>[ 1.431467] brd: module loaded
626 03:01:20.192266 <6>[ 1.462937] loop: module loaded
627 03:01:20.234440 <6>[ 1.504784] CAN device driver interface
628 03:01:20.240934 <6>[ 1.510073] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
629 03:01:20.246653 <6>[ 1.517084] e1000e: Intel(R) PRO/1000 Network Driver
630 03:01:20.252474 <6>[ 1.522472] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
631 03:01:20.258210 <6>[ 1.528917] igb: Intel(R) Gigabit Ethernet Network Driver
632 03:01:20.266499 <6>[ 1.534739] igb: Copyright (c) 2007-2014 Intel Corporation.
633 03:01:20.278243 <6>[ 1.543860] pegasus: Pegasus/Pegasus II USB Ethernet driver
634 03:01:20.283979 <6>[ 1.550014] usbcore: registered new interface driver pegasus
635 03:01:20.289763 <6>[ 1.556142] usbcore: registered new interface driver asix
636 03:01:20.295812 <6>[ 1.562029] usbcore: registered new interface driver ax88179_178a
637 03:01:20.301449 <6>[ 1.568636] usbcore: registered new interface driver cdc_ether
638 03:01:20.307160 <6>[ 1.574936] usbcore: registered new interface driver smsc75xx
639 03:01:20.313065 <6>[ 1.581180] usbcore: registered new interface driver smsc95xx
640 03:01:20.318657 <6>[ 1.587410] usbcore: registered new interface driver net1080
641 03:01:20.324447 <6>[ 1.593531] usbcore: registered new interface driver cdc_subset
642 03:01:20.330285 <6>[ 1.599942] usbcore: registered new interface driver zaurus
643 03:01:20.337927 <6>[ 1.606008] usbcore: registered new interface driver cdc_ncm
644 03:01:20.347681 <6>[ 1.615380] usbcore: registered new interface driver usb-storage
645 03:01:20.446836 <6>[ 1.717307] i2c_dev: i2c /dev entries driver
646 03:01:20.500275 <5>[ 1.763581] cpuidle: enable-method property 'ti,am3352' found operations
647 03:01:20.506129 <6>[ 1.773251] sdhci: Secure Digital Host Controller Interface driver
648 03:01:20.513855 <6>[ 1.780023] sdhci: Copyright(c) Pierre Ossman
649 03:01:20.521005 <6>[ 1.786376] Synopsys Designware Multimedia Card Interface Driver
650 03:01:20.526168 <6>[ 1.794281] sdhci-pltfm: SDHCI platform and OF driver helper
651 03:01:20.597128 <6>[ 1.864881] ledtrig-cpu: registered to indicate activity on CPUs
652 03:01:20.642152 <6>[ 1.905935] usbcore: registered new interface driver usbhid
653 03:01:20.642386 <6>[ 1.912108] usbhid: USB HID core driver
654 03:01:20.674165 <6>[ 1.942954] NET: Registered PF_INET6 protocol family
655 03:01:20.727208 <6>[ 1.998629] Segment Routing with IPv6
656 03:01:20.733126 <6>[ 2.002773] In-situ OAM (IOAM) with IPv6
657 03:01:20.739980 <6>[ 2.007295] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
658 03:01:20.747386 <6>[ 2.014596] NET: Registered PF_PACKET protocol family
659 03:01:20.753173 <6>[ 2.020168] can: controller area network core
660 03:01:20.753351 <6>[ 2.024995] NET: Registered PF_CAN protocol family
661 03:01:20.758914 <6>[ 2.030219] can: raw protocol
662 03:01:20.764666 <6>[ 2.033543] can: broadcast manager protocol
663 03:01:20.771729 <6>[ 2.038139] can: netlink gateway - max_hops=1
664 03:01:20.771905 <5>[ 2.043644] Key type dns_resolver registered
665 03:01:20.777345 <6>[ 2.048714] ThumbEE CPU extension supported.
666 03:01:20.783611 <5>[ 2.053403] Registering SWP/SWPB emulation handler
667 03:01:20.791713 <3>[ 2.059092] omap_voltage_late_init: Voltage driver support not added
668 03:01:20.868195 <5>[ 2.137129] Loading compiled-in X.509 certificates
669 03:01:21.037391 <6>[ 2.295618] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
670 03:01:21.044373 <6>[ 2.312317] pinctrl-single 44e10800.pinmux: 142 pins, size 568
671 03:01:21.071189 <3>[ 2.336222] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
672 03:01:21.165148 <3>[ 2.431312] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
673 03:01:21.257956 <6>[ 2.527458] OMAP GPIO hardware version 0.1
674 03:01:21.278787 <6>[ 2.546314] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
675 03:01:21.343157 <4>[ 2.610523] at24 2-0054: supply vcc not found, using dummy regulator
676 03:01:21.405232 <4>[ 2.672590] at24 2-0055: supply vcc not found, using dummy regulator
677 03:01:21.477314 <4>[ 2.744679] at24 2-0056: supply vcc not found, using dummy regulator
678 03:01:21.526383 <4>[ 2.793742] at24 2-0057: supply vcc not found, using dummy regulator
679 03:01:21.564883 <6>[ 2.833107] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
680 03:01:21.637487 <3>[ 2.901597] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
681 03:01:21.662245 <6>[ 2.922727] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
682 03:01:21.685928 <4>[ 2.952017] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
683 03:01:21.731732 <4>[ 2.997899] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
684 03:01:21.790085 <6>[ 3.057643] omap_rng 48310000.rng: Random Number Generator ver. 20
685 03:01:21.813867 <5>[ 3.084276] random: crng init done
686 03:01:21.921524 <6>[ 3.187544] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
687 03:01:22.451248 <6>[ 3.721935] Freeing initrd memory: 14984K
688 03:01:22.494360 <6>[ 3.759356] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
689 03:01:22.500058 <6>[ 3.769583] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
690 03:01:22.511983 <6>[ 3.776924] cpsw-switch 4a100000.switch: ALE Table size 1024
691 03:01:22.517705 <6>[ 3.783342] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
692 03:01:22.529083 <6>[ 3.791475] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
693 03:01:22.536595 <6>[ 3.803111] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
694 03:01:22.548862 <5>[ 3.812245] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
695 03:01:22.577457 <3>[ 3.842529] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
696 03:01:22.582710 <6>[ 3.851115] edma 49000000.dma: TI EDMA DMA engine driver
697 03:01:22.654017 <3>[ 3.919848] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
698 03:01:22.668643 <6>[ 3.934224] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
699 03:01:22.687364 <3>[ 3.956080] l3-aon-clkctrl:0000:0: failed to disable
700 03:01:22.732401 <6>[ 3.998057] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
701 03:01:22.738136 <6>[ 4.007516] printk: legacy console [ttyS0] enabled
702 03:01:22.741096 <6>[ 4.007516] printk: legacy console [ttyS0] enabled
703 03:01:22.746582 <6>[ 4.017840] printk: legacy bootconsole [omap8250] disabled
704 03:01:22.752356 <6>[ 4.017840] printk: legacy bootconsole [omap8250] disabled
705 03:01:22.803090 <4>[ 4.067618] tps65217-pmic: Failed to locate of_node [id: -1]
706 03:01:22.806640 <4>[ 4.075015] tps65217-bl: Failed to locate of_node [id: -1]
707 03:01:22.823049 <6>[ 4.094716] tps65217 0-0024: TPS65217 ID 0xe version 1.2
708 03:01:22.841620 <6>[ 4.101696] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
709 03:01:22.853204 <6>[ 4.115389] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
710 03:01:22.859031 <6>[ 4.127356] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
711 03:01:22.882441 <6>[ 4.148245] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
712 03:01:22.888289 <6>[ 4.157410] sdhci-omap 48060000.mmc: Got CD GPIO
713 03:01:22.896245 <4>[ 4.162531] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
714 03:01:22.911818 <4>[ 4.176539] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
715 03:01:22.918044 <4>[ 4.185594] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
716 03:01:22.927937 <4>[ 4.194244] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
717 03:01:23.049820 <6>[ 4.317534] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
718 03:01:23.085059 <6>[ 4.350933] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
719 03:01:23.120473 <6>[ 4.385656] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
720 03:01:23.127616 <6>[ 4.394575] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
721 03:01:23.172337 <6>[ 4.434146] mmc1: new high speed MMC card at address 0001
722 03:01:23.172640 <6>[ 4.441479] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
723 03:01:23.181741 <6>[ 4.450802] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
724 03:01:23.190675 <6>[ 4.459162] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
725 03:01:23.199599 <6>[ 4.467321] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
726 03:01:23.224649 <6>[ 4.488043] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
727 03:01:23.314374 <6>[ 4.576539] mmc0: new high speed SDHC card at address aaaa
728 03:01:23.314683 <6>[ 4.583880] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
729 03:01:23.338778 <6>[ 4.608003] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
730 03:01:25.342449 <6>[ 6.607884] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
731 03:01:31.455654 <5>[ 6.656953] Sending DHCP requests ..., OK
732 03:01:31.466879 <6>[ 12.731460] IP-Config: Got DHCP answer from 192.168.56.254, my address is 192.168.56.6
733 03:01:31.467121 <6>[ 12.739902] IP-Config: Complete:
734 03:01:31.480910 <6>[ 12.743437] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.56.6, mask=255.255.255.0, gw=192.168.56.254
735 03:01:31.486795 <6>[ 12.754214] host=192.168.56.6, domain=mayfield.sirena.org.uk, nis-domain=(none)
736 03:01:31.497865 <6>[ 12.762347] bootserver=192.168.56.254, rootserver=192.168.56.193, rootpath=
737 03:01:31.498156 <6>[ 12.762380] nameserver0=192.168.56.254
738 03:01:31.510756 <6>[ 12.774645] ntpserver0=50.205.244.22, ntpserver1=85.199.214.99
739 03:01:31.511024 <6>[ 12.782302] clk: Disabling unused clocks
740 03:01:31.518002 <6>[ 12.787101] PM: genpd: Disabling unused power domains
741 03:01:31.535990 <6>[ 12.804130] Freeing unused kernel image (initmem) memory: 2048K
742 03:01:31.543431 <6>[ 12.813868] Run /init as init process
743 03:01:31.567342 Loading, please wait...
744 03:01:31.644020 Starting systemd-udevd version 252.22-1~deb12u1
745 03:01:34.654132 <4>[ 15.918661] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
746 03:01:34.845632 <4>[ 16.110116] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
747 03:01:34.965523 <6>[ 16.237563] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
748 03:01:34.976377 <6>[ 16.243235] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
749 03:01:35.126781 <6>[ 16.397331] hub 1-0:1.0: USB hub found
750 03:01:35.144008 <6>[ 16.415326] hub 1-0:1.0: 1 port detected
751 03:01:35.280117 <6>[ 16.550253] tda998x 0-0070: found TDA19988
752 03:01:38.400976 Begin: Loading essential drivers ... done.
753 03:01:38.406340 Begin: Running /scripts/init-premount ... done.
754 03:01:38.412011 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
755 03:01:38.419943 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
756 03:01:38.425820 Device /sys/class/net/eth0 found
757 03:01:38.425979 done.
758 03:01:38.495748 Begin: Waiting up to 180 secs for any network device to become available ... done.
759 03:01:38.577923 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
760 03:01:38.674405 IP-Config: eth0 complete (dhcp from 192.168.56.254):
761 03:01:38.685544 address: 192.168.56.6 broadcast: 192.168.56.255 netmask: 255.255.255.0
762 03:01:38.691187 gateway: 192.168.56.254 dns0 : 192.168.56.254 dns1 : 0.0.0.0
763 03:01:38.696824 domain : mayfield.sirena.org.uk
764 03:01:38.702387 rootserver: 192.168.56.254 rootpath:
765 03:01:38.702742 filename :
766 03:01:38.823164 done.
767 03:01:38.833780 Begin: Running /scripts/nfs-bottom ... done.
768 03:01:38.903612 Begin: Running /scripts/init-bottom ... done.
769 03:01:40.671902 <30>[ 21.939463] systemd[1]: System time before build time, advancing clock.
770 03:01:40.832451 <30>[ 22.073893] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
771 03:01:40.841104 <30>[ 22.110620] systemd[1]: Detected architecture arm.
772 03:01:40.854475
773 03:01:40.854695 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
774 03:01:40.854820
775 03:01:40.888324 <30>[ 22.156602] systemd[1]: Hostname set to <debian-bookworm-armhf>.
776 03:01:43.018935 <30>[ 24.286019] systemd[1]: Queued start job for default target graphical.target.
777 03:01:43.035900 <30>[ 24.300889] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
778 03:01:43.043420 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
779 03:01:43.075616 <30>[ 24.339670] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
780 03:01:43.083246 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
781 03:01:43.118197 <30>[ 24.382739] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
782 03:01:43.125781 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
783 03:01:43.162870 <30>[ 24.428734] systemd[1]: Created slice user.slice - User and Session Slice.
784 03:01:43.169538 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
785 03:01:43.205903 <30>[ 24.469155] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
786 03:01:43.219262 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
787 03:01:43.252658 <30>[ 24.518148] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
788 03:01:43.263700 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
789 03:01:43.302174 <30>[ 24.559074] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
790 03:01:43.317941 <30>[ 24.582791] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
791 03:01:43.323514 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
792 03:01:43.361769 <30>[ 24.627335] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
793 03:01:43.369876 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
794 03:01:43.402225 <30>[ 24.667698] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
795 03:01:43.410735 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
796 03:01:43.443620 <30>[ 24.708786] systemd[1]: Reached target paths.target - Path Units.
797 03:01:43.448822 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
798 03:01:43.483226 <30>[ 24.748068] systemd[1]: Reached target remote-fs.target - Remote File Systems.
799 03:01:43.490641 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
800 03:01:43.521730 <30>[ 24.787470] systemd[1]: Reached target slices.target - Slice Units.
801 03:01:43.527250 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
802 03:01:43.562018 <30>[ 24.827719] systemd[1]: Reached target swap.target - Swaps.
803 03:01:43.566059 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
804 03:01:43.602493 <30>[ 24.868412] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
805 03:01:43.615090 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
806 03:01:43.653269 <30>[ 24.918463] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
807 03:01:43.661294 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
808 03:01:43.751011 <30>[ 25.011800] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
809 03:01:43.763760 <30>[ 25.029303] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
810 03:01:43.772226 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
811 03:01:43.804360 <30>[ 25.069337] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
812 03:01:43.811578 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
813 03:01:43.845229 <30>[ 25.110447] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
814 03:01:43.853316 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
815 03:01:43.886472 <30>[ 25.151760] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
816 03:01:43.892249 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
817 03:01:43.934224 <30>[ 25.200615] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
818 03:01:43.947140 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
819 03:01:43.989196 <30>[ 25.248641] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
820 03:01:44.005807 <30>[ 25.265352] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
821 03:01:44.042815 <30>[ 25.309362] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
822 03:01:44.061897 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
823 03:01:44.125278 <30>[ 25.391627] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
824 03:01:44.138884 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
825 03:01:44.211659 <30>[ 25.478030] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
826 03:01:44.230963 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
827 03:01:44.262510 <30>[ 25.528469] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
828 03:01:44.284898 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
829 03:01:44.331703 <30>[ 25.598054] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
830 03:01:44.347679 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
831 03:01:44.371467 <30>[ 25.638327] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
832 03:01:44.403073 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
833 03:01:44.475371 <30>[ 25.740986] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
834 03:01:44.501299 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
835 03:01:44.562951 <30>[ 25.829478] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
836 03:01:44.589236 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
837 03:01:44.654682 <30>[ 25.921329] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
838 03:01:44.690468 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
839 03:01:44.728885 <28>[ 25.989048] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
840 03:01:44.737552 <28>[ 26.003153] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
841 03:01:44.785063 <30>[ 26.052102] systemd[1]: Starting systemd-journald.service - Journal Service...
842 03:01:44.804596 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
843 03:01:44.861826 <30>[ 26.128234] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
844 03:01:44.888483 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
845 03:01:44.954619 <30>[ 26.221295] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
846 03:01:45.003530 Starting [0;1;39msystemd-network-g… units from Kernel command line...
847 03:01:45.055735 <30>[ 26.320790] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
848 03:01:45.102322 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
849 03:01:45.180066 <30>[ 26.445836] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
850 03:01:45.228181 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
851 03:01:45.285797 <30>[ 26.552596] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
852 03:01:45.341738 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
853 03:01:45.376444 <30>[ 26.642939] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
854 03:01:45.418243 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
855 03:01:45.458101 <30>[ 26.723674] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
856 03:01:45.489931 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
857 03:01:45.601148 <30>[ 26.868188] systemd[1]: modprobe@configfs.service: Deactivated successfully.
858 03:01:45.631561 <30>[ 26.897464] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
859 03:01:45.640458 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
860 03:01:45.662249 <30>[ 26.929669] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
861 03:01:45.692379 <30>[ 26.958779] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
862 03:01:45.721814 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
863 03:01:45.752834 <30>[ 27.018634] systemd[1]: Started systemd-journald.service - Journal Service.
864 03:01:45.759567 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
865 03:01:45.802384 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
866 03:01:45.836602 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
867 03:01:45.877066 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
868 03:01:45.897119 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
869 03:01:45.935052 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
870 03:01:45.974054 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
871 03:01:46.004128 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
872 03:01:46.051885 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
873 03:01:46.121800 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
874 03:01:46.163525 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
875 03:01:46.241955 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
876 03:01:46.338840 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
877 03:01:46.433601 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
878 03:01:46.515963 <46>[ 27.782598] systemd-journald[165]: Received client request to flush runtime journal.
879 03:01:46.582912 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
880 03:01:46.652230 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
881 03:01:47.542742 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
882 03:01:47.899349 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
883 03:01:47.944354 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
884 03:01:48.324929 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
885 03:01:48.507649 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
886 03:01:48.523067 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
887 03:01:48.552935 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
888 03:01:48.632035 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
889 03:01:48.670752 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
890 03:01:49.583548 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
891 03:01:49.661676 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
892 03:01:50.221192 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
893 03:01:50.422880 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
894 03:01:50.601324 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
895 03:01:52.090420 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
896 03:01:52.654339 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
897 03:01:52.781597 <5>[ 34.048390] cfg80211: Loading compiled-in X.509 certificates for regulatory database
898 03:01:53.299714 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
899 03:01:54.214959 <5>[ 35.483718] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
900 03:01:54.284858 <5>[ 35.548856] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
901 03:01:54.290219 <4>[ 35.558559] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
902 03:01:54.297919 <6>[ 35.567667] cfg80211: failed to load regulatory.db
903 03:01:54.763112 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
904 03:01:55.039168 <46>[ 36.296391] systemd-journald[165]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
905 03:01:55.239003 <46>[ 36.498333] systemd-journald[165]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
906 03:01:55.447373 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
907 03:02:04.443344 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
908 03:02:04.482769 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
909 03:02:04.516332 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
910 03:02:04.553769 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
911 03:02:04.634591 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
912 03:02:04.673858 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
913 03:02:04.731589 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
914 03:02:04.785477 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
915 03:02:04.832876 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
916 03:02:04.878153 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
917 03:02:04.929750 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
918 03:02:04.973918 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
919 03:02:05.005333 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
920 03:02:05.077944 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
921 03:02:05.117326 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
922 03:02:05.152515 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
923 03:02:05.199671 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
924 03:02:05.238351 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
925 03:02:05.275761 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
926 03:02:05.311810 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
927 03:02:05.351878 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
928 03:02:05.383749 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
929 03:02:05.406866 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
930 03:02:05.456231 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
931 03:02:05.493246 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
932 03:02:05.616343 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
933 03:02:05.691462 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
934 03:02:05.764021 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
935 03:02:05.803847 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
936 03:02:05.835219 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
937 03:02:06.019428 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
938 03:02:06.092716 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
939 03:02:06.172781 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
940 03:02:06.204083 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
941 03:02:06.244471 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
942 03:02:06.520295 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
943 03:02:06.558106 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
944 03:02:06.913695 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
945 03:02:07.197985 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
946 03:02:07.273490 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
947 03:02:07.307263 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
948 03:02:07.394851 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
949 03:02:07.598020 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
950 03:02:07.687731
951 03:02:07.687971 Debian GNU/Linux worm-armhf login: root (automatic login)
952 03:02:07.691075
953 03:02:08.017956 Linux debian-bookworm-armhf 6.11.0-rc6 #1 SMP Thu Sep 5 02:06:34 UTC 2024 armv7l
954 03:02:08.018184
955 03:02:08.023569 The programs included with the Debian GNU/Linux system are free software;
956 03:02:08.029262 the exact distribution terms for each program are described in the
957 03:02:08.034821 individual files in /usr/share/doc/*/copyright.
958 03:02:08.035065
959 03:02:08.042761 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
960 03:02:08.043010 permitted by applicable law.
961 03:02:13.082117 Unable to match end of the kernel message
963 03:02:13.082656 Setting prompt string to ['/ #']
964 03:02:13.082844 end: 2.4.4.1 login-action (duration 00:00:55) [common]
966 03:02:13.083237 end: 2.4.4 auto-login-action (duration 00:00:56) [common]
967 03:02:13.083412 start: 2.4.5 expect-shell-connection (timeout 00:03:02) [common]
968 03:02:13.083547 Setting prompt string to ['/ #']
969 03:02:13.083667 Forcing a shell prompt, looking for ['/ #']
971 03:02:13.134001 / #
972 03:02:13.134520 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
973 03:02:13.134689 Waiting using forced prompt support (timeout 00:02:30)
974 03:02:13.137991
975 03:02:13.146709 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
976 03:02:13.146881 start: 2.4.6 export-device-env (timeout 00:03:02) [common]
977 03:02:13.146966 Sending with 10 millisecond of delay
979 03:02:18.131456 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf'
980 03:02:18.141957 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/707117/extract-nfsrootfs-q74hbitf'
981 03:02:18.142494 Sending with 10 millisecond of delay
983 03:02:20.420310 / # export NFS_SERVER_IP='192.168.56.193'
984 03:02:20.430814 export NFS_SERVER_IP='192.168.56.193'
985 03:02:20.431350 end: 2.4.6 export-device-env (duration 00:00:07) [common]
986 03:02:20.431658 end: 2.4 uboot-commands (duration 00:02:05) [common]
987 03:02:20.431938 end: 2 uboot-action (duration 00:02:05) [common]
988 03:02:20.432184 start: 3 lava-test-retry (timeout 00:07:10) [common]
989 03:02:20.432450 start: 3.1 lava-test-shell (timeout 00:07:10) [common]
990 03:02:20.432688 Using namespace: common
992 03:02:20.533303 / # #
993 03:02:20.533755 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
994 03:02:20.537333 #
995 03:02:20.543959 Using /lava-707117
997 03:02:20.644582 / # export SHELL=/bin/bash
998 03:02:20.648943 export SHELL=/bin/bash
1000 03:02:20.755248 / # . /lava-707117/environment
1001 03:02:20.759253 . /lava-707117/environment
1003 03:02:20.872731 / # /lava-707117/bin/lava-test-runner /lava-707117/0
1004 03:02:20.873132 Test shell timeout: 10s (minimum of the action and connection timeout)
1005 03:02:20.877230 /lava-707117/bin/lava-test-runner /lava-707117/0
1006 03:02:21.289316 + export TESTRUN_ID=0_timesync-off
1007 03:02:21.296843 + TESTRUN_ID=0_timesync-off
1008 03:02:21.297106 + cd /lava-707117/0/tests/0_timesync-off
1009 03:02:21.297290 ++ cat uuid
1010 03:02:21.313214 + UUID=707117_1.6.2.4.1
1011 03:02:21.313516 + set +x
1012 03:02:21.321457 <LAVA_SIGNAL_STARTRUN 0_timesync-off 707117_1.6.2.4.1>
1013 03:02:21.321724 + systemctl stop systemd-timesyncd
1014 03:02:21.322154 Received signal: <STARTRUN> 0_timesync-off 707117_1.6.2.4.1
1015 03:02:21.322349 Starting test lava.0_timesync-off (707117_1.6.2.4.1)
1016 03:02:21.322573 Skipping test definition patterns.
1017 03:02:21.607182 + set +x
1018 03:02:21.607420 <LAVA_SIGNAL_ENDRUN 0_timesync-off 707117_1.6.2.4.1>
1019 03:02:21.607742 Received signal: <ENDRUN> 0_timesync-off 707117_1.6.2.4.1
1020 03:02:21.607894 Ending use of test pattern.
1021 03:02:21.608008 Ending test lava.0_timesync-off (707117_1.6.2.4.1), duration 0.29
1023 03:02:21.768290 + export TESTRUN_ID=1_kselftest-dt
1024 03:02:21.775422 + TESTRUN_ID=1_kselftest-dt
1025 03:02:21.775683 + cd /lava-707117/0/tests/1_kselftest-dt
1026 03:02:21.775872 ++ cat uuid
1027 03:02:21.791148 + UUID=707117_1.6.2.4.5
1028 03:02:21.791413 + set +x
1029 03:02:21.796795 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 707117_1.6.2.4.5>
1030 03:02:21.797044 + cd ./automated/linux/kselftest/
1031 03:02:21.797408 Received signal: <STARTRUN> 1_kselftest-dt 707117_1.6.2.4.5
1032 03:02:21.797585 Starting test lava.1_kselftest-dt (707117_1.6.2.4.5)
1033 03:02:21.797775 Skipping test definition patterns.
1034 03:02:21.824577 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1035 03:02:21.936057 INFO: install_deps skipped
1036 03:02:22.600199 --2024-09-05 03:02:22-- http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
1037 03:02:22.860551 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1038 03:02:23.003369 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1039 03:02:23.145629 HTTP request sent, awaiting response... 200 OK
1040 03:02:23.145934 Length: 2516636 (2.4M) [application/octet-stream]
1041 03:02:23.151346 Saving to: 'kselftest_armhf.tar.gz'
1042 03:02:23.151602
1043 03:02:24.366591
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 2%[ ] 49.92K 176KB/s
kselftest_armhf.tar 7%[> ] 194.76K 340KB/s
kselftest_armhf.tar 32%[=====> ] 798.04K 941KB/s
kselftest_armhf.tar 48%[========> ] 1.16M 1.05MB/s
kselftest_armhf.tar 100%[===================>] 2.40M 1.97MB/s in 1.2s
1044 03:02:24.366909
1045 03:02:24.604447 2024-09-05 03:02:24 (1.97 MB/s) - 'kselftest_armhf.tar.gz' saved [2516636/2516636]
1046 03:02:24.604745
1047 03:02:39.328283 skiplist:
1048 03:02:39.328536 ========================================
1049 03:02:39.333928 ========================================
1050 03:02:39.427697 dt:test_unprobed_devices.sh
1051 03:02:39.454433 ============== Tests to run ===============
1052 03:02:39.463682 dt:test_unprobed_devices.sh
1053 03:02:39.467684 ===========End Tests to run ===============
1054 03:02:39.479010 shardfile-dt pass
1055 03:02:39.691927 <12>[ 80.963354] kselftest: Running tests in dt
1056 03:02:39.720302 TAP version 13
1057 03:02:39.743529 1..1
1058 03:02:39.797880 # timeout set to 45
1059 03:02:39.798138 # selftests: dt: test_unprobed_devices.sh
1060 03:02:40.600938 # TAP version 13
1061 03:02:53.245211 # 1..255
1062 03:02:53.442238 # ok 1 / # SKIP
1063 03:02:53.464220 # ok 2 /clk_mcasp0
1064 03:02:53.542021 # ok 3 /clk_mcasp0_fixed # SKIP
1065 03:02:53.621957 # ok 4 /cpus/cpu@0 # SKIP
1066 03:02:53.693990 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1067 03:02:53.719445 # ok 6 /fixedregulator0
1068 03:02:53.740986 # ok 7 /leds
1069 03:02:53.761993 # ok 8 /ocp
1070 03:02:53.783190 # ok 9 /ocp/interconnect@44c00000
1071 03:02:53.812740 # ok 10 /ocp/interconnect@44c00000/segment@0
1072 03:02:53.835528 # ok 11 /ocp/interconnect@44c00000/segment@100000
1073 03:02:53.857906 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1074 03:02:53.939419 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1075 03:02:53.963566 # ok 14 /ocp/interconnect@44c00000/segment@200000
1076 03:02:53.986875 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1077 03:02:54.110719 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1078 03:02:54.186681 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1079 03:02:54.263442 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1080 03:02:54.346625 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1081 03:02:54.423605 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1082 03:02:54.500648 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1083 03:02:54.581600 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1084 03:02:54.657671 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1085 03:02:54.738011 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1086 03:02:54.813253 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1087 03:02:54.892551 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1088 03:02:54.971499 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1089 03:02:55.057165 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1090 03:02:55.130399 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1091 03:02:55.210401 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1092 03:02:55.286531 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1093 03:02:55.367111 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1094 03:02:55.432128 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1095 03:02:55.509769 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1096 03:02:55.574729 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1097 03:02:55.652316 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1098 03:02:55.724672 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1099 03:02:55.799899 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1100 03:02:55.868708 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1101 03:02:55.942841 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1102 03:02:56.017886 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1103 03:02:56.092512 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1104 03:02:56.157537 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1105 03:02:56.238261 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1106 03:02:56.311084 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1107 03:02:56.381803 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1108 03:02:56.452740 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1109 03:02:56.521244 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1110 03:02:56.599875 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1111 03:02:56.670001 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1112 03:02:56.741770 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1113 03:02:56.815694 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1114 03:02:56.892551 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1115 03:02:56.957446 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1116 03:02:57.032196 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1117 03:02:57.109513 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1118 03:02:57.178534 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1119 03:02:57.251636 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1120 03:02:57.323641 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1121 03:02:57.392258 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1122 03:02:57.468971 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1123 03:02:57.533386 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1124 03:02:57.610877 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1125 03:02:57.680285 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1126 03:02:57.753009 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1127 03:02:57.818078 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1128 03:02:57.893967 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1129 03:02:57.968292 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1130 03:02:58.038569 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1131 03:02:58.103831 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1132 03:02:58.182384 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1133 03:02:58.251800 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1134 03:02:58.323600 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1135 03:02:58.388848 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1136 03:02:58.461979 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1137 03:02:58.535544 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1138 03:02:58.609790 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1139 03:02:58.673631 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1140 03:02:58.749460 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1141 03:02:58.824116 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1142 03:02:58.903974 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1143 03:02:58.977238 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1144 03:02:59.063143 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1145 03:02:59.142449 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1146 03:02:59.219552 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1147 03:02:59.291848 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1148 03:02:59.367016 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1149 03:02:59.452144 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1150 03:02:59.524494 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1151 03:02:59.611282 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1152 03:02:59.684608 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1153 03:02:59.760817 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1154 03:02:59.843919 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1155 03:02:59.922853 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1156 03:02:59.941092 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1157 03:02:59.967111 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1158 03:02:59.991368 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1159 03:03:00.011149 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1160 03:03:00.041069 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1161 03:03:00.060466 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1162 03:03:00.089776 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1163 03:03:00.112443 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1164 03:03:00.226179 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1165 03:03:00.249443 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1166 03:03:00.279211 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1167 03:03:00.302009 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1168 03:03:00.407973 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1169 03:03:00.494800 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1170 03:03:00.571438 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1171 03:03:00.641767 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1172 03:03:00.724396 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1173 03:03:00.804926 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1174 03:03:00.881939 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1175 03:03:00.961769 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1176 03:03:01.040233 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1177 03:03:01.117158 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1178 03:03:01.196024 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1179 03:03:01.273255 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1180 03:03:01.352107 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1181 03:03:01.425217 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1182 03:03:01.506346 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1183 03:03:01.591600 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1184 03:03:01.613314 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1185 03:03:01.690047 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1186 03:03:01.757462 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1187 03:03:01.835952 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1188 03:03:01.862924 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1189 03:03:01.937700 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1190 03:03:01.966667 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1191 03:03:02.036371 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1192 03:03:02.065685 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1193 03:03:02.088226 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1194 03:03:02.115544 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1195 03:03:02.133006 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1196 03:03:02.162648 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1197 03:03:02.187109 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1198 03:03:02.213466 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1199 03:03:02.239797 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1200 03:03:02.257124 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1201 03:03:02.339142 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1202 03:03:02.416325 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1203 03:03:02.440418 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1204 03:03:02.516979 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1205 03:03:02.602498 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1206 03:03:02.715589 # not ok 145 /ocp/interconnect@47c00000
1207 03:03:02.789632 # not ok 146 /ocp/interconnect@47c00000/segment@0
1208 03:03:02.812373 # ok 147 /ocp/interconnect@48000000
1209 03:03:02.834960 # ok 148 /ocp/interconnect@48000000/segment@0
1210 03:03:02.858220 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1211 03:03:02.890362 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1212 03:03:02.906932 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1213 03:03:02.935848 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1214 03:03:02.959377 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1215 03:03:02.984862 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1216 03:03:03.009458 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1217 03:03:03.081466 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1218 03:03:03.166663 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1219 03:03:03.186612 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1220 03:03:03.208252 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1221 03:03:03.233697 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1222 03:03:03.260352 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1223 03:03:03.282026 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1224 03:03:03.307078 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1225 03:03:03.335909 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1226 03:03:03.358238 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1227 03:03:03.383528 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1228 03:03:03.408137 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1229 03:03:03.436256 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1230 03:03:03.453755 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1231 03:03:03.482846 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1232 03:03:03.510709 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1233 03:03:03.527829 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1234 03:03:03.552896 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1235 03:03:03.585280 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1236 03:03:03.609177 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1237 03:03:03.633178 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1238 03:03:03.655017 # ok 177 /ocp/interconnect@48000000/segment@100000
1239 03:03:03.678458 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1240 03:03:03.705027 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1241 03:03:03.785391 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1242 03:03:03.863393 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1243 03:03:03.935609 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1244 03:03:04.022911 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1245 03:03:04.041924 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1246 03:03:04.067580 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1247 03:03:04.090298 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1248 03:03:04.115820 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1249 03:03:04.139937 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1250 03:03:04.160074 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1251 03:03:04.190375 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1252 03:03:04.208855 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1253 03:03:04.239680 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1254 03:03:04.257690 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1255 03:03:04.287927 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1256 03:03:04.307667 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1257 03:03:04.337001 # ok 196 /ocp/interconnect@48000000/segment@200000
1258 03:03:04.356640 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1259 03:03:04.438612 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1260 03:03:04.453120 # ok 199 /ocp/interconnect@48000000/segment@300000
1261 03:03:04.479445 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1262 03:03:04.508215 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1263 03:03:04.527768 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1264 03:03:04.551758 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1265 03:03:04.579590 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1266 03:03:04.597624 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1267 03:03:04.677319 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1268 03:03:04.701022 # ok 207 /ocp/interconnect@4a000000
1269 03:03:04.718137 # ok 208 /ocp/interconnect@4a000000/segment@0
1270 03:03:04.748067 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1271 03:03:04.769823 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1272 03:03:04.800609 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1273 03:03:04.816906 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1274 03:03:04.897547 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1275 03:03:05.008929 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1276 03:03:05.088135 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1277 03:03:05.191876 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1278 03:03:05.263743 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1279 03:03:05.338627 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1280 03:03:05.442450 # not ok 219 /ocp/interconnect@4b140000
1281 03:03:05.507003 # not ok 220 /ocp/interconnect@4b140000/segment@0
1282 03:03:05.579862 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1283 03:03:05.601151 # ok 222 /ocp/target-module@40300000
1284 03:03:05.628698 # ok 223 /ocp/target-module@40300000/sram@0
1285 03:03:05.697264 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1286 03:03:05.776507 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1287 03:03:05.793585 # ok 226 /ocp/target-module@47400000
1288 03:03:05.815507 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1289 03:03:05.836825 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1290 03:03:05.863785 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1291 03:03:05.884484 # ok 230 /ocp/target-module@47400000/usb@1400
1292 03:03:05.908857 # ok 231 /ocp/target-module@47400000/usb@1800
1293 03:03:05.931897 # ok 232 /ocp/target-module@47810000
1294 03:03:05.953847 # ok 233 /ocp/target-module@49000000
1295 03:03:05.973329 # ok 234 /ocp/target-module@49000000/dma@0
1296 03:03:05.995464 # ok 235 /ocp/target-module@49800000
1297 03:03:06.022702 # ok 236 /ocp/target-module@49800000/dma@0
1298 03:03:06.040572 # ok 237 /ocp/target-module@49900000
1299 03:03:06.069305 # ok 238 /ocp/target-module@49900000/dma@0
1300 03:03:06.090558 # ok 239 /ocp/target-module@49a00000
1301 03:03:06.114658 # ok 240 /ocp/target-module@49a00000/dma@0
1302 03:03:06.133650 # ok 241 /ocp/target-module@4c000000
1303 03:03:06.204766 # not ok 242 /ocp/target-module@4c000000/emif@0
1304 03:03:06.232806 # ok 243 /ocp/target-module@50000000
1305 03:03:06.253120 # ok 244 /ocp/target-module@53100000
1306 03:03:06.324855 # not ok 245 /ocp/target-module@53100000/sham@0
1307 03:03:06.344007 # ok 246 /ocp/target-module@53500000
1308 03:03:06.416429 # not ok 247 /ocp/target-module@53500000/aes@0
1309 03:03:06.441386 # ok 248 /ocp/target-module@56000000
1310 03:03:06.544685 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1311 03:03:06.612020 # ok 250 /opp-table # SKIP
1312 03:03:06.688169 # ok 251 /soc # SKIP
1313 03:03:06.704818 # ok 252 /sound
1314 03:03:06.733626 # ok 253 /target-module@4b000000
1315 03:03:06.760600 # ok 254 /target-module@4b000000/target-module@140000
1316 03:03:06.777998 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1317 03:03:06.785950 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1318 03:03:06.791245 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1319 03:03:08.963490 dt_test_unprobed_devices_sh_ skip
1320 03:03:08.968745 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1321 03:03:08.974703 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1322 03:03:08.975004 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1323 03:03:08.979967 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1324 03:03:08.985531 dt_test_unprobed_devices_sh_fixedregulator0 pass
1325 03:03:08.991515 dt_test_unprobed_devices_sh_leds pass
1326 03:03:08.991819 dt_test_unprobed_devices_sh_ocp pass
1327 03:03:08.996970 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1328 03:03:09.002381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1329 03:03:09.007986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1330 03:03:09.019175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1331 03:03:09.025175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1332 03:03:09.030765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1333 03:03:09.041983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1334 03:03:09.047457 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1335 03:03:09.058424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1336 03:03:09.069784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1337 03:03:09.080942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1338 03:03:09.086830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1339 03:03:09.097839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1340 03:03:09.108897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1341 03:03:09.120500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1342 03:03:09.131243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1343 03:03:09.137205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1344 03:03:09.148547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1345 03:03:09.159546 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1346 03:03:09.170768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1347 03:03:09.181611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1348 03:03:09.187421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1349 03:03:09.198329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1350 03:03:09.209680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1351 03:03:09.220803 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1352 03:03:09.226806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1353 03:03:09.237583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1354 03:03:09.248699 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1355 03:03:09.260025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1356 03:03:09.271053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1357 03:03:09.276646 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1358 03:03:09.287800 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1359 03:03:09.298969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1360 03:03:09.310245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1361 03:03:09.321459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1362 03:03:09.332741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1363 03:03:09.343865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1364 03:03:09.354968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1365 03:03:09.366225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1366 03:03:09.377533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1367 03:03:09.388866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1368 03:03:09.399948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1369 03:03:09.410967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1370 03:03:09.422078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1371 03:03:09.433281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1372 03:03:09.444497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1373 03:03:09.455789 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1374 03:03:09.466874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1375 03:03:09.478041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1376 03:03:09.489264 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1377 03:03:09.501125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1378 03:03:09.512113 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1379 03:03:09.523220 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1380 03:03:09.534519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1381 03:03:09.545710 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1382 03:03:09.556549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1383 03:03:09.562087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1384 03:03:09.573242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1385 03:03:09.584413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1386 03:03:09.595714 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1387 03:03:09.607241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1388 03:03:09.618053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1389 03:03:09.629712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1390 03:03:09.640433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1391 03:03:09.651620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1392 03:03:09.662959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1393 03:03:09.674055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1394 03:03:09.685175 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1395 03:03:09.696337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1396 03:03:09.707999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1397 03:03:09.718862 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1398 03:03:09.729998 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1399 03:03:09.741640 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1400 03:03:09.752477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1401 03:03:09.757929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1402 03:03:09.769122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1403 03:03:09.780281 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1404 03:03:09.791557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1405 03:03:09.802733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1406 03:03:09.808403 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1407 03:03:09.825297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1408 03:03:09.836400 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1409 03:03:09.842030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1410 03:03:09.858794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1411 03:03:09.869988 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1412 03:03:09.881693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1413 03:03:09.887343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1414 03:03:09.898017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1415 03:03:09.909095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1416 03:03:09.914839 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1417 03:03:09.925942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1418 03:03:09.937121 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1419 03:03:09.942748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1420 03:03:09.953924 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1421 03:03:09.959509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1422 03:03:09.970765 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1423 03:03:09.981916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1424 03:03:09.993098 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1425 03:03:10.004333 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1426 03:03:10.015556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1427 03:03:10.026756 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1428 03:03:10.038277 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1429 03:03:10.049563 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1430 03:03:10.060737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1431 03:03:10.071832 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1432 03:03:10.083145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1433 03:03:10.094271 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1434 03:03:10.111080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1435 03:03:10.122218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1436 03:03:10.133446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1437 03:03:10.144265 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1438 03:03:10.155799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1439 03:03:10.172560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1440 03:03:10.183773 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1441 03:03:10.195095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1442 03:03:10.205898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1443 03:03:10.211480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1444 03:03:10.222726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1445 03:03:10.234190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1446 03:03:10.239705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1447 03:03:10.251054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1448 03:03:10.256635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1449 03:03:10.267484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1450 03:03:10.272964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1451 03:03:10.284111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1452 03:03:10.289858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1453 03:03:10.300937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1454 03:03:10.306509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1455 03:03:10.317830 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1456 03:03:10.328876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1457 03:03:10.340003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1458 03:03:10.345555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1459 03:03:10.356866 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1460 03:03:10.368378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1461 03:03:10.373874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1462 03:03:10.384854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1463 03:03:10.390483 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1464 03:03:10.396086 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1465 03:03:10.401837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1466 03:03:10.407656 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1467 03:03:10.418480 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1468 03:03:10.424246 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1469 03:03:10.429863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1470 03:03:10.440839 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1471 03:03:10.446416 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1472 03:03:10.457831 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1473 03:03:10.463252 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1474 03:03:10.474432 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1475 03:03:10.479944 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1476 03:03:10.485525 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1477 03:03:10.496824 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1478 03:03:10.502435 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1479 03:03:10.513819 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1480 03:03:10.519249 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1481 03:03:10.530826 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1482 03:03:10.536214 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1483 03:03:10.547142 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1484 03:03:10.552893 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1485 03:03:10.564109 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1486 03:03:10.569876 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1487 03:03:10.580830 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1488 03:03:10.586492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1489 03:03:10.597692 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1490 03:03:10.603491 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1491 03:03:10.609178 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1492 03:03:10.620352 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1493 03:03:10.625679 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1494 03:03:10.637087 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1495 03:03:10.642325 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1496 03:03:10.654049 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1497 03:03:10.659508 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1498 03:03:10.670733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1499 03:03:10.681666 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1500 03:03:10.692858 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1501 03:03:10.698667 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1502 03:03:10.709657 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1503 03:03:10.715144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1504 03:03:10.726370 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1505 03:03:10.731929 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1506 03:03:10.743120 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1507 03:03:10.748718 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1508 03:03:10.760143 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1509 03:03:10.771591 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1510 03:03:10.776839 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1511 03:03:10.787990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1512 03:03:10.793542 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1513 03:03:10.804901 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1514 03:03:10.810629 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1515 03:03:10.815987 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1516 03:03:10.827014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1517 03:03:10.832619 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1518 03:03:10.838702 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1519 03:03:10.849550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1520 03:03:10.855406 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1521 03:03:10.866351 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1522 03:03:10.872010 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1523 03:03:10.883106 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1524 03:03:10.888731 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1525 03:03:10.894267 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1526 03:03:10.900101 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1527 03:03:10.911015 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1528 03:03:10.916711 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1529 03:03:10.928004 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1530 03:03:10.933535 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1531 03:03:10.944671 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1532 03:03:10.955761 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1533 03:03:10.967336 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1534 03:03:10.972982 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1535 03:03:10.984129 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1536 03:03:10.995059 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1537 03:03:11.000645 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1538 03:03:11.006201 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1539 03:03:11.011881 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1540 03:03:11.017354 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1541 03:03:11.022840 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1542 03:03:11.028726 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1543 03:03:11.039759 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1544 03:03:11.045379 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1545 03:03:11.051099 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1546 03:03:11.056538 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1547 03:03:11.062302 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1548 03:03:11.067863 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1549 03:03:11.073477 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1550 03:03:11.079089 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1551 03:03:11.084661 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1552 03:03:11.090225 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1553 03:03:11.095910 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1554 03:03:11.101455 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1555 03:03:11.107058 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1556 03:03:11.112560 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1557 03:03:11.118254 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1558 03:03:11.123966 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1559 03:03:11.129418 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1560 03:03:11.135057 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1561 03:03:11.140637 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1562 03:03:11.146316 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1563 03:03:11.152188 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1564 03:03:11.157462 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1565 03:03:11.163151 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1566 03:03:11.168667 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1567 03:03:11.174270 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1568 03:03:11.179907 dt_test_unprobed_devices_sh_opp-table skip
1569 03:03:11.185447 dt_test_unprobed_devices_sh_soc skip
1570 03:03:11.185692 dt_test_unprobed_devices_sh_sound pass
1571 03:03:11.191085 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1572 03:03:11.196647 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1573 03:03:11.207941 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1574 03:03:11.208233 dt_test_unprobed_devices_sh fail
1575 03:03:11.213446 + ../../utils/send-to-lava.sh ./output/result.txt
1576 03:03:11.217899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1577 03:03:11.218397 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1579 03:03:11.266161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1580 03:03:11.266789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1582 03:03:11.356928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1583 03:03:11.357466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1585 03:03:11.450385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1586 03:03:11.450836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1588 03:03:11.541720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1589 03:03:11.542234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1591 03:03:11.634031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1592 03:03:11.634503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1594 03:03:11.721363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1595 03:03:11.721810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1597 03:03:11.811620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1598 03:03:11.812107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1600 03:03:11.900397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1601 03:03:11.900825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1603 03:03:11.994608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1604 03:03:11.995045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1606 03:03:12.086791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1607 03:03:12.087297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1609 03:03:12.169016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1610 03:03:12.169525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1612 03:03:12.264447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1613 03:03:12.264969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1615 03:03:12.354660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1616 03:03:12.355284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1618 03:03:12.443474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1619 03:03:12.443948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1621 03:03:12.535654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1622 03:03:12.536174 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1624 03:03:12.626608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1625 03:03:12.627147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1627 03:03:12.717211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1628 03:03:12.717859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1630 03:03:12.812202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1631 03:03:12.812678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1633 03:03:12.904936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1634 03:03:12.905423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1636 03:03:13.001307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1637 03:03:13.001849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1639 03:03:13.093026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1640 03:03:13.093538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1642 03:03:13.185174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1643 03:03:13.185635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1645 03:03:13.274911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1646 03:03:13.275402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1648 03:03:13.370387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1649 03:03:13.370984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1651 03:03:13.459320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1652 03:03:13.459844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1654 03:03:13.550401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1655 03:03:13.550944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1657 03:03:13.644272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1658 03:03:13.644708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1660 03:03:13.733492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1661 03:03:13.733975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1663 03:03:13.824549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1664 03:03:13.825072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1666 03:03:13.916832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1667 03:03:13.917381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1669 03:03:14.007994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1670 03:03:14.008502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1672 03:03:14.097051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1673 03:03:14.097540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1675 03:03:14.185378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1676 03:03:14.185914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1678 03:03:14.277496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1679 03:03:14.278040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1681 03:03:14.367019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1682 03:03:14.367517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1684 03:03:14.456608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1685 03:03:14.457124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1687 03:03:14.548886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1688 03:03:14.549425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1690 03:03:14.638833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1691 03:03:14.639342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1693 03:03:14.728016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1694 03:03:14.728552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1696 03:03:14.819023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1697 03:03:14.819474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1699 03:03:14.905308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1700 03:03:14.905805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1702 03:03:14.989113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1703 03:03:14.989605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1705 03:03:15.075812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1706 03:03:15.076335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1708 03:03:15.165647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1709 03:03:15.166147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1711 03:03:15.255585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1712 03:03:15.256088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1714 03:03:15.347009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1715 03:03:15.347546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1717 03:03:15.439533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1718 03:03:15.440114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1720 03:03:15.527442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1721 03:03:15.528019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1723 03:03:15.616064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1724 03:03:15.616495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1726 03:03:15.708707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1727 03:03:15.709261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1729 03:03:15.801172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1730 03:03:15.801631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1732 03:03:15.889757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1733 03:03:15.890221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1735 03:03:15.977580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1736 03:03:15.978172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1738 03:03:16.068000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1739 03:03:16.068445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1741 03:03:16.156830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1742 03:03:16.157275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1744 03:03:16.246552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1745 03:03:16.247063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1747 03:03:16.334937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1748 03:03:16.335408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1750 03:03:16.424035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1751 03:03:16.424619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1753 03:03:16.513379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1754 03:03:16.513883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1756 03:03:16.602856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1757 03:03:16.603299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1759 03:03:16.695191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1760 03:03:16.695662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1762 03:03:16.785153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1763 03:03:16.785626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1765 03:03:16.874634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1766 03:03:16.875004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1768 03:03:16.963845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1769 03:03:16.964292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1771 03:03:17.052759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1772 03:03:17.053212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1774 03:03:17.143357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1775 03:03:17.143750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1777 03:03:17.235517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1778 03:03:17.235902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1780 03:03:17.323801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1781 03:03:17.324235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1783 03:03:17.412472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1784 03:03:17.412913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1786 03:03:17.505325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1787 03:03:17.505756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1789 03:03:17.594968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1790 03:03:17.595400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1792 03:03:17.687310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1793 03:03:17.687762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1795 03:03:17.776014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1796 03:03:17.776475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1798 03:03:17.866795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1799 03:03:17.867272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1801 03:03:17.957157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1802 03:03:17.957634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1804 03:03:18.045889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1805 03:03:18.046361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1807 03:03:18.135687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1808 03:03:18.136150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1810 03:03:18.225656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1811 03:03:18.226144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1813 03:03:18.314673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1814 03:03:18.315172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1816 03:03:18.403620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1817 03:03:18.404054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1819 03:03:18.493553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1820 03:03:18.494016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1822 03:03:18.583218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1823 03:03:18.583666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1825 03:03:18.671287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1826 03:03:18.671722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1828 03:03:18.760747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1829 03:03:18.761181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1831 03:03:18.849839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1832 03:03:18.850286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1834 03:03:18.932708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1835 03:03:18.933179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1837 03:03:19.021149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1838 03:03:19.021613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1840 03:03:19.112322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1841 03:03:19.112785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1843 03:03:19.203646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1844 03:03:19.204098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1846 03:03:19.286938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1847 03:03:19.287385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1849 03:03:19.368735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1850 03:03:19.369181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1852 03:03:19.453852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1853 03:03:19.454302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1855 03:03:19.538249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1856 03:03:19.538703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1858 03:03:19.626684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1859 03:03:19.627142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1861 03:03:19.713490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1862 03:03:19.713967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1864 03:03:19.803586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1865 03:03:19.804032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1867 03:03:19.893527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1868 03:03:19.894015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1870 03:03:19.983748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1871 03:03:19.984184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1873 03:03:20.075103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1874 03:03:20.075579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1876 03:03:20.166288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1877 03:03:20.166761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1879 03:03:20.255708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1880 03:03:20.256166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1882 03:03:20.343588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1883 03:03:20.344036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1885 03:03:20.432611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1886 03:03:20.433052 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1888 03:03:20.525444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1889 03:03:20.525924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1891 03:03:20.615499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1892 03:03:20.615969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1894 03:03:20.701960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1895 03:03:20.702474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1897 03:03:20.790143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1898 03:03:20.790598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1900 03:03:20.881629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1901 03:03:20.882059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1903 03:03:20.970495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1904 03:03:20.970964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1906 03:03:21.052051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1907 03:03:21.052500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1909 03:03:21.133641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1910 03:03:21.134087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1912 03:03:21.216411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1913 03:03:21.216847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1915 03:03:21.305943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1916 03:03:21.306386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1918 03:03:21.393040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1919 03:03:21.393495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1921 03:03:21.480601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1922 03:03:21.481037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1924 03:03:21.562501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1925 03:03:21.562941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1927 03:03:21.652392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1928 03:03:21.652869 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1930 03:03:21.733652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1931 03:03:21.734082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1933 03:03:21.821319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1934 03:03:21.821743 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1936 03:03:21.902219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1938 03:03:21.905311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1939 03:03:21.990361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1941 03:03:21.992647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1942 03:03:22.079487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1944 03:03:22.081541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1945 03:03:22.167822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1946 03:03:22.168273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1948 03:03:22.250660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1949 03:03:22.251101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1951 03:03:22.332581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1952 03:03:22.333015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1954 03:03:22.424624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1955 03:03:22.425053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1957 03:03:22.513196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1958 03:03:22.513606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1960 03:03:22.604264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1961 03:03:22.604682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1963 03:03:22.692064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1964 03:03:22.692529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1966 03:03:22.781723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1967 03:03:22.782171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1969 03:03:22.869506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1970 03:03:22.869966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1972 03:03:22.960074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1973 03:03:22.960521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1975 03:03:23.043049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1976 03:03:23.043521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1978 03:03:23.126272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1979 03:03:23.126739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1981 03:03:23.209423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1982 03:03:23.209914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1984 03:03:23.293915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1985 03:03:23.294345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1987 03:03:23.386160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1988 03:03:23.386593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1990 03:03:23.477680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1991 03:03:23.478110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1993 03:03:23.566046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1994 03:03:23.566519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
1996 03:03:23.656324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
1997 03:03:23.656747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
1999 03:03:23.747289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2000 03:03:23.747710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2002 03:03:23.835143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2003 03:03:23.835566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2005 03:03:23.924104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2006 03:03:23.924524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2008 03:03:24.013972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2009 03:03:24.014386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2011 03:03:24.097883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2012 03:03:24.098303 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2014 03:03:24.188157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2015 03:03:24.188592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2017 03:03:24.275798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2018 03:03:24.276222 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2020 03:03:24.367066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2021 03:03:24.367499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2023 03:03:24.457345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2024 03:03:24.457790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2026 03:03:24.540417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2027 03:03:24.540845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2029 03:03:24.629553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2030 03:03:24.629987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2032 03:03:24.718491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2033 03:03:24.718915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2035 03:03:24.812031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2036 03:03:24.812466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2038 03:03:24.901959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2039 03:03:24.902439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2041 03:03:24.991322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2042 03:03:24.991775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2044 03:03:25.079546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2045 03:03:25.080005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2047 03:03:25.168882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2048 03:03:25.169326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2050 03:03:25.257966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2051 03:03:25.258409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2053 03:03:25.344727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2054 03:03:25.345166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2056 03:03:25.432560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2057 03:03:25.432993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2059 03:03:25.524834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2060 03:03:25.525274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2062 03:03:25.611951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2063 03:03:25.612381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2065 03:03:25.701086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2066 03:03:25.701524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2068 03:03:25.790220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2069 03:03:25.790668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2071 03:03:25.882031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2072 03:03:25.882467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2074 03:03:25.970509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2075 03:03:25.970947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2077 03:03:26.060451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2078 03:03:26.060943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2080 03:03:26.147538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2081 03:03:26.147968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2083 03:03:26.231814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2084 03:03:26.232250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2086 03:03:26.320286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2087 03:03:26.320758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2089 03:03:26.413654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2090 03:03:26.414123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2092 03:03:26.502649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2093 03:03:26.502995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2095 03:03:26.593385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2096 03:03:26.593844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2098 03:03:26.682975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2099 03:03:26.683466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2101 03:03:26.772212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2102 03:03:26.772638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2104 03:03:26.861424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2105 03:03:26.861852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2107 03:03:26.947971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2108 03:03:26.948410 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2110 03:03:27.038311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2111 03:03:27.038749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2113 03:03:27.127421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2114 03:03:27.127834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2116 03:03:27.212501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2117 03:03:27.212931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2119 03:03:27.302796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2120 03:03:27.303261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2122 03:03:27.392828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2123 03:03:27.393286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2125 03:03:27.482948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2126 03:03:27.483413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2128 03:03:27.569831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2129 03:03:27.570254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2131 03:03:27.658512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2132 03:03:27.658930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2134 03:03:27.745949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2135 03:03:27.746377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2137 03:03:27.830152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2138 03:03:27.830593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2140 03:03:27.921113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2141 03:03:27.921586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2143 03:03:28.011499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2144 03:03:28.011940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2146 03:03:28.142047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2147 03:03:28.142477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2149 03:03:28.270764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2150 03:03:28.271217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2152 03:03:28.368928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2153 03:03:28.369368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2155 03:03:28.457816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2156 03:03:28.458258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2158 03:03:28.539536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2159 03:03:28.539939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2161 03:03:28.623391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2162 03:03:28.623850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2164 03:03:28.708531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2165 03:03:28.708966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2167 03:03:28.798968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2168 03:03:28.799392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2170 03:03:28.914919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2171 03:03:28.915355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2173 03:03:29.004181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2174 03:03:29.004603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2176 03:03:29.086588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2177 03:03:29.087018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2179 03:03:29.168229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2180 03:03:29.168674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2182 03:03:29.250642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2183 03:03:29.251067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2185 03:03:29.332856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2186 03:03:29.333314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2188 03:03:29.422271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2189 03:03:29.422697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2191 03:03:29.509552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2192 03:03:29.509944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2194 03:03:29.598883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2195 03:03:29.599273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2197 03:03:29.676793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2198 03:03:29.677184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2200 03:03:29.766831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2201 03:03:29.767215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2203 03:03:29.850140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2204 03:03:29.850511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2206 03:03:29.939027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2207 03:03:29.939380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2209 03:03:30.027818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2210 03:03:30.028183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2212 03:03:30.115640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2213 03:03:30.116019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2215 03:03:30.198301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2216 03:03:30.198661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2218 03:03:30.281865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2219 03:03:30.282253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2221 03:03:30.371636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2222 03:03:30.372064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2224 03:03:30.452387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2225 03:03:30.452819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2227 03:03:30.541124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2228 03:03:30.541551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2230 03:03:30.629261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2231 03:03:30.629692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2233 03:03:30.713662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2234 03:03:30.714101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2236 03:03:30.796324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2237 03:03:30.796759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2239 03:03:30.877514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2240 03:03:30.877969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2242 03:03:30.959492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2243 03:03:30.959921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2245 03:03:31.050518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2246 03:03:31.050977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2248 03:03:31.141622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2249 03:03:31.142068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2251 03:03:31.225686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2253 03:03:31.228941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2254 03:03:31.309362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2255 03:03:31.309820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2257 03:03:31.392387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2258 03:03:31.392818 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2260 03:03:31.473662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2261 03:03:31.474030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2263 03:03:31.555449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2264 03:03:31.555835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2266 03:03:31.637243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2267 03:03:31.637817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2269 03:03:31.719197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2270 03:03:31.719572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2272 03:03:31.802094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2273 03:03:31.802478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2275 03:03:31.888954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2276 03:03:31.889314 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2278 03:03:31.976648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2279 03:03:31.977055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2281 03:03:32.065984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2282 03:03:32.066355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2284 03:03:32.155760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2285 03:03:32.156200 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2287 03:03:32.239770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2288 03:03:32.240167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2290 03:03:32.330127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2291 03:03:32.330646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2293 03:03:32.429479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2294 03:03:32.430027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2296 03:03:32.520099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2297 03:03:32.520563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2299 03:03:32.611548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2300 03:03:32.612071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2302 03:03:32.705149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2303 03:03:32.705614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2305 03:03:32.797232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2306 03:03:32.797711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2308 03:03:32.889579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2309 03:03:32.890036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2311 03:03:32.978284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2312 03:03:32.978793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2314 03:03:33.073904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2315 03:03:33.074346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2317 03:03:33.169168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2318 03:03:33.169668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2320 03:03:33.268456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2321 03:03:33.269029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2323 03:03:33.358794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2324 03:03:33.359285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2326 03:03:33.471461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2327 03:03:33.471968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2329 03:03:33.638311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2330 03:03:33.638829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2332 03:03:33.758059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2333 03:03:33.758540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2335 03:03:33.870040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2336 03:03:33.870703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2338 03:03:33.968369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2339 03:03:33.968952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2341 03:03:34.059528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2342 03:03:34.059856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2344 03:03:34.146425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2345 03:03:34.146706 + set +x
2346 03:03:34.147075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2348 03:03:34.150642 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 707117_1.6.2.4.5>
2349 03:03:34.151153 Received signal: <ENDRUN> 1_kselftest-dt 707117_1.6.2.4.5
2350 03:03:34.151339 Ending use of test pattern.
2351 03:03:34.151480 Ending test lava.1_kselftest-dt (707117_1.6.2.4.5), duration 72.35
2353 03:03:34.156337 <LAVA_TEST_RUNNER EXIT>
2354 03:03:34.156847 ok: lava_test_shell seems to have completed
2355 03:03:34.158767 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2356 03:03:34.159096 end: 3.1 lava-test-shell (duration 00:01:14) [common]
2357 03:03:34.159193 end: 3 lava-test-retry (duration 00:01:14) [common]
2358 03:03:34.159276 start: 4 finalize (timeout 00:05:56) [common]
2359 03:03:34.159363 start: 4.1 power-off (timeout 00:00:30) [common]
2360 03:03:34.159504 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2361 03:03:34.176991 >> OK - accepted request
2362 03:03:34.178914 Returned 0 in 0 seconds
2363 03:03:34.279714 end: 4.1 power-off (duration 00:00:00) [common]
2365 03:03:34.280307 start: 4.2 read-feedback (timeout 00:05:56) [common]
2366 03:03:34.280770 Listened to connection for namespace 'common' for up to 1s
2367 03:03:34.281218 Listened to connection for namespace 'common' for up to 1s
2368 03:03:35.281854 Finalising connection for namespace 'common'
2369 03:03:35.282179 Disconnecting from shell: Finalise
2370 03:03:35.282347 / #
2371 03:03:35.382839 end: 4.2 read-feedback (duration 00:00:01) [common]
2372 03:03:35.383215 end: 4 finalize (duration 00:00:01) [common]
2373 03:03:35.383482 Cleaning after the job
2374 03:03:35.383739 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/ramdisk
2375 03:03:35.390924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/kernel
2376 03:03:35.397355 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/dtb
2377 03:03:35.397889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/nfsrootfs
2378 03:03:35.511358 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707117/tftp-deploy-ustv2ygg/modules
2379 03:03:35.517785 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/707117
2380 03:03:36.519175 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/707117
2381 03:03:36.519423 Job finished correctly