Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 02:34:09.106560 lava-dispatcher, installed at version: 2024.01
2 02:34:09.107334 start: 0 validate
3 02:34:09.107823 Start time: 2024-09-05 02:34:09.107794+00:00 (UTC)
4 02:34:09.108403 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:34:09.108962 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 02:34:09.149930 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:34:09.150470 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-70-gc763c43396883%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 02:34:09.180147 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:34:09.180779 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-70-gc763c43396883%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 02:34:09.208355 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:34:09.208851 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 02:34:09.244230 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 02:34:09.244715 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-70-gc763c43396883%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 02:34:09.284090 validate duration: 0.18
16 02:34:09.285018 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 02:34:09.285371 start: 1.1 download-retry (timeout 00:10:00) [common]
18 02:34:09.285712 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 02:34:09.286326 Not decompressing ramdisk as can be used compressed.
20 02:34:09.286773 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 02:34:09.287061 saving as /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/ramdisk/initrd.cpio.gz
22 02:34:09.287344 total size: 4775763 (4 MB)
23 02:34:09.326260 progress 0 % (0 MB)
24 02:34:09.330630 progress 5 % (0 MB)
25 02:34:09.334099 progress 10 % (0 MB)
26 02:34:09.337537 progress 15 % (0 MB)
27 02:34:09.341348 progress 20 % (0 MB)
28 02:34:09.344678 progress 25 % (1 MB)
29 02:34:09.347939 progress 30 % (1 MB)
30 02:34:09.351675 progress 35 % (1 MB)
31 02:34:09.355003 progress 40 % (1 MB)
32 02:34:09.358526 progress 45 % (2 MB)
33 02:34:09.361838 progress 50 % (2 MB)
34 02:34:09.365568 progress 55 % (2 MB)
35 02:34:09.368862 progress 60 % (2 MB)
36 02:34:09.372175 progress 65 % (2 MB)
37 02:34:09.375864 progress 70 % (3 MB)
38 02:34:09.379197 progress 75 % (3 MB)
39 02:34:09.382392 progress 80 % (3 MB)
40 02:34:09.385721 progress 85 % (3 MB)
41 02:34:09.389143 progress 90 % (4 MB)
42 02:34:09.392028 progress 95 % (4 MB)
43 02:34:09.394915 progress 100 % (4 MB)
44 02:34:09.395587 4 MB downloaded in 0.11 s (42.08 MB/s)
45 02:34:09.396159 end: 1.1.1 http-download (duration 00:00:00) [common]
47 02:34:09.397109 end: 1.1 download-retry (duration 00:00:00) [common]
48 02:34:09.397430 start: 1.2 download-retry (timeout 00:10:00) [common]
49 02:34:09.397726 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 02:34:09.398241 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 02:34:09.398516 saving as /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/kernel/zImage
52 02:34:09.398740 total size: 11354624 (10 MB)
53 02:34:09.398966 No compression specified
54 02:34:09.436607 progress 0 % (0 MB)
55 02:34:09.443964 progress 5 % (0 MB)
56 02:34:09.451121 progress 10 % (1 MB)
57 02:34:09.458184 progress 15 % (1 MB)
58 02:34:09.465562 progress 20 % (2 MB)
59 02:34:09.472542 progress 25 % (2 MB)
60 02:34:09.479640 progress 30 % (3 MB)
61 02:34:09.487062 progress 35 % (3 MB)
62 02:34:09.494018 progress 40 % (4 MB)
63 02:34:09.501074 progress 45 % (4 MB)
64 02:34:09.508442 progress 50 % (5 MB)
65 02:34:09.515421 progress 55 % (5 MB)
66 02:34:09.522400 progress 60 % (6 MB)
67 02:34:09.530075 progress 65 % (7 MB)
68 02:34:09.537120 progress 70 % (7 MB)
69 02:34:09.544151 progress 75 % (8 MB)
70 02:34:09.551485 progress 80 % (8 MB)
71 02:34:09.558429 progress 85 % (9 MB)
72 02:34:09.565345 progress 90 % (9 MB)
73 02:34:09.572566 progress 95 % (10 MB)
74 02:34:09.578943 progress 100 % (10 MB)
75 02:34:09.579529 10 MB downloaded in 0.18 s (59.90 MB/s)
76 02:34:09.580040 end: 1.2.1 http-download (duration 00:00:00) [common]
78 02:34:09.580888 end: 1.2 download-retry (duration 00:00:00) [common]
79 02:34:09.581174 start: 1.3 download-retry (timeout 00:10:00) [common]
80 02:34:09.581446 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 02:34:09.581917 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 02:34:09.582199 saving as /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/dtb/am335x-boneblack.dtb
83 02:34:09.582414 total size: 70308 (0 MB)
84 02:34:09.582627 No compression specified
85 02:34:09.622572 progress 46 % (0 MB)
86 02:34:09.623734 progress 93 % (0 MB)
87 02:34:09.624747 progress 100 % (0 MB)
88 02:34:09.625379 0 MB downloaded in 0.04 s (1.56 MB/s)
89 02:34:09.626083 end: 1.3.1 http-download (duration 00:00:00) [common]
91 02:34:09.627367 end: 1.3 download-retry (duration 00:00:00) [common]
92 02:34:09.627822 start: 1.4 download-retry (timeout 00:10:00) [common]
93 02:34:09.628307 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 02:34:09.629008 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 02:34:09.629401 saving as /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/nfsrootfs/full.rootfs.tar
96 02:34:09.629736 total size: 117747780 (112 MB)
97 02:34:09.630092 Using unxz to decompress xz
98 02:34:09.669930 progress 0 % (0 MB)
99 02:34:10.445123 progress 5 % (5 MB)
100 02:34:11.170488 progress 10 % (11 MB)
101 02:34:11.928582 progress 15 % (16 MB)
102 02:34:12.631818 progress 20 % (22 MB)
103 02:34:13.205633 progress 25 % (28 MB)
104 02:34:13.998589 progress 30 % (33 MB)
105 02:34:14.788930 progress 35 % (39 MB)
106 02:34:15.131279 progress 40 % (44 MB)
107 02:34:15.500287 progress 45 % (50 MB)
108 02:34:16.142372 progress 50 % (56 MB)
109 02:34:16.937426 progress 55 % (61 MB)
110 02:34:17.655758 progress 60 % (67 MB)
111 02:34:18.359818 progress 65 % (73 MB)
112 02:34:19.110972 progress 70 % (78 MB)
113 02:34:19.857956 progress 75 % (84 MB)
114 02:34:20.579747 progress 80 % (89 MB)
115 02:34:21.283698 progress 85 % (95 MB)
116 02:34:22.062055 progress 90 % (101 MB)
117 02:34:22.814775 progress 95 % (106 MB)
118 02:34:23.620553 progress 100 % (112 MB)
119 02:34:23.632764 112 MB downloaded in 14.00 s (8.02 MB/s)
120 02:34:23.633712 end: 1.4.1 http-download (duration 00:00:14) [common]
122 02:34:23.635517 end: 1.4 download-retry (duration 00:00:14) [common]
123 02:34:23.636156 start: 1.5 download-retry (timeout 00:09:46) [common]
124 02:34:23.636737 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 02:34:23.637714 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 02:34:23.638240 saving as /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/modules/modules.tar
127 02:34:23.638695 total size: 6605692 (6 MB)
128 02:34:23.639165 Using unxz to decompress xz
129 02:34:23.683726 progress 0 % (0 MB)
130 02:34:23.719548 progress 5 % (0 MB)
131 02:34:23.761660 progress 10 % (0 MB)
132 02:34:23.805172 progress 15 % (0 MB)
133 02:34:23.851082 progress 20 % (1 MB)
134 02:34:23.894307 progress 25 % (1 MB)
135 02:34:23.938942 progress 30 % (1 MB)
136 02:34:23.981483 progress 35 % (2 MB)
137 02:34:24.023890 progress 40 % (2 MB)
138 02:34:24.066236 progress 45 % (2 MB)
139 02:34:24.109271 progress 50 % (3 MB)
140 02:34:24.151125 progress 55 % (3 MB)
141 02:34:24.193506 progress 60 % (3 MB)
142 02:34:24.241846 progress 65 % (4 MB)
143 02:34:24.284954 progress 70 % (4 MB)
144 02:34:24.328065 progress 75 % (4 MB)
145 02:34:24.372623 progress 80 % (5 MB)
146 02:34:24.416989 progress 85 % (5 MB)
147 02:34:24.458722 progress 90 % (5 MB)
148 02:34:24.500739 progress 95 % (6 MB)
149 02:34:24.543467 progress 100 % (6 MB)
150 02:34:24.555714 6 MB downloaded in 0.92 s (6.87 MB/s)
151 02:34:24.556623 end: 1.5.1 http-download (duration 00:00:01) [common]
153 02:34:24.558261 end: 1.5 download-retry (duration 00:00:01) [common]
154 02:34:24.558789 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 02:34:24.559316 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 02:34:40.862930 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4
157 02:34:40.863739 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 02:34:40.864217 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 02:34:40.865070 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y
160 02:34:40.865965 makedir: /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin
161 02:34:40.866424 makedir: /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/tests
162 02:34:40.866765 makedir: /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/results
163 02:34:40.867120 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-add-keys
164 02:34:40.867684 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-add-sources
165 02:34:40.868304 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-background-process-start
166 02:34:40.868947 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-background-process-stop
167 02:34:40.870029 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-common-functions
168 02:34:40.871624 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-echo-ipv4
169 02:34:40.872195 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-install-packages
170 02:34:40.872718 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-installed-packages
171 02:34:40.873246 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-os-build
172 02:34:40.873753 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-probe-channel
173 02:34:40.874761 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-probe-ip
174 02:34:40.875366 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-target-ip
175 02:34:40.875883 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-target-mac
176 02:34:40.876442 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-target-storage
177 02:34:40.877086 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-test-case
178 02:34:40.877704 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-test-event
179 02:34:40.879209 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-test-feedback
180 02:34:40.879759 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-test-raise
181 02:34:40.880332 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-test-reference
182 02:34:40.881209 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-test-runner
183 02:34:40.881875 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-test-set
184 02:34:40.882768 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-test-shell
185 02:34:40.883285 Updating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-add-keys (debian)
186 02:34:40.883858 Updating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-add-sources (debian)
187 02:34:40.884564 Updating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-install-packages (debian)
188 02:34:40.885171 Updating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-installed-packages (debian)
189 02:34:40.885717 Updating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/bin/lava-os-build (debian)
190 02:34:40.886449 Creating /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/environment
191 02:34:40.886869 LAVA metadata
192 02:34:40.887233 - LAVA_JOB_ID=707040
193 02:34:40.887458 - LAVA_DISPATCHER_IP=192.168.6.2
194 02:34:40.887863 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 02:34:40.888958 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 02:34:40.889315 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 02:34:40.889936 skipped lava-vland-overlay
198 02:34:40.890192 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 02:34:40.890453 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 02:34:40.890674 skipped lava-multinode-overlay
201 02:34:40.890920 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 02:34:40.891671 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 02:34:40.891938 Loading test definitions
204 02:34:40.892298 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 02:34:40.892538 Using /lava-707040 at stage 0
206 02:34:40.893766 uuid=707040_1.6.2.4.1 testdef=None
207 02:34:40.894127 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 02:34:40.894397 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 02:34:40.896076 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 02:34:40.896912 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 02:34:40.899150 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 02:34:40.900102 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 02:34:40.902115 runner path: /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/0/tests/0_timesync-off test_uuid 707040_1.6.2.4.1
216 02:34:40.902995 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 02:34:40.904147 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 02:34:40.904398 Using /lava-707040 at stage 0
220 02:34:40.904791 Fetching tests from https://github.com/kernelci/test-definitions.git
221 02:34:40.905100 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/0/tests/1_kselftest-dt'
222 02:34:44.451759 Running '/usr/bin/git checkout kernelci.org
223 02:34:44.822811 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 02:34:44.825169 uuid=707040_1.6.2.4.5 testdef=None
225 02:34:44.825798 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 02:34:44.827273 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 02:34:44.832705 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 02:34:44.834314 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 02:34:44.841511 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 02:34:44.843193 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 02:34:44.850217 runner path: /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/0/tests/1_kselftest-dt test_uuid 707040_1.6.2.4.5
235 02:34:44.850751 BOARD='beaglebone-black'
236 02:34:44.851167 BRANCH='mainline'
237 02:34:44.851567 SKIPFILE='/dev/null'
238 02:34:44.851961 SKIP_INSTALL='True'
239 02:34:44.852391 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 02:34:44.852798 TST_CASENAME=''
241 02:34:44.853192 TST_CMDFILES='dt'
242 02:34:44.854194 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 02:34:44.855752 Creating lava-test-runner.conf files
245 02:34:44.856196 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/707040/lava-overlay-slyp694y/lava-707040/0 for stage 0
246 02:34:44.856863 - 0_timesync-off
247 02:34:44.857329 - 1_kselftest-dt
248 02:34:44.857969 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 02:34:44.858521 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 02:35:08.127207 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 02:35:08.127645 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 02:35:08.127906 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 02:35:08.128203 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 02:35:08.128469 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 02:35:08.487199 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 02:35:08.487661 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 02:35:08.487908 extracting modules file /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4
258 02:35:09.363852 extracting modules file /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/707040/extract-overlay-ramdisk-aatliwhs/ramdisk
259 02:35:10.260154 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 02:35:10.260621 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 02:35:10.260897 [common] Applying overlay to NFS
262 02:35:10.261113 [common] Applying overlay /var/lib/lava/dispatcher/tmp/707040/compress-overlay-4n0qsekg/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4
263 02:35:12.967218 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 02:35:12.967688 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 02:35:12.967964 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 02:35:12.968276 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 02:35:12.968529 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 02:35:12.968790 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 02:35:12.969039 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 02:35:12.969292 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 02:35:12.969543 Building ramdisk /var/lib/lava/dispatcher/tmp/707040/extract-overlay-ramdisk-aatliwhs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/707040/extract-overlay-ramdisk-aatliwhs/ramdisk
272 02:35:13.953171 >> 74799 blocks
273 02:35:18.508420 Adding RAMdisk u-boot header.
274 02:35:18.509131 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/707040/extract-overlay-ramdisk-aatliwhs/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/707040/extract-overlay-ramdisk-aatliwhs/ramdisk.cpio.gz.uboot
275 02:35:18.697470 output: Image Name:
276 02:35:18.697882 output: Created: Thu Sep 5 02:35:18 2024
277 02:35:18.698094 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 02:35:18.698300 output: Data Size: 14795114 Bytes = 14448.35 KiB = 14.11 MiB
279 02:35:18.698505 output: Load Address: 00000000
280 02:35:18.698705 output: Entry Point: 00000000
281 02:35:18.698904 output:
282 02:35:18.699486 rename /var/lib/lava/dispatcher/tmp/707040/extract-overlay-ramdisk-aatliwhs/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/ramdisk/ramdisk.cpio.gz.uboot
283 02:35:18.699905 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 02:35:18.700411 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 02:35:18.700942 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:51) [common]
286 02:35:18.701397 No LXC device requested
287 02:35:18.701892 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 02:35:18.702396 start: 1.8 deploy-device-env (timeout 00:08:51) [common]
289 02:35:18.702886 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 02:35:18.703297 Checking files for TFTP limit of 4294967296 bytes.
291 02:35:18.705966 end: 1 tftp-deploy (duration 00:01:09) [common]
292 02:35:18.706539 start: 2 uboot-action (timeout 00:05:00) [common]
293 02:35:18.707059 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 02:35:18.707549 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 02:35:18.708078 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 02:35:18.708832 substitutions:
297 02:35:18.709247 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 02:35:18.709649 - {DTB_ADDR}: 0x88000000
299 02:35:18.710049 - {DTB}: 707040/tftp-deploy-r95935d4/dtb/am335x-boneblack.dtb
300 02:35:18.710444 - {INITRD}: 707040/tftp-deploy-r95935d4/ramdisk/ramdisk.cpio.gz.uboot
301 02:35:18.710834 - {KERNEL_ADDR}: 0x82000000
302 02:35:18.711224 - {KERNEL}: 707040/tftp-deploy-r95935d4/kernel/zImage
303 02:35:18.711615 - {LAVA_MAC}: None
304 02:35:18.712083 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4
305 02:35:18.712487 - {NFS_SERVER_IP}: 192.168.6.2
306 02:35:18.712880 - {PRESEED_CONFIG}: None
307 02:35:18.713270 - {PRESEED_LOCAL}: None
308 02:35:18.713659 - {RAMDISK_ADDR}: 0x83000000
309 02:35:18.714047 - {RAMDISK}: 707040/tftp-deploy-r95935d4/ramdisk/ramdisk.cpio.gz.uboot
310 02:35:18.714438 - {ROOT_PART}: None
311 02:35:18.714822 - {ROOT}: None
312 02:35:18.715206 - {SERVER_IP}: 192.168.6.2
313 02:35:18.715590 - {TEE_ADDR}: 0x83000000
314 02:35:18.715975 - {TEE}: None
315 02:35:18.716389 Parsed boot commands:
316 02:35:18.716763 - setenv autoload no
317 02:35:18.717147 - setenv initrd_high 0xffffffff
318 02:35:18.717531 - setenv fdt_high 0xffffffff
319 02:35:18.717912 - dhcp
320 02:35:18.718294 - setenv serverip 192.168.6.2
321 02:35:18.718679 - tftp 0x82000000 707040/tftp-deploy-r95935d4/kernel/zImage
322 02:35:18.719060 - tftp 0x83000000 707040/tftp-deploy-r95935d4/ramdisk/ramdisk.cpio.gz.uboot
323 02:35:18.719445 - setenv initrd_size ${filesize}
324 02:35:18.719829 - tftp 0x88000000 707040/tftp-deploy-r95935d4/dtb/am335x-boneblack.dtb
325 02:35:18.720241 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 02:35:18.720641 - bootz 0x82000000 0x83000000 0x88000000
327 02:35:18.721123 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 02:35:18.722593 start: 2.3 connect-device (timeout 00:05:00) [common]
330 02:35:18.723011 [common] connect-device Connecting to device using 'telnet conserv2 3006'
331 02:35:18.738078 Setting prompt string to ['lava-test: # ']
332 02:35:18.739557 end: 2.3 connect-device (duration 00:00:00) [common]
333 02:35:18.740191 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 02:35:18.740785 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 02:35:18.741397 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 02:35:18.742634 Calling: 'curl' 'http://conserv2.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-02'
337 02:35:18.791284 >> OK - accepted request
338 02:35:18.793118 Returned 0 in 0 seconds
339 02:35:18.894219 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 02:35:18.895824 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 02:35:18.896424 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 02:35:18.896947 Setting prompt string to ['Hit any key to stop autoboot']
344 02:35:18.897411 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 02:35:18.898959 Trying 192.168.56.183...
346 02:35:18.899437 Connected to conserv2.
347 02:35:18.899853 Escape character is '^]'.
348 02:35:18.900291
349 02:35:18.900715 ser2net port telnet,3006 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.1.3.4:1.0-port0, 115200n81, [] (Debian GNU/Linux)
350 02:35:18.901135
351 02:35:26.497140
352 02:35:26.504106 U-Boot SPL 2022.04-00708-g42a2d90cf5-dirty (Apr 30 2022 - 01:31:21 +0100)
353 02:35:26.504578 Trying to boot from MMC1
354 02:35:27.061144
355 02:35:27.061730
356 02:35:27.066511 U-Boot 2022.04-00708-g42a2d90cf5-dirty (Apr 30 2022 - 01:31:21 +0100)
357 02:35:27.066958
358 02:35:27.067364 CPU : AM335X-GP rev 2.0
359 02:35:27.072027 Model: TI AM335x BeagleBone Black
360 02:35:27.072470 DRAM: 512 MiB
361 02:35:27.147295 Core: 152 devices, 15 uclasses, devicetree: separate
362 02:35:27.156929 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 02:35:30.550194 NAND:
364 02:35:30.557484 U-Boot SPL 2022.04-00708-g42a2d90cf5-dirty (Apr 30 2022 - 01:31:21 +0100)
365 02:35:30.557962 Trying to boot from MMC1
366 02:35:31.115441
367 02:35:31.116109
368 02:35:31.120837 U-Boot 2022.04-00708-g42a2d90cf5-dirty (Apr 30 2022 - 01:31:21 +0100)
369 02:35:31.121299
370 02:35:31.121724 CPU : AM335X-GP rev 2.0
371 02:35:31.126236 Model: TI AM335x BeagleBone Black
372 02:35:31.126685 DRAM: 512 MiB
373 02:35:31.201754 Core: 152 devices, 15 uclasses, devicetree: separate
374 02:35:31.211111 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 02:35:33.397267 NAND:
376 02:35:33.404736 U-Boot SPL 2022.04-00708-g42a2d90cf5-dirty (Apr 30 2022 - 01:31:21 +0100)
377 02:35:33.405277 Trying to boot from MMC1
378 02:35:33.962291
379 02:35:33.962934
380 02:35:33.967693 U-Boot 2022.04-00708-g42a2d90cf5-dirty (Apr 30 2022 - 01:31:21 +0100)
381 02:35:33.968398
382 02:35:33.968961 CPU : AM335X-GP rev 2.0
383 02:35:33.973035 Model: TI AM335x BeagleBone Black
384 02:35:33.973601 DRAM: 512 MiB
385 02:35:34.048506 Core: 152 devices, 15 uclasses, devicetree: separate
386 02:35:34.058013 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 02:35:34.462330 NAND: 0 MiB
388 02:35:34.472124 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 02:35:34.545264 Loading Environment from FAT... Unable to use mmc 0:1...
390 02:35:34.566007 <ethaddr> not set. Validating first E-fuse MAC
391 02:35:34.595462 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 02:35:34.654189 Hit any key to stop autoboot: 2
394 02:35:34.655385 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 02:35:34.656193 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 02:35:34.656833 Setting prompt string to ['=>']
397 02:35:34.657470 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 02:35:34.663756 0
399 02:35:34.664928 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 02:35:34.665589 Sending with 10 millisecond of delay
402 02:35:35.801199 => setenv autoload no
403 02:35:35.812257 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 02:35:35.818553 setenv autoload no
405 02:35:35.819452 Sending with 10 millisecond of delay
407 02:35:37.617605 => setenv initrd_high 0xffffffff
408 02:35:37.628620 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 02:35:37.629760 setenv initrd_high 0xffffffff
410 02:35:37.630639 Sending with 10 millisecond of delay
412 02:35:39.248045 => setenv fdt_high 0xffffffff
413 02:35:39.259069 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 02:35:39.260176 setenv fdt_high 0xffffffff
415 02:35:39.261072 Sending with 10 millisecond of delay
417 02:35:39.553358 => dhcp
418 02:35:39.564158 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 02:35:39.565056 dhcp
420 02:35:39.565500 link up on port 0, speed 100, full duplex
421 02:35:39.565915 BOOTP broadcast 1
422 02:35:39.819340 BOOTP broadcast 2
423 02:35:40.321397 BOOTP broadcast 3
424 02:35:41.323356 BOOTP broadcast 4
425 02:35:43.325304 BOOTP broadcast 5
426 02:35:43.375961 DHCP client bound to address 192.168.6.29 (3806 ms)
427 02:35:43.376871 Sending with 10 millisecond of delay
429 02:35:45.054711 => setenv serverip 192.168.6.2
430 02:35:45.065555 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
431 02:35:45.066488 setenv serverip 192.168.6.2
432 02:35:45.067278 Sending with 10 millisecond of delay
434 02:35:48.550633 => tftp 0x82000000 707040/tftp-deploy-r95935d4/kernel/zImage
435 02:35:48.561512 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:30)
436 02:35:48.562470 tftp 0x82000000 707040/tftp-deploy-r95935d4/kernel/zImage
437 02:35:48.562945 link up on port 0, speed 100, full duplex
438 02:35:48.566700 Using ethernet@4a100000 device
439 02:35:48.571975 TFTP from server 192.168.6.2; our IP address is 192.168.6.29
440 02:35:48.572507 Filename '707040/tftp-deploy-r95935d4/kernel/zImage'.
441 02:35:48.575900 Load address: 0x82000000
442 02:35:50.787966 Loading: *################################################## 10.8 MiB
443 02:35:50.788818 4.9 MiB/s
444 02:35:50.789320 done
445 02:35:50.791840 Bytes transferred = 11354624 (ad4200 hex)
446 02:35:50.792665 Sending with 10 millisecond of delay
448 02:35:55.239266 => tftp 0x83000000 707040/tftp-deploy-r95935d4/ramdisk/ramdisk.cpio.gz.uboot
449 02:35:55.250093 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
450 02:35:55.251017 tftp 0x83000000 707040/tftp-deploy-r95935d4/ramdisk/ramdisk.cpio.gz.uboot
451 02:35:55.251486 link up on port 0, speed 100, full duplex
452 02:35:55.255573 Using ethernet@4a100000 device
453 02:35:55.260991 TFTP from server 192.168.6.2; our IP address is 192.168.6.29
454 02:35:55.264469 Filename '707040/tftp-deploy-r95935d4/ramdisk/ramdisk.cpio.gz.uboot'.
455 02:35:55.269228 Load address: 0x83000000
456 02:35:58.142107 Loading: *################################################## 14.1 MiB
457 02:35:58.142753 4.9 MiB/s
458 02:35:58.143233 done
459 02:35:58.146141 Bytes transferred = 14795178 (e1c1aa hex)
460 02:35:58.146978 Sending with 10 millisecond of delay
462 02:36:00.004166 => setenv initrd_size ${filesize}
463 02:36:00.014982 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
464 02:36:00.015888 setenv initrd_size ${filesize}
465 02:36:00.016722 Sending with 10 millisecond of delay
467 02:36:04.162061 => tftp 0x88000000 707040/tftp-deploy-r95935d4/dtb/am335x-boneblack.dtb
468 02:36:04.172927 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
469 02:36:04.173866 tftp 0x88000000 707040/tftp-deploy-r95935d4/dtb/am335x-boneblack.dtb
470 02:36:04.174339 link up on port 0, speed 100, full duplex
471 02:36:04.177922 Using ethernet@4a100000 device
472 02:36:04.183541 TFTP from server 192.168.6.2; our IP address is 192.168.6.29
473 02:36:04.194233 Filename '707040/tftp-deploy-r95935d4/dtb/am335x-boneblack.dtb'.
474 02:36:04.194759 Load address: 0x88000000
475 02:36:04.204471 Loading: *################################################## 68.7 KiB
476 02:36:04.204984 4.8 MiB/s
477 02:36:04.212863 done
478 02:36:04.213369 Bytes transferred = 70308 (112a4 hex)
479 02:36:04.214093 Sending with 10 millisecond of delay
481 02:36:17.404828 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
482 02:36:17.415706 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
483 02:36:17.416726 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
484 02:36:17.417503 Sending with 10 millisecond of delay
486 02:36:19.756737 => bootz 0x82000000 0x83000000 0x88000000
487 02:36:19.767589 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
488 02:36:19.768250 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:59)
489 02:36:19.769385 bootz 0x82000000 0x83000000 0x88000000
490 02:36:19.769886 Kernel image @ 0x82000000 [ 0x000000 - 0xad4200 ]
491 02:36:19.770439 ## Loading init Ramdisk from Legacy Image at 83000000 ...
492 02:36:19.775190 Image Name:
493 02:36:19.775678 Created: 2024-09-05 2:35:18 UTC
494 02:36:19.780739 Image Type: ARM Linux RAMDisk Image (uncompressed)
495 02:36:19.786314 Data Size: 14795114 Bytes = 14.1 MiB
496 02:36:19.786795 Load Address: 00000000
497 02:36:19.792447 Entry Point: 00000000
498 02:36:19.960846 Verifying Checksum ... OK
499 02:36:19.961374 ## Flattened Device Tree blob at 88000000
500 02:36:19.967326 Booting using the fdt blob at 0x88000000
501 02:36:19.972254 Using Device Tree in place at 88000000, end 880142a3
502 02:36:19.985104
503 02:36:19.985584 Starting kernel ...
504 02:36:19.986036
505 02:36:19.986959 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
506 02:36:19.987606 start: 2.4.4 auto-login-action (timeout 00:03:59) [common]
507 02:36:19.988150 Setting prompt string to ['Linux version [0-9]']
508 02:36:19.988658 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
509 02:36:19.989171 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
510 02:36:20.818502 [ 0.000000] Booting Linux on physical CPU 0x0
511 02:36:20.824482 start: 2.4.4.1 login-action (timeout 00:03:58) [common]
512 02:36:20.825084 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
513 02:36:20.825602 Setting prompt string to []
514 02:36:20.826137 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
515 02:36:20.826643 Using line separator: #'\n'#
516 02:36:20.827094 No login prompt set.
517 02:36:20.827574 Parsing kernel messages
518 02:36:20.828051 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
519 02:36:20.828938 [login-action] Waiting for messages, (timeout 00:03:58)
520 02:36:20.829443 Waiting using forced prompt support (timeout 00:01:59)
521 02:36:20.838592 [ 0.000000] Linux version 6.11.0-rc6 (KernelCI@build-j308072-arm-gcc-12-multi-v7-defconfig-ttl66) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Sep 5 02:11:20 UTC 2024
522 02:36:20.850025 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
523 02:36:20.855764 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
524 02:36:20.861463 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
525 02:36:20.867201 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
526 02:36:20.872915 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
527 02:36:20.879626 [ 0.000000] Memory policy: Data cache writeback
528 02:36:20.880142 [ 0.000000] efi: UEFI not found.
529 02:36:20.888331 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
530 02:36:20.893963 [ 0.000000] Zone ranges:
531 02:36:20.899729 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
532 02:36:20.900237 [ 0.000000] Normal empty
533 02:36:20.905528 [ 0.000000] HighMem empty
534 02:36:20.911260 [ 0.000000] Movable zone start for each node
535 02:36:20.911744 [ 0.000000] Early memory node ranges
536 02:36:20.917053 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
537 02:36:20.927339 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
538 02:36:20.951957 [ 0.000000] CPU: All CPU(s) started in SVC mode.
539 02:36:20.957667 [ 0.000000] AM335X ES2.0 (sgx neon)
540 02:36:20.969336 [ 0.000000] percpu: Embedded 17 pages/cpu s40332 r8192 d21108 u69632
541 02:36:20.987016 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
542 02:36:20.998544 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
543 02:36:21.004293 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
544 02:36:21.010024 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
545 02:36:21.020081 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
546 02:36:21.049047 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
547 02:36:21.054994 <6>[ 0.000000] trace event string verifier disabled
548 02:36:21.055496 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
549 02:36:21.060745 <6>[ 0.000000] rcu: RCU event tracing is enabled.
550 02:36:21.072211 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
551 02:36:21.077927 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
552 02:36:21.085202 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
553 02:36:21.100038 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
554 02:36:21.117343 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
555 02:36:21.124037 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
556 02:36:21.216849 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
557 02:36:21.228322 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
558 02:36:21.235048 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
559 02:36:21.248170 <6>[ 0.019163] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
560 02:36:21.255452 <6>[ 0.033981] Console: colour dummy device 80x30
561 02:36:21.261599 Matched prompt #6: WARNING:
562 02:36:21.262126 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
563 02:36:21.266987 <3>[ 0.038879] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
564 02:36:21.272717 <3>[ 0.045950] This ensures that you still see kernel messages. Please
565 02:36:21.275964 <3>[ 0.052675] update your kernel commandline.
566 02:36:21.316635 <6>[ 0.057281] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
567 02:36:21.322390 <6>[ 0.096165] CPU: Testing write buffer coherency: ok
568 02:36:21.328362 <6>[ 0.101533] CPU0: Spectre v2: using BPIALL workaround
569 02:36:21.328834 <6>[ 0.106997] pid_max: default: 32768 minimum: 301
570 02:36:21.339785 <6>[ 0.112182] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
571 02:36:21.346593 <6>[ 0.120002] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
572 02:36:21.353607 <6>[ 0.129286] CPU0: thread -1, cpu 0, socket -1, mpidr 0
573 02:36:21.361893 <6>[ 0.136130] Setting up static identity map for 0x80300000 - 0x803000ac
574 02:36:21.367697 <6>[ 0.145668] rcu: Hierarchical SRCU implementation.
575 02:36:21.375310 <6>[ 0.150942] rcu: Max phase no-delay instances is 1000.
576 02:36:21.383716 <6>[ 0.161993] EFI services will not be available.
577 02:36:21.389534 <6>[ 0.167233] smp: Bringing up secondary CPUs ...
578 02:36:21.395351 <6>[ 0.172270] smp: Brought up 1 node, 1 CPU
579 02:36:21.401041 <6>[ 0.176668] SMP: Total of 1 processors activated (996.14 BogoMIPS).
580 02:36:21.406950 <6>[ 0.183422] CPU: All CPU(s) started in SVC mode.
581 02:36:21.427272 <6>[ 0.188599] Memory: 407008K/522240K available (16384K kernel code, 2540K rwdata, 6736K rodata, 2048K init, 430K bss, 48028K reserved, 65536K cma-reserved, 0K highmem)
582 02:36:21.427790 <6>[ 0.204842] devtmpfs: initialized
583 02:36:21.449027 <6>[ 0.221493] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
584 02:36:21.460549 <6>[ 0.230061] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
585 02:36:21.466490 <6>[ 0.240497] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
586 02:36:21.477191 <6>[ 0.252784] pinctrl core: initialized pinctrl subsystem
587 02:36:21.486424 <6>[ 0.263470] DMI not present or invalid.
588 02:36:21.494729 <6>[ 0.269221] NET: Registered PF_NETLINK/PF_ROUTE protocol family
589 02:36:21.504225 <6>[ 0.278135] DMA: preallocated 256 KiB pool for atomic coherent allocations
590 02:36:21.519126 <6>[ 0.289399] thermal_sys: Registered thermal governor 'step_wise'
591 02:36:21.519643 <6>[ 0.289642] cpuidle: using governor menu
592 02:36:21.546389 <6>[ 0.324896] No ATAGs?
593 02:36:21.552536 <6>[ 0.327538] hw-breakpoint: debug architecture 0x4 unsupported.
594 02:36:21.562788 <6>[ 0.339554] Serial: AMBA PL011 UART driver
595 02:36:21.604484 <6>[ 0.382960] iommu: Default domain type: Translated
596 02:36:21.613527 <6>[ 0.388190] iommu: DMA domain TLB invalidation policy: strict mode
597 02:36:21.623475 <5>[ 0.400525] SCSI subsystem initialized
598 02:36:21.647428 <6>[ 0.420235] usbcore: registered new interface driver usbfs
599 02:36:21.654262 <6>[ 0.426193] usbcore: registered new interface driver hub
600 02:36:21.654736 <6>[ 0.432015] usbcore: registered new device driver usb
601 02:36:21.660091 <6>[ 0.438518] pps_core: LinuxPPS API ver. 1 registered
602 02:36:21.671531 <6>[ 0.443950] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
603 02:36:21.676669 <6>[ 0.453649] PTP clock support registered
604 02:36:21.701895 <6>[ 0.479642] EDAC MC: Ver: 3.0.0
605 02:36:21.720647 <6>[ 0.496554] scmi_core: SCMI protocol bus registered
606 02:36:21.735683 <6>[ 0.513829] vgaarb: loaded
607 02:36:21.748209 <6>[ 0.526764] clocksource: Switched to clocksource dmtimer
608 02:36:21.784342 <6>[ 0.562537] NET: Registered PF_INET protocol family
609 02:36:21.796908 <6>[ 0.568194] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
610 02:36:21.802651 <6>[ 0.577035] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
611 02:36:21.814135 <6>[ 0.585925] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
612 02:36:21.819901 <6>[ 0.594194] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
613 02:36:21.831511 <6>[ 0.602482] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
614 02:36:21.837442 <6>[ 0.610199] TCP: Hash tables configured (established 4096 bind 4096)
615 02:36:21.843094 <6>[ 0.617118] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
616 02:36:21.849008 <6>[ 0.624127] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
617 02:36:21.856554 <6>[ 0.631737] NET: Registered PF_UNIX/PF_LOCAL protocol family
618 02:36:21.893422 <6>[ 0.666178] RPC: Registered named UNIX socket transport module.
619 02:36:21.893950 <6>[ 0.672606] RPC: Registered udp transport module.
620 02:36:21.899099 <6>[ 0.677739] RPC: Registered tcp transport module.
621 02:36:21.904868 <6>[ 0.682842] RPC: Registered tcp-with-tls transport module.
622 02:36:21.917830 <6>[ 0.688773] RPC: Registered tcp NFSv4.1 backchannel transport module.
623 02:36:21.918319 <6>[ 0.695679] PCI: CLS 0 bytes, default 64
624 02:36:21.925019 <5>[ 0.701446] Initialise system trusted keyrings
625 02:36:21.949968 <6>[ 0.725392] Trying to unpack rootfs image as initramfs...
626 02:36:21.975441 <6>[ 0.747663] workingset: timestamp_bits=30 max_order=17 bucket_order=0
627 02:36:21.980164 <6>[ 0.755143] squashfs: version 4.0 (2009/01/31) Phillip Lougher
628 02:36:22.018694 <5>[ 0.797192] NFS: Registering the id_resolver key type
629 02:36:22.024481 <5>[ 0.802777] Key type id_resolver registered
630 02:36:22.030267 <5>[ 0.807408] Key type id_legacy registered
631 02:36:22.036099 <6>[ 0.811841] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
632 02:36:22.045639 <6>[ 0.819059] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
633 02:36:22.091937 <5>[ 0.870490] Key type asymmetric registered
634 02:36:22.097865 <5>[ 0.875010] Asymmetric key parser 'x509' registered
635 02:36:22.109463 <6>[ 0.880511] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
636 02:36:22.109948 <6>[ 0.888451] io scheduler mq-deadline registered
637 02:36:22.115188 <6>[ 0.893381] io scheduler kyber registered
638 02:36:22.120772 <6>[ 0.897845] io scheduler bfq registered
639 02:36:22.474105 <6>[ 1.248655] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
640 02:36:22.513478 <6>[ 1.291718] msm_serial: driver initialized
641 02:36:22.519591 <6>[ 1.296504] SuperH (H)SCI(F) driver initialized
642 02:36:22.525472 <6>[ 1.301843] STMicroelectronics ASC driver initialized
643 02:36:22.530701 <6>[ 1.307509] STM32 USART driver initialized
644 02:36:22.623667 <6>[ 1.401405] brd: module loaded
645 02:36:22.656033 <6>[ 1.433745] loop: module loaded
646 02:36:22.696536 <6>[ 1.474174] CAN device driver interface
647 02:36:22.703023 <6>[ 1.479422] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
648 02:36:22.708833 <6>[ 1.486300] e1000e: Intel(R) PRO/1000 Network Driver
649 02:36:22.714637 <6>[ 1.491761] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
650 02:36:22.720351 <6>[ 1.498198] igb: Intel(R) Gigabit Ethernet Network Driver
651 02:36:22.728626 <6>[ 1.504023] igb: Copyright (c) 2007-2014 Intel Corporation.
652 02:36:22.740344 <6>[ 1.513115] pegasus: Pegasus/Pegasus II USB Ethernet driver
653 02:36:22.746085 <6>[ 1.519265] usbcore: registered new interface driver pegasus
654 02:36:22.751882 <6>[ 1.525388] usbcore: registered new interface driver asix
655 02:36:22.757666 <6>[ 1.531270] usbcore: registered new interface driver ax88179_178a
656 02:36:22.763439 <6>[ 1.537860] usbcore: registered new interface driver cdc_ether
657 02:36:22.769228 <6>[ 1.544170] usbcore: registered new interface driver smsc75xx
658 02:36:22.774986 <6>[ 1.550406] usbcore: registered new interface driver smsc95xx
659 02:36:22.780865 <6>[ 1.556613] usbcore: registered new interface driver net1080
660 02:36:22.786586 <6>[ 1.562754] usbcore: registered new interface driver cdc_subset
661 02:36:22.792370 <6>[ 1.569177] usbcore: registered new interface driver zaurus
662 02:36:22.800039 <6>[ 1.575247] usbcore: registered new interface driver cdc_ncm
663 02:36:22.809698 <6>[ 1.584565] usbcore: registered new interface driver usb-storage
664 02:36:22.931563 <6>[ 1.708049] i2c_dev: i2c /dev entries driver
665 02:36:22.972303 <5>[ 1.742814] cpuidle: enable-method property 'ti,am3352' found operations
666 02:36:22.978158 <6>[ 1.752377] sdhci: Secure Digital Host Controller Interface driver
667 02:36:22.985796 <6>[ 1.759144] sdhci: Copyright(c) Pierre Ossman
668 02:36:22.992887 <6>[ 1.765438] Synopsys Designware Multimedia Card Interface Driver
669 02:36:22.998022 <6>[ 1.773256] sdhci-pltfm: SDHCI platform and OF driver helper
670 02:36:23.061939 <6>[ 1.836820] ledtrig-cpu: registered to indicate activity on CPUs
671 02:36:23.099865 <6>[ 1.870829] usbcore: registered new interface driver usbhid
672 02:36:23.100435 <6>[ 1.876984] usbhid: USB HID core driver
673 02:36:23.146483 <6>[ 1.922370] NET: Registered PF_INET6 protocol family
674 02:36:23.202889 <6>[ 1.981412] Segment Routing with IPv6
675 02:36:23.208775 <6>[ 1.985557] In-situ OAM (IOAM) with IPv6
676 02:36:23.215489 <6>[ 1.990035] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
677 02:36:23.221222 <6>[ 1.997345] NET: Registered PF_PACKET protocol family
678 02:36:23.227077 <6>[ 2.002833] can: controller area network core
679 02:36:23.232831 <6>[ 2.007713] NET: Registered PF_CAN protocol family
680 02:36:23.233314 <6>[ 2.012915] can: raw protocol
681 02:36:23.238615 <6>[ 2.016237] can: broadcast manager protocol
682 02:36:23.245106 <6>[ 2.020836] can: netlink gateway - max_hops=1
683 02:36:23.251245 <5>[ 2.026347] Key type dns_resolver registered
684 02:36:23.257506 <6>[ 2.031419] ThumbEE CPU extension supported.
685 02:36:23.258007 <5>[ 2.036106] Registering SWP/SWPB emulation handler
686 02:36:23.267280 <3>[ 2.041795] omap_voltage_late_init: Voltage driver support not added
687 02:36:23.341851 <5>[ 2.117872] Loading compiled-in X.509 certificates
688 02:36:23.499884 <6>[ 2.265462] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
689 02:36:23.507108 <6>[ 2.282106] pinctrl-single 44e10800.pinmux: 142 pins, size 568
690 02:36:23.533215 <3>[ 2.305618] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
691 02:36:23.617618 <3>[ 2.390029] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
692 02:36:23.710630 <6>[ 2.487403] OMAP GPIO hardware version 0.1
693 02:36:23.731050 <6>[ 2.505879] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
694 02:36:23.813905 <4>[ 2.588304] at24 2-0054: supply vcc not found, using dummy regulator
695 02:36:23.871713 <4>[ 2.646203] at24 2-0055: supply vcc not found, using dummy regulator
696 02:36:23.920024 <4>[ 2.694489] at24 2-0056: supply vcc not found, using dummy regulator
697 02:36:23.956132 <4>[ 2.730609] at24 2-0057: supply vcc not found, using dummy regulator
698 02:36:24.002450 <6>[ 2.777734] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
699 02:36:24.071667 <3>[ 2.842932] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
700 02:36:24.096057 <6>[ 2.863640] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
701 02:36:24.126919 <4>[ 2.900175] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
702 02:36:24.174485 <4>[ 2.947726] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
703 02:36:24.231646 <6>[ 3.006340] omap_rng 48310000.rng: Random Number Generator ver. 20
704 02:36:24.254752 <5>[ 3.032260] random: crng init done
705 02:36:24.364158 <6>[ 3.137292] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
706 02:36:25.005600 <6>[ 3.782386] Freeing initrd memory: 14452K
707 02:36:25.046703 <6>[ 3.819220] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
708 02:36:25.052426 <6>[ 3.829417] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
709 02:36:25.060870 <6>[ 3.836683] cpsw-switch 4a100000.switch: ALE Table size 1024
710 02:36:25.072406 <6>[ 3.843153] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
711 02:36:25.083947 <6>[ 3.851283] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
712 02:36:25.091341 <6>[ 3.862918] cpsw-switch 4a100000.switch: Detected MACID = c8:a0:30:ab:e7:47
713 02:36:25.101074 <5>[ 3.871949] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
714 02:36:25.128598 <3>[ 3.901497] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
715 02:36:25.134342 <6>[ 3.910070] edma 49000000.dma: TI EDMA DMA engine driver
716 02:36:25.205165 <3>[ 3.977272] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
717 02:36:25.218718 <6>[ 3.991482] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 counters available
718 02:36:25.237354 <3>[ 4.013301] l3-aon-clkctrl:0000:0: failed to disable
719 02:36:25.274928 <6>[ 4.047671] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
720 02:36:25.280471 <6>[ 4.057090] printk: legacy console [ttyS0] enabled
721 02:36:25.286170 <6>[ 4.057090] printk: legacy console [ttyS0] enabled
722 02:36:25.291937 <6>[ 4.067404] printk: legacy bootconsole [omap8250] disabled
723 02:36:25.297684 <6>[ 4.067404] printk: legacy bootconsole [omap8250] disabled
724 02:36:25.355699 <4>[ 4.127511] tps65217-pmic: Failed to locate of_node [id: -1]
725 02:36:25.359308 <4>[ 4.134895] tps65217-bl: Failed to locate of_node [id: -1]
726 02:36:25.375312 <6>[ 4.154115] tps65217 0-0024: TPS65217 ID 0xe version 1.2
727 02:36:25.393709 <6>[ 4.161053] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
728 02:36:25.405363 <6>[ 4.174742] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
729 02:36:25.411038 <6>[ 4.186582] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
730 02:36:25.433336 <6>[ 4.206349] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
731 02:36:25.439176 <6>[ 4.215588] sdhci-omap 48060000.mmc: Got CD GPIO
732 02:36:25.447222 <4>[ 4.220749] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
733 02:36:25.461941 <4>[ 4.234096] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
734 02:36:25.468437 <4>[ 4.243027] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
735 02:36:25.478287 <4>[ 4.251816] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
736 02:36:25.548036 <6>[ 4.322175] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
737 02:36:25.606260 <6>[ 4.379589] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
738 02:36:25.644961 <6>[ 4.417357] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
739 02:36:25.651685 <6>[ 4.426265] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
740 02:36:25.694804 <6>[ 4.463634] mmc1: new high speed MMC card at address 0001
741 02:36:25.695340 <6>[ 4.471402] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
742 02:36:25.703277 <6>[ 4.480496] mmcblk1: p1 p2
743 02:36:25.711496 <6>[ 4.485199] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
744 02:36:25.716774 <6>[ 4.492989] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
745 02:36:25.726272 <6>[ 4.501200] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
746 02:36:25.747421 <6>[ 4.517991] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
747 02:36:25.764024 <6>[ 4.541423] mmc0: new SD card at address e624
748 02:36:25.772521 <6>[ 4.547432] mmcblk0: mmc0:e624 SU512 484 MiB
749 02:36:25.776384 <6>[ 4.554965] mmcblk0: p1
750 02:36:27.835057 <6>[ 6.607774] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
751 02:36:35.368261 <5>[ 6.656832] Sending DHCP requests ..., OK
752 02:36:35.379461 <6>[ 14.151360] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.29
753 02:36:35.380128 <6>[ 14.159519] IP-Config: Complete:
754 02:36:35.390689 <6>[ 14.163055] device=eth0, hwaddr=c8:a0:30:ab:e7:47, ipaddr=192.168.6.29, mask=255.255.255.0, gw=192.168.6.1
755 02:36:35.396472 <6>[ 14.173571] host=192.168.6.29, domain=, nis-domain=(none)
756 02:36:35.408722 <6>[ 14.179776] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
757 02:36:35.409202 <6>[ 14.179807] nameserver0=10.255.253.1
758 02:36:35.414878 <6>[ 14.192332] clk: Disabling unused clocks
759 02:36:35.420691 <6>[ 14.197045] PM: genpd: Disabling unused power domains
760 02:36:35.440225 <6>[ 14.215676] Freeing unused kernel image (initmem) memory: 2048K
761 02:36:35.447600 <6>[ 14.225391] Run /init as init process
762 02:36:35.473031 Loading, please wait...
763 02:36:35.547675 Starting systemd-udevd version 252.22-1~deb12u1
764 02:36:38.492257 <4>[ 17.263816] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
765 02:36:38.706810 <4>[ 17.478407] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
766 02:36:38.846896 <6>[ 17.625916] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
767 02:36:38.857682 <6>[ 17.631742] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
768 02:36:39.009788 <6>[ 17.787446] hub 1-0:1.0: USB hub found
769 02:36:39.040283 <6>[ 17.817677] hub 1-0:1.0: 1 port detected
770 02:36:39.325649 <6>[ 18.102835] tda998x 0-0070: found TDA19988
771 02:36:42.118718 Begin: Loading essential drivers ... done.
772 02:36:42.124499 Begin: Running /scripts/init-premount ... done.
773 02:36:42.130088 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
774 02:36:42.137568 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
775 02:36:42.143383 Device /sys/class/net/eth0 found
776 02:36:42.143877 done.
777 02:36:42.199366 Begin: Waiting up to 180 secs for any network device to become available ... done.
778 02:36:42.260806 IP-Config: eth0 hardware address c8:a0:30:ab:e7:47 mtu 1500 DHCP
779 02:36:42.340489 IP-Config: eth0 guessed broadcast address 192.168.6.255
780 02:36:42.346127 IP-Config: eth0 complete (dhcp from 192.168.6.1):
781 02:36:42.351739 address: 192.168.6.29 broadcast: 192.168.6.255 netmask: 255.255.255.0
782 02:36:42.360602 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
783 02:36:42.366319 rootserver: 192.168.6.1 rootpath:
784 02:36:42.366793 filename :
785 02:36:42.489365 done.
786 02:36:42.498433 Begin: Running /scripts/nfs-bottom ... done.
787 02:36:42.560743 Begin: Running /scripts/init-bottom ... done.
788 02:36:43.758496 <30>[ 22.533407] systemd[1]: System time before build time, advancing clock.
789 02:36:43.928960 <30>[ 22.677603] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
790 02:36:43.937591 <30>[ 22.714278] systemd[1]: Detected architecture arm.
791 02:36:43.951564
792 02:36:43.952282 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
793 02:36:43.952776
794 02:36:43.991805 <30>[ 22.767215] systemd[1]: Hostname set to <debian-bookworm-armhf>.
795 02:36:46.224930 <30>[ 24.999373] systemd[1]: Queued start job for default target graphical.target.
796 02:36:46.241689 <30>[ 25.014081] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
797 02:36:46.249390 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
798 02:36:46.288082 <30>[ 25.059549] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
799 02:36:46.295531 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
800 02:36:46.329841 <30>[ 25.102695] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
801 02:36:46.342768 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
802 02:36:46.376144 <30>[ 25.149024] systemd[1]: Created slice user.slice - User and Session Slice.
803 02:36:46.382899 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
804 02:36:46.418452 <30>[ 25.189064] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
805 02:36:46.431119 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
806 02:36:46.465128 <30>[ 25.237981] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
807 02:36:46.476189 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
808 02:36:46.515815 <30>[ 25.277824] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
809 02:36:46.522280 <30>[ 25.298327] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
810 02:36:46.530809 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
811 02:36:46.566961 <30>[ 25.338183] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
812 02:36:46.574233 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
813 02:36:46.605296 <30>[ 25.377467] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
814 02:36:46.612654 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
815 02:36:46.644640 <30>[ 25.417741] systemd[1]: Reached target paths.target - Path Units.
816 02:36:46.649670 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
817 02:36:46.687081 <30>[ 25.458404] systemd[1]: Reached target remote-fs.target - Remote File Systems.
818 02:36:46.694388 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
819 02:36:46.724112 <30>[ 25.497329] systemd[1]: Reached target slices.target - Slice Units.
820 02:36:46.729458 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
821 02:36:46.765600 <30>[ 25.538184] systemd[1]: Reached target swap.target - Swaps.
822 02:36:46.769612 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
823 02:36:46.804994 <30>[ 25.577574] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
824 02:36:46.812934 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
825 02:36:46.845708 <30>[ 25.618326] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
826 02:36:46.853897 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
827 02:36:46.943913 <30>[ 25.712036] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
828 02:36:46.956587 <30>[ 25.729675] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
829 02:36:46.965044 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
830 02:36:46.996650 <30>[ 25.769178] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
831 02:36:47.004041 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
832 02:36:47.037807 <30>[ 25.810459] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
833 02:36:47.045945 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
834 02:36:47.080936 <30>[ 25.854502] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
835 02:36:47.094314 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
836 02:36:47.126035 <30>[ 25.898908] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
837 02:36:47.134612 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
838 02:36:47.171770 <30>[ 25.938583] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
839 02:36:47.188482 <30>[ 25.955209] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
840 02:36:47.225393 <30>[ 25.999185] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
841 02:36:47.244029 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
842 02:36:47.314243 <30>[ 26.088002] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
843 02:36:47.334955 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
844 02:36:47.405033 <30>[ 26.177694] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
845 02:36:47.432603 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
846 02:36:47.498161 <30>[ 26.271452] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
847 02:36:47.523190 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
848 02:36:47.587782 <30>[ 26.361375] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
849 02:36:47.613318 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
850 02:36:47.677274 <30>[ 26.451401] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
851 02:36:47.695401 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
852 02:36:47.768511 <30>[ 26.541417] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
853 02:36:47.803150 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
854 02:36:47.867043 <30>[ 26.641138] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
855 02:36:47.894729 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
856 02:36:47.943894 <30>[ 26.717972] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
857 02:36:47.956431 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
858 02:36:48.000984 <28>[ 26.769055] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
859 02:36:48.009468 <28>[ 26.782680] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
860 02:36:48.048948 <30>[ 26.823444] systemd[1]: Starting systemd-journald.service - Journal Service...
861 02:36:48.072602 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
862 02:36:48.154304 <30>[ 26.928070] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
863 02:36:48.177661 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
864 02:36:48.266234 <30>[ 27.040179] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
865 02:36:48.304612 Starting [0;1;39msystemd-network-g… units from Kernel command line...
866 02:36:48.367469 <30>[ 27.139921] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
867 02:36:48.411249 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
868 02:36:48.481713 <30>[ 27.254929] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
869 02:36:48.523778 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
870 02:36:48.596241 <30>[ 27.370297] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
871 02:36:48.635530 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
872 02:36:48.664509 <30>[ 27.438459] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
873 02:36:48.693512 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
874 02:36:48.726662 <30>[ 27.499489] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
875 02:36:48.749285 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
876 02:36:48.901353 <30>[ 27.676038] systemd[1]: Started systemd-journald.service - Journal Service.
877 02:36:48.923513 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
878 02:36:48.974215 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
879 02:36:49.014275 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
880 02:36:49.034107 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
881 02:36:49.054514 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
882 02:36:49.089699 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
883 02:36:49.108833 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
884 02:36:49.126709 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
885 02:36:49.164234 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
886 02:36:49.196460 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
887 02:36:49.218739 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
888 02:36:49.283633 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
889 02:36:49.328951 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
890 02:36:49.416206 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
891 02:36:49.518590 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
892 02:36:49.635914 <46>[ 28.407493] systemd-journald[165]: Received client request to flush runtime journal.
893 02:36:49.643450 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
894 02:36:49.758420 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
895 02:36:49.838870 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
896 02:36:50.646508 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
897 02:36:50.815341 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
898 02:36:50.905451 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
899 02:36:51.466577 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
900 02:36:51.559592 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
901 02:36:51.595475 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
902 02:36:51.633346 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
903 02:36:51.704260 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
904 02:36:51.758082 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
905 02:36:52.670592 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
906 02:36:52.755207 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
907 02:36:53.009975 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
908 02:36:53.134358 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
909 02:36:53.219683 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
910 02:36:55.271165 [[0m[0;31m* [0m] (1 of 5) Job systemd-update-utmp.service/start running (9s / no limit)
911 02:36:55.464869 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
912 02:36:55.495783 [K<5>[ 34.270038] cfg80211: Loading compiled-in X.509 certificates for regulatory database
913 02:36:55.724550 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
914 02:36:56.795816 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
915 02:36:57.102018 <5>[ 35.878254] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
916 02:36:57.148114 <5>[ 35.922935] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
917 02:36:57.193583 <4>[ 35.967757] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
918 02:36:57.199544 <6>[ 35.976854] cfg80211: failed to load regulatory.db
919 02:36:57.819344 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
920 02:36:57.915660 <46>[ 36.680879] systemd-journald[165]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
921 02:36:58.080794 <46>[ 36.847958] systemd-journald[165]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
922 02:36:58.180438 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
923 02:37:07.089600 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
924 02:37:07.124046 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
925 02:37:07.158166 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
926 02:37:07.194561 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
927 02:37:07.289412 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
928 02:37:07.368230 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
929 02:37:07.423576 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
930 02:37:07.454139 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
931 02:37:07.481736 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
932 02:37:07.520465 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
933 02:37:07.559763 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
934 02:37:07.608449 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
935 02:37:07.678102 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
936 02:37:07.707577 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
937 02:37:07.755938 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
938 02:37:07.786236 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
939 02:37:07.822077 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
940 02:37:07.858220 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
941 02:37:07.897655 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
942 02:37:07.939380 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
943 02:37:07.981989 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
944 02:37:07.994560 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
945 02:37:08.012073 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
946 02:37:08.068582 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
947 02:37:08.144816 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
948 02:37:08.246445 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
949 02:37:08.369097 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
950 02:37:08.445467 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
951 02:37:08.497969 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
952 02:37:08.522207 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
953 02:37:08.690267 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
954 02:37:08.728147 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
955 02:37:08.823935 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
956 02:37:08.885809 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
957 02:37:08.914557 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
958 02:37:09.029345 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
959 02:37:09.392834 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
960 02:37:09.454109 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
961 02:37:09.491108 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
962 02:37:09.587642 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
963 02:37:09.759811 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
964 02:37:09.923822
965 02:37:09.924468 Debian GNU/Linux 12worm-armhf login: root (automatic login)
966 02:37:09.927025
967 02:37:10.251429 Linux debian-bookworm-armhf 6.11.0-rc6 #1 SMP Thu Sep 5 02:11:20 UTC 2024 armv7l
968 02:37:10.252048
969 02:37:10.257051 The programs included with the Debian GNU/Linux system are free software;
970 02:37:10.262700 the exact distribution terms for each program are described in the
971 02:37:10.268276 individual files in /usr/share/doc/*/copyright.
972 02:37:10.268754
973 02:37:10.276204 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
974 02:37:10.276694 permitted by applicable law.
975 02:37:15.091522 Unable to match end of the kernel message
977 02:37:15.093148 Setting prompt string to ['/ #']
978 02:37:15.093735 end: 2.4.4.1 login-action (duration 00:00:54) [common]
980 02:37:15.095129 end: 2.4.4 auto-login-action (duration 00:00:55) [common]
981 02:37:15.095688 start: 2.4.5 expect-shell-connection (timeout 00:03:04) [common]
982 02:37:15.096193 Setting prompt string to ['/ #']
983 02:37:15.096725 Forcing a shell prompt, looking for ['/ #']
985 02:37:15.147756 / #
986 02:37:15.148457 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
987 02:37:15.148910 Waiting using forced prompt support (timeout 00:02:30)
988 02:37:15.152175
989 02:37:15.160025 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
990 02:37:15.160597 start: 2.4.6 export-device-env (timeout 00:03:04) [common]
991 02:37:15.161055 Sending with 10 millisecond of delay
993 02:37:20.155895 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4'
994 02:37:20.166864 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/707040/extract-nfsrootfs-biwq1ac4'
995 02:37:20.170187 Sending with 10 millisecond of delay
997 02:37:22.267488 / # export NFS_SERVER_IP='192.168.6.2'
998 02:37:22.278380 export NFS_SERVER_IP='192.168.6.2'
999 02:37:22.279470 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1000 02:37:22.280066 end: 2.4 uboot-commands (duration 00:02:04) [common]
1001 02:37:22.280646 end: 2 uboot-action (duration 00:02:04) [common]
1002 02:37:22.281207 start: 3 lava-test-retry (timeout 00:06:47) [common]
1003 02:37:22.281773 start: 3.1 lava-test-shell (timeout 00:06:47) [common]
1004 02:37:22.282224 Using namespace: common
1006 02:37:22.383352 / # #
1007 02:37:22.383926 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1008 02:37:22.388535 #
1009 02:37:22.394423 Using /lava-707040
1011 02:37:22.495505 / # export SHELL=/bin/bash
1012 02:37:22.499866 export SHELL=/bin/bash
1014 02:37:22.607959 / # . /lava-707040/environment
1015 02:37:22.612210 . /lava-707040/environment
1017 02:37:22.725609 / # /lava-707040/bin/lava-test-runner /lava-707040/0
1018 02:37:22.726171 Test shell timeout: 10s (minimum of the action and connection timeout)
1019 02:37:22.730780 /lava-707040/bin/lava-test-runner /lava-707040/0
1020 02:37:23.150684 + export TESTRUN_ID=0_timesync-off
1021 02:37:23.158540 + TESTRUN_ID=0_timesync-off
1022 02:37:23.158992 + cd /lava-707040/0/tests/0_timesync-off
1023 02:37:23.159412 ++ cat uuid
1024 02:37:23.173431 + UUID=707040_1.6.2.4.1
1025 02:37:23.173868 + set +x
1026 02:37:23.182040 <LAVA_SIGNAL_STARTRUN 0_timesync-off 707040_1.6.2.4.1>
1027 02:37:23.182473 + systemctl stop systemd-timesyncd
1028 02:37:23.183153 Received signal: <STARTRUN> 0_timesync-off 707040_1.6.2.4.1
1029 02:37:23.183577 Starting test lava.0_timesync-off (707040_1.6.2.4.1)
1030 02:37:23.184104 Skipping test definition patterns.
1031 02:37:23.498245 + set +x
1032 02:37:23.498732 <LAVA_SIGNAL_ENDRUN 0_timesync-off 707040_1.6.2.4.1>
1033 02:37:23.499398 Received signal: <ENDRUN> 0_timesync-off 707040_1.6.2.4.1
1034 02:37:23.499907 Ending use of test pattern.
1035 02:37:23.500380 Ending test lava.0_timesync-off (707040_1.6.2.4.1), duration 0.32
1037 02:37:23.666562 + export TESTRUN_ID=1_kselftest-dt
1038 02:37:23.674587 + TESTRUN_ID=1_kselftest-dt
1039 02:37:23.675036 + cd /lava-707040/0/tests/1_kselftest-dt
1040 02:37:23.675453 ++ cat uuid
1041 02:37:23.689268 + UUID=707040_1.6.2.4.5
1042 02:37:23.689703 + set +x
1043 02:37:23.694785 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 707040_1.6.2.4.5>
1044 02:37:23.695214 + cd ./automated/linux/kselftest/
1045 02:37:23.695871 Received signal: <STARTRUN> 1_kselftest-dt 707040_1.6.2.4.5
1046 02:37:23.696335 Starting test lava.1_kselftest-dt (707040_1.6.2.4.5)
1047 02:37:23.696816 Skipping test definition patterns.
1048 02:37:23.722975 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1049 02:37:23.825175 INFO: install_deps skipped
1050 02:37:24.279264 --2024-09-05 02:37:24-- http://storage.kernelci.org/mainline/master/v6.11-rc6-70-gc763c43396883/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1051 02:37:24.304192 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1052 02:37:24.448778 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1053 02:37:24.591410 HTTP request sent, awaiting response... 200 OK
1054 02:37:24.591876 Length: 3834120 (3.7M) [application/octet-stream]
1055 02:37:24.596820 Saving to: 'kselftest_armhf.tar.gz'
1056 02:37:24.597248
1057 02:37:27.343392
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 47.54K 169KB/s
kselftest_armhf.tar 5%[> ] 218.67K 383KB/s
kselftest_armhf.tar 19%[==> ] 740.39K 873KB/s
kselftest_armhf.tar 26%[====> ] 983.67K 914KB/s
kselftest_armhf.tar 67%[============> ] 2.48M 1.95MB/s
kselftest_armhf.tar 93%[=================> ] 3.41M 2.27MB/s
kselftest_armhf.tar 98%[==================> ] 3.62M 1.67MB/s
kselftest_armhf.tar 99%[==================> ] 3.62M 1.48MB/s
kselftest_armhf.tar 99%[==================> ] 3.64M 1.33MB/s
kselftest_armhf.tar 100%[===================>] 3.66M 1.33MB/s in 2.7s
1058 02:37:27.344041
1059 02:37:27.860750 2024-09-05 02:37:27 (1.33 MB/s) - 'kselftest_armhf.tar.gz' saved [3834120/3834120]
1060 02:37:27.861349
1061 02:37:38.900634 skiplist:
1062 02:37:38.901269 ========================================
1063 02:37:38.906062 ========================================
1064 02:37:39.009059 dt:test_unprobed_devices.sh
1065 02:37:39.038890 ============== Tests to run ===============
1066 02:37:39.047144 dt:test_unprobed_devices.sh
1067 02:37:39.051215 ===========End Tests to run ===============
1068 02:37:39.058882 shardfile-dt pass
1069 02:37:39.278325 <12>[ 78.057474] kselftest: Running tests in dt
1070 02:37:39.305457 TAP version 13
1071 02:37:39.328640 1..1
1072 02:37:39.380525 # timeout set to 45
1073 02:37:39.381008 # selftests: dt: test_unprobed_devices.sh
1074 02:37:40.203327 # TAP version 13
1075 02:37:52.142537 # 1..255
1076 02:37:52.302275 # ok 1 / # SKIP
1077 02:37:52.323338 # ok 2 /clk_mcasp0
1078 02:37:52.399127 # ok 3 /clk_mcasp0_fixed # SKIP
1079 02:37:52.464923 # ok 4 /cpus/cpu@0 # SKIP
1080 02:37:52.536564 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1081 02:37:52.554331 # ok 6 /fixedregulator0
1082 02:37:52.574251 # ok 7 /leds
1083 02:37:52.594967 # ok 8 /ocp
1084 02:37:52.618324 # ok 9 /ocp/interconnect@44c00000
1085 02:37:52.640840 # ok 10 /ocp/interconnect@44c00000/segment@0
1086 02:37:52.663127 # ok 11 /ocp/interconnect@44c00000/segment@100000
1087 02:37:52.688627 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1088 02:37:52.761104 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1089 02:37:52.784511 # ok 14 /ocp/interconnect@44c00000/segment@200000
1090 02:37:52.806693 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1091 02:37:52.908365 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1092 02:37:52.980880 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1093 02:37:53.043652 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1094 02:37:53.119904 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1095 02:37:53.186880 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1096 02:37:53.259041 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1097 02:37:53.328806 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1098 02:37:53.398645 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1099 02:37:53.462159 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1100 02:37:53.534857 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1101 02:37:53.603956 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1102 02:37:53.669462 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1103 02:37:53.744973 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1104 02:37:53.810853 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1105 02:37:53.883823 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1106 02:37:53.954626 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1107 02:37:54.018594 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1108 02:37:54.094738 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1109 02:37:54.163869 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1110 02:37:54.227623 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1111 02:37:54.303758 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1112 02:37:54.372461 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1113 02:37:54.441697 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1114 02:37:54.505930 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1115 02:37:54.583943 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1116 02:37:54.652128 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1117 02:37:54.725383 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1118 02:37:54.793714 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1119 02:37:54.863711 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1120 02:37:54.934037 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1121 02:37:55.003968 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1122 02:37:55.072544 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1123 02:37:55.143320 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1124 02:37:55.212275 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1125 02:37:55.283809 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1126 02:37:55.346422 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1127 02:37:55.423497 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1128 02:37:55.486318 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1129 02:37:55.562875 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1130 02:37:55.632100 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1131 02:37:55.702885 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1132 02:37:55.773598 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1133 02:37:55.840763 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1134 02:37:55.912929 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1135 02:37:55.976911 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1136 02:37:56.052962 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1137 02:37:56.122993 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1138 02:37:56.194984 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1139 02:37:56.259490 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1140 02:37:56.334461 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1141 02:37:56.403249 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1142 02:37:56.476038 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1143 02:37:56.545436 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1144 02:37:56.616924 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1145 02:37:56.690179 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1146 02:37:56.758551 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1147 02:37:56.830491 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1148 02:37:56.897436 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1149 02:37:56.969994 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1150 02:37:57.039853 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1151 02:37:57.110681 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1152 02:37:57.174049 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1153 02:37:57.250931 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1154 02:37:57.317616 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1155 02:37:57.387876 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1156 02:37:57.460299 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1157 02:37:57.530050 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1158 02:37:57.597792 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1159 02:37:57.671021 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1160 02:37:57.741418 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1161 02:37:57.804504 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1162 02:37:57.878947 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1163 02:37:57.951052 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1164 02:37:58.015168 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1165 02:37:58.093379 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1166 02:37:58.161146 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1167 02:37:58.226709 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1168 02:37:58.303830 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1169 02:37:58.373084 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1170 02:37:58.396806 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1171 02:37:58.413927 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1172 02:37:58.442931 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1173 02:37:58.464388 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1174 02:37:58.489142 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1175 02:37:58.506929 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1176 02:37:58.539136 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1177 02:37:58.558794 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1178 02:37:58.655334 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1179 02:37:58.682151 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1180 02:37:58.710618 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1181 02:37:58.731483 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1182 02:37:58.831003 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1183 02:37:58.910697 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1184 02:37:58.980644 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1185 02:37:59.051685 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1186 02:37:59.115972 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1187 02:37:59.200714 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1188 02:37:59.271124 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1189 02:37:59.338769 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1190 02:37:59.412431 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1191 02:37:59.476307 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1192 02:37:59.553266 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1193 02:37:59.624995 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1194 02:37:59.694153 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1195 02:37:59.768540 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1196 02:37:59.833689 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1197 02:37:59.912252 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1198 02:37:59.932461 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1199 02:38:00.000382 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1200 02:38:00.069855 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1201 02:38:00.141074 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1202 02:38:00.155605 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1203 02:38:00.226770 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1204 02:38:00.254761 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1205 02:38:00.325586 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1206 02:38:00.350376 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1207 02:38:00.366388 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1208 02:38:00.393988 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1209 02:38:00.419419 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1210 02:38:00.434956 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1211 02:38:00.466756 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1212 02:38:00.484299 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1213 02:38:00.513638 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1214 02:38:00.538406 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1215 02:38:00.602440 # not ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1216 02:38:00.676945 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1217 02:38:00.699546 # ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1218 02:38:00.766490 # not ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/adc
1219 02:38:00.835834 # not ok 144 /ocp/interconnect@44c00000/segment@200000/target-module@d000/tscadc@0/tsc
1220 02:38:00.938462 # not ok 145 /ocp/interconnect@47c00000
1221 02:38:01.000361 # not ok 146 /ocp/interconnect@47c00000/segment@0
1222 02:38:01.020910 # ok 147 /ocp/interconnect@48000000
1223 02:38:01.043520 # ok 148 /ocp/interconnect@48000000/segment@0
1224 02:38:01.069956 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@22000
1225 02:38:01.090999 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@24000
1226 02:38:01.120871 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@2a000
1227 02:38:01.136118 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@30000
1228 02:38:01.164402 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000
1229 02:38:01.187663 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1230 02:38:01.211115 # ok 155 /ocp/interconnect@48000000/segment@0/target-module@3c000
1231 02:38:01.273067 # not ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000
1232 02:38:01.344386 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1233 02:38:01.371573 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000
1234 02:38:01.389499 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1235 02:38:01.417079 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000
1236 02:38:01.442072 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1237 02:38:01.457268 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000
1238 02:38:01.486230 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1239 02:38:01.509686 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000
1240 02:38:01.528445 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1241 02:38:01.555635 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000
1242 02:38:01.574954 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1243 02:38:01.601704 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000
1244 02:38:01.620591 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1245 02:38:01.644859 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000
1246 02:38:01.671811 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1247 02:38:01.691127 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@80000
1248 02:38:01.716742 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@c8000
1249 02:38:01.742667 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1250 02:38:01.757716 # ok 175 /ocp/interconnect@48000000/segment@0/target-module@ca000
1251 02:38:01.786867 # ok 176 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1252 02:38:01.807065 # ok 177 /ocp/interconnect@48000000/segment@100000
1253 02:38:01.828392 # ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1254 02:38:01.856122 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1255 02:38:01.926734 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1256 02:38:01.994436 # not ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1257 02:38:02.064356 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1258 02:38:02.134449 # not ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1259 02:38:02.148334 # ok 184 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 02:38:02.178376 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 02:38:02.193713 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 02:38:02.221718 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 02:38:02.239636 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 02:38:02.268288 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 02:38:02.290710 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 02:38:02.312691 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 02:38:02.331787 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 02:38:02.361716 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 02:38:02.377452 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 02:38:02.407238 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 02:38:02.429560 # ok 196 /ocp/interconnect@48000000/segment@200000
1272 02:38:02.449699 # ok 197 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 02:38:02.520103 # ok 198 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 02:38:02.542598 # ok 199 /ocp/interconnect@48000000/segment@300000
1275 02:38:02.566944 # ok 200 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 02:38:02.592096 # ok 201 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 02:38:02.607915 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 02:38:02.636962 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 02:38:02.661749 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 02:38:02.676800 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 02:38:02.751211 # not ok 206 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 02:38:02.773937 # ok 207 /ocp/interconnect@4a000000
1283 02:38:02.789226 # ok 208 /ocp/interconnect@4a000000/segment@0
1284 02:38:02.816722 # ok 209 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 02:38:02.838761 # ok 210 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 02:38:02.864136 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 02:38:02.891406 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 02:38:02.957216 # not ok 213 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 02:38:03.060435 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 02:38:03.135200 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 02:38:03.235862 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 02:38:03.301312 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 02:38:03.371422 # not ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 02:38:03.469156 # not ok 219 /ocp/interconnect@4b140000
1295 02:38:03.533466 # not ok 220 /ocp/interconnect@4b140000/segment@0
1296 02:38:03.607163 # ok 221 /ocp/interrupt-controller@48200000 # SKIP
1297 02:38:03.626377 # ok 222 /ocp/target-module@40300000
1298 02:38:03.651854 # ok 223 /ocp/target-module@40300000/sram@0
1299 02:38:03.720258 # ok 224 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 02:38:03.793529 # ok 225 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 02:38:03.815062 # ok 226 /ocp/target-module@47400000
1302 02:38:03.836304 # ok 227 /ocp/target-module@47400000/dma-controller@2000
1303 02:38:03.857783 # ok 228 /ocp/target-module@47400000/usb-phy@1300
1304 02:38:03.877365 # ok 229 /ocp/target-module@47400000/usb-phy@1b00
1305 02:38:03.902994 # ok 230 /ocp/target-module@47400000/usb@1400
1306 02:38:03.923744 # ok 231 /ocp/target-module@47400000/usb@1800
1307 02:38:03.945357 # ok 232 /ocp/target-module@47810000
1308 02:38:03.966674 # ok 233 /ocp/target-module@49000000
1309 02:38:03.986495 # ok 234 /ocp/target-module@49000000/dma@0
1310 02:38:04.005355 # ok 235 /ocp/target-module@49800000
1311 02:38:04.029022 # ok 236 /ocp/target-module@49800000/dma@0
1312 02:38:04.054262 # ok 237 /ocp/target-module@49900000
1313 02:38:04.077127 # ok 238 /ocp/target-module@49900000/dma@0
1314 02:38:04.095773 # ok 239 /ocp/target-module@49a00000
1315 02:38:04.116466 # ok 240 /ocp/target-module@49a00000/dma@0
1316 02:38:04.143253 # ok 241 /ocp/target-module@4c000000
1317 02:38:04.210885 # not ok 242 /ocp/target-module@4c000000/emif@0
1318 02:38:04.231765 # ok 243 /ocp/target-module@50000000
1319 02:38:04.248970 # ok 244 /ocp/target-module@53100000
1320 02:38:04.322633 # not ok 245 /ocp/target-module@53100000/sham@0
1321 02:38:04.344432 # ok 246 /ocp/target-module@53500000
1322 02:38:04.413269 # not ok 247 /ocp/target-module@53500000/aes@0
1323 02:38:04.435643 # ok 248 /ocp/target-module@56000000
1324 02:38:04.530165 # ok 249 /ocp/target-module@56000000/gpu@0 # SKIP
1325 02:38:04.596994 # ok 250 /opp-table # SKIP
1326 02:38:04.664278 # ok 251 /soc # SKIP
1327 02:38:04.684286 # ok 252 /sound
1328 02:38:04.711643 # ok 253 /target-module@4b000000
1329 02:38:04.735388 # ok 254 /target-module@4b000000/target-module@140000
1330 02:38:04.751414 # ok 255 /target-module@4b000000/target-module@140000/pmu@0
1331 02:38:04.759456 # # Totals: pass:118 fail:29 xfail:0 xpass:0 skip:108 error:0
1332 02:38:04.766493 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 02:38:06.938003 dt_test_unprobed_devices_sh_ skip
1334 02:38:06.943495 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 02:38:06.949097 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 02:38:06.949379 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 02:38:06.958011 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 02:38:06.958403 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 02:38:06.963644 dt_test_unprobed_devices_sh_leds pass
1340 02:38:06.969225 dt_test_unprobed_devices_sh_ocp pass
1341 02:38:06.974798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 02:38:06.980413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 02:38:06.986087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 02:38:06.991537 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 02:38:07.002761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 02:38:07.008346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 02:38:07.014063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 02:38:07.025195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 02:38:07.030924 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 02:38:07.041949 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 02:38:07.053186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 02:38:07.064372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 02:38:07.075643 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 02:38:07.081428 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 02:38:07.092545 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 02:38:07.103731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 02:38:07.114920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 02:38:07.126231 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 02:38:07.131767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 02:38:07.142913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 02:38:07.154079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 02:38:07.165318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 02:38:07.176484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 02:38:07.182118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 02:38:07.193312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 02:38:07.204453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 02:38:07.215634 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 02:38:07.221297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 02:38:07.232441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 02:38:07.243889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 02:38:07.254806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 02:38:07.265987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 02:38:07.277222 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 02:38:07.288364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 02:38:07.299574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 02:38:07.310767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 02:38:07.321982 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 02:38:07.333134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 02:38:07.344353 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 02:38:07.355535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 02:38:07.366732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 02:38:07.377893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 02:38:07.389112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 02:38:07.400275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 02:38:07.411474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 02:38:07.422647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 02:38:07.433857 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 02:38:07.445048 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 02:38:07.456256 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 02:38:07.467417 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 02:38:07.473063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 02:38:07.484258 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 02:38:07.495365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 02:38:07.506567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 02:38:07.517749 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 02:38:07.528922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 02:38:07.540132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 02:38:07.551302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 02:38:07.562499 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 02:38:07.573692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 02:38:07.579354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 02:38:07.590512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 02:38:07.601685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 02:38:07.612873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 02:38:07.624087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 02:38:07.635269 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 02:38:07.646433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 02:38:07.657648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 02:38:07.668815 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 02:38:07.680049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 02:38:07.691291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 02:38:07.702409 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 02:38:07.713577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 02:38:07.724791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 02:38:07.735968 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 02:38:07.747164 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 02:38:07.752824 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 02:38:07.763943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 02:38:07.775156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 02:38:07.786339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 02:38:07.797519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 02:38:07.808709 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 02:38:07.819892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 02:38:07.831063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 02:38:07.842266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 02:38:07.853467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 02:38:07.864658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 02:38:07.875829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 02:38:07.881490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 02:38:07.892635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 02:38:07.903825 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 02:38:07.909459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 02:38:07.920595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 02:38:07.926232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 02:38:07.937378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 02:38:07.948544 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 02:38:07.954227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 02:38:07.965381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 02:38:07.976548 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 02:38:07.987746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 02:38:07.998953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 02:38:08.010138 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 02:38:08.021377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 02:38:08.038097 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 02:38:08.049322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 02:38:08.060495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 02:38:08.071678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 02:38:08.082872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 02:38:08.094065 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 02:38:08.105331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 02:38:08.116446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 02:38:08.133226 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 02:38:08.144418 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 02:38:08.161216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 02:38:08.172389 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 02:38:08.178034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 02:38:08.189184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 02:38:08.194807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 02:38:08.205961 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 02:38:08.217144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 02:38:08.222814 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 02:38:08.233923 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 02:38:08.239582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 02:38:08.250718 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 02:38:08.256399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 02:38:08.267491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 02:38:08.273141 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 02:38:08.284368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 02:38:08.295461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 02:38:08.301103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1471 02:38:08.312262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1472 02:38:08.323438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1473 02:38:08.334606 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1474 02:38:08.340287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1475 02:38:08.351424 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc fail
1476 02:38:08.357075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc fail
1477 02:38:08.362621 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1478 02:38:08.373811 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1479 02:38:08.374336 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1480 02:38:08.385062 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1481 02:38:08.390618 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1482 02:38:08.396293 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1483 02:38:08.407368 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1484 02:38:08.413047 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1485 02:38:08.424229 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1486 02:38:08.429779 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1487 02:38:08.440971 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1488 02:38:08.446632 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1489 02:38:08.452193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1490 02:38:08.463455 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1491 02:38:08.469012 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1492 02:38:08.480200 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1493 02:38:08.485750 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1494 02:38:08.496945 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1495 02:38:08.502589 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1496 02:38:08.513675 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1497 02:38:08.519335 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1498 02:38:08.530476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1499 02:38:08.536112 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1500 02:38:08.547259 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1501 02:38:08.552912 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1502 02:38:08.558498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1503 02:38:08.569644 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1504 02:38:08.575300 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 pass
1505 02:38:08.586452 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1506 02:38:08.592215 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1507 02:38:08.603348 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1508 02:38:08.608901 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1509 02:38:08.614554 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1510 02:38:08.625602 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1511 02:38:08.636827 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1512 02:38:08.642480 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1513 02:38:08.653630 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1514 02:38:08.664863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 02:38:08.676012 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1516 02:38:08.681622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1517 02:38:08.692810 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1518 02:38:08.698475 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1519 02:38:08.709562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1520 02:38:08.715207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1521 02:38:08.726415 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1522 02:38:08.732024 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1523 02:38:08.743151 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1524 02:38:08.748773 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1525 02:38:08.760013 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1526 02:38:08.765564 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1527 02:38:08.776743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1528 02:38:08.782509 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1529 02:38:08.793552 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1530 02:38:08.799198 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1531 02:38:08.804775 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1532 02:38:08.815890 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1533 02:38:08.821617 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1534 02:38:08.832704 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1535 02:38:08.838351 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1536 02:38:08.849607 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1537 02:38:08.855299 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1538 02:38:08.866412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1539 02:38:08.872054 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1540 02:38:08.877591 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1541 02:38:08.883185 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1542 02:38:08.894306 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1543 02:38:08.900027 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1544 02:38:08.911118 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1545 02:38:08.916772 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1546 02:38:08.927910 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1547 02:38:08.939064 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1548 02:38:08.950239 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1549 02:38:08.961532 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1550 02:38:08.967141 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1551 02:38:08.972709 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1552 02:38:08.978283 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1553 02:38:08.983893 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1554 02:38:08.989540 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1555 02:38:08.995106 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1556 02:38:09.006335 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1557 02:38:09.012101 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1558 02:38:09.017679 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1559 02:38:09.023251 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1560 02:38:09.028874 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1561 02:38:09.040046 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1562 02:38:09.045649 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1563 02:38:09.051262 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1564 02:38:09.056873 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1565 02:38:09.062503 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1566 02:38:09.068100 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1567 02:38:09.073663 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1568 02:38:09.079272 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1569 02:38:09.084882 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1570 02:38:09.090500 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1571 02:38:09.096079 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1572 02:38:09.101736 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1573 02:38:09.107256 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1574 02:38:09.112878 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1575 02:38:09.118503 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1576 02:38:09.124095 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1577 02:38:09.129682 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1578 02:38:09.135278 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1579 02:38:09.140877 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1580 02:38:09.146506 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1581 02:38:09.152101 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1582 02:38:09.152608 dt_test_unprobed_devices_sh_opp-table skip
1583 02:38:09.157685 dt_test_unprobed_devices_sh_soc skip
1584 02:38:09.163262 dt_test_unprobed_devices_sh_sound pass
1585 02:38:09.163758 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1586 02:38:09.174472 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1587 02:38:09.180097 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1588 02:38:09.185676 dt_test_unprobed_devices_sh fail
1589 02:38:09.186182 + ../../utils/send-to-lava.sh ./output/result.txt
1590 02:38:09.193319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1591 02:38:09.194288 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1593 02:38:09.212717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1594 02:38:09.213503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1596 02:38:09.297683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1597 02:38:09.298498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1599 02:38:09.381992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1600 02:38:09.382861 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1602 02:38:09.470371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1603 02:38:09.471193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1605 02:38:09.559240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1606 02:38:09.560090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1608 02:38:09.641167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1609 02:38:09.641981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1611 02:38:09.727612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1612 02:38:09.728458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1614 02:38:09.810450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1615 02:38:09.811250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1617 02:38:09.900669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1618 02:38:09.901468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1620 02:38:09.988959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1621 02:38:09.989767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1623 02:38:10.079216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1624 02:38:10.080077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1626 02:38:10.163759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1627 02:38:10.164648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1629 02:38:10.246805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1630 02:38:10.247623 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1632 02:38:10.327603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1633 02:38:10.328448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1635 02:38:10.413530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1636 02:38:10.414359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1638 02:38:10.501785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1639 02:38:10.502605 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1641 02:38:10.584107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1642 02:38:10.584935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1644 02:38:10.674216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1645 02:38:10.675040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1647 02:38:10.764583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1648 02:38:10.765414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1650 02:38:10.852719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1651 02:38:10.853632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1653 02:38:10.935269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1654 02:38:10.936090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1656 02:38:11.024788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1657 02:38:11.025596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1659 02:38:11.113411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1660 02:38:11.114281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1662 02:38:11.231912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1663 02:38:11.232928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1665 02:38:11.327037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1666 02:38:11.327865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1668 02:38:11.417419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1669 02:38:11.418305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1671 02:38:11.505463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1672 02:38:11.506356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1674 02:38:11.593574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1675 02:38:11.594459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1677 02:38:11.676425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1678 02:38:11.677248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1680 02:38:11.763286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1681 02:38:11.764112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1683 02:38:11.852093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1684 02:38:11.853281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1686 02:38:11.935391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1687 02:38:11.936400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1689 02:38:12.018633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1690 02:38:12.019742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1692 02:38:12.105535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1693 02:38:12.106367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1695 02:38:12.194282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1696 02:38:12.195168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1698 02:38:12.275496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1699 02:38:12.276526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1701 02:38:12.364095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1702 02:38:12.364907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1704 02:38:12.453083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1705 02:38:12.453906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1707 02:38:12.539829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1708 02:38:12.540717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1710 02:38:12.622482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1711 02:38:12.623319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1713 02:38:12.703677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1714 02:38:12.704531 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1716 02:38:12.787208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1717 02:38:12.788066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1719 02:38:12.870423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1720 02:38:12.871237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1722 02:38:12.953451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1723 02:38:12.954705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1725 02:38:13.036717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1726 02:38:13.037540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1728 02:38:13.119481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1729 02:38:13.120395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1731 02:38:13.202679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1732 02:38:13.203911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1734 02:38:13.284453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1735 02:38:13.285344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1737 02:38:13.367699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1738 02:38:13.368553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1740 02:38:13.455432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1741 02:38:13.456270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1743 02:38:13.543732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1744 02:38:13.544676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1746 02:38:13.634795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1747 02:38:13.635942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1749 02:38:13.723732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1750 02:38:13.725204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1752 02:38:13.807653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1753 02:38:13.808571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1755 02:38:13.890742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1756 02:38:13.891687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1758 02:38:13.978073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1759 02:38:13.979046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1761 02:38:14.067652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1762 02:38:14.068622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1764 02:38:14.158402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1765 02:38:14.159355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1767 02:38:14.244377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1768 02:38:14.245262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1770 02:38:14.326957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1771 02:38:14.327856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1773 02:38:14.408610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1774 02:38:14.409603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1776 02:38:14.490818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1777 02:38:14.491661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1779 02:38:14.573220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1780 02:38:14.574108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1782 02:38:14.655689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1783 02:38:14.656615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1785 02:38:14.738932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1786 02:38:14.739764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1788 02:38:14.825630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1789 02:38:14.826485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1791 02:38:14.911104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1792 02:38:14.911944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1794 02:38:14.997162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1795 02:38:14.998092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1797 02:38:15.087163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1798 02:38:15.088030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1800 02:38:15.178188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1801 02:38:15.179029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1803 02:38:15.270664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1804 02:38:15.271520 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1806 02:38:15.358808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1807 02:38:15.359647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1809 02:38:15.449562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1810 02:38:15.450417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1812 02:38:15.537514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1813 02:38:15.538421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1815 02:38:15.626261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1816 02:38:15.627478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1818 02:38:15.710183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1819 02:38:15.711016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1821 02:38:15.797534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1822 02:38:15.798579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1824 02:38:15.887265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1825 02:38:15.888159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1827 02:38:15.975212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1828 02:38:15.976130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1830 02:38:16.064390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1831 02:38:16.065373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1833 02:38:16.148503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1834 02:38:16.149347 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1836 02:38:16.237410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1837 02:38:16.238566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1839 02:38:16.323877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1840 02:38:16.324989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1842 02:38:16.406817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1843 02:38:16.407866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1845 02:38:16.499611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1846 02:38:16.500675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1848 02:38:16.587100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1849 02:38:16.588126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1851 02:38:16.680053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1852 02:38:16.681039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1854 02:38:16.768529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1855 02:38:16.769504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1857 02:38:16.853150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1858 02:38:16.854130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1860 02:38:16.936806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1861 02:38:16.937784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1863 02:38:17.022920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1864 02:38:17.023898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1866 02:38:17.108313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1867 02:38:17.109280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1869 02:38:17.191152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1870 02:38:17.192171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1872 02:38:17.274774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1873 02:38:17.275801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1875 02:38:17.362408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1876 02:38:17.363367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1878 02:38:17.451692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1879 02:38:17.452734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1881 02:38:17.539541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1882 02:38:17.540581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1884 02:38:17.622742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1885 02:38:17.623793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1887 02:38:17.710269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1888 02:38:17.711273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1890 02:38:17.793116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1891 02:38:17.794136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1893 02:38:17.881438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1894 02:38:17.882431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1896 02:38:17.963209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1897 02:38:17.964209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1899 02:38:18.051973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1900 02:38:18.053004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1902 02:38:18.136248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1903 02:38:18.137129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1905 02:38:18.224430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1906 02:38:18.225425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1908 02:38:18.312526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1909 02:38:18.313515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1911 02:38:18.400861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1912 02:38:18.401837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1914 02:38:18.486532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1915 02:38:18.487540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1917 02:38:18.575041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1918 02:38:18.576113 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1920 02:38:18.658649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1921 02:38:18.659667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1923 02:38:18.749536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1924 02:38:18.750999 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1926 02:38:18.877285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1927 02:38:18.878366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1929 02:38:18.969560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1930 02:38:18.970571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1932 02:38:19.057628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1933 02:38:19.058509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1935 02:38:19.146775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1936 02:38:19.147804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1938 02:38:19.237467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1939 02:38:19.238459 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1941 02:38:19.325271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1942 02:38:19.326320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1944 02:38:19.413341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1945 02:38:19.414331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1947 02:38:19.501063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1948 02:38:19.502090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1950 02:38:19.582404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1952 02:38:19.585394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1953 02:38:19.666519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1955 02:38:19.669655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1956 02:38:19.754952 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1958 02:38:19.758022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1959 02:38:19.843932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1960 02:38:19.844964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1962 02:38:19.931803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1963 02:38:19.932800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1965 02:38:20.012115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1966 02:38:20.013132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1968 02:38:20.096485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1969 02:38:20.097516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1971 02:38:20.181508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1972 02:38:20.182480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1974 02:38:20.265705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1975 02:38:20.266652 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1977 02:38:20.354925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1978 02:38:20.355902 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1980 02:38:20.443354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1981 02:38:20.444378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1983 02:38:20.532651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1984 02:38:20.533669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1986 02:38:20.622141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1987 02:38:20.623249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1989 02:38:20.709755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1990 02:38:20.710777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1992 02:38:20.798393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1993 02:38:20.799378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1995 02:38:20.879933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1996 02:38:20.880926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1998 02:38:20.962380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1999 02:38:20.963317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2001 02:38:21.047708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2002 02:38:21.048744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2004 02:38:21.132529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2005 02:38:21.133507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2007 02:38:21.213915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2008 02:38:21.214838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2010 02:38:21.302837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2011 02:38:21.303741 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2013 02:38:21.386245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2014 02:38:21.387194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2016 02:38:21.472314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2017 02:38:21.473240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2019 02:38:21.562402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail>
2020 02:38:21.563344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc RESULT=fail
2022 02:38:21.652445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail>
2023 02:38:21.653460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc RESULT=fail
2025 02:38:21.731514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2026 02:38:21.732488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2028 02:38:21.820754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2029 02:38:21.821800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2031 02:38:21.902704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2032 02:38:21.903724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2034 02:38:21.992928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2035 02:38:21.993928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2037 02:38:22.077701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2038 02:38:22.078697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2040 02:38:22.166055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2041 02:38:22.167030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2043 02:38:22.252853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2044 02:38:22.253906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2046 02:38:22.340813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2047 02:38:22.341810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2049 02:38:22.423573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2050 02:38:22.424669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2052 02:38:22.508289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2053 02:38:22.509230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2055 02:38:22.596957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2056 02:38:22.597761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2058 02:38:22.686198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2059 02:38:22.687014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2061 02:38:22.769267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2062 02:38:22.770193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2064 02:38:22.850629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2065 02:38:22.851468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2067 02:38:22.939102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2068 02:38:22.939936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2070 02:38:23.020401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2071 02:38:23.021283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2073 02:38:23.108716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2074 02:38:23.109684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2076 02:38:23.192737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2077 02:38:23.193545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2079 02:38:23.280971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2080 02:38:23.281834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2082 02:38:23.362154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2083 02:38:23.362775 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2085 02:38:23.445994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2086 02:38:23.446789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2088 02:38:23.528098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2089 02:38:23.528806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2091 02:38:23.609387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2092 02:38:23.610099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2094 02:38:23.690398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2095 02:38:23.691454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2097 02:38:23.779505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2098 02:38:23.780495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2100 02:38:23.868217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2101 02:38:23.869197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2103 02:38:23.956617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2104 02:38:23.957702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2106 02:38:24.066398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass>
2107 02:38:24.067490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000 RESULT=pass
2109 02:38:24.164918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2110 02:38:24.165868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2112 02:38:24.257156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2113 02:38:24.258074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2115 02:38:24.343936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2116 02:38:24.344916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2118 02:38:24.436772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2119 02:38:24.437706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2121 02:38:24.532416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2122 02:38:24.533141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2124 02:38:24.628408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2125 02:38:24.629300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2127 02:38:24.720930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2128 02:38:24.721929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2130 02:38:24.813626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2131 02:38:24.814256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2133 02:38:24.903136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2134 02:38:24.903769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2136 02:38:24.992561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2137 02:38:24.993152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2139 02:38:25.076069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2140 02:38:25.076610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2142 02:38:25.157459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2143 02:38:25.158010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2145 02:38:25.240286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2146 02:38:25.240833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2148 02:38:25.322986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2149 02:38:25.323546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2151 02:38:25.407502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2152 02:38:25.408271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2154 02:38:25.490153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2155 02:38:25.490858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2157 02:38:25.573979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2158 02:38:25.574700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2160 02:38:25.662467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2161 02:38:25.663170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2163 02:38:25.751350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2164 02:38:25.752072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2166 02:38:25.839178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2167 02:38:25.839889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2169 02:38:25.921585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2170 02:38:25.922285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2172 02:38:26.003884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2173 02:38:26.004611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2175 02:38:26.086459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2176 02:38:26.087219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2178 02:38:26.170099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2179 02:38:26.170812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2181 02:38:26.253689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2182 02:38:26.254399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2184 02:38:26.341617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2185 02:38:26.342335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2187 02:38:26.420714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2188 02:38:26.421416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2190 02:38:26.509397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2191 02:38:26.510099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2193 02:38:26.591966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2194 02:38:26.592707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2196 02:38:26.682558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2197 02:38:26.683269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2199 02:38:26.769873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2200 02:38:26.770571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2202 02:38:26.859166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2203 02:38:26.859880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2205 02:38:26.942322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2206 02:38:26.943017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2208 02:38:27.031705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2209 02:38:27.032432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2211 02:38:27.117288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2212 02:38:27.118039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2214 02:38:27.207343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2215 02:38:27.208074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2217 02:38:27.292142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2218 02:38:27.292836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2220 02:38:27.381584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2221 02:38:27.382281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2223 02:38:27.470072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2224 02:38:27.470781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2226 02:38:27.556524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2227 02:38:27.557238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2229 02:38:27.642551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2230 02:38:27.643283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2232 02:38:27.726457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2233 02:38:27.727173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2235 02:38:27.808248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2236 02:38:27.808967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2238 02:38:27.888338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2239 02:38:27.889075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2241 02:38:27.969212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2242 02:38:27.969931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2244 02:38:28.051310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2245 02:38:28.052040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2247 02:38:28.135515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2248 02:38:28.136294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2250 02:38:28.226041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2251 02:38:28.226760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2253 02:38:28.313361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2254 02:38:28.314136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2256 02:38:28.395308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2257 02:38:28.396075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2259 02:38:28.477703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2260 02:38:28.478419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2262 02:38:28.567674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2263 02:38:28.568455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2265 02:38:28.646927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2267 02:38:28.650088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2268 02:38:28.730730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2269 02:38:28.731438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2271 02:38:28.813451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2272 02:38:28.814159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2274 02:38:28.894667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2275 02:38:28.895379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2277 02:38:28.976449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2278 02:38:28.977155 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2280 02:38:29.058263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2281 02:38:29.059016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2283 02:38:29.146237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2284 02:38:29.146957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2286 02:38:29.227195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2287 02:38:29.227906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2289 02:38:29.309423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2290 02:38:29.310129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2292 02:38:29.398476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2293 02:38:29.399202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2295 02:38:29.485722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2296 02:38:29.486439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2298 02:38:29.573815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2299 02:38:29.574527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2301 02:38:29.655703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2302 02:38:29.656460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2304 02:38:29.737122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2305 02:38:29.737813 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2307 02:38:29.818169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2308 02:38:29.818905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2310 02:38:29.908052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2311 02:38:29.908785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2313 02:38:29.988979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2314 02:38:29.989682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2316 02:38:30.076737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2317 02:38:30.077477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2319 02:38:30.158599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2320 02:38:30.159312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2322 02:38:30.240220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2323 02:38:30.240915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2325 02:38:30.323269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2326 02:38:30.323958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2328 02:38:30.411329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2329 02:38:30.412062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2331 02:38:30.504834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2332 02:38:30.505546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2334 02:38:30.593371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2335 02:38:30.594059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2337 02:38:30.682395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2338 02:38:30.683101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2340 02:38:30.762589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2341 02:38:30.763286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2343 02:38:30.850293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2344 02:38:30.850992 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2346 02:38:30.937133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2347 02:38:30.937832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2349 02:38:31.025658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2350 02:38:31.026343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2352 02:38:31.108509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2353 02:38:31.109254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2355 02:38:31.191514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2356 02:38:31.192216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2358 02:38:31.276382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2359 02:38:31.276837 + set +x
2360 02:38:31.277489 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2362 02:38:31.284604 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 707040_1.6.2.4.5>
2363 02:38:31.285047 <LAVA_TEST_RUNNER EXIT>
2364 02:38:31.285693 Received signal: <ENDRUN> 1_kselftest-dt 707040_1.6.2.4.5
2365 02:38:31.286137 Ending use of test pattern.
2366 02:38:31.286543 Ending test lava.1_kselftest-dt (707040_1.6.2.4.5), duration 67.59
2368 02:38:31.288101 ok: lava_test_shell seems to have completed
2369 02:38:31.300615 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_adc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000_tscadc_0_tsc: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_80000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2370 02:38:31.302480 end: 3.1 lava-test-shell (duration 00:01:09) [common]
2371 02:38:31.303047 end: 3 lava-test-retry (duration 00:01:09) [common]
2372 02:38:31.303614 start: 4 finalize (timeout 00:05:38) [common]
2373 02:38:31.304196 start: 4.1 power-off (timeout 00:00:30) [common]
2374 02:38:31.305146 Calling: 'curl' 'http://conserv2.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-02'
2375 02:38:31.339227 >> OK - accepted request
2376 02:38:31.341449 Returned 0 in 0 seconds
2377 02:38:31.442818 end: 4.1 power-off (duration 00:00:00) [common]
2379 02:38:31.444615 start: 4.2 read-feedback (timeout 00:05:38) [common]
2380 02:38:31.446058 Listened to connection for namespace 'common' for up to 1s
2381 02:38:31.446961 Listened to connection for namespace 'common' for up to 1s
2382 02:38:32.446521 Finalising connection for namespace 'common'
2383 02:38:32.447229 Disconnecting from shell: Finalise
2384 02:38:32.447814 / #
2385 02:38:32.548930 end: 4.2 read-feedback (duration 00:00:01) [common]
2386 02:38:32.549738 end: 4 finalize (duration 00:00:01) [common]
2387 02:38:32.550436 Cleaning after the job
2388 02:38:32.551066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/ramdisk
2389 02:38:32.560444 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/kernel
2390 02:38:32.567262 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/dtb
2391 02:38:32.568516 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/nfsrootfs
2392 02:38:32.715656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/707040/tftp-deploy-r95935d4/modules
2393 02:38:32.725094 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/707040
2394 02:38:35.783421 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/707040
2395 02:38:35.784038 Job finished correctly