Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:53:12.516057 lava-dispatcher, installed at version: 2024.01
2 22:53:12.516874 start: 0 validate
3 22:53:12.517376 Start time: 2024-09-05 22:53:12.517345+00:00 (UTC)
4 22:53:12.517928 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:53:12.518476 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:53:12.564322 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:53:12.564902 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fkernel%2FImage exists
8 22:53:12.601334 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:53:12.602016 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:53:12.636376 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:53:12.636928 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:53:12.671871 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 22:53:12.672424 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-15%2Fmodules.tar.xz exists
14 22:53:12.712360 validate duration: 0.20
16 22:53:12.713572 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:53:12.713942 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:53:12.714267 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:53:12.714968 Not decompressing ramdisk as can be used compressed.
20 22:53:12.715752 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 22:53:12.716317 saving as /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/ramdisk/initrd.cpio.gz
22 22:53:12.716815 total size: 5628182 (5 MB)
23 22:53:12.761904 progress 0 % (0 MB)
24 22:53:12.770085 progress 5 % (0 MB)
25 22:53:12.778349 progress 10 % (0 MB)
26 22:53:12.782933 progress 15 % (0 MB)
27 22:53:12.787083 progress 20 % (1 MB)
28 22:53:12.790958 progress 25 % (1 MB)
29 22:53:12.795660 progress 30 % (1 MB)
30 22:53:12.800067 progress 35 % (1 MB)
31 22:53:12.803765 progress 40 % (2 MB)
32 22:53:12.807889 progress 45 % (2 MB)
33 22:53:12.811589 progress 50 % (2 MB)
34 22:53:12.815631 progress 55 % (2 MB)
35 22:53:12.819749 progress 60 % (3 MB)
36 22:53:12.823673 progress 65 % (3 MB)
37 22:53:12.827797 progress 70 % (3 MB)
38 22:53:12.831557 progress 75 % (4 MB)
39 22:53:12.836162 progress 80 % (4 MB)
40 22:53:12.840143 progress 85 % (4 MB)
41 22:53:12.844374 progress 90 % (4 MB)
42 22:53:12.848224 progress 95 % (5 MB)
43 22:53:12.851552 progress 100 % (5 MB)
44 22:53:12.852254 5 MB downloaded in 0.14 s (39.63 MB/s)
45 22:53:12.852826 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:53:12.853727 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:53:12.854016 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:53:12.854287 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:53:12.854810 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/kernel/Image
51 22:53:12.855082 saving as /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/kernel/Image
52 22:53:12.855291 total size: 39019008 (37 MB)
53 22:53:12.855500 No compression specified
54 22:53:12.889966 progress 0 % (0 MB)
55 22:53:12.914897 progress 5 % (1 MB)
56 22:53:12.939161 progress 10 % (3 MB)
57 22:53:12.963245 progress 15 % (5 MB)
58 22:53:12.987730 progress 20 % (7 MB)
59 22:53:13.011877 progress 25 % (9 MB)
60 22:53:13.036492 progress 30 % (11 MB)
61 22:53:13.060755 progress 35 % (13 MB)
62 22:53:13.088145 progress 40 % (14 MB)
63 22:53:13.112416 progress 45 % (16 MB)
64 22:53:13.137292 progress 50 % (18 MB)
65 22:53:13.161273 progress 55 % (20 MB)
66 22:53:13.186031 progress 60 % (22 MB)
67 22:53:13.210229 progress 65 % (24 MB)
68 22:53:13.234917 progress 70 % (26 MB)
69 22:53:13.258922 progress 75 % (27 MB)
70 22:53:13.282622 progress 80 % (29 MB)
71 22:53:13.307215 progress 85 % (31 MB)
72 22:53:13.335428 progress 90 % (33 MB)
73 22:53:13.360344 progress 95 % (35 MB)
74 22:53:13.383902 progress 100 % (37 MB)
75 22:53:13.384686 37 MB downloaded in 0.53 s (70.29 MB/s)
76 22:53:13.385186 end: 1.2.1 http-download (duration 00:00:01) [common]
78 22:53:13.386069 end: 1.2 download-retry (duration 00:00:01) [common]
79 22:53:13.386373 start: 1.3 download-retry (timeout 00:09:59) [common]
80 22:53:13.386654 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 22:53:13.387140 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 22:53:13.387397 saving as /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/dtb/meson-g12b-a311d-libretech-cc.dtb
83 22:53:13.387610 total size: 54667 (0 MB)
84 22:53:13.387828 No compression specified
85 22:53:13.426043 progress 59 % (0 MB)
86 22:53:13.426926 progress 100 % (0 MB)
87 22:53:13.427493 0 MB downloaded in 0.04 s (1.31 MB/s)
88 22:53:13.428018 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:53:13.428886 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:53:13.429169 start: 1.4 download-retry (timeout 00:09:59) [common]
92 22:53:13.429445 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 22:53:13.429908 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 22:53:13.430153 saving as /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/nfsrootfs/full.rootfs.tar
95 22:53:13.430365 total size: 107552908 (102 MB)
96 22:53:13.430581 Using unxz to decompress xz
97 22:53:13.467117 progress 0 % (0 MB)
98 22:53:14.192470 progress 5 % (5 MB)
99 22:53:14.926444 progress 10 % (10 MB)
100 22:53:15.656601 progress 15 % (15 MB)
101 22:53:16.431273 progress 20 % (20 MB)
102 22:53:17.016580 progress 25 % (25 MB)
103 22:53:17.642067 progress 30 % (30 MB)
104 22:53:18.392645 progress 35 % (35 MB)
105 22:53:18.746961 progress 40 % (41 MB)
106 22:53:19.181064 progress 45 % (46 MB)
107 22:53:19.880304 progress 50 % (51 MB)
108 22:53:20.563834 progress 55 % (56 MB)
109 22:53:21.321876 progress 60 % (61 MB)
110 22:53:22.078550 progress 65 % (66 MB)
111 22:53:22.815831 progress 70 % (71 MB)
112 22:53:23.585366 progress 75 % (76 MB)
113 22:53:24.268226 progress 80 % (82 MB)
114 22:53:24.977392 progress 85 % (87 MB)
115 22:53:25.712251 progress 90 % (92 MB)
116 22:53:26.425153 progress 95 % (97 MB)
117 22:53:27.166370 progress 100 % (102 MB)
118 22:53:27.179195 102 MB downloaded in 13.75 s (7.46 MB/s)
119 22:53:27.179964 end: 1.4.1 http-download (duration 00:00:14) [common]
121 22:53:27.181844 end: 1.4 download-retry (duration 00:00:14) [common]
122 22:53:27.182426 start: 1.5 download-retry (timeout 00:09:46) [common]
123 22:53:27.182999 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 22:53:27.183863 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-15/modules.tar.xz
125 22:53:27.184400 saving as /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/modules/modules.tar
126 22:53:27.184857 total size: 11622752 (11 MB)
127 22:53:27.185322 Using unxz to decompress xz
128 22:53:27.232447 progress 0 % (0 MB)
129 22:53:27.300548 progress 5 % (0 MB)
130 22:53:27.383621 progress 10 % (1 MB)
131 22:53:27.467125 progress 15 % (1 MB)
132 22:53:27.548085 progress 20 % (2 MB)
133 22:53:27.626643 progress 25 % (2 MB)
134 22:53:27.704760 progress 30 % (3 MB)
135 22:53:27.781795 progress 35 % (3 MB)
136 22:53:27.857831 progress 40 % (4 MB)
137 22:53:27.941843 progress 45 % (5 MB)
138 22:53:28.024263 progress 50 % (5 MB)
139 22:53:28.111631 progress 55 % (6 MB)
140 22:53:28.186990 progress 60 % (6 MB)
141 22:53:28.275234 progress 65 % (7 MB)
142 22:53:28.359716 progress 70 % (7 MB)
143 22:53:28.442601 progress 75 % (8 MB)
144 22:53:28.530437 progress 80 % (8 MB)
145 22:53:28.628186 progress 85 % (9 MB)
146 22:53:28.702379 progress 90 % (10 MB)
147 22:53:28.777367 progress 95 % (10 MB)
148 22:53:28.853617 progress 100 % (11 MB)
149 22:53:28.866897 11 MB downloaded in 1.68 s (6.59 MB/s)
150 22:53:28.867886 end: 1.5.1 http-download (duration 00:00:02) [common]
152 22:53:28.869677 end: 1.5 download-retry (duration 00:00:02) [common]
153 22:53:28.870247 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 22:53:28.870810 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 22:53:39.090142 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/713439/extract-nfsrootfs-hvrm0phi
156 22:53:39.090738 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 22:53:39.091026 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 22:53:39.091628 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw
159 22:53:39.092102 makedir: /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin
160 22:53:39.092467 makedir: /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/tests
161 22:53:39.092787 makedir: /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/results
162 22:53:39.093112 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-add-keys
163 22:53:39.093663 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-add-sources
164 22:53:39.094187 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-background-process-start
165 22:53:39.094696 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-background-process-stop
166 22:53:39.095248 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-common-functions
167 22:53:39.095769 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-echo-ipv4
168 22:53:39.096299 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-install-packages
169 22:53:39.096806 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-installed-packages
170 22:53:39.097295 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-os-build
171 22:53:39.097784 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-probe-channel
172 22:53:39.098276 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-probe-ip
173 22:53:39.098765 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-target-ip
174 22:53:39.099258 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-target-mac
175 22:53:39.099751 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-target-storage
176 22:53:39.100280 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-test-case
177 22:53:39.100779 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-test-event
178 22:53:39.101267 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-test-feedback
179 22:53:39.101766 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-test-raise
180 22:53:39.102246 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-test-reference
181 22:53:39.102738 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-test-runner
182 22:53:39.103230 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-test-set
183 22:53:39.103712 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-test-shell
184 22:53:39.104243 Updating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-install-packages (oe)
185 22:53:39.104798 Updating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/bin/lava-installed-packages (oe)
186 22:53:39.105255 Creating /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/environment
187 22:53:39.105651 LAVA metadata
188 22:53:39.105915 - LAVA_JOB_ID=713439
189 22:53:39.106129 - LAVA_DISPATCHER_IP=192.168.6.2
190 22:53:39.106500 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 22:53:39.107586 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 22:53:39.107914 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 22:53:39.108152 skipped lava-vland-overlay
194 22:53:39.108397 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 22:53:39.108652 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 22:53:39.108871 skipped lava-multinode-overlay
197 22:53:39.109113 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 22:53:39.109363 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 22:53:39.109634 Loading test definitions
200 22:53:39.109938 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 22:53:39.110172 Using /lava-713439 at stage 0
202 22:53:39.111480 uuid=713439_1.6.2.4.1 testdef=None
203 22:53:39.111799 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 22:53:39.112094 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 22:53:39.114050 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 22:53:39.114865 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 22:53:39.117426 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 22:53:39.118261 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 22:53:39.120550 runner path: /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/0/tests/0_dmesg test_uuid 713439_1.6.2.4.1
212 22:53:39.121138 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 22:53:39.121892 Creating lava-test-runner.conf files
215 22:53:39.122091 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/713439/lava-overlay-qg1wghnw/lava-713439/0 for stage 0
216 22:53:39.122493 - 0_dmesg
217 22:53:39.122882 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 22:53:39.123172 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 22:53:39.146143 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 22:53:39.146553 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 22:53:39.146811 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 22:53:39.147078 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 22:53:39.147337 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 22:53:39.775736 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 22:53:39.776232 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 22:53:39.776490 extracting modules file /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/modules/modules.tar to /var/lib/lava/dispatcher/tmp/713439/extract-nfsrootfs-hvrm0phi
227 22:53:41.156370 extracting modules file /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/modules/modules.tar to /var/lib/lava/dispatcher/tmp/713439/extract-overlay-ramdisk-449i3gc4/ramdisk
228 22:53:42.574044 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 22:53:42.574547 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 22:53:42.574839 [common] Applying overlay to NFS
231 22:53:42.575055 [common] Applying overlay /var/lib/lava/dispatcher/tmp/713439/compress-overlay-7mzyfkat/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/713439/extract-nfsrootfs-hvrm0phi
232 22:53:42.605636 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 22:53:42.606130 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 22:53:42.606418 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 22:53:42.606662 Converting downloaded kernel to a uImage
236 22:53:42.607019 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/kernel/Image /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/kernel/uImage
237 22:53:43.034441 output: Image Name:
238 22:53:43.034839 output: Created: Thu Sep 5 22:53:42 2024
239 22:53:43.035053 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 22:53:43.035261 output: Data Size: 39019008 Bytes = 38104.50 KiB = 37.21 MiB
241 22:53:43.035465 output: Load Address: 01080000
242 22:53:43.035667 output: Entry Point: 01080000
243 22:53:43.035865 output:
244 22:53:43.036242 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 22:53:43.036517 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 22:53:43.036786 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 22:53:43.037035 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 22:53:43.037289 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 22:53:43.037543 Building ramdisk /var/lib/lava/dispatcher/tmp/713439/extract-overlay-ramdisk-449i3gc4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/713439/extract-overlay-ramdisk-449i3gc4/ramdisk
250 22:53:45.522592 >> 171814 blocks
251 22:53:53.222580 Adding RAMdisk u-boot header.
252 22:53:53.223033 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/713439/extract-overlay-ramdisk-449i3gc4/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/713439/extract-overlay-ramdisk-449i3gc4/ramdisk.cpio.gz.uboot
253 22:53:53.467966 output: Image Name:
254 22:53:53.468405 output: Created: Thu Sep 5 22:53:53 2024
255 22:53:53.468634 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 22:53:53.468848 output: Data Size: 23945615 Bytes = 23384.39 KiB = 22.84 MiB
257 22:53:53.469057 output: Load Address: 00000000
258 22:53:53.469263 output: Entry Point: 00000000
259 22:53:53.469468 output:
260 22:53:53.470173 rename /var/lib/lava/dispatcher/tmp/713439/extract-overlay-ramdisk-449i3gc4/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/ramdisk/ramdisk.cpio.gz.uboot
261 22:53:53.470632 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 22:53:53.470940 end: 1.6 prepare-tftp-overlay (duration 00:00:25) [common]
263 22:53:53.471233 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 22:53:53.471488 No LXC device requested
265 22:53:53.471762 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 22:53:53.472102 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 22:53:53.472396 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 22:53:53.472622 Checking files for TFTP limit of 4294967296 bytes.
269 22:53:53.474214 end: 1 tftp-deploy (duration 00:00:41) [common]
270 22:53:53.474568 start: 2 uboot-action (timeout 00:05:00) [common]
271 22:53:53.474856 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 22:53:53.475125 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 22:53:53.475394 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 22:53:53.475689 Using kernel file from prepare-kernel: 713439/tftp-deploy-l7w08tui/kernel/uImage
275 22:53:53.476052 substitutions:
276 22:53:53.476285 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 22:53:53.476495 - {DTB_ADDR}: 0x01070000
278 22:53:53.476701 - {DTB}: 713439/tftp-deploy-l7w08tui/dtb/meson-g12b-a311d-libretech-cc.dtb
279 22:53:53.476905 - {INITRD}: 713439/tftp-deploy-l7w08tui/ramdisk/ramdisk.cpio.gz.uboot
280 22:53:53.477111 - {KERNEL_ADDR}: 0x01080000
281 22:53:53.477310 - {KERNEL}: 713439/tftp-deploy-l7w08tui/kernel/uImage
282 22:53:53.477512 - {LAVA_MAC}: None
283 22:53:53.477737 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/713439/extract-nfsrootfs-hvrm0phi
284 22:53:53.477950 - {NFS_SERVER_IP}: 192.168.6.2
285 22:53:53.478155 - {PRESEED_CONFIG}: None
286 22:53:53.478355 - {PRESEED_LOCAL}: None
287 22:53:53.478553 - {RAMDISK_ADDR}: 0x08000000
288 22:53:53.478751 - {RAMDISK}: 713439/tftp-deploy-l7w08tui/ramdisk/ramdisk.cpio.gz.uboot
289 22:53:53.478950 - {ROOT_PART}: None
290 22:53:53.479152 - {ROOT}: None
291 22:53:53.479361 - {SERVER_IP}: 192.168.6.2
292 22:53:53.479560 - {TEE_ADDR}: 0x83000000
293 22:53:53.479770 - {TEE}: None
294 22:53:53.480293 Parsed boot commands:
295 22:53:53.480508 - setenv autoload no
296 22:53:53.480714 - setenv initrd_high 0xffffffff
297 22:53:53.480920 - setenv fdt_high 0xffffffff
298 22:53:53.481123 - dhcp
299 22:53:53.481323 - setenv serverip 192.168.6.2
300 22:53:53.481521 - tftpboot 0x01080000 713439/tftp-deploy-l7w08tui/kernel/uImage
301 22:53:53.481724 - tftpboot 0x08000000 713439/tftp-deploy-l7w08tui/ramdisk/ramdisk.cpio.gz.uboot
302 22:53:53.481926 - tftpboot 0x01070000 713439/tftp-deploy-l7w08tui/dtb/meson-g12b-a311d-libretech-cc.dtb
303 22:53:53.482127 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/713439/extract-nfsrootfs-hvrm0phi,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 22:53:53.482331 - bootm 0x01080000 0x08000000 0x01070000
305 22:53:53.482620 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 22:53:53.483432 start: 2.3 connect-device (timeout 00:05:00) [common]
308 22:53:53.483668 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 22:53:53.495635 Setting prompt string to ['lava-test: # ']
310 22:53:53.496645 end: 2.3 connect-device (duration 00:00:00) [common]
311 22:53:53.497009 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 22:53:53.497318 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 22:53:53.497611 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 22:53:53.498250 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 22:53:53.532626 >> OK - accepted request
316 22:53:53.534760 Returned 0 in 0 seconds
317 22:53:53.635551 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 22:53:53.636585 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 22:53:53.636922 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 22:53:53.637213 Setting prompt string to ['Hit any key to stop autoboot']
322 22:53:53.637468 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 22:53:53.638393 Trying 192.168.56.21...
324 22:53:53.638670 Connected to conserv1.
325 22:53:53.638891 Escape character is '^]'.
326 22:53:53.639108
327 22:53:53.639327 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 22:53:53.639537
329 22:54:05.044374 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 22:54:05.045435 bl2_stage_init 0x01
331 22:54:05.046148 bl2_stage_init 0x81
332 22:54:05.049973 hw id: 0x0000 - pwm id 0x01
333 22:54:05.050771 bl2_stage_init 0xc1
334 22:54:05.051549 bl2_stage_init 0x02
335 22:54:05.052366
336 22:54:05.055504 L0:00000000
337 22:54:05.056310 L1:20000703
338 22:54:05.057132 L2:00008067
339 22:54:05.057840 L3:14000000
340 22:54:05.058969 B2:00402000
341 22:54:05.059778 B1:e0f83180
342 22:54:05.060633
343 22:54:05.061331 TE: 58124
344 22:54:05.062027
345 22:54:05.069537 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 22:54:05.070349
347 22:54:05.071060 Board ID = 1
348 22:54:05.071798 Set A53 clk to 24M
349 22:54:05.072540 Set A73 clk to 24M
350 22:54:05.075275 Set clk81 to 24M
351 22:54:05.076083 A53 clk: 1200 MHz
352 22:54:05.076797 A73 clk: 1200 MHz
353 22:54:05.080738 CLK81: 166.6M
354 22:54:05.081553 smccc: 00012a91
355 22:54:05.086394 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 22:54:05.087205 board id: 1
357 22:54:05.094953 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 22:54:05.105642 fw parse done
359 22:54:05.111579 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 22:54:05.154251 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 22:54:05.165103 PIEI prepare done
362 22:54:05.165868 fastboot data load
363 22:54:05.166599 fastboot data verify
364 22:54:05.170765 verify result: 266
365 22:54:05.176353 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 22:54:05.177166 LPDDR4 probe
367 22:54:05.177861 ddr clk to 1584MHz
368 22:54:05.184518 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 22:54:05.221648
370 22:54:05.222512 dmc_version 0001
371 22:54:05.228354 Check phy result
372 22:54:05.234174 INFO : End of CA training
373 22:54:05.234904 INFO : End of initialization
374 22:54:05.239830 INFO : Training has run successfully!
375 22:54:05.240673 Check phy result
376 22:54:05.245364 INFO : End of initialization
377 22:54:05.246152 INFO : End of read enable training
378 22:54:05.250967 INFO : End of fine write leveling
379 22:54:05.256582 INFO : End of Write leveling coarse delay
380 22:54:05.257417 INFO : Training has run successfully!
381 22:54:05.258120 Check phy result
382 22:54:05.262204 INFO : End of initialization
383 22:54:05.262932 INFO : End of read dq deskew training
384 22:54:05.267779 INFO : End of MPR read delay center optimization
385 22:54:05.273380 INFO : End of write delay center optimization
386 22:54:05.279054 INFO : End of read delay center optimization
387 22:54:05.279899 INFO : End of max read latency training
388 22:54:05.284635 INFO : Training has run successfully!
389 22:54:05.285378 1D training succeed
390 22:54:05.293782 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 22:54:05.341420 Check phy result
392 22:54:05.342421 INFO : End of initialization
393 22:54:05.363000 INFO : End of 2D read delay Voltage center optimization
394 22:54:05.383163 INFO : End of 2D read delay Voltage center optimization
395 22:54:05.435066 INFO : End of 2D write delay Voltage center optimization
396 22:54:05.484268 INFO : End of 2D write delay Voltage center optimization
397 22:54:05.489738 INFO : Training has run successfully!
398 22:54:05.490302
399 22:54:05.490832 channel==0
400 22:54:05.495416 RxClkDly_Margin_A0==88 ps 9
401 22:54:05.496069 TxDqDly_Margin_A0==98 ps 10
402 22:54:05.500898 RxClkDly_Margin_A1==88 ps 9
403 22:54:05.501446 TxDqDly_Margin_A1==98 ps 10
404 22:54:05.501963 TrainedVREFDQ_A0==74
405 22:54:05.506526 TrainedVREFDQ_A1==74
406 22:54:05.507085 VrefDac_Margin_A0==25
407 22:54:05.507613 DeviceVref_Margin_A0==40
408 22:54:05.512176 VrefDac_Margin_A1==25
409 22:54:05.512635 DeviceVref_Margin_A1==40
410 22:54:05.513045
411 22:54:05.513446
412 22:54:05.517906 channel==1
413 22:54:05.518334 RxClkDly_Margin_A0==98 ps 10
414 22:54:05.518735 TxDqDly_Margin_A0==98 ps 10
415 22:54:05.523466 RxClkDly_Margin_A1==88 ps 9
416 22:54:05.523895 TxDqDly_Margin_A1==88 ps 9
417 22:54:05.528903 TrainedVREFDQ_A0==77
418 22:54:05.529331 TrainedVREFDQ_A1==77
419 22:54:05.529730 VrefDac_Margin_A0==22
420 22:54:05.534513 DeviceVref_Margin_A0==37
421 22:54:05.534937 VrefDac_Margin_A1==24
422 22:54:05.540862 DeviceVref_Margin_A1==37
423 22:54:05.541280
424 22:54:05.541676 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 22:54:05.542070
426 22:54:05.573709 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 22:54:05.574229 2D training succeed
428 22:54:05.579386 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 22:54:05.585007 auto size-- 65535DDR cs0 size: 2048MB
430 22:54:05.585436 DDR cs1 size: 2048MB
431 22:54:05.590516 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 22:54:05.590936 cs0 DataBus test pass
433 22:54:05.596116 cs1 DataBus test pass
434 22:54:05.596540 cs0 AddrBus test pass
435 22:54:05.596931 cs1 AddrBus test pass
436 22:54:05.597318
437 22:54:05.601693 100bdlr_step_size ps== 420
438 22:54:05.602127 result report
439 22:54:05.607387 boot times 0Enable ddr reg access
440 22:54:05.612660 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 22:54:05.626210 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 22:54:06.198216 0.0;M3 CHK:0;cm4_sp_mode 0
443 22:54:06.198802 MVN_1=0x00000000
444 22:54:06.203723 MVN_2=0x00000000
445 22:54:06.209529 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 22:54:06.209962 OPS=0x10
447 22:54:06.210363 ring efuse init
448 22:54:06.210766 chipver efuse init
449 22:54:06.217807 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 22:54:06.218247 [0.018961 Inits done]
451 22:54:06.225299 secure task start!
452 22:54:06.225724 high task start!
453 22:54:06.226122 low task start!
454 22:54:06.226511 run into bl31
455 22:54:06.231944 NOTICE: BL31: v1.3(release):4fc40b1
456 22:54:06.239747 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 22:54:06.240218 NOTICE: BL31: G12A normal boot!
458 22:54:06.265149 NOTICE: BL31: BL33 decompress pass
459 22:54:06.270775 ERROR: Error initializing runtime service opteed_fast
460 22:54:07.503739
461 22:54:07.504556
462 22:54:07.512307 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 22:54:07.512901
464 22:54:07.513446 Model: Libre Computer AML-A311D-CC Alta
465 22:54:07.720686 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 22:54:07.743957 DRAM: 2 GiB (effective 3.8 GiB)
467 22:54:07.886856 Core: 408 devices, 31 uclasses, devicetree: separate
468 22:54:07.892893 WDT: Not starting watchdog@f0d0
469 22:54:07.925088 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 22:54:07.937492 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 22:54:07.942502 ** Bad device specification mmc 0 **
472 22:54:07.952790 Card did not respond to voltage select! : -110
473 22:54:07.960484 ** Bad device specification mmc 0 **
474 22:54:07.961063 Couldn't find partition mmc 0
475 22:54:07.968793 Card did not respond to voltage select! : -110
476 22:54:07.974216 ** Bad device specification mmc 0 **
477 22:54:07.974780 Couldn't find partition mmc 0
478 22:54:07.979364 Error: could not access storage.
479 22:54:09.244845 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 22:54:09.245650 bl2_stage_init 0x01
481 22:54:09.246219 bl2_stage_init 0x81
482 22:54:09.250426 hw id: 0x0000 - pwm id 0x01
483 22:54:09.251040 bl2_stage_init 0xc1
484 22:54:09.251574 bl2_stage_init 0x02
485 22:54:09.252167
486 22:54:09.255977 L0:00000000
487 22:54:09.256586 L1:20000703
488 22:54:09.257126 L2:00008067
489 22:54:09.257644 L3:14000000
490 22:54:09.261600 B2:00402000
491 22:54:09.262200 B1:e0f83180
492 22:54:09.262725
493 22:54:09.263255 TE: 58167
494 22:54:09.263772
495 22:54:09.267151 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 22:54:09.267722
497 22:54:09.268290 Board ID = 1
498 22:54:09.272786 Set A53 clk to 24M
499 22:54:09.273347 Set A73 clk to 24M
500 22:54:09.273885 Set clk81 to 24M
501 22:54:09.278373 A53 clk: 1200 MHz
502 22:54:09.278930 A73 clk: 1200 MHz
503 22:54:09.279465 CLK81: 166.6M
504 22:54:09.280018 smccc: 00012abd
505 22:54:09.284055 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 22:54:09.289638 board id: 1
507 22:54:09.295591 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 22:54:09.306006 fw parse done
509 22:54:09.311945 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 22:54:09.354669 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 22:54:09.365507 PIEI prepare done
512 22:54:09.366003 fastboot data load
513 22:54:09.366426 fastboot data verify
514 22:54:09.371129 verify result: 266
515 22:54:09.376789 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 22:54:09.377253 LPDDR4 probe
517 22:54:09.377661 ddr clk to 1584MHz
518 22:54:09.384750 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 22:54:09.422106
520 22:54:09.422609 dmc_version 0001
521 22:54:09.428690 Check phy result
522 22:54:09.434577 INFO : End of CA training
523 22:54:09.435039 INFO : End of initialization
524 22:54:09.440247 INFO : Training has run successfully!
525 22:54:09.440700 Check phy result
526 22:54:09.445818 INFO : End of initialization
527 22:54:09.446275 INFO : End of read enable training
528 22:54:09.451428 INFO : End of fine write leveling
529 22:54:09.456940 INFO : End of Write leveling coarse delay
530 22:54:09.457399 INFO : Training has run successfully!
531 22:54:09.457813 Check phy result
532 22:54:09.462551 INFO : End of initialization
533 22:54:09.463005 INFO : End of read dq deskew training
534 22:54:09.468200 INFO : End of MPR read delay center optimization
535 22:54:09.473808 INFO : End of write delay center optimization
536 22:54:09.479271 INFO : End of read delay center optimization
537 22:54:09.479731 INFO : End of max read latency training
538 22:54:09.484963 INFO : Training has run successfully!
539 22:54:09.485431 1D training succeed
540 22:54:09.494287 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 22:54:09.541756 Check phy result
542 22:54:09.542237 INFO : End of initialization
543 22:54:09.563442 INFO : End of 2D read delay Voltage center optimization
544 22:54:09.583665 INFO : End of 2D read delay Voltage center optimization
545 22:54:09.635835 INFO : End of 2D write delay Voltage center optimization
546 22:54:09.685184 INFO : End of 2D write delay Voltage center optimization
547 22:54:09.690787 INFO : Training has run successfully!
548 22:54:09.691252
549 22:54:09.691665 channel==0
550 22:54:09.696417 RxClkDly_Margin_A0==88 ps 9
551 22:54:09.696879 TxDqDly_Margin_A0==98 ps 10
552 22:54:09.702231 RxClkDly_Margin_A1==88 ps 9
553 22:54:09.702675 TxDqDly_Margin_A1==98 ps 10
554 22:54:09.703089 TrainedVREFDQ_A0==74
555 22:54:09.707689 TrainedVREFDQ_A1==74
556 22:54:09.708175 VrefDac_Margin_A0==25
557 22:54:09.708585 DeviceVref_Margin_A0==40
558 22:54:09.713232 VrefDac_Margin_A1==25
559 22:54:09.713677 DeviceVref_Margin_A1==40
560 22:54:09.714082
561 22:54:09.714479
562 22:54:09.718864 channel==1
563 22:54:09.719307 RxClkDly_Margin_A0==98 ps 10
564 22:54:09.719711 TxDqDly_Margin_A0==98 ps 10
565 22:54:09.724414 RxClkDly_Margin_A1==98 ps 10
566 22:54:09.724856 TxDqDly_Margin_A1==88 ps 9
567 22:54:09.729929 TrainedVREFDQ_A0==77
568 22:54:09.730379 TrainedVREFDQ_A1==77
569 22:54:09.730790 VrefDac_Margin_A0==22
570 22:54:09.735706 DeviceVref_Margin_A0==37
571 22:54:09.736184 VrefDac_Margin_A1==24
572 22:54:09.741116 DeviceVref_Margin_A1==37
573 22:54:09.741553
574 22:54:09.741961 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 22:54:09.746648
576 22:54:09.774714 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 22:54:09.775228 2D training succeed
578 22:54:09.780316 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 22:54:09.785888 auto size-- 65535DDR cs0 size: 2048MB
580 22:54:09.786329 DDR cs1 size: 2048MB
581 22:54:09.791454 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 22:54:09.791892 cs0 DataBus test pass
583 22:54:09.797109 cs1 DataBus test pass
584 22:54:09.797555 cs0 AddrBus test pass
585 22:54:09.797957 cs1 AddrBus test pass
586 22:54:09.798352
587 22:54:09.802624 100bdlr_step_size ps== 420
588 22:54:09.803078 result report
589 22:54:09.808297 boot times 0Enable ddr reg access
590 22:54:09.813707 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 22:54:09.827279 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 22:54:10.400821 0.0;M3 CHK:0;cm4_sp_mode 0
593 22:54:10.401411 MVN_1=0x00000000
594 22:54:10.406336 MVN_2=0x00000000
595 22:54:10.412104 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 22:54:10.412588 OPS=0x10
597 22:54:10.413018 ring efuse init
598 22:54:10.413441 chipver efuse init
599 22:54:10.417709 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 22:54:10.423252 [0.018961 Inits done]
601 22:54:10.423678 secure task start!
602 22:54:10.424101 high task start!
603 22:54:10.427830 low task start!
604 22:54:10.428279 run into bl31
605 22:54:10.434537 NOTICE: BL31: v1.3(release):4fc40b1
606 22:54:10.442337 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 22:54:10.442774 NOTICE: BL31: G12A normal boot!
608 22:54:10.467721 NOTICE: BL31: BL33 decompress pass
609 22:54:10.473401 ERROR: Error initializing runtime service opteed_fast
610 22:54:11.706416
611 22:54:11.707008
612 22:54:11.714688 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 22:54:11.715207
614 22:54:11.715688 Model: Libre Computer AML-A311D-CC Alta
615 22:54:11.922995 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 22:54:11.946412 DRAM: 2 GiB (effective 3.8 GiB)
617 22:54:12.089394 Core: 408 devices, 31 uclasses, devicetree: separate
618 22:54:12.095256 WDT: Not starting watchdog@f0d0
619 22:54:12.127535 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 22:54:12.139967 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 22:54:12.144920 ** Bad device specification mmc 0 **
622 22:54:12.155263 Card did not respond to voltage select! : -110
623 22:54:12.163026 ** Bad device specification mmc 0 **
624 22:54:12.163582 Couldn't find partition mmc 0
625 22:54:12.171324 Card did not respond to voltage select! : -110
626 22:54:12.176917 ** Bad device specification mmc 0 **
627 22:54:12.177445 Couldn't find partition mmc 0
628 22:54:12.181939 Error: could not access storage.
629 22:54:12.524381 Net: eth0: ethernet@ff3f0000
630 22:54:12.524831 starting USB...
631 22:54:12.776282 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 22:54:12.776956 Starting the controller
633 22:54:12.783207 USB XHCI 1.10
634 22:54:14.495133 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
635 22:54:14.495828 bl2_stage_init 0x81
636 22:54:14.500746 hw id: 0x0000 - pwm id 0x01
637 22:54:14.501331 bl2_stage_init 0xc1
638 22:54:14.501799 bl2_stage_init 0x02
639 22:54:14.502259
640 22:54:14.506368 L0:00000000
641 22:54:14.506909 L1:20000703
642 22:54:14.507371 L2:00008067
643 22:54:14.507820 L3:14000000
644 22:54:14.508316 B2:00402000
645 22:54:14.509386 B1:e0f83180
646 22:54:14.509916
647 22:54:14.510383 TE: 58150
648 22:54:14.510840
649 22:54:14.520219 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 22:54:14.520790
651 22:54:14.521257 Board ID = 1
652 22:54:14.521712 Set A53 clk to 24M
653 22:54:14.522155 Set A73 clk to 24M
654 22:54:14.525865 Set clk81 to 24M
655 22:54:14.526390 A53 clk: 1200 MHz
656 22:54:14.526846 A73 clk: 1200 MHz
657 22:54:14.531468 CLK81: 166.6M
658 22:54:14.532039 smccc: 00012aab
659 22:54:14.537036 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 22:54:14.537567 board id: 1
661 22:54:14.545724 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 22:54:14.556325 fw parse done
663 22:54:14.561927 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 22:54:14.604881 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 22:54:14.615834 PIEI prepare done
666 22:54:14.616458 fastboot data load
667 22:54:14.616933 fastboot data verify
668 22:54:14.621566 verify result: 266
669 22:54:14.627056 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 22:54:14.627615 LPDDR4 probe
671 22:54:14.628122 ddr clk to 1584MHz
672 22:54:14.635096 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 22:54:14.672351
674 22:54:14.672939 dmc_version 0001
675 22:54:14.678988 Check phy result
676 22:54:14.684890 INFO : End of CA training
677 22:54:14.685445 INFO : End of initialization
678 22:54:14.690469 INFO : Training has run successfully!
679 22:54:14.690993 Check phy result
680 22:54:14.696094 INFO : End of initialization
681 22:54:14.696620 INFO : End of read enable training
682 22:54:14.699386 INFO : End of fine write leveling
683 22:54:14.705003 INFO : End of Write leveling coarse delay
684 22:54:14.710573 INFO : Training has run successfully!
685 22:54:14.711104 Check phy result
686 22:54:14.711563 INFO : End of initialization
687 22:54:14.716242 INFO : End of read dq deskew training
688 22:54:14.721840 INFO : End of MPR read delay center optimization
689 22:54:14.722378 INFO : End of write delay center optimization
690 22:54:14.727404 INFO : End of read delay center optimization
691 22:54:14.733023 INFO : End of max read latency training
692 22:54:14.733554 INFO : Training has run successfully!
693 22:54:14.738576 1D training succeed
694 22:54:14.744481 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 22:54:14.792087 Check phy result
696 22:54:14.792666 INFO : End of initialization
697 22:54:14.813852 INFO : End of 2D read delay Voltage center optimization
698 22:54:14.834191 INFO : End of 2D read delay Voltage center optimization
699 22:54:14.886277 INFO : End of 2D write delay Voltage center optimization
700 22:54:14.935540 INFO : End of 2D write delay Voltage center optimization
701 22:54:14.941123 INFO : Training has run successfully!
702 22:54:14.941631
703 22:54:14.942089 channel==0
704 22:54:14.946673 RxClkDly_Margin_A0==88 ps 9
705 22:54:14.947180 TxDqDly_Margin_A0==98 ps 10
706 22:54:14.950161 RxClkDly_Margin_A1==88 ps 9
707 22:54:14.950662 TxDqDly_Margin_A1==98 ps 10
708 22:54:14.955685 TrainedVREFDQ_A0==74
709 22:54:14.956240 TrainedVREFDQ_A1==74
710 22:54:14.956702 VrefDac_Margin_A0==25
711 22:54:14.961231 DeviceVref_Margin_A0==40
712 22:54:14.961737 VrefDac_Margin_A1==25
713 22:54:14.966864 DeviceVref_Margin_A1==40
714 22:54:14.967368
715 22:54:14.967821
716 22:54:14.968308 channel==1
717 22:54:14.968750 RxClkDly_Margin_A0==98 ps 10
718 22:54:14.970488 TxDqDly_Margin_A0==98 ps 10
719 22:54:14.976079 RxClkDly_Margin_A1==98 ps 10
720 22:54:14.976592 TxDqDly_Margin_A1==88 ps 9
721 22:54:14.977055 TrainedVREFDQ_A0==77
722 22:54:14.981697 TrainedVREFDQ_A1==77
723 22:54:14.982207 VrefDac_Margin_A0==22
724 22:54:14.987292 DeviceVref_Margin_A0==37
725 22:54:14.987795 VrefDac_Margin_A1==22
726 22:54:14.988283 DeviceVref_Margin_A1==37
727 22:54:14.988727
728 22:54:14.996275 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 22:54:14.996798
730 22:54:15.022165 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
731 22:54:15.027971 2D training succeed
732 22:54:15.033456 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 22:54:15.033974 auto size-- 65535DDR cs0 size: 2048MB
734 22:54:15.038917 DDR cs1 size: 2048MB
735 22:54:15.039425 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 22:54:15.044535 cs0 DataBus test pass
737 22:54:15.045042 cs1 DataBus test pass
738 22:54:15.045496 cs0 AddrBus test pass
739 22:54:15.050154 cs1 AddrBus test pass
740 22:54:15.050655
741 22:54:15.051111 100bdlr_step_size ps== 420
742 22:54:15.055797 result report
743 22:54:15.056351 boot times 0Enable ddr reg access
744 22:54:15.063964 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 22:54:15.077427 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 22:54:15.651049 0.0;M3 CHK:0;cm4_sp_mode 0
747 22:54:15.651702 MVN_1=0x00000000
748 22:54:15.656638 MVN_2=0x00000000
749 22:54:15.662421 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 22:54:15.662976 OPS=0x10
751 22:54:15.663418 ring efuse init
752 22:54:15.663852 chipver efuse init
753 22:54:15.668015 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 22:54:15.673526 [0.018961 Inits done]
755 22:54:15.674028 secure task start!
756 22:54:15.674468 high task start!
757 22:54:15.677102 low task start!
758 22:54:15.677598 run into bl31
759 22:54:15.684732 NOTICE: BL31: v1.3(release):4fc40b1
760 22:54:15.691711 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 22:54:15.692264 NOTICE: BL31: G12A normal boot!
762 22:54:15.717935 NOTICE: BL31: BL33 decompress pass
763 22:54:15.722687 ERROR: Error initializing runtime service opteed_fast
764 22:54:16.956411
765 22:54:16.957025
766 22:54:16.964148 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 22:54:16.964669
768 22:54:16.965124 Model: Libre Computer AML-A311D-CC Alta
769 22:54:17.172328 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 22:54:17.196764 DRAM: 2 GiB (effective 3.8 GiB)
771 22:54:17.339784 Core: 408 devices, 31 uclasses, devicetree: separate
772 22:54:17.345629 WDT: Not starting watchdog@f0d0
773 22:54:17.377879 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 22:54:17.390306 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 22:54:17.395464 ** Bad device specification mmc 0 **
776 22:54:17.405630 Card did not respond to voltage select! : -110
777 22:54:17.412331 ** Bad device specification mmc 0 **
778 22:54:17.412866 Couldn't find partition mmc 0
779 22:54:17.421584 Card did not respond to voltage select! : -110
780 22:54:17.427117 ** Bad device specification mmc 0 **
781 22:54:17.427616 Couldn't find partition mmc 0
782 22:54:17.432162 Error: could not access storage.
783 22:54:17.775735 Net: eth0: ethernet@ff3f0000
784 22:54:17.776415 starting USB...
785 22:54:18.027517 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 22:54:18.028221 Starting the controller
787 22:54:18.034441 USB XHCI 1.10
788 22:54:20.195513 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 22:54:20.196251 bl2_stage_init 0x01
790 22:54:20.196738 bl2_stage_init 0x81
791 22:54:20.200792 hw id: 0x0000 - pwm id 0x01
792 22:54:20.201328 bl2_stage_init 0xc1
793 22:54:20.201790 bl2_stage_init 0x02
794 22:54:20.202242
795 22:54:20.206575 L0:00000000
796 22:54:20.207118 L1:20000703
797 22:54:20.207583 L2:00008067
798 22:54:20.208074 L3:14000000
799 22:54:20.212141 B2:00402000
800 22:54:20.212664 B1:e0f83180
801 22:54:20.213119
802 22:54:20.213568 TE: 58124
803 22:54:20.214022
804 22:54:20.217811 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 22:54:20.218343
806 22:54:20.218807 Board ID = 1
807 22:54:20.223416 Set A53 clk to 24M
808 22:54:20.223934 Set A73 clk to 24M
809 22:54:20.224490 Set clk81 to 24M
810 22:54:20.228922 A53 clk: 1200 MHz
811 22:54:20.229441 A73 clk: 1200 MHz
812 22:54:20.229896 CLK81: 166.6M
813 22:54:20.230346 smccc: 00012a92
814 22:54:20.234413 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 22:54:20.240122 board id: 1
816 22:54:20.245964 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 22:54:20.256641 fw parse done
818 22:54:20.262404 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 22:54:20.305045 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 22:54:20.316008 PIEI prepare done
821 22:54:20.316575 fastboot data load
822 22:54:20.317040 fastboot data verify
823 22:54:20.321606 verify result: 266
824 22:54:20.327306 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 22:54:20.327840 LPDDR4 probe
826 22:54:20.328342 ddr clk to 1584MHz
827 22:54:20.335165 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 22:54:20.372433
829 22:54:20.373001 dmc_version 0001
830 22:54:20.379137 Check phy result
831 22:54:20.385053 INFO : End of CA training
832 22:54:20.385605 INFO : End of initialization
833 22:54:20.390580 INFO : Training has run successfully!
834 22:54:20.391096 Check phy result
835 22:54:20.396327 INFO : End of initialization
836 22:54:20.396909 INFO : End of read enable training
837 22:54:20.401800 INFO : End of fine write leveling
838 22:54:20.407364 INFO : End of Write leveling coarse delay
839 22:54:20.407900 INFO : Training has run successfully!
840 22:54:20.408413 Check phy result
841 22:54:20.413071 INFO : End of initialization
842 22:54:20.413624 INFO : End of read dq deskew training
843 22:54:20.418591 INFO : End of MPR read delay center optimization
844 22:54:20.424312 INFO : End of write delay center optimization
845 22:54:20.429748 INFO : End of read delay center optimization
846 22:54:20.430278 INFO : End of max read latency training
847 22:54:20.435366 INFO : Training has run successfully!
848 22:54:20.435909 1D training succeed
849 22:54:20.444541 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 22:54:20.492162 Check phy result
851 22:54:20.492702 INFO : End of initialization
852 22:54:20.513902 INFO : End of 2D read delay Voltage center optimization
853 22:54:20.534166 INFO : End of 2D read delay Voltage center optimization
854 22:54:20.586163 INFO : End of 2D write delay Voltage center optimization
855 22:54:20.635592 INFO : End of 2D write delay Voltage center optimization
856 22:54:20.641087 INFO : Training has run successfully!
857 22:54:20.641656
858 22:54:20.642165 channel==0
859 22:54:20.646679 RxClkDly_Margin_A0==88 ps 9
860 22:54:20.647197 TxDqDly_Margin_A0==98 ps 10
861 22:54:20.652363 RxClkDly_Margin_A1==88 ps 9
862 22:54:20.652854 TxDqDly_Margin_A1==88 ps 9
863 22:54:20.653324 TrainedVREFDQ_A0==74
864 22:54:20.657905 TrainedVREFDQ_A1==74
865 22:54:20.658428 VrefDac_Margin_A0==25
866 22:54:20.658879 DeviceVref_Margin_A0==40
867 22:54:20.663492 VrefDac_Margin_A1==25
868 22:54:20.664047 DeviceVref_Margin_A1==40
869 22:54:20.664487
870 22:54:20.664913
871 22:54:20.665339 channel==1
872 22:54:20.669115 RxClkDly_Margin_A0==98 ps 10
873 22:54:20.669586 TxDqDly_Margin_A0==88 ps 9
874 22:54:20.674716 RxClkDly_Margin_A1==98 ps 10
875 22:54:20.675182 TxDqDly_Margin_A1==98 ps 10
876 22:54:20.680317 TrainedVREFDQ_A0==77
877 22:54:20.680799 TrainedVREFDQ_A1==77
878 22:54:20.681237 VrefDac_Margin_A0==22
879 22:54:20.685882 DeviceVref_Margin_A0==37
880 22:54:20.686353 VrefDac_Margin_A1==24
881 22:54:20.691534 DeviceVref_Margin_A1==37
882 22:54:20.692039
883 22:54:20.692479 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 22:54:20.692911
885 22:54:20.725134 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
886 22:54:20.725714 2D training succeed
887 22:54:20.730730 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 22:54:20.736337 auto size-- 65535DDR cs0 size: 2048MB
889 22:54:20.736818 DDR cs1 size: 2048MB
890 22:54:20.741927 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 22:54:20.742390 cs0 DataBus test pass
892 22:54:20.747527 cs1 DataBus test pass
893 22:54:20.748029 cs0 AddrBus test pass
894 22:54:20.748469 cs1 AddrBus test pass
895 22:54:20.748896
896 22:54:20.753113 100bdlr_step_size ps== 420
897 22:54:20.753582 result report
898 22:54:20.758733 boot times 0Enable ddr reg access
899 22:54:20.764076 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 22:54:20.777539 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 22:54:21.351306 0.0;M3 CHK:0;cm4_sp_mode 0
902 22:54:21.351971 MVN_1=0x00000000
903 22:54:21.356761 MVN_2=0x00000000
904 22:54:21.362498 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 22:54:21.362998 OPS=0x10
906 22:54:21.363453 ring efuse init
907 22:54:21.363898 chipver efuse init
908 22:54:21.368120 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 22:54:21.373714 [0.018961 Inits done]
910 22:54:21.374208 secure task start!
911 22:54:21.374656 high task start!
912 22:54:21.378252 low task start!
913 22:54:21.378745 run into bl31
914 22:54:21.384873 NOTICE: BL31: v1.3(release):4fc40b1
915 22:54:21.392696 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 22:54:21.393219 NOTICE: BL31: G12A normal boot!
917 22:54:21.418028 NOTICE: BL31: BL33 decompress pass
918 22:54:21.423695 ERROR: Error initializing runtime service opteed_fast
919 22:54:22.656584
920 22:54:22.657223
921 22:54:22.664980 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 22:54:22.665474
923 22:54:22.665927 Model: Libre Computer AML-A311D-CC Alta
924 22:54:22.873456 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 22:54:22.896818 DRAM: 2 GiB (effective 3.8 GiB)
926 22:54:23.039783 Core: 408 devices, 31 uclasses, devicetree: separate
927 22:54:23.045732 WDT: Not starting watchdog@f0d0
928 22:54:23.077893 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 22:54:23.090413 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 22:54:23.095307 ** Bad device specification mmc 0 **
931 22:54:23.105624 Card did not respond to voltage select! : -110
932 22:54:23.113279 ** Bad device specification mmc 0 **
933 22:54:23.113757 Couldn't find partition mmc 0
934 22:54:23.121672 Card did not respond to voltage select! : -110
935 22:54:23.127151 ** Bad device specification mmc 0 **
936 22:54:23.127629 Couldn't find partition mmc 0
937 22:54:23.132179 Error: could not access storage.
938 22:54:23.474736 Net: eth0: ethernet@ff3f0000
939 22:54:23.475348 starting USB...
940 22:54:23.726454 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 22:54:23.727052 Starting the controller
942 22:54:23.733412 USB XHCI 1.10
943 22:54:25.595112 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 22:54:25.595730 bl2_stage_init 0x01
945 22:54:25.596245 bl2_stage_init 0x81
946 22:54:25.600527 hw id: 0x0000 - pwm id 0x01
947 22:54:25.601011 bl2_stage_init 0xc1
948 22:54:25.601465 bl2_stage_init 0x02
949 22:54:25.601912
950 22:54:25.606314 L0:00000000
951 22:54:25.606791 L1:20000703
952 22:54:25.607241 L2:00008067
953 22:54:25.607682 L3:14000000
954 22:54:25.609173 B2:00402000
955 22:54:25.609644 B1:e0f83180
956 22:54:25.610093
957 22:54:25.610537 TE: 58159
958 22:54:25.610980
959 22:54:25.620319 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 22:54:25.620798
961 22:54:25.621248 Board ID = 1
962 22:54:25.621688 Set A53 clk to 24M
963 22:54:25.622125 Set A73 clk to 24M
964 22:54:25.625934 Set clk81 to 24M
965 22:54:25.626406 A53 clk: 1200 MHz
966 22:54:25.626852 A73 clk: 1200 MHz
967 22:54:25.631409 CLK81: 166.6M
968 22:54:25.631880 smccc: 00012ab5
969 22:54:25.637085 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 22:54:25.637562 board id: 1
971 22:54:25.645828 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 22:54:25.656280 fw parse done
973 22:54:25.662214 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 22:54:25.704973 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 22:54:25.715831 PIEI prepare done
976 22:54:25.716364 fastboot data load
977 22:54:25.716799 fastboot data verify
978 22:54:25.721387 verify result: 266
979 22:54:25.727058 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 22:54:25.727524 LPDDR4 probe
981 22:54:25.727948 ddr clk to 1584MHz
982 22:54:25.734965 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 22:54:25.772242
984 22:54:25.772726 dmc_version 0001
985 22:54:25.778951 Check phy result
986 22:54:25.784833 INFO : End of CA training
987 22:54:25.785290 INFO : End of initialization
988 22:54:25.790387 INFO : Training has run successfully!
989 22:54:25.790914 Check phy result
990 22:54:25.796123 INFO : End of initialization
991 22:54:25.796598 INFO : End of read enable training
992 22:54:25.801636 INFO : End of fine write leveling
993 22:54:25.807248 INFO : End of Write leveling coarse delay
994 22:54:25.807729 INFO : Training has run successfully!
995 22:54:25.808225 Check phy result
996 22:54:25.812852 INFO : End of initialization
997 22:54:25.813320 INFO : End of read dq deskew training
998 22:54:25.818418 INFO : End of MPR read delay center optimization
999 22:54:25.824149 INFO : End of write delay center optimization
1000 22:54:25.829640 INFO : End of read delay center optimization
1001 22:54:25.830107 INFO : End of max read latency training
1002 22:54:25.835196 INFO : Training has run successfully!
1003 22:54:25.835665 1D training succeed
1004 22:54:25.844457 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 22:54:25.891972 Check phy result
1006 22:54:25.892535 INFO : End of initialization
1007 22:54:25.913580 INFO : End of 2D read delay Voltage center optimization
1008 22:54:25.933656 INFO : End of 2D read delay Voltage center optimization
1009 22:54:25.985593 INFO : End of 2D write delay Voltage center optimization
1010 22:54:26.034814 INFO : End of 2D write delay Voltage center optimization
1011 22:54:26.040448 INFO : Training has run successfully!
1012 22:54:26.040951
1013 22:54:26.041411 channel==0
1014 22:54:26.046006 RxClkDly_Margin_A0==88 ps 9
1015 22:54:26.046484 TxDqDly_Margin_A0==98 ps 10
1016 22:54:26.051657 RxClkDly_Margin_A1==88 ps 9
1017 22:54:26.052173 TxDqDly_Margin_A1==98 ps 10
1018 22:54:26.052631 TrainedVREFDQ_A0==74
1019 22:54:26.057174 TrainedVREFDQ_A1==74
1020 22:54:26.057651 VrefDac_Margin_A0==25
1021 22:54:26.058107 DeviceVref_Margin_A0==40
1022 22:54:26.062845 VrefDac_Margin_A1==25
1023 22:54:26.063329 DeviceVref_Margin_A1==40
1024 22:54:26.063777
1025 22:54:26.064262
1026 22:54:26.068368 channel==1
1027 22:54:26.068848 RxClkDly_Margin_A0==98 ps 10
1028 22:54:26.069291 TxDqDly_Margin_A0==98 ps 10
1029 22:54:26.074036 RxClkDly_Margin_A1==88 ps 9
1030 22:54:26.074516 TxDqDly_Margin_A1==88 ps 9
1031 22:54:26.079568 TrainedVREFDQ_A0==76
1032 22:54:26.080076 TrainedVREFDQ_A1==77
1033 22:54:26.080528 VrefDac_Margin_A0==22
1034 22:54:26.085177 DeviceVref_Margin_A0==38
1035 22:54:26.085647 VrefDac_Margin_A1==24
1036 22:54:26.090758 DeviceVref_Margin_A1==37
1037 22:54:26.091263
1038 22:54:26.091710 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 22:54:26.092188
1040 22:54:26.124413 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1041 22:54:26.124975 2D training succeed
1042 22:54:26.129949 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 22:54:26.135555 auto size-- 65535DDR cs0 size: 2048MB
1044 22:54:26.136059 DDR cs1 size: 2048MB
1045 22:54:26.141987 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 22:54:26.142458 cs0 DataBus test pass
1047 22:54:26.146878 cs1 DataBus test pass
1048 22:54:26.147351 cs0 AddrBus test pass
1049 22:54:26.147795 cs1 AddrBus test pass
1050 22:54:26.148274
1051 22:54:26.152370 100bdlr_step_size ps== 420
1052 22:54:26.152876 result report
1053 22:54:26.157996 boot times 0Enable ddr reg access
1054 22:54:26.163359 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 22:54:26.176792 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 22:54:26.748850 0.0;M3 CHK:0;cm4_sp_mode 0
1057 22:54:26.749264 MVN_1=0x00000000
1058 22:54:26.754302 MVN_2=0x00000000
1059 22:54:26.760270 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 22:54:26.760567 OPS=0x10
1061 22:54:26.760798 ring efuse init
1062 22:54:26.761015 chipver efuse init
1063 22:54:26.765683 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 22:54:26.771286 [0.018961 Inits done]
1065 22:54:26.771677 secure task start!
1066 22:54:26.772055 high task start!
1067 22:54:26.775871 low task start!
1068 22:54:26.776716 run into bl31
1069 22:54:26.782482 NOTICE: BL31: v1.3(release):4fc40b1
1070 22:54:26.790284 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 22:54:26.790600 NOTICE: BL31: G12A normal boot!
1072 22:54:26.815575 NOTICE: BL31: BL33 decompress pass
1073 22:54:26.821259 ERROR: Error initializing runtime service opteed_fast
1074 22:54:28.054378
1075 22:54:28.055008
1076 22:54:28.062955 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 22:54:28.063561
1078 22:54:28.064087 Model: Libre Computer AML-A311D-CC Alta
1079 22:54:28.271213 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 22:54:28.294697 DRAM: 2 GiB (effective 3.8 GiB)
1081 22:54:28.437567 Core: 408 devices, 31 uclasses, devicetree: separate
1082 22:54:28.443329 WDT: Not starting watchdog@f0d0
1083 22:54:28.475723 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 22:54:28.488157 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 22:54:28.493108 ** Bad device specification mmc 0 **
1086 22:54:28.503554 Card did not respond to voltage select! : -110
1087 22:54:28.511056 ** Bad device specification mmc 0 **
1088 22:54:28.511572 Couldn't find partition mmc 0
1089 22:54:28.519447 Card did not respond to voltage select! : -110
1090 22:54:28.524782 ** Bad device specification mmc 0 **
1091 22:54:28.525278 Couldn't find partition mmc 0
1092 22:54:28.529928 Error: could not access storage.
1093 22:54:28.873629 Net: eth0: ethernet@ff3f0000
1094 22:54:28.874254 starting USB...
1095 22:54:29.125286 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 22:54:29.125890 Starting the controller
1097 22:54:29.132231 USB XHCI 1.10
1098 22:54:30.686352 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 22:54:30.694655 scanning usb for storage devices... 0 Storage Device(s) found
1101 22:54:30.746477 Hit any key to stop autoboot: 1
1102 22:54:30.747413 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1103 22:54:30.748078 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1104 22:54:30.748593 Setting prompt string to ['=>']
1105 22:54:30.749108 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1106 22:54:30.762262 0
1107 22:54:30.763192 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 22:54:30.763711 Sending with 10 millisecond of delay
1110 22:54:31.898878 => setenv autoload no
1111 22:54:31.909753 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1112 22:54:31.915206 setenv autoload no
1113 22:54:31.916066 Sending with 10 millisecond of delay
1115 22:54:33.714257 => setenv initrd_high 0xffffffff
1116 22:54:33.725066 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1117 22:54:33.725982 setenv initrd_high 0xffffffff
1118 22:54:33.726747 Sending with 10 millisecond of delay
1120 22:54:35.344091 => setenv fdt_high 0xffffffff
1121 22:54:35.355319 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 22:54:35.356664 setenv fdt_high 0xffffffff
1123 22:54:35.357666 Sending with 10 millisecond of delay
1125 22:54:35.650493 => dhcp
1126 22:54:35.661700 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1127 22:54:35.663066 dhcp
1128 22:54:35.663835 Speed: 1000, full duplex
1129 22:54:35.664585 BOOTP broadcast 1
1130 22:54:35.909797 BOOTP broadcast 2
1131 22:54:36.410845 BOOTP broadcast 3
1132 22:54:36.437800 DHCP client bound to address 192.168.6.33 (775 ms)
1133 22:54:36.438352 Sending with 10 millisecond of delay
1135 22:54:38.113562 => setenv serverip 192.168.6.2
1136 22:54:38.124104 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1137 22:54:38.124611 setenv serverip 192.168.6.2
1138 22:54:38.125076 Sending with 10 millisecond of delay
1140 22:54:41.847115 => tftpboot 0x01080000 713439/tftp-deploy-l7w08tui/kernel/uImage
1141 22:54:41.857944 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1142 22:54:41.858893 tftpboot 0x01080000 713439/tftp-deploy-l7w08tui/kernel/uImage
1143 22:54:41.859345 Speed: 1000, full duplex
1144 22:54:41.859751 Using ethernet@ff3f0000 device
1145 22:54:41.860691 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 22:54:41.866224 Filename '713439/tftp-deploy-l7w08tui/kernel/uImage'.
1147 22:54:41.870145 Load address: 0x1080000
1148 22:54:42.403490 Loading: *########## UDP wrong checksum 000000ff 0000681b
1149 22:54:42.434137 UDP wrong checksum 000000ff 0000fe0d
1150 22:54:44.459716 ######################################## 37.2 MiB
1151 22:54:44.460566 14.4 MiB/s
1152 22:54:44.461131 done
1153 22:54:44.463914 Bytes transferred = 39019072 (2536240 hex)
1154 22:54:44.464896 Sending with 10 millisecond of delay
1156 22:54:49.154966 => tftpboot 0x08000000 713439/tftp-deploy-l7w08tui/ramdisk/ramdisk.cpio.gz.uboot
1157 22:54:49.166003 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1158 22:54:49.167113 tftpboot 0x08000000 713439/tftp-deploy-l7w08tui/ramdisk/ramdisk.cpio.gz.uboot
1159 22:54:49.167707 Speed: 1000, full duplex
1160 22:54:49.168381 Using ethernet@ff3f0000 device
1161 22:54:49.169019 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1162 22:54:49.177551 Filename '713439/tftp-deploy-l7w08tui/ramdisk/ramdisk.cpio.gz.uboot'.
1163 22:54:49.178737 Load address: 0x8000000
1164 22:54:55.877365 Loading: *########################T ######################### UDP wrong checksum 00000005 0000e5ef
1165 22:55:00.878276 T UDP wrong checksum 00000005 0000e5ef
1166 22:55:07.188722 T UDP wrong checksum 000000ff 00000939
1167 22:55:07.207159 UDP wrong checksum 000000ff 0000a22b
1168 22:55:10.880449 T UDP wrong checksum 00000005 0000e5ef
1169 22:55:22.951537 T T UDP wrong checksum 000000ff 0000e433
1170 22:55:23.004547 UDP wrong checksum 000000ff 00006b26
1171 22:55:30.884763 T T UDP wrong checksum 00000005 0000e5ef
1172 22:55:39.045413 T UDP wrong checksum 000000ff 00004923
1173 22:55:39.096917 UDP wrong checksum 000000ff 0000da15
1174 22:55:45.887506 T
1175 22:55:45.888226 Retry count exceeded; starting again
1177 22:55:45.889764 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1180 22:55:45.891840 end: 2.4 uboot-commands (duration 00:01:52) [common]
1182 22:55:45.893526 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1184 22:55:45.894698 end: 2 uboot-action (duration 00:01:52) [common]
1186 22:55:45.896459 Cleaning after the job
1187 22:55:45.897101 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/ramdisk
1188 22:55:45.898476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/kernel
1189 22:55:45.944360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/dtb
1190 22:55:45.945323 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/nfsrootfs
1191 22:55:46.108094 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713439/tftp-deploy-l7w08tui/modules
1192 22:55:46.131064 start: 4.1 power-off (timeout 00:00:30) [common]
1193 22:55:46.131755 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1194 22:55:46.167300 >> OK - accepted request
1195 22:55:46.169448 Returned 0 in 0 seconds
1196 22:55:46.270275 end: 4.1 power-off (duration 00:00:00) [common]
1198 22:55:46.271342 start: 4.2 read-feedback (timeout 00:10:00) [common]
1199 22:55:46.272097 Listened to connection for namespace 'common' for up to 1s
1200 22:55:47.272302 Finalising connection for namespace 'common'
1201 22:55:47.272917 Disconnecting from shell: Finalise
1202 22:55:47.273313 =>
1203 22:55:47.374279 end: 4.2 read-feedback (duration 00:00:01) [common]
1204 22:55:47.375255 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/713439
1205 22:55:49.360410 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/713439
1206 22:55:49.361115 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.