Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:58:12.704774 lava-dispatcher, installed at version: 2024.01
2 22:58:12.705589 start: 0 validate
3 22:58:12.706062 Start time: 2024-09-05 22:58:12.706032+00:00 (UTC)
4 22:58:12.706624 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:58:12.707165 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 22:58:12.753516 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:58:12.754109 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 22:58:12.783137 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:58:12.783775 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 22:58:13.848678 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:58:13.849206 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
12 22:58:13.893870 validate duration: 1.19
14 22:58:13.895415 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:58:13.896047 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:58:13.896634 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:58:13.897626 Not decompressing ramdisk as can be used compressed.
18 22:58:13.898408 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 22:58:13.898918 saving as /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/ramdisk/rootfs.cpio.gz
20 22:58:13.899423 total size: 8181887 (7 MB)
21 22:58:13.946299 progress 0 % (0 MB)
22 22:58:13.957834 progress 5 % (0 MB)
23 22:58:13.968403 progress 10 % (0 MB)
24 22:58:13.979514 progress 15 % (1 MB)
25 22:58:13.987146 progress 20 % (1 MB)
26 22:58:13.993434 progress 25 % (1 MB)
27 22:58:13.999174 progress 30 % (2 MB)
28 22:58:14.005106 progress 35 % (2 MB)
29 22:58:14.010518 progress 40 % (3 MB)
30 22:58:14.016413 progress 45 % (3 MB)
31 22:58:14.021785 progress 50 % (3 MB)
32 22:58:14.027488 progress 55 % (4 MB)
33 22:58:14.032910 progress 60 % (4 MB)
34 22:58:14.038760 progress 65 % (5 MB)
35 22:58:14.044190 progress 70 % (5 MB)
36 22:58:14.049963 progress 75 % (5 MB)
37 22:58:14.055448 progress 80 % (6 MB)
38 22:58:14.061363 progress 85 % (6 MB)
39 22:58:14.066876 progress 90 % (7 MB)
40 22:58:14.072768 progress 95 % (7 MB)
41 22:58:14.077743 progress 100 % (7 MB)
42 22:58:14.078450 7 MB downloaded in 0.18 s (43.59 MB/s)
43 22:58:14.079060 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:58:14.080063 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:58:14.080403 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:58:14.080704 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:58:14.081232 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig/clang-15/kernel/Image
49 22:58:14.081500 saving as /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/kernel/Image
50 22:58:14.081728 total size: 37407232 (35 MB)
51 22:58:14.081950 No compression specified
52 22:58:14.129590 progress 0 % (0 MB)
53 22:58:14.156795 progress 5 % (1 MB)
54 22:58:14.181939 progress 10 % (3 MB)
55 22:58:14.209067 progress 15 % (5 MB)
56 22:58:14.236979 progress 20 % (7 MB)
57 22:58:14.264194 progress 25 % (8 MB)
58 22:58:14.290590 progress 30 % (10 MB)
59 22:58:14.319881 progress 35 % (12 MB)
60 22:58:14.346119 progress 40 % (14 MB)
61 22:58:14.372264 progress 45 % (16 MB)
62 22:58:14.398743 progress 50 % (17 MB)
63 22:58:14.427948 progress 55 % (19 MB)
64 22:58:14.454164 progress 60 % (21 MB)
65 22:58:14.479962 progress 65 % (23 MB)
66 22:58:14.506317 progress 70 % (25 MB)
67 22:58:14.533296 progress 75 % (26 MB)
68 22:58:14.558843 progress 80 % (28 MB)
69 22:58:14.584601 progress 85 % (30 MB)
70 22:58:14.610178 progress 90 % (32 MB)
71 22:58:14.638861 progress 95 % (33 MB)
72 22:58:14.664551 progress 100 % (35 MB)
73 22:58:14.665296 35 MB downloaded in 0.58 s (61.13 MB/s)
74 22:58:14.665831 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:58:14.666740 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:58:14.667048 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:58:14.667325 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:58:14.667836 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig/clang-15/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 22:58:14.668203 saving as /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 22:58:14.668461 total size: 53173 (0 MB)
82 22:58:14.668673 No compression specified
83 22:58:14.715897 progress 61 % (0 MB)
84 22:58:14.717180 progress 100 % (0 MB)
85 22:58:14.717951 0 MB downloaded in 0.05 s (1.02 MB/s)
86 22:58:14.718678 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:58:14.719811 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:58:14.720236 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:58:14.720644 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:58:14.721277 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig/clang-15/modules.tar.xz
92 22:58:14.721637 saving as /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/modules/modules.tar
93 22:58:14.721907 total size: 11642308 (11 MB)
94 22:58:14.722235 Using unxz to decompress xz
95 22:58:14.768020 progress 0 % (0 MB)
96 22:58:14.838846 progress 5 % (0 MB)
97 22:58:14.918369 progress 10 % (1 MB)
98 22:58:15.009940 progress 15 % (1 MB)
99 22:58:15.092626 progress 20 % (2 MB)
100 22:58:15.170424 progress 25 % (2 MB)
101 22:58:15.255891 progress 30 % (3 MB)
102 22:58:15.337695 progress 35 % (3 MB)
103 22:58:15.419652 progress 40 % (4 MB)
104 22:58:15.496775 progress 45 % (5 MB)
105 22:58:15.576678 progress 50 % (5 MB)
106 22:58:15.654872 progress 55 % (6 MB)
107 22:58:15.741023 progress 60 % (6 MB)
108 22:58:15.824242 progress 65 % (7 MB)
109 22:58:15.907839 progress 70 % (7 MB)
110 22:58:16.002178 progress 75 % (8 MB)
111 22:58:16.098721 progress 80 % (8 MB)
112 22:58:16.181432 progress 85 % (9 MB)
113 22:58:16.253787 progress 90 % (10 MB)
114 22:58:16.333247 progress 95 % (10 MB)
115 22:58:16.411932 progress 100 % (11 MB)
116 22:58:16.422898 11 MB downloaded in 1.70 s (6.53 MB/s)
117 22:58:16.423472 end: 1.4.1 http-download (duration 00:00:02) [common]
119 22:58:16.424831 end: 1.4 download-retry (duration 00:00:02) [common]
120 22:58:16.425453 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 22:58:16.426026 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 22:58:16.426565 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:58:16.427116 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 22:58:16.428232 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h
125 22:58:16.429172 makedir: /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin
126 22:58:16.429865 makedir: /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/tests
127 22:58:16.430530 makedir: /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/results
128 22:58:16.431192 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-add-keys
129 22:58:16.432263 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-add-sources
130 22:58:16.433282 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-background-process-start
131 22:58:16.434288 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-background-process-stop
132 22:58:16.435336 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-common-functions
133 22:58:16.436379 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-echo-ipv4
134 22:58:16.437374 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-install-packages
135 22:58:16.438340 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-installed-packages
136 22:58:16.439292 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-os-build
137 22:58:16.440283 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-probe-channel
138 22:58:16.441279 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-probe-ip
139 22:58:16.442244 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-target-ip
140 22:58:16.443199 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-target-mac
141 22:58:16.444223 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-target-storage
142 22:58:16.445268 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-test-case
143 22:58:16.446249 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-test-event
144 22:58:16.447198 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-test-feedback
145 22:58:16.448194 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-test-raise
146 22:58:16.449184 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-test-reference
147 22:58:16.450151 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-test-runner
148 22:58:16.451121 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-test-set
149 22:58:16.452138 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-test-shell
150 22:58:16.453151 Updating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-install-packages (oe)
151 22:58:16.454185 Updating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/bin/lava-installed-packages (oe)
152 22:58:16.455067 Creating /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/environment
153 22:58:16.455831 LAVA metadata
154 22:58:16.456410 - LAVA_JOB_ID=713197
155 22:58:16.456881 - LAVA_DISPATCHER_IP=192.168.6.2
156 22:58:16.457608 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 22:58:16.459608 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 22:58:16.460326 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 22:58:16.460743 skipped lava-vland-overlay
160 22:58:16.461240 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 22:58:16.461747 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 22:58:16.462174 skipped lava-multinode-overlay
163 22:58:16.462651 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 22:58:16.463144 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 22:58:16.463621 Loading test definitions
166 22:58:16.464192 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 22:58:16.464639 Using /lava-713197 at stage 0
168 22:58:16.466823 uuid=713197_1.5.2.4.1 testdef=None
169 22:58:16.467382 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 22:58:16.467891 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 22:58:16.469870 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 22:58:16.470680 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 22:58:16.472987 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 22:58:16.473877 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 22:58:16.476142 runner path: /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/0/tests/0_dmesg test_uuid 713197_1.5.2.4.1
178 22:58:16.476731 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 22:58:16.477503 Creating lava-test-runner.conf files
181 22:58:16.477708 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/713197/lava-overlay-muf6yv6h/lava-713197/0 for stage 0
182 22:58:16.478059 - 0_dmesg
183 22:58:16.478408 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 22:58:16.478687 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 22:58:16.502529 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 22:58:16.502940 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 22:58:16.503205 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 22:58:16.503471 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 22:58:16.503737 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 22:58:17.536374 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 22:58:17.536850 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 22:58:17.537098 extracting modules file /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/713197/extract-overlay-ramdisk-g4e6s6nn/ramdisk
193 22:58:18.864244 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 22:58:18.864727 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 22:58:18.865000 [common] Applying overlay /var/lib/lava/dispatcher/tmp/713197/compress-overlay-9utknrru/overlay-1.5.2.5.tar.gz to ramdisk
196 22:58:18.865215 [common] Applying overlay /var/lib/lava/dispatcher/tmp/713197/compress-overlay-9utknrru/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/713197/extract-overlay-ramdisk-g4e6s6nn/ramdisk
197 22:58:18.895724 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 22:58:18.896182 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 22:58:18.896458 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 22:58:18.896687 Converting downloaded kernel to a uImage
201 22:58:18.896990 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/kernel/Image /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/kernel/uImage
202 22:58:19.281067 output: Image Name:
203 22:58:19.281482 output: Created: Thu Sep 5 22:58:18 2024
204 22:58:19.281694 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 22:58:19.281901 output: Data Size: 37407232 Bytes = 36530.50 KiB = 35.67 MiB
206 22:58:19.282105 output: Load Address: 01080000
207 22:58:19.282308 output: Entry Point: 01080000
208 22:58:19.282505 output:
209 22:58:19.282836 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 22:58:19.283102 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 22:58:19.283371 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 22:58:19.283623 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 22:58:19.283879 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 22:58:19.284171 Building ramdisk /var/lib/lava/dispatcher/tmp/713197/extract-overlay-ramdisk-g4e6s6nn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/713197/extract-overlay-ramdisk-g4e6s6nn/ramdisk
215 22:58:21.888770 >> 186582 blocks
216 22:58:30.323430 Adding RAMdisk u-boot header.
217 22:58:30.324184 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/713197/extract-overlay-ramdisk-g4e6s6nn/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/713197/extract-overlay-ramdisk-g4e6s6nn/ramdisk.cpio.gz.uboot
218 22:58:30.603636 output: Image Name:
219 22:58:30.604186 output: Created: Thu Sep 5 22:58:30 2024
220 22:58:30.604705 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 22:58:30.605225 output: Data Size: 26585359 Bytes = 25962.26 KiB = 25.35 MiB
222 22:58:30.605736 output: Load Address: 00000000
223 22:58:30.606234 output: Entry Point: 00000000
224 22:58:30.606725 output:
225 22:58:30.608008 rename /var/lib/lava/dispatcher/tmp/713197/extract-overlay-ramdisk-g4e6s6nn/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/ramdisk/ramdisk.cpio.gz.uboot
226 22:58:30.608821 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 22:58:30.609457 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 22:58:30.610076 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 22:58:30.610603 No LXC device requested
230 22:58:30.611195 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 22:58:30.611779 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 22:58:30.612409 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 22:58:30.612896 Checking files for TFTP limit of 4294967296 bytes.
234 22:58:30.615940 end: 1 tftp-deploy (duration 00:00:17) [common]
235 22:58:30.616651 start: 2 uboot-action (timeout 00:05:00) [common]
236 22:58:30.617264 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 22:58:30.617841 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 22:58:30.618407 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 22:58:30.619018 Using kernel file from prepare-kernel: 713197/tftp-deploy-7cyhqjj5/kernel/uImage
240 22:58:30.619722 substitutions:
241 22:58:30.620299 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 22:58:30.620777 - {DTB_ADDR}: 0x01070000
243 22:58:30.621259 - {DTB}: 713197/tftp-deploy-7cyhqjj5/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 22:58:30.621767 - {INITRD}: 713197/tftp-deploy-7cyhqjj5/ramdisk/ramdisk.cpio.gz.uboot
245 22:58:30.622250 - {KERNEL_ADDR}: 0x01080000
246 22:58:30.622726 - {KERNEL}: 713197/tftp-deploy-7cyhqjj5/kernel/uImage
247 22:58:30.623170 - {LAVA_MAC}: None
248 22:58:30.623666 - {PRESEED_CONFIG}: None
249 22:58:30.624156 - {PRESEED_LOCAL}: None
250 22:58:30.624590 - {RAMDISK_ADDR}: 0x08000000
251 22:58:30.625019 - {RAMDISK}: 713197/tftp-deploy-7cyhqjj5/ramdisk/ramdisk.cpio.gz.uboot
252 22:58:30.625464 - {ROOT_PART}: None
253 22:58:30.625917 - {ROOT}: None
254 22:58:30.626351 - {SERVER_IP}: 192.168.6.2
255 22:58:30.626803 - {TEE_ADDR}: 0x83000000
256 22:58:30.627253 - {TEE}: None
257 22:58:30.627686 Parsed boot commands:
258 22:58:30.628159 - setenv autoload no
259 22:58:30.628618 - setenv initrd_high 0xffffffff
260 22:58:30.629048 - setenv fdt_high 0xffffffff
261 22:58:30.629488 - dhcp
262 22:58:30.629926 - setenv serverip 192.168.6.2
263 22:58:30.630385 - tftpboot 0x01080000 713197/tftp-deploy-7cyhqjj5/kernel/uImage
264 22:58:30.630817 - tftpboot 0x08000000 713197/tftp-deploy-7cyhqjj5/ramdisk/ramdisk.cpio.gz.uboot
265 22:58:30.631244 - tftpboot 0x01070000 713197/tftp-deploy-7cyhqjj5/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 22:58:30.631670 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 22:58:30.632151 - bootm 0x01080000 0x08000000 0x01070000
268 22:58:30.632718 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 22:58:30.634348 start: 2.3 connect-device (timeout 00:05:00) [common]
271 22:58:30.634837 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 22:58:30.649129 Setting prompt string to ['lava-test: # ']
273 22:58:30.650742 end: 2.3 connect-device (duration 00:00:00) [common]
274 22:58:30.651403 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 22:58:30.652034 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 22:58:30.652615 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 22:58:30.653851 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 22:58:30.688289 >> OK - accepted request
279 22:58:30.690561 Returned 0 in 0 seconds
280 22:58:30.791921 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 22:58:30.793914 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 22:58:30.794601 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 22:58:30.795191 Setting prompt string to ['Hit any key to stop autoboot']
285 22:58:30.795708 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 22:58:30.797509 Trying 192.168.56.21...
287 22:58:30.798114 Connected to conserv1.
288 22:58:30.798637 Escape character is '^]'.
289 22:58:30.799126
290 22:58:30.799641 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 22:58:30.800156
292 22:58:37.674099 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 22:58:37.674775 bl2_stage_init 0x01
294 22:58:37.675278 bl2_stage_init 0x81
295 22:58:37.679743 hw id: 0x0000 - pwm id 0x01
296 22:58:37.680304 bl2_stage_init 0xc1
297 22:58:37.680777 bl2_stage_init 0x02
298 22:58:37.681242
299 22:58:37.685435 L0:00000000
300 22:58:37.685945 L1:00000703
301 22:58:37.686412 L2:00008067
302 22:58:37.686858 L3:15000000
303 22:58:37.687316 S1:00000000
304 22:58:37.691265 B2:20282000
305 22:58:37.691745 B1:a0f83180
306 22:58:37.692229
307 22:58:37.692675 TE: 69669
308 22:58:37.693115
309 22:58:37.696525 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 22:58:37.697055
311 22:58:37.702113 Board ID = 1
312 22:58:37.702654 Set cpu clk to 24M
313 22:58:37.703129 Set clk81 to 24M
314 22:58:37.707686 Use GP1_pll as DSU clk.
315 22:58:37.708294 DSU clk: 1200 Mhz
316 22:58:37.708775 CPU clk: 1200 MHz
317 22:58:37.709231 Set clk81 to 166.6M
318 22:58:37.718802 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 22:58:37.719397 board id: 1
320 22:58:37.725193 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 22:58:37.735855 fw parse done
322 22:58:37.740907 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 22:58:37.784501 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 22:58:37.795353 PIEI prepare done
325 22:58:37.795876 fastboot data load
326 22:58:37.796358 fastboot data verify
327 22:58:37.801010 verify result: 266
328 22:58:37.806579 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 22:58:37.807045 LPDDR4 probe
330 22:58:37.807485 ddr clk to 1584MHz
331 22:58:37.814592 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 22:58:37.851870
333 22:58:37.852500 dmc_version 0001
334 22:58:37.858514 Check phy result
335 22:58:37.864483 INFO : End of CA training
336 22:58:37.864973 INFO : End of initialization
337 22:58:37.870108 INFO : Training has run successfully!
338 22:58:37.870578 Check phy result
339 22:58:37.875852 INFO : End of initialization
340 22:58:37.876190 INFO : End of read enable training
341 22:58:37.878839 INFO : End of fine write leveling
342 22:58:37.884507 INFO : End of Write leveling coarse delay
343 22:58:37.890041 INFO : Training has run successfully!
344 22:58:37.890531 Check phy result
345 22:58:37.890969 INFO : End of initialization
346 22:58:37.895706 INFO : End of read dq deskew training
347 22:58:37.899063 INFO : End of MPR read delay center optimization
348 22:58:37.904675 INFO : End of write delay center optimization
349 22:58:37.910368 INFO : End of read delay center optimization
350 22:58:37.910832 INFO : End of max read latency training
351 22:58:37.915831 INFO : Training has run successfully!
352 22:58:37.916330 1D training succeed
353 22:58:37.924220 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 22:58:37.971612 Check phy result
355 22:58:37.972031 INFO : End of initialization
356 22:58:37.993959 INFO : End of 2D read delay Voltage center optimization
357 22:58:38.013306 INFO : End of 2D read delay Voltage center optimization
358 22:58:38.064971 INFO : End of 2D write delay Voltage center optimization
359 22:58:38.114237 INFO : End of 2D write delay Voltage center optimization
360 22:58:38.119795 INFO : Training has run successfully!
361 22:58:38.120400
362 22:58:38.120871 channel==0
363 22:58:38.125383 RxClkDly_Margin_A0==78 ps 8
364 22:58:38.125956 TxDqDly_Margin_A0==98 ps 10
365 22:58:38.130890 RxClkDly_Margin_A1==69 ps 7
366 22:58:38.131447 TxDqDly_Margin_A1==98 ps 10
367 22:58:38.131895 TrainedVREFDQ_A0==75
368 22:58:38.136586 TrainedVREFDQ_A1==75
369 22:58:38.137180 VrefDac_Margin_A0==24
370 22:58:38.137625 DeviceVref_Margin_A0==39
371 22:58:38.142210 VrefDac_Margin_A1==23
372 22:58:38.142528 DeviceVref_Margin_A1==39
373 22:58:38.142760
374 22:58:38.142978
375 22:58:38.147699 channel==1
376 22:58:38.148304 RxClkDly_Margin_A0==88 ps 9
377 22:58:38.148769 TxDqDly_Margin_A0==98 ps 10
378 22:58:38.153315 RxClkDly_Margin_A1==78 ps 8
379 22:58:38.153861 TxDqDly_Margin_A1==88 ps 9
380 22:58:38.158921 TrainedVREFDQ_A0==78
381 22:58:38.159451 TrainedVREFDQ_A1==75
382 22:58:38.159894 VrefDac_Margin_A0==23
383 22:58:38.164469 DeviceVref_Margin_A0==36
384 22:58:38.165008 VrefDac_Margin_A1==22
385 22:58:38.170134 DeviceVref_Margin_A1==39
386 22:58:38.170466
387 22:58:38.170677 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 22:58:38.170877
389 22:58:38.203696 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 22:58:38.204420 2D training succeed
391 22:58:38.209329 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 22:58:38.214737 auto size-- 65535DDR cs0 size: 2048MB
393 22:58:38.215047 DDR cs1 size: 2048MB
394 22:58:38.220517 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 22:58:38.221092 cs0 DataBus test pass
396 22:58:38.226106 cs1 DataBus test pass
397 22:58:38.226674 cs0 AddrBus test pass
398 22:58:38.227123 cs1 AddrBus test pass
399 22:58:38.227559
400 22:58:38.231769 100bdlr_step_size ps== 464
401 22:58:38.232354 result report
402 22:58:38.237290 boot times 0Enable ddr reg access
403 22:58:38.242588 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 22:58:38.256444 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 22:58:38.911279 bl2z: ptr: 05129330, size: 00001e40
406 22:58:38.917685 0.0;M3 CHK:0;cm4_sp_mode 0
407 22:58:38.918214 MVN_1=0x00000000
408 22:58:38.918695 MVN_2=0x00000000
409 22:58:38.929240 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 22:58:38.929807 OPS=0x04
411 22:58:38.930272 ring efuse init
412 22:58:38.932180 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 22:58:38.938172 [0.017319 Inits done]
414 22:58:38.938676 secure task start!
415 22:58:38.939137 high task start!
416 22:58:38.939587 low task start!
417 22:58:38.942400 run into bl31
418 22:58:38.951027 NOTICE: BL31: v1.3(release):4fc40b1
419 22:58:38.958875 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 22:58:38.959178 NOTICE: BL31: G12A normal boot!
421 22:58:38.974342 NOTICE: BL31: BL33 decompress pass
422 22:58:38.980147 ERROR: Error initializing runtime service opteed_fast
423 22:58:40.221288 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 22:58:40.221967 bl2_stage_init 0x01
425 22:58:40.222464 bl2_stage_init 0x81
426 22:58:40.226715 hw id: 0x0000 - pwm id 0x01
427 22:58:40.227291 bl2_stage_init 0xc1
428 22:58:40.232462 bl2_stage_init 0x02
429 22:58:40.232821
430 22:58:40.233048 L0:00000000
431 22:58:40.233306 L1:00000703
432 22:58:40.233533 L2:00008067
433 22:58:40.233741 L3:15000000
434 22:58:40.237888 S1:00000000
435 22:58:40.238204 B2:20282000
436 22:58:40.238425 B1:a0f83180
437 22:58:40.238633
438 22:58:40.238837 TE: 68539
439 22:58:40.239220
440 22:58:40.243438 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 22:58:40.243737
442 22:58:40.249141 Board ID = 1
443 22:58:40.249438 Set cpu clk to 24M
444 22:58:40.249666 Set clk81 to 24M
445 22:58:40.254751 Use GP1_pll as DSU clk.
446 22:58:40.255204 DSU clk: 1200 Mhz
447 22:58:40.255553 CPU clk: 1200 MHz
448 22:58:40.260285 Set clk81 to 166.6M
449 22:58:40.265906 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 22:58:40.266229 board id: 1
451 22:58:40.273053 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 22:58:40.284049 fw parse done
453 22:58:40.288993 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 22:58:40.333699 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 22:58:40.344235 PIEI prepare done
456 22:58:40.344699 fastboot data load
457 22:58:40.344958 fastboot data verify
458 22:58:40.349795 verify result: 266
459 22:58:40.355362 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 22:58:40.355680 LPDDR4 probe
461 22:58:40.355900 ddr clk to 1584MHz
462 22:58:41.726885 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
463 22:58:41.727475 bl2_stage_init 0x01
464 22:58:41.727791 bl2_stage_init 0x81
465 22:58:41.732331 hw id: 0x0000 - pwm id 0x01
466 22:58:41.732728 bl2_stage_init 0xc1
467 22:58:41.737850 bl2_stage_init 0x02
468 22:58:41.738183
469 22:58:41.738433 L0:00000000
470 22:58:41.738743 L1:00000703
471 22:58:41.738992 L2:00008067
472 22:58:41.739225 L3:15000000
473 22:58:41.743494 S1:00000000
474 22:58:41.743907 B2:20282000
475 22:58:41.744247 B1:a0f83180
476 22:58:41.744612
477 22:58:41.744929 TE: 73017
478 22:58:41.745221
479 22:58:41.749029 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
480 22:58:41.749403
481 22:58:41.754616 Board ID = 1
482 22:58:41.754962 Set cpu clk to 24M
483 22:58:41.755194 Set clk81 to 24M
484 22:58:41.760378 Use GP1_pll as DSU clk.
485 22:58:41.760807 DSU clk: 1200 Mhz
486 22:58:41.761110 CPU clk: 1200 MHz
487 22:58:41.765869 Set clk81 to 166.6M
488 22:58:41.771389 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
489 22:58:41.771685 board id: 1
490 22:58:41.778723 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
491 22:58:41.789362 fw parse done
492 22:58:41.794961 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
493 22:58:41.837928 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
494 22:58:41.848887 PIEI prepare done
495 22:58:41.849426 fastboot data load
496 22:58:41.849813 fastboot data verify
497 22:58:41.854465 verify result: 266
498 22:58:41.860052 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
499 22:58:41.860356 LPDDR4 probe
500 22:58:41.860578 ddr clk to 1584MHz
501 22:58:41.867080 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
502 22:58:41.905350
503 22:58:41.905721 dmc_version 0001
504 22:58:41.911937 Check phy result
505 22:58:41.917892 INFO : End of CA training
506 22:58:41.918275 INFO : End of initialization
507 22:58:41.923573 INFO : Training has run successfully!
508 22:58:41.923896 Check phy result
509 22:58:41.929131 INFO : End of initialization
510 22:58:41.929554 INFO : End of read enable training
511 22:58:41.932391 INFO : End of fine write leveling
512 22:58:41.938061 INFO : End of Write leveling coarse delay
513 22:58:41.943602 INFO : Training has run successfully!
514 22:58:41.943921 Check phy result
515 22:58:41.944177 INFO : End of initialization
516 22:58:41.949206 INFO : End of read dq deskew training
517 22:58:41.954779 INFO : End of MPR read delay center optimization
518 22:58:41.955200 INFO : End of write delay center optimization
519 22:58:41.960424 INFO : End of read delay center optimization
520 22:58:41.966044 INFO : End of max read latency training
521 22:58:41.966515 INFO : Training has run successfully!
522 22:58:41.971584 1D training succeed
523 22:58:41.977526 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
524 22:58:42.025187 Check phy result
525 22:58:42.025720 INFO : End of initialization
526 22:58:42.047627 INFO : End of 2D read delay Voltage center optimization
527 22:58:42.066648 INFO : End of 2D read delay Voltage center optimization
528 22:58:42.118695 INFO : End of 2D write delay Voltage center optimization
529 22:58:42.167661 INFO : End of 2D write delay Voltage center optimization
530 22:58:42.173221 INFO : Training has run successfully!
531 22:58:42.173646
532 22:58:42.173926 channel==0
533 22:58:42.178853 RxClkDly_Margin_A0==78 ps 8
534 22:58:42.179395 TxDqDly_Margin_A0==98 ps 10
535 22:58:42.184512 RxClkDly_Margin_A1==88 ps 9
536 22:58:42.185014 TxDqDly_Margin_A1==98 ps 10
537 22:58:42.185458 TrainedVREFDQ_A0==74
538 22:58:42.190114 TrainedVREFDQ_A1==75
539 22:58:42.190981 VrefDac_Margin_A0==24
540 22:58:42.191819 DeviceVref_Margin_A0==40
541 22:58:42.195667 VrefDac_Margin_A1==23
542 22:58:42.196573 DeviceVref_Margin_A1==39
543 22:58:42.197439
544 22:58:42.198218
545 22:58:42.201400 channel==1
546 22:58:42.201895 RxClkDly_Margin_A0==88 ps 9
547 22:58:42.202411 TxDqDly_Margin_A0==98 ps 10
548 22:58:42.206832 RxClkDly_Margin_A1==78 ps 8
549 22:58:42.207329 TxDqDly_Margin_A1==78 ps 8
550 22:58:42.212518 TrainedVREFDQ_A0==78
551 22:58:42.213396 TrainedVREFDQ_A1==75
552 22:58:42.214144 VrefDac_Margin_A0==22
553 22:58:42.218061 DeviceVref_Margin_A0==36
554 22:58:42.218845 VrefDac_Margin_A1==22
555 22:58:42.223600 DeviceVref_Margin_A1==39
556 22:58:42.224136
557 22:58:42.224653 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
558 22:58:42.225094
559 22:58:42.257181 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
560 22:58:42.257805 2D training succeed
561 22:58:42.262771 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
562 22:58:42.268493 auto size-- 65535DDR cs0 size: 2048MB
563 22:58:42.269022 DDR cs1 size: 2048MB
564 22:58:42.274009 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
565 22:58:42.274523 cs0 DataBus test pass
566 22:58:42.279572 cs1 DataBus test pass
567 22:58:42.280113 cs0 AddrBus test pass
568 22:58:42.280563 cs1 AddrBus test pass
569 22:58:42.280999
570 22:58:42.285150 100bdlr_step_size ps== 478
571 22:58:42.285671 result report
572 22:58:42.290777 boot times 0Enable ddr reg access
573 22:58:42.296088 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
574 22:58:42.309979 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
575 22:58:42.964804 bl2z: ptr: 05129330, size: 00001e40
576 22:58:42.971182 0.0;M3 CHK:0;cm4_sp_mode 0
577 22:58:42.972269 MVN_1=0x00000000
578 22:58:42.973003 MVN_2=0x00000000
579 22:58:42.982688 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
580 22:58:42.983344 OPS=0x04
581 22:58:42.983972 ring efuse init
582 22:58:42.988241 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
583 22:58:42.988944 [0.017319 Inits done]
584 22:58:42.989499 secure task start!
585 22:58:42.995614 high task start!
586 22:58:42.996185 low task start!
587 22:58:42.996717 run into bl31
588 22:58:43.004099 NOTICE: BL31: v1.3(release):4fc40b1
589 22:58:43.010984 NOTICE: BL31: Built : 15:57:33, May 22 2019
590 22:58:43.011507 NOTICE: BL31: G12A normal boot!
591 22:58:43.027568 NOTICE: BL31: BL33 decompress pass
592 22:58:43.033119 ERROR: Error initializing runtime service opteed_fast
593 22:58:44.274545 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
594 22:58:44.274932 bl2_stage_init 0x01
595 22:58:44.275149 bl2_stage_init 0x81
596 22:58:44.280002 hw id: 0x0000 - pwm id 0x01
597 22:58:44.280290 bl2_stage_init 0xc1
598 22:58:44.285558 bl2_stage_init 0x02
599 22:58:44.285868
600 22:58:44.286082 L0:00000000
601 22:58:44.286287 L1:00000703
602 22:58:44.286489 L2:00008067
603 22:58:44.286693 L3:15000000
604 22:58:44.291175 S1:00000000
605 22:58:44.291440 B2:20282000
606 22:58:44.291649 B1:a0f83180
607 22:58:44.291847
608 22:58:44.292073 TE: 71556
609 22:58:44.292276
610 22:58:44.296803 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
611 22:58:44.297110
612 22:58:44.302322 Board ID = 1
613 22:58:44.302594 Set cpu clk to 24M
614 22:58:44.302803 Set clk81 to 24M
615 22:58:44.307945 Use GP1_pll as DSU clk.
616 22:58:44.308276 DSU clk: 1200 Mhz
617 22:58:44.308491 CPU clk: 1200 MHz
618 22:58:44.313443 Set clk81 to 166.6M
619 22:58:44.319263 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
620 22:58:44.319562 board id: 1
621 22:58:44.325559 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
622 22:58:44.337222 fw parse done
623 22:58:44.343218 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
624 22:58:44.385653 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
625 22:58:44.397515 PIEI prepare done
626 22:58:44.397854 fastboot data load
627 22:58:44.398078 fastboot data verify
628 22:58:44.403082 verify result: 266
629 22:58:44.408675 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
630 22:58:44.408999 LPDDR4 probe
631 22:58:44.409222 ddr clk to 1584MHz
632 22:58:44.416607 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
633 22:58:44.454475
634 22:58:44.454887 dmc_version 0001
635 22:58:44.461356 Check phy result
636 22:58:44.467373 INFO : End of CA training
637 22:58:44.467704 INFO : End of initialization
638 22:58:44.473029 INFO : Training has run successfully!
639 22:58:44.473378 Check phy result
640 22:58:44.478514 INFO : End of initialization
641 22:58:44.478834 INFO : End of read enable training
642 22:58:44.484216 INFO : End of fine write leveling
643 22:58:44.489879 INFO : End of Write leveling coarse delay
644 22:58:44.490229 INFO : Training has run successfully!
645 22:58:44.490455 Check phy result
646 22:58:44.495461 INFO : End of initialization
647 22:58:44.495786 INFO : End of read dq deskew training
648 22:58:44.501104 INFO : End of MPR read delay center optimization
649 22:58:44.506609 INFO : End of write delay center optimization
650 22:58:44.512178 INFO : End of read delay center optimization
651 22:58:44.512529 INFO : End of max read latency training
652 22:58:44.517860 INFO : Training has run successfully!
653 22:58:44.518200 1D training succeed
654 22:58:44.526991 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
655 22:58:44.574359 Check phy result
656 22:58:44.574771 INFO : End of initialization
657 22:58:44.602747 INFO : End of 2D read delay Voltage center optimization
658 22:58:44.626878 INFO : End of 2D read delay Voltage center optimization
659 22:58:44.683529 INFO : End of 2D write delay Voltage center optimization
660 22:58:44.737447 INFO : End of 2D write delay Voltage center optimization
661 22:58:44.742971 INFO : Training has run successfully!
662 22:58:44.743222
663 22:58:44.743423 channel==0
664 22:58:44.748541 RxClkDly_Margin_A0==78 ps 8
665 22:58:44.748775 TxDqDly_Margin_A0==98 ps 10
666 22:58:44.751870 RxClkDly_Margin_A1==88 ps 9
667 22:58:44.752130 TxDqDly_Margin_A1==88 ps 9
668 22:58:44.757473 TrainedVREFDQ_A0==77
669 22:58:44.757709 TrainedVREFDQ_A1==74
670 22:58:44.757910 VrefDac_Margin_A0==24
671 22:58:44.763082 DeviceVref_Margin_A0==37
672 22:58:44.763315 VrefDac_Margin_A1==23
673 22:58:44.768853 DeviceVref_Margin_A1==40
674 22:58:44.769082
675 22:58:44.769282
676 22:58:44.769479 channel==1
677 22:58:44.769673 RxClkDly_Margin_A0==88 ps 9
678 22:58:44.774357 TxDqDly_Margin_A0==98 ps 10
679 22:58:44.774598 RxClkDly_Margin_A1==88 ps 9
680 22:58:44.779928 TxDqDly_Margin_A1==88 ps 9
681 22:58:44.780183 TrainedVREFDQ_A0==78
682 22:58:44.780387 TrainedVREFDQ_A1==77
683 22:58:44.785467 VrefDac_Margin_A0==22
684 22:58:44.785708 DeviceVref_Margin_A0==36
685 22:58:44.785908 VrefDac_Margin_A1==22
686 22:58:44.791127 DeviceVref_Margin_A1==37
687 22:58:44.791362
688 22:58:44.796829 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
689 22:58:44.797072
690 22:58:44.824705 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000016 dram_vref_reg_value 0x 00000061
691 22:58:44.830320 2D training succeed
692 22:58:44.835898 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
693 22:58:44.836154 auto size-- 65535DDR cs0 size: 2048MB
694 22:58:44.841519 DDR cs1 size: 2048MB
695 22:58:44.841754 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
696 22:58:44.847105 cs0 DataBus test pass
697 22:58:44.847338 cs1 DataBus test pass
698 22:58:44.847537 cs0 AddrBus test pass
699 22:58:44.852841 cs1 AddrBus test pass
700 22:58:44.853091
701 22:58:44.853295 100bdlr_step_size ps== 471
702 22:58:44.853498 result report
703 22:58:44.858362 boot times 0Enable ddr reg access
704 22:58:44.865708 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
705 22:58:44.879571 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
706 22:58:45.538630 bl2z: ptr: 05129330, size: 00001e40
707 22:58:45.547542 0.0;M3 CHK:0;cm4_sp_mode 0
708 22:58:45.548087 MVN_1=0x00000000
709 22:58:45.548550 MVN_2=0x00000000
710 22:58:45.559116 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
711 22:58:45.559660 OPS=0x04
712 22:58:45.560160 ring efuse init
713 22:58:45.561995 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
714 22:58:45.567469 [0.017354 Inits done]
715 22:58:45.567945 secure task start!
716 22:58:45.568487 high task start!
717 22:58:45.568960 low task start!
718 22:58:45.572811 run into bl31
719 22:58:45.581438 NOTICE: BL31: v1.3(release):4fc40b1
720 22:58:45.588900 NOTICE: BL31: Built : 15:57:33, May 22 2019
721 22:58:45.589386 NOTICE: BL31: G12A normal boot!
722 22:58:45.605055 NOTICE: BL31: BL33 decompress pass
723 22:58:45.610533 ERROR: Error initializing runtime service opteed_fast
724 22:58:46.405863
725 22:58:46.406481
726 22:58:46.411241 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
727 22:58:46.411727
728 22:58:46.413858 Model: Libre Computer AML-S905D3-CC Solitude
729 22:58:46.561787 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
730 22:58:46.577215 DRAM: 2 GiB (effective 3.8 GiB)
731 22:58:46.678216 Core: 406 devices, 33 uclasses, devicetree: separate
732 22:58:46.684165 WDT: Not starting watchdog@f0d0
733 22:58:46.709114 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
734 22:58:46.721499 Loading Environment from FAT... Card did not respond to voltage select! : -110
735 22:58:46.725568 ** Bad device specification mmc 0 **
736 22:58:46.736709 Card did not respond to voltage select! : -110
737 22:58:46.744754 ** Bad device specification mmc 0 **
738 22:58:46.745093 Couldn't find partition mmc 0
739 22:58:46.752716 Card did not respond to voltage select! : -110
740 22:58:46.758241 ** Bad device specification mmc 0 **
741 22:58:46.758564 Couldn't find partition mmc 0
742 22:58:46.763029 Error: could not access storage.
743 22:58:47.059840 Net: eth0: ethernet@ff3f0000
744 22:58:47.060274 starting USB...
745 22:58:47.305143 Bus usb@ff500000: Register 3000140 NbrPorts 3
746 22:58:47.305876 Starting the controller
747 22:58:47.311974 USB XHCI 1.10
748 22:58:48.865269 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
749 22:58:48.873639 scanning usb for storage devices... 0 Storage Device(s) found
751 22:58:48.925375 Hit any key to stop autoboot: 1
752 22:58:48.926605 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
753 22:58:48.927265 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
754 22:58:48.927781 Setting prompt string to ['=>']
755 22:58:48.928342 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
756 22:58:48.939673 0
757 22:58:48.940738 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
759 22:58:49.042136 => setenv autoload no
760 22:58:49.043272 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
761 22:58:49.048826 setenv autoload no
763 22:58:49.150532 => setenv initrd_high 0xffffffff
764 22:58:49.151453 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
765 22:58:49.155726 setenv initrd_high 0xffffffff
767 22:58:49.257201 => setenv fdt_high 0xffffffff
768 22:58:49.258063 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
769 22:58:49.262487 setenv fdt_high 0xffffffff
771 22:58:49.364092 => dhcp
772 22:58:49.365095 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
773 22:58:49.369210 dhcp
774 22:58:49.924673 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
775 22:58:49.925183 Speed: 1000, full duplex
776 22:58:49.925420 BOOTP broadcast 1
777 22:58:50.337660 BOOTP broadcast 2
778 22:58:50.673785 BOOTP broadcast 3
779 22:58:51.675017 BOOTP broadcast 4
780 22:58:53.675784 BOOTP broadcast 5
781 22:58:53.693689 DHCP client bound to address 192.168.6.12 (3762 ms)
783 22:58:53.795148 => setenv serverip 192.168.6.2
784 22:58:53.795745 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
785 22:58:53.800217 setenv serverip 192.168.6.2
787 22:58:53.901349 => tftpboot 0x01080000 713197/tftp-deploy-7cyhqjj5/kernel/uImage
788 22:58:53.901947 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
789 22:58:53.908578 tftpboot 0x01080000 713197/tftp-deploy-7cyhqjj5/kernel/uImage
790 22:58:53.908899 Speed: 1000, full duplex
791 22:58:53.909123 Using ethernet@ff3f0000 device
792 22:58:53.914110 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
793 22:58:53.919643 Filename '713197/tftp-deploy-7cyhqjj5/kernel/uImage'.
794 22:58:53.923709 Load address: 0x1080000
795 22:58:56.360356 Loading: *################################################## 35.7 MiB
796 22:58:56.361021 14.6 MiB/s
797 22:58:56.361527 done
798 22:58:56.364681 Bytes transferred = 37407296 (23aca40 hex)
800 22:58:56.466496 => tftpboot 0x08000000 713197/tftp-deploy-7cyhqjj5/ramdisk/ramdisk.cpio.gz.uboot
801 22:58:56.467727 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
802 22:58:56.475730 tftpboot 0x08000000 713197/tftp-deploy-7cyhqjj5/ramdisk/ramdisk.cpio.gz.uboot
803 22:58:56.476609 Speed: 1000, full duplex
804 22:58:56.477338 Using ethernet@ff3f0000 device
805 22:58:56.481227 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
806 22:58:56.490933 Filename '713197/tftp-deploy-7cyhqjj5/ramdisk/ramdisk.cpio.gz.uboot'.
807 22:58:56.491822 Load address: 0x8000000
808 22:58:58.128883 Loading: *################################################# UDP wrong checksum 00000005 0000ffbe
809 22:59:03.128840 T UDP wrong checksum 00000005 0000ffbe
810 22:59:13.130629 T T UDP wrong checksum 00000005 0000ffbe
811 22:59:23.053702 T UDP wrong checksum 000000ff 0000e883
812 22:59:23.080564 UDP wrong checksum 000000ff 00007976
813 22:59:33.131368 T T UDP wrong checksum 00000005 0000ffbe
814 22:59:53.139522 T T T T
815 22:59:53.139966 Retry count exceeded; starting again
817 22:59:53.140974 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
820 22:59:53.142051 end: 2.4 uboot-commands (duration 00:01:22) [common]
822 22:59:53.142838 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
824 22:59:53.143449 end: 2 uboot-action (duration 00:01:23) [common]
826 22:59:53.144420 Cleaning after the job
827 22:59:53.144753 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/ramdisk
828 22:59:53.145736 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/kernel
829 22:59:53.165674 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/dtb
830 22:59:53.166618 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713197/tftp-deploy-7cyhqjj5/modules
831 22:59:53.187404 start: 4.1 power-off (timeout 00:00:30) [common]
832 22:59:53.188084 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
833 22:59:53.221741 >> OK - accepted request
834 22:59:53.224510 Returned 0 in 0 seconds
835 22:59:53.325364 end: 4.1 power-off (duration 00:00:00) [common]
837 22:59:53.326340 start: 4.2 read-feedback (timeout 00:10:00) [common]
838 22:59:53.327003 Listened to connection for namespace 'common' for up to 1s
839 22:59:54.327913 Finalising connection for namespace 'common'
840 22:59:54.328442 Disconnecting from shell: Finalise
841 22:59:54.328737 =>
842 22:59:54.429407 end: 4.2 read-feedback (duration 00:00:01) [common]
843 22:59:54.429907 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/713197
844 22:59:54.689001 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/713197
845 22:59:54.689594 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.