Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:22:55.755730 lava-dispatcher, installed at version: 2024.01
2 00:22:55.756512 start: 0 validate
3 00:22:55.756988 Start time: 2024-09-06 00:22:55.756958+00:00 (UTC)
4 00:22:55.757515 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:22:55.758041 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:22:55.796707 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:22:55.797257 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2Fclang-15%2Fkernel%2FImage exists
8 00:22:55.824675 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:22:55.825277 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2Fclang-15%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:22:55.856401 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:22:55.856875 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:22:55.885921 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:22:55.886385 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6-75-gad618736883b8%2Farm64%2Fdefconfig%2Fclang-15%2Fmodules.tar.xz exists
14 00:22:55.925667 validate duration: 0.17
16 00:22:55.926475 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:22:55.926798 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:22:55.927116 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:22:55.927743 Not decompressing ramdisk as can be used compressed.
20 00:22:55.928208 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:22:55.928495 saving as /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/ramdisk/initrd.cpio.gz
22 00:22:55.928768 total size: 5628169 (5 MB)
23 00:22:55.966909 progress 0 % (0 MB)
24 00:22:55.973818 progress 5 % (0 MB)
25 00:22:55.981566 progress 10 % (0 MB)
26 00:22:55.988466 progress 15 % (0 MB)
27 00:22:55.995951 progress 20 % (1 MB)
28 00:22:55.999507 progress 25 % (1 MB)
29 00:22:56.003414 progress 30 % (1 MB)
30 00:22:56.007359 progress 35 % (1 MB)
31 00:22:56.010838 progress 40 % (2 MB)
32 00:22:56.014719 progress 45 % (2 MB)
33 00:22:56.018193 progress 50 % (2 MB)
34 00:22:56.022054 progress 55 % (2 MB)
35 00:22:56.025957 progress 60 % (3 MB)
36 00:22:56.029439 progress 65 % (3 MB)
37 00:22:56.033408 progress 70 % (3 MB)
38 00:22:56.036881 progress 75 % (4 MB)
39 00:22:56.040749 progress 80 % (4 MB)
40 00:22:56.044208 progress 85 % (4 MB)
41 00:22:56.047919 progress 90 % (4 MB)
42 00:22:56.051485 progress 95 % (5 MB)
43 00:22:56.054670 progress 100 % (5 MB)
44 00:22:56.055286 5 MB downloaded in 0.13 s (42.43 MB/s)
45 00:22:56.055790 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:22:56.056717 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:22:56.057007 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:22:56.057272 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:22:56.057734 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig/clang-15/kernel/Image
51 00:22:56.057982 saving as /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/kernel/Image
52 00:22:56.058192 total size: 37407232 (35 MB)
53 00:22:56.058400 No compression specified
54 00:22:56.092379 progress 0 % (0 MB)
55 00:22:56.115483 progress 5 % (1 MB)
56 00:22:56.138520 progress 10 % (3 MB)
57 00:22:56.161116 progress 15 % (5 MB)
58 00:22:56.183685 progress 20 % (7 MB)
59 00:22:56.206346 progress 25 % (8 MB)
60 00:22:56.229209 progress 30 % (10 MB)
61 00:22:56.251721 progress 35 % (12 MB)
62 00:22:56.274291 progress 40 % (14 MB)
63 00:22:56.297092 progress 45 % (16 MB)
64 00:22:56.319708 progress 50 % (17 MB)
65 00:22:56.342608 progress 55 % (19 MB)
66 00:22:56.365211 progress 60 % (21 MB)
67 00:22:56.387922 progress 65 % (23 MB)
68 00:22:56.410369 progress 70 % (25 MB)
69 00:22:56.433039 progress 75 % (26 MB)
70 00:22:56.455610 progress 80 % (28 MB)
71 00:22:56.478173 progress 85 % (30 MB)
72 00:22:56.500618 progress 90 % (32 MB)
73 00:22:56.523284 progress 95 % (33 MB)
74 00:22:56.545068 progress 100 % (35 MB)
75 00:22:56.545694 35 MB downloaded in 0.49 s (73.18 MB/s)
76 00:22:56.546160 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:22:56.546973 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:22:56.547245 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:22:56.547510 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:22:56.547968 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig/clang-15/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 00:22:56.548261 saving as /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/dtb/meson-g12b-a311d-libretech-cc.dtb
83 00:22:56.548471 total size: 54667 (0 MB)
84 00:22:56.548678 No compression specified
85 00:22:56.587119 progress 59 % (0 MB)
86 00:22:56.587943 progress 100 % (0 MB)
87 00:22:56.588506 0 MB downloaded in 0.04 s (1.30 MB/s)
88 00:22:56.588978 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:22:56.589786 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:22:56.590047 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:22:56.590309 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:22:56.590752 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:22:56.590987 saving as /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/nfsrootfs/full.rootfs.tar
95 00:22:56.591192 total size: 120894716 (115 MB)
96 00:22:56.591401 Using unxz to decompress xz
97 00:22:56.624527 progress 0 % (0 MB)
98 00:22:57.405017 progress 5 % (5 MB)
99 00:22:58.232578 progress 10 % (11 MB)
100 00:22:59.024745 progress 15 % (17 MB)
101 00:22:59.759531 progress 20 % (23 MB)
102 00:23:00.349489 progress 25 % (28 MB)
103 00:23:01.174778 progress 30 % (34 MB)
104 00:23:01.962687 progress 35 % (40 MB)
105 00:23:02.308138 progress 40 % (46 MB)
106 00:23:02.677541 progress 45 % (51 MB)
107 00:23:03.386166 progress 50 % (57 MB)
108 00:23:04.282892 progress 55 % (63 MB)
109 00:23:05.061912 progress 60 % (69 MB)
110 00:23:05.811440 progress 65 % (74 MB)
111 00:23:06.587289 progress 70 % (80 MB)
112 00:23:07.419080 progress 75 % (86 MB)
113 00:23:08.200807 progress 80 % (92 MB)
114 00:23:08.956787 progress 85 % (98 MB)
115 00:23:09.802035 progress 90 % (103 MB)
116 00:23:10.568824 progress 95 % (109 MB)
117 00:23:11.399815 progress 100 % (115 MB)
118 00:23:11.412214 115 MB downloaded in 14.82 s (7.78 MB/s)
119 00:23:11.413096 end: 1.4.1 http-download (duration 00:00:15) [common]
121 00:23:11.414723 end: 1.4 download-retry (duration 00:00:15) [common]
122 00:23:11.415260 start: 1.5 download-retry (timeout 00:09:45) [common]
123 00:23:11.415785 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 00:23:11.416812 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig/clang-15/modules.tar.xz
125 00:23:11.417301 saving as /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/modules/modules.tar
126 00:23:11.417723 total size: 11642308 (11 MB)
127 00:23:11.418152 Using unxz to decompress xz
128 00:23:11.460846 progress 0 % (0 MB)
129 00:23:11.529235 progress 5 % (0 MB)
130 00:23:11.607063 progress 10 % (1 MB)
131 00:23:11.694917 progress 15 % (1 MB)
132 00:23:11.775905 progress 20 % (2 MB)
133 00:23:11.851319 progress 25 % (2 MB)
134 00:23:11.934674 progress 30 % (3 MB)
135 00:23:12.013940 progress 35 % (3 MB)
136 00:23:12.092677 progress 40 % (4 MB)
137 00:23:12.167263 progress 45 % (5 MB)
138 00:23:12.245193 progress 50 % (5 MB)
139 00:23:12.321610 progress 55 % (6 MB)
140 00:23:12.405920 progress 60 % (6 MB)
141 00:23:12.487143 progress 65 % (7 MB)
142 00:23:12.568922 progress 70 % (7 MB)
143 00:23:12.660961 progress 75 % (8 MB)
144 00:23:12.755390 progress 80 % (8 MB)
145 00:23:12.836538 progress 85 % (9 MB)
146 00:23:12.907364 progress 90 % (10 MB)
147 00:23:12.987244 progress 95 % (10 MB)
148 00:23:13.064130 progress 100 % (11 MB)
149 00:23:13.077073 11 MB downloaded in 1.66 s (6.69 MB/s)
150 00:23:13.077934 end: 1.5.1 http-download (duration 00:00:02) [common]
152 00:23:13.079529 end: 1.5 download-retry (duration 00:00:02) [common]
153 00:23:13.080080 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 00:23:13.080599 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 00:23:29.979025 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/713216/extract-nfsrootfs-tuvtlek3
156 00:23:29.979624 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 00:23:29.979913 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 00:23:29.980605 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy
159 00:23:29.981066 makedir: /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin
160 00:23:29.981396 makedir: /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/tests
161 00:23:29.981706 makedir: /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/results
162 00:23:29.982033 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-add-keys
163 00:23:29.982554 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-add-sources
164 00:23:29.983086 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-background-process-start
165 00:23:29.983618 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-background-process-stop
166 00:23:29.984169 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-common-functions
167 00:23:29.984685 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-echo-ipv4
168 00:23:29.985165 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-install-packages
169 00:23:29.985639 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-installed-packages
170 00:23:29.986108 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-os-build
171 00:23:29.986582 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-probe-channel
172 00:23:29.987075 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-probe-ip
173 00:23:29.987576 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-target-ip
174 00:23:29.988071 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-target-mac
175 00:23:29.988629 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-target-storage
176 00:23:29.989124 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-test-case
177 00:23:29.989600 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-test-event
178 00:23:29.990072 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-test-feedback
179 00:23:29.990542 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-test-raise
180 00:23:29.991024 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-test-reference
181 00:23:29.991519 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-test-runner
182 00:23:29.992013 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-test-set
183 00:23:29.992518 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-test-shell
184 00:23:29.993009 Updating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-add-keys (debian)
185 00:23:29.993538 Updating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-add-sources (debian)
186 00:23:29.994058 Updating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-install-packages (debian)
187 00:23:29.994560 Updating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-installed-packages (debian)
188 00:23:29.995051 Updating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/bin/lava-os-build (debian)
189 00:23:29.995478 Creating /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/environment
190 00:23:29.995841 LAVA metadata
191 00:23:29.996118 - LAVA_JOB_ID=713216
192 00:23:29.996334 - LAVA_DISPATCHER_IP=192.168.6.2
193 00:23:29.996693 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 00:23:29.997628 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 00:23:29.997933 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 00:23:29.998140 skipped lava-vland-overlay
197 00:23:29.998380 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 00:23:29.998633 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 00:23:29.998850 skipped lava-multinode-overlay
200 00:23:29.999091 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 00:23:29.999341 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 00:23:29.999586 Loading test definitions
203 00:23:29.999858 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 00:23:30.000115 Using /lava-713216 at stage 0
205 00:23:30.001326 uuid=713216_1.6.2.4.1 testdef=None
206 00:23:30.001638 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 00:23:30.001900 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 00:23:30.003456 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 00:23:30.004269 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 00:23:30.006175 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 00:23:30.006986 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 00:23:30.008812 runner path: /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/0/tests/0_timesync-off test_uuid 713216_1.6.2.4.1
215 00:23:30.009347 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 00:23:30.010155 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 00:23:30.010394 Using /lava-713216 at stage 0
219 00:23:30.010745 Fetching tests from https://github.com/kernelci/test-definitions.git
220 00:23:30.011030 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/0/tests/1_kselftest-rtc'
221 00:23:33.368408 Running '/usr/bin/git checkout kernelci.org
222 00:23:33.690965 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 00:23:33.693576 uuid=713216_1.6.2.4.5 testdef=None
224 00:23:33.694375 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 00:23:33.696321 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 00:23:33.703224 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 00:23:33.705278 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 00:23:33.714427 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 00:23:33.716646 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 00:23:33.725650 runner path: /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/0/tests/1_kselftest-rtc test_uuid 713216_1.6.2.4.5
234 00:23:33.726319 BOARD='meson-g12b-a311d-libretech-cc'
235 00:23:33.726846 BRANCH='mainline'
236 00:23:33.727340 SKIPFILE='/dev/null'
237 00:23:33.727843 SKIP_INSTALL='True'
238 00:23:33.728391 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6-75-gad618736883b8/arm64/defconfig/clang-15/kselftest.tar.xz'
239 00:23:33.728919 TST_CASENAME=''
240 00:23:33.729432 TST_CMDFILES='rtc'
241 00:23:33.730658 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 00:23:33.732689 Creating lava-test-runner.conf files
244 00:23:33.733210 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/713216/lava-overlay-id1htsmy/lava-713216/0 for stage 0
245 00:23:33.734010 - 0_timesync-off
246 00:23:33.734589 - 1_kselftest-rtc
247 00:23:33.735369 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 00:23:33.736084 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 00:23:58.568455 end: 1.6.2.5 compress-overlay (duration 00:00:25) [common]
250 00:23:58.568981 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 00:23:58.569351 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 00:23:58.569725 end: 1.6.2 lava-overlay (duration 00:00:29) [common]
253 00:23:58.570086 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 00:23:59.194035 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 00:23:59.194512 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 00:23:59.194763 extracting modules file /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/modules/modules.tar to /var/lib/lava/dispatcher/tmp/713216/extract-nfsrootfs-tuvtlek3
257 00:24:00.545324 extracting modules file /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/modules/modules.tar to /var/lib/lava/dispatcher/tmp/713216/extract-overlay-ramdisk-yjvi27d9/ramdisk
258 00:24:01.935137 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 00:24:01.935623 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 00:24:01.935900 [common] Applying overlay to NFS
261 00:24:01.936144 [common] Applying overlay /var/lib/lava/dispatcher/tmp/713216/compress-overlay-770j8yc2/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/713216/extract-nfsrootfs-tuvtlek3
262 00:24:04.649319 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 00:24:04.649765 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 00:24:04.650038 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 00:24:04.650268 Converting downloaded kernel to a uImage
266 00:24:04.650575 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/kernel/Image /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/kernel/uImage
267 00:24:05.038349 output: Image Name:
268 00:24:05.038777 output: Created: Fri Sep 6 00:24:04 2024
269 00:24:05.038988 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 00:24:05.039191 output: Data Size: 37407232 Bytes = 36530.50 KiB = 35.67 MiB
271 00:24:05.039393 output: Load Address: 01080000
272 00:24:05.039593 output: Entry Point: 01080000
273 00:24:05.039790 output:
274 00:24:05.040156 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 00:24:05.040434 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 00:24:05.040704 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 00:24:05.040958 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 00:24:05.041216 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 00:24:05.041481 Building ramdisk /var/lib/lava/dispatcher/tmp/713216/extract-overlay-ramdisk-yjvi27d9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/713216/extract-overlay-ramdisk-yjvi27d9/ramdisk
280 00:24:07.238551 >> 171799 blocks
281 00:24:15.289475 Adding RAMdisk u-boot header.
282 00:24:15.289909 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/713216/extract-overlay-ramdisk-yjvi27d9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/713216/extract-overlay-ramdisk-yjvi27d9/ramdisk.cpio.gz.uboot
283 00:24:15.545339 output: Image Name:
284 00:24:15.545755 output: Created: Fri Sep 6 00:24:15 2024
285 00:24:15.545967 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 00:24:15.546173 output: Data Size: 23959897 Bytes = 23398.34 KiB = 22.85 MiB
287 00:24:15.546376 output: Load Address: 00000000
288 00:24:15.546576 output: Entry Point: 00000000
289 00:24:15.546776 output:
290 00:24:15.547362 rename /var/lib/lava/dispatcher/tmp/713216/extract-overlay-ramdisk-yjvi27d9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/ramdisk/ramdisk.cpio.gz.uboot
291 00:24:15.547773 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 00:24:15.548221 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 00:24:15.548816 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 00:24:15.549344 No LXC device requested
295 00:24:15.549905 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 00:24:15.550469 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 00:24:15.551017 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 00:24:15.551469 Checking files for TFTP limit of 4294967296 bytes.
299 00:24:15.554396 end: 1 tftp-deploy (duration 00:01:20) [common]
300 00:24:15.555025 start: 2 uboot-action (timeout 00:05:00) [common]
301 00:24:15.555597 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 00:24:15.556179 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 00:24:15.556735 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 00:24:15.557309 Using kernel file from prepare-kernel: 713216/tftp-deploy-p1jqj5ld/kernel/uImage
305 00:24:15.558003 substitutions:
306 00:24:15.558449 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 00:24:15.558893 - {DTB_ADDR}: 0x01070000
308 00:24:15.559331 - {DTB}: 713216/tftp-deploy-p1jqj5ld/dtb/meson-g12b-a311d-libretech-cc.dtb
309 00:24:15.559771 - {INITRD}: 713216/tftp-deploy-p1jqj5ld/ramdisk/ramdisk.cpio.gz.uboot
310 00:24:15.560247 - {KERNEL_ADDR}: 0x01080000
311 00:24:15.560688 - {KERNEL}: 713216/tftp-deploy-p1jqj5ld/kernel/uImage
312 00:24:15.561124 - {LAVA_MAC}: None
313 00:24:15.561606 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/713216/extract-nfsrootfs-tuvtlek3
314 00:24:15.562046 - {NFS_SERVER_IP}: 192.168.6.2
315 00:24:15.562477 - {PRESEED_CONFIG}: None
316 00:24:15.562907 - {PRESEED_LOCAL}: None
317 00:24:15.563342 - {RAMDISK_ADDR}: 0x08000000
318 00:24:15.563768 - {RAMDISK}: 713216/tftp-deploy-p1jqj5ld/ramdisk/ramdisk.cpio.gz.uboot
319 00:24:15.564231 - {ROOT_PART}: None
320 00:24:15.564662 - {ROOT}: None
321 00:24:15.565089 - {SERVER_IP}: 192.168.6.2
322 00:24:15.565514 - {TEE_ADDR}: 0x83000000
323 00:24:15.565937 - {TEE}: None
324 00:24:15.566364 Parsed boot commands:
325 00:24:15.566777 - setenv autoload no
326 00:24:15.567200 - setenv initrd_high 0xffffffff
327 00:24:15.567620 - setenv fdt_high 0xffffffff
328 00:24:15.568069 - dhcp
329 00:24:15.568495 - setenv serverip 192.168.6.2
330 00:24:15.568919 - tftpboot 0x01080000 713216/tftp-deploy-p1jqj5ld/kernel/uImage
331 00:24:15.569350 - tftpboot 0x08000000 713216/tftp-deploy-p1jqj5ld/ramdisk/ramdisk.cpio.gz.uboot
332 00:24:15.569777 - tftpboot 0x01070000 713216/tftp-deploy-p1jqj5ld/dtb/meson-g12b-a311d-libretech-cc.dtb
333 00:24:15.570206 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/713216/extract-nfsrootfs-tuvtlek3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 00:24:15.570646 - bootm 0x01080000 0x08000000 0x01070000
335 00:24:15.571190 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 00:24:15.572908 start: 2.3 connect-device (timeout 00:05:00) [common]
338 00:24:15.573372 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 00:24:15.588711 Setting prompt string to ['lava-test: # ']
340 00:24:15.590355 end: 2.3 connect-device (duration 00:00:00) [common]
341 00:24:15.591028 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 00:24:15.591636 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 00:24:15.592261 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 00:24:15.593516 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 00:24:15.627918 >> OK - accepted request
346 00:24:15.630076 Returned 0 in 0 seconds
347 00:24:15.731250 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 00:24:15.733057 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 00:24:15.733657 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 00:24:15.734215 Setting prompt string to ['Hit any key to stop autoboot']
352 00:24:15.734714 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 00:24:15.736438 Trying 192.168.56.21...
354 00:24:15.736981 Connected to conserv1.
355 00:24:15.737443 Escape character is '^]'.
356 00:24:15.737889
357 00:24:15.738356 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 00:24:15.738822
359 00:24:27.160287 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 00:24:27.160705 bl2_stage_init 0x01
361 00:24:27.160931 bl2_stage_init 0x81
362 00:24:27.165823 hw id: 0x0000 - pwm id 0x01
363 00:24:27.166125 bl2_stage_init 0xc1
364 00:24:27.166346 bl2_stage_init 0x02
365 00:24:27.166552
366 00:24:27.171405 L0:00000000
367 00:24:27.171685 L1:20000703
368 00:24:27.171907 L2:00008067
369 00:24:27.172167 L3:14000000
370 00:24:27.174353 B2:00402000
371 00:24:27.174601 B1:e0f83180
372 00:24:27.174819
373 00:24:27.175018 TE: 58124
374 00:24:27.175217
375 00:24:27.185411 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 00:24:27.185671
377 00:24:27.185875 Board ID = 1
378 00:24:27.186071 Set A53 clk to 24M
379 00:24:27.186264 Set A73 clk to 24M
380 00:24:27.190965 Set clk81 to 24M
381 00:24:27.191208 A53 clk: 1200 MHz
382 00:24:27.191407 A73 clk: 1200 MHz
383 00:24:27.196625 CLK81: 166.6M
384 00:24:27.196881 smccc: 00012a92
385 00:24:27.202231 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 00:24:27.202496 board id: 1
387 00:24:27.207771 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 00:24:27.221585 fw parse done
389 00:24:27.227001 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 00:24:27.269227 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 00:24:27.281044 PIEI prepare done
392 00:24:27.281326 fastboot data load
393 00:24:27.281533 fastboot data verify
394 00:24:27.286691 verify result: 266
395 00:24:27.292247 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 00:24:27.292518 LPDDR4 probe
397 00:24:27.292728 ddr clk to 1584MHz
398 00:24:27.299335 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 00:24:27.336526
400 00:24:27.336856 dmc_version 0001
401 00:24:27.343182 Check phy result
402 00:24:27.350039 INFO : End of CA training
403 00:24:27.350318 INFO : End of initialization
404 00:24:27.355654 INFO : Training has run successfully!
405 00:24:27.355933 Check phy result
406 00:24:27.361223 INFO : End of initialization
407 00:24:27.361479 INFO : End of read enable training
408 00:24:27.366825 INFO : End of fine write leveling
409 00:24:27.372447 INFO : End of Write leveling coarse delay
410 00:24:27.372730 INFO : Training has run successfully!
411 00:24:27.372945 Check phy result
412 00:24:27.378008 INFO : End of initialization
413 00:24:27.378297 INFO : End of read dq deskew training
414 00:24:27.383658 INFO : End of MPR read delay center optimization
415 00:24:27.389207 INFO : End of write delay center optimization
416 00:24:27.394834 INFO : End of read delay center optimization
417 00:24:27.395094 INFO : End of max read latency training
418 00:24:27.400420 INFO : Training has run successfully!
419 00:24:27.400684 1D training succeed
420 00:24:27.408983 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 00:24:27.456454 Check phy result
422 00:24:27.456787 INFO : End of initialization
423 00:24:27.478834 INFO : End of 2D read delay Voltage center optimization
424 00:24:27.499086 INFO : End of 2D read delay Voltage center optimization
425 00:24:27.550236 INFO : End of 2D write delay Voltage center optimization
426 00:24:27.600597 INFO : End of 2D write delay Voltage center optimization
427 00:24:27.606144 INFO : Training has run successfully!
428 00:24:27.606403
429 00:24:27.606612 channel==0
430 00:24:27.611747 RxClkDly_Margin_A0==88 ps 9
431 00:24:27.612043 TxDqDly_Margin_A0==98 ps 10
432 00:24:27.617371 RxClkDly_Margin_A1==88 ps 9
433 00:24:27.617641 TxDqDly_Margin_A1==88 ps 9
434 00:24:27.617850 TrainedVREFDQ_A0==74
435 00:24:27.623064 TrainedVREFDQ_A1==74
436 00:24:27.623322 VrefDac_Margin_A0==24
437 00:24:27.623532 DeviceVref_Margin_A0==40
438 00:24:27.628560 VrefDac_Margin_A1==24
439 00:24:27.628819 DeviceVref_Margin_A1==40
440 00:24:27.629021
441 00:24:27.629223
442 00:24:27.629425 channel==1
443 00:24:27.634182 RxClkDly_Margin_A0==78 ps 8
444 00:24:27.634437 TxDqDly_Margin_A0==88 ps 9
445 00:24:27.639730 RxClkDly_Margin_A1==88 ps 9
446 00:24:27.640016 TxDqDly_Margin_A1==88 ps 9
447 00:24:27.645355 TrainedVREFDQ_A0==77
448 00:24:27.645614 TrainedVREFDQ_A1==77
449 00:24:27.645819 VrefDac_Margin_A0==23
450 00:24:27.651050 DeviceVref_Margin_A0==37
451 00:24:27.651305 VrefDac_Margin_A1==24
452 00:24:27.651509 DeviceVref_Margin_A1==37
453 00:24:27.656586
454 00:24:27.656847 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 00:24:27.657055
456 00:24:27.690148 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 00:24:27.690495 2D training succeed
458 00:24:27.695714 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 00:24:27.701367 auto size-- 65535DDR cs0 size: 2048MB
460 00:24:27.701632 DDR cs1 size: 2048MB
461 00:24:27.707078 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 00:24:27.707342 cs0 DataBus test pass
463 00:24:27.712540 cs1 DataBus test pass
464 00:24:27.712800 cs0 AddrBus test pass
465 00:24:27.713007 cs1 AddrBus test pass
466 00:24:27.713209
467 00:24:27.718145 100bdlr_step_size ps== 420
468 00:24:27.718409 result report
469 00:24:27.723792 boot times 0Enable ddr reg access
470 00:24:27.728023 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 00:24:27.742250 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 00:24:28.316033 0.0;M3 CHK:0;cm4_sp_mode 0
473 00:24:28.316653 MVN_1=0x00000000
474 00:24:28.321440 MVN_2=0x00000000
475 00:24:28.327202 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 00:24:28.327694 OPS=0x10
477 00:24:28.328182 ring efuse init
478 00:24:28.328631 chipver efuse init
479 00:24:28.332779 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 00:24:28.338381 [0.018961 Inits done]
481 00:24:28.338853 secure task start!
482 00:24:28.339303 high task start!
483 00:24:28.342520 low task start!
484 00:24:28.343001 run into bl31
485 00:24:28.349629 NOTICE: BL31: v1.3(release):4fc40b1
486 00:24:28.356541 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 00:24:28.357023 NOTICE: BL31: G12A normal boot!
488 00:24:28.382740 NOTICE: BL31: BL33 decompress pass
489 00:24:28.387479 ERROR: Error initializing runtime service opteed_fast
490 00:24:29.621484
491 00:24:29.622120
492 00:24:29.628909 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 00:24:29.629399
494 00:24:29.629850 Model: Libre Computer AML-A311D-CC Alta
495 00:24:29.838099 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 00:24:29.860521 DRAM: 2 GiB (effective 3.8 GiB)
497 00:24:30.004513 Core: 408 devices, 31 uclasses, devicetree: separate
498 00:24:30.010452 WDT: Not starting watchdog@f0d0
499 00:24:30.042617 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 00:24:30.055067 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 00:24:30.059946 ** Bad device specification mmc 0 **
502 00:24:30.070394 Card did not respond to voltage select! : -110
503 00:24:30.077916 ** Bad device specification mmc 0 **
504 00:24:30.078387 Couldn't find partition mmc 0
505 00:24:30.086361 Card did not respond to voltage select! : -110
506 00:24:30.091866 ** Bad device specification mmc 0 **
507 00:24:30.092387 Couldn't find partition mmc 0
508 00:24:30.096078 Error: could not access storage.
509 00:24:31.360648 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 00:24:31.361306 bl2_stage_init 0x01
511 00:24:31.361780 bl2_stage_init 0x81
512 00:24:31.366150 hw id: 0x0000 - pwm id 0x01
513 00:24:31.366650 bl2_stage_init 0xc1
514 00:24:31.367106 bl2_stage_init 0x02
515 00:24:31.367551
516 00:24:31.371787 L0:00000000
517 00:24:31.372296 L1:20000703
518 00:24:31.372745 L2:00008067
519 00:24:31.373187 L3:14000000
520 00:24:31.377333 B2:00402000
521 00:24:31.377815 B1:e0f83180
522 00:24:31.378261
523 00:24:31.378705 TE: 58159
524 00:24:31.379146
525 00:24:31.382949 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 00:24:31.383428
527 00:24:31.383877 Board ID = 1
528 00:24:31.388529 Set A53 clk to 24M
529 00:24:31.389006 Set A73 clk to 24M
530 00:24:31.389455 Set clk81 to 24M
531 00:24:31.394164 A53 clk: 1200 MHz
532 00:24:31.394638 A73 clk: 1200 MHz
533 00:24:31.395082 CLK81: 166.6M
534 00:24:31.395522 smccc: 00012ab5
535 00:24:31.399720 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 00:24:31.405311 board id: 1
537 00:24:31.410278 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 00:24:31.421861 fw parse done
539 00:24:31.427149 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 00:24:31.470251 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 00:24:31.481372 PIEI prepare done
542 00:24:31.481852 fastboot data load
543 00:24:31.482307 fastboot data verify
544 00:24:31.487174 verify result: 266
545 00:24:31.492635 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 00:24:31.493111 LPDDR4 probe
547 00:24:31.493556 ddr clk to 1584MHz
548 00:24:31.500571 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 00:24:31.537977
550 00:24:31.538470 dmc_version 0001
551 00:24:31.543628 Check phy result
552 00:24:31.550419 INFO : End of CA training
553 00:24:31.550902 INFO : End of initialization
554 00:24:31.556060 INFO : Training has run successfully!
555 00:24:31.556537 Check phy result
556 00:24:31.561621 INFO : End of initialization
557 00:24:31.562092 INFO : End of read enable training
558 00:24:31.567252 INFO : End of fine write leveling
559 00:24:31.572814 INFO : End of Write leveling coarse delay
560 00:24:31.573284 INFO : Training has run successfully!
561 00:24:31.573728 Check phy result
562 00:24:31.578422 INFO : End of initialization
563 00:24:31.578895 INFO : End of read dq deskew training
564 00:24:31.584017 INFO : End of MPR read delay center optimization
565 00:24:31.589613 INFO : End of write delay center optimization
566 00:24:31.595260 INFO : End of read delay center optimization
567 00:24:31.595731 INFO : End of max read latency training
568 00:24:31.600815 INFO : Training has run successfully!
569 00:24:31.601290 1D training succeed
570 00:24:31.609048 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 00:24:31.657646 Check phy result
572 00:24:31.658186 INFO : End of initialization
573 00:24:31.679171 INFO : End of 2D read delay Voltage center optimization
574 00:24:31.698774 INFO : End of 2D read delay Voltage center optimization
575 00:24:31.750729 INFO : End of 2D write delay Voltage center optimization
576 00:24:31.800967 INFO : End of 2D write delay Voltage center optimization
577 00:24:31.806683 INFO : Training has run successfully!
578 00:24:31.807155
579 00:24:31.807608 channel==0
580 00:24:31.812154 RxClkDly_Margin_A0==88 ps 9
581 00:24:31.812634 TxDqDly_Margin_A0==98 ps 10
582 00:24:31.815453 RxClkDly_Margin_A1==88 ps 9
583 00:24:31.815924 TxDqDly_Margin_A1==98 ps 10
584 00:24:31.820961 TrainedVREFDQ_A0==74
585 00:24:31.821435 TrainedVREFDQ_A1==74
586 00:24:31.826656 VrefDac_Margin_A0==25
587 00:24:31.827128 DeviceVref_Margin_A0==40
588 00:24:31.827570 VrefDac_Margin_A1==25
589 00:24:31.832315 DeviceVref_Margin_A1==40
590 00:24:31.832789
591 00:24:31.833237
592 00:24:31.833683 channel==1
593 00:24:31.834122 RxClkDly_Margin_A0==98 ps 10
594 00:24:31.837819 TxDqDly_Margin_A0==88 ps 9
595 00:24:31.838297 RxClkDly_Margin_A1==88 ps 9
596 00:24:31.843371 TxDqDly_Margin_A1==88 ps 9
597 00:24:31.843852 TrainedVREFDQ_A0==77
598 00:24:31.844340 TrainedVREFDQ_A1==77
599 00:24:31.848994 VrefDac_Margin_A0==22
600 00:24:31.849475 DeviceVref_Margin_A0==37
601 00:24:31.854687 VrefDac_Margin_A1==24
602 00:24:31.855161 DeviceVref_Margin_A1==37
603 00:24:31.855606
604 00:24:31.860258 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 00:24:31.860744
606 00:24:31.888237 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 00:24:31.893832 2D training succeed
608 00:24:31.899349 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 00:24:31.899835 auto size-- 65535DDR cs0 size: 2048MB
610 00:24:31.904977 DDR cs1 size: 2048MB
611 00:24:31.905460 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 00:24:31.910807 cs0 DataBus test pass
613 00:24:31.911286 cs1 DataBus test pass
614 00:24:31.911737 cs0 AddrBus test pass
615 00:24:31.916232 cs1 AddrBus test pass
616 00:24:31.916707
617 00:24:31.917156 100bdlr_step_size ps== 420
618 00:24:31.917607 result report
619 00:24:31.921800 boot times 0Enable ddr reg access
620 00:24:31.928422 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 00:24:31.941987 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 00:24:32.516773 0.0;M3 CHK:0;cm4_sp_mode 0
623 00:24:32.517398 MVN_1=0x00000000
624 00:24:32.522256 MVN_2=0x00000000
625 00:24:32.528044 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 00:24:32.528562 OPS=0x10
627 00:24:32.529034 ring efuse init
628 00:24:32.529498 chipver efuse init
629 00:24:32.533560 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 00:24:32.539097 [0.018961 Inits done]
631 00:24:32.539563 secure task start!
632 00:24:32.540024 high task start!
633 00:24:32.542869 low task start!
634 00:24:32.543321 run into bl31
635 00:24:32.550336 NOTICE: BL31: v1.3(release):4fc40b1
636 00:24:32.557337 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 00:24:32.557817 NOTICE: BL31: G12A normal boot!
638 00:24:32.583550 NOTICE: BL31: BL33 decompress pass
639 00:24:32.588332 ERROR: Error initializing runtime service opteed_fast
640 00:24:33.821920
641 00:24:33.822563
642 00:24:33.830332 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 00:24:33.830832
644 00:24:33.831294 Model: Libre Computer AML-A311D-CC Alta
645 00:24:34.038694 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 00:24:34.062097 DRAM: 2 GiB (effective 3.8 GiB)
647 00:24:34.205122 Core: 408 devices, 31 uclasses, devicetree: separate
648 00:24:34.210272 WDT: Not starting watchdog@f0d0
649 00:24:34.243433 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 00:24:34.255791 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 00:24:34.260796 ** Bad device specification mmc 0 **
652 00:24:34.270998 Card did not respond to voltage select! : -110
653 00:24:34.277900 ** Bad device specification mmc 0 **
654 00:24:34.278385 Couldn't find partition mmc 0
655 00:24:34.287330 Card did not respond to voltage select! : -110
656 00:24:34.292526 ** Bad device specification mmc 0 **
657 00:24:34.293013 Couldn't find partition mmc 0
658 00:24:34.296784 Error: could not access storage.
659 00:24:34.639543 Net: eth0: ethernet@ff3f0000
660 00:24:34.640237 starting USB...
661 00:24:34.891977 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 00:24:34.892650 Starting the controller
663 00:24:34.898755 USB XHCI 1.10
664 00:24:36.610932 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 00:24:36.611602 bl2_stage_init 0x01
666 00:24:36.612130 bl2_stage_init 0x81
667 00:24:36.617467 hw id: 0x0000 - pwm id 0x01
668 00:24:36.617959 bl2_stage_init 0xc1
669 00:24:36.618417 bl2_stage_init 0x02
670 00:24:36.618868
671 00:24:36.622247 L0:00000000
672 00:24:36.622754 L1:20000703
673 00:24:36.623213 L2:00008067
674 00:24:36.623657 L3:14000000
675 00:24:36.627873 B2:00402000
676 00:24:36.628402 B1:e0f83180
677 00:24:36.628892
678 00:24:36.629366 TE: 58159
679 00:24:36.629840
680 00:24:36.633625 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 00:24:36.634135
682 00:24:36.634588 Board ID = 1
683 00:24:36.639051 Set A53 clk to 24M
684 00:24:36.639525 Set A73 clk to 24M
685 00:24:36.639970 Set clk81 to 24M
686 00:24:36.644624 A53 clk: 1200 MHz
687 00:24:36.645149 A73 clk: 1200 MHz
688 00:24:36.645615 CLK81: 166.6M
689 00:24:36.646073 smccc: 00012ab5
690 00:24:36.650261 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 00:24:36.655826 board id: 1
692 00:24:36.661148 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 00:24:36.672565 fw parse done
694 00:24:36.677655 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 00:24:36.720836 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 00:24:36.731802 PIEI prepare done
697 00:24:36.732368 fastboot data load
698 00:24:36.732844 fastboot data verify
699 00:24:36.737448 verify result: 266
700 00:24:36.742964 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 00:24:36.743472 LPDDR4 probe
702 00:24:36.743935 ddr clk to 1584MHz
703 00:24:36.751025 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 00:24:36.787432
705 00:24:36.788019 dmc_version 0001
706 00:24:36.794726 Check phy result
707 00:24:36.800725 INFO : End of CA training
708 00:24:36.801194 INFO : End of initialization
709 00:24:36.806439 INFO : Training has run successfully!
710 00:24:36.806909 Check phy result
711 00:24:36.811932 INFO : End of initialization
712 00:24:36.812429 INFO : End of read enable training
713 00:24:36.817575 INFO : End of fine write leveling
714 00:24:36.823170 INFO : End of Write leveling coarse delay
715 00:24:36.823637 INFO : Training has run successfully!
716 00:24:36.824084 Check phy result
717 00:24:36.828728 INFO : End of initialization
718 00:24:36.829197 INFO : End of read dq deskew training
719 00:24:36.834415 INFO : End of MPR read delay center optimization
720 00:24:36.839928 INFO : End of write delay center optimization
721 00:24:36.845586 INFO : End of read delay center optimization
722 00:24:36.846058 INFO : End of max read latency training
723 00:24:36.851118 INFO : Training has run successfully!
724 00:24:36.851582 1D training succeed
725 00:24:36.860263 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 00:24:36.907205 Check phy result
727 00:24:36.907720 INFO : End of initialization
728 00:24:36.929640 INFO : End of 2D read delay Voltage center optimization
729 00:24:36.949728 INFO : End of 2D read delay Voltage center optimization
730 00:24:37.001522 INFO : End of 2D write delay Voltage center optimization
731 00:24:37.051210 INFO : End of 2D write delay Voltage center optimization
732 00:24:37.056795 INFO : Training has run successfully!
733 00:24:37.057274
734 00:24:37.057701 channel==0
735 00:24:37.062411 RxClkDly_Margin_A0==88 ps 9
736 00:24:37.062866 TxDqDly_Margin_A0==98 ps 10
737 00:24:37.068050 RxClkDly_Margin_A1==88 ps 9
738 00:24:37.068553 TxDqDly_Margin_A1==88 ps 9
739 00:24:37.068981 TrainedVREFDQ_A0==74
740 00:24:37.073720 TrainedVREFDQ_A1==74
741 00:24:37.074195 VrefDac_Margin_A0==25
742 00:24:37.074617 DeviceVref_Margin_A0==40
743 00:24:37.079220 VrefDac_Margin_A1==25
744 00:24:37.079679 DeviceVref_Margin_A1==40
745 00:24:37.080130
746 00:24:37.080550
747 00:24:37.080962 channel==1
748 00:24:37.084805 RxClkDly_Margin_A0==98 ps 10
749 00:24:37.085271 TxDqDly_Margin_A0==88 ps 9
750 00:24:37.090392 RxClkDly_Margin_A1==88 ps 9
751 00:24:37.090850 TxDqDly_Margin_A1==88 ps 9
752 00:24:37.096032 TrainedVREFDQ_A0==74
753 00:24:37.096504 TrainedVREFDQ_A1==77
754 00:24:37.096921 VrefDac_Margin_A0==22
755 00:24:37.101614 DeviceVref_Margin_A0==40
756 00:24:37.102070 VrefDac_Margin_A1==24
757 00:24:37.107198 DeviceVref_Margin_A1==37
758 00:24:37.107651
759 00:24:37.108104 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 00:24:37.108522
761 00:24:37.140865 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 00:24:37.141365 2D training succeed
763 00:24:37.146421 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 00:24:37.152070 auto size-- 65535DDR cs0 size: 2048MB
765 00:24:37.152539 DDR cs1 size: 2048MB
766 00:24:37.157581 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 00:24:37.158037 cs0 DataBus test pass
768 00:24:37.163205 cs1 DataBus test pass
769 00:24:37.163669 cs0 AddrBus test pass
770 00:24:37.164117 cs1 AddrBus test pass
771 00:24:37.164535
772 00:24:37.168782 100bdlr_step_size ps== 420
773 00:24:37.169254 result report
774 00:24:37.174409 boot times 0Enable ddr reg access
775 00:24:37.178669 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 00:24:37.192368 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 00:24:37.766797 0.0;M3 CHK:0;cm4_sp_mode 0
778 00:24:37.767376 MVN_1=0x00000000
779 00:24:37.772240 MVN_2=0x00000000
780 00:24:37.778028 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 00:24:37.778558 OPS=0x10
782 00:24:37.778956 ring efuse init
783 00:24:37.779345 chipver efuse init
784 00:24:37.783591 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 00:24:37.789195 [0.018960 Inits done]
786 00:24:37.789636 secure task start!
787 00:24:37.790030 high task start!
788 00:24:37.792897 low task start!
789 00:24:37.793327 run into bl31
790 00:24:37.800498 NOTICE: BL31: v1.3(release):4fc40b1
791 00:24:37.807513 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 00:24:37.807959 NOTICE: BL31: G12A normal boot!
793 00:24:37.833670 NOTICE: BL31: BL33 decompress pass
794 00:24:37.838378 ERROR: Error initializing runtime service opteed_fast
795 00:24:39.072338
796 00:24:39.072977
797 00:24:39.079873 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 00:24:39.080388
799 00:24:39.080815 Model: Libre Computer AML-A311D-CC Alta
800 00:24:39.288100 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 00:24:39.311413 DRAM: 2 GiB (effective 3.8 GiB)
802 00:24:39.455397 Core: 408 devices, 31 uclasses, devicetree: separate
803 00:24:39.460911 WDT: Not starting watchdog@f0d0
804 00:24:39.493420 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 00:24:39.505942 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 00:24:39.509954 ** Bad device specification mmc 0 **
807 00:24:39.521210 Card did not respond to voltage select! : -110
808 00:24:39.528399 ** Bad device specification mmc 0 **
809 00:24:39.528853 Couldn't find partition mmc 0
810 00:24:39.537230 Card did not respond to voltage select! : -110
811 00:24:39.542744 ** Bad device specification mmc 0 **
812 00:24:39.543201 Couldn't find partition mmc 0
813 00:24:39.546817 Error: could not access storage.
814 00:24:39.890402 Net: eth0: ethernet@ff3f0000
815 00:24:39.890995 starting USB...
816 00:24:40.143109 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 00:24:40.143694 Starting the controller
818 00:24:40.150050 USB XHCI 1.10
819 00:24:42.310888 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 00:24:42.311488 bl2_stage_init 0x01
821 00:24:42.311917 bl2_stage_init 0x81
822 00:24:42.316498 hw id: 0x0000 - pwm id 0x01
823 00:24:42.316965 bl2_stage_init 0xc1
824 00:24:42.317385 bl2_stage_init 0x02
825 00:24:42.317795
826 00:24:42.322130 L0:00000000
827 00:24:42.322580 L1:20000703
828 00:24:42.322987 L2:00008067
829 00:24:42.323390 L3:14000000
830 00:24:42.324971 B2:00402000
831 00:24:42.325703 B1:e0f83180
832 00:24:42.326127
833 00:24:42.326562 TE: 58124
834 00:24:42.326992
835 00:24:42.336115 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 00:24:42.336596
837 00:24:42.337014 Board ID = 1
838 00:24:42.337418 Set A53 clk to 24M
839 00:24:42.337814 Set A73 clk to 24M
840 00:24:42.341695 Set clk81 to 24M
841 00:24:42.342148 A53 clk: 1200 MHz
842 00:24:42.342556 A73 clk: 1200 MHz
843 00:24:42.347267 CLK81: 166.6M
844 00:24:42.347712 smccc: 00012a92
845 00:24:42.352847 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 00:24:42.353296 board id: 1
847 00:24:42.358456 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 00:24:42.372222 fw parse done
849 00:24:42.378159 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 00:24:42.419945 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 00:24:42.431750 PIEI prepare done
852 00:24:42.432229 fastboot data load
853 00:24:42.432640 fastboot data verify
854 00:24:42.437420 verify result: 266
855 00:24:42.443016 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 00:24:42.443491 LPDDR4 probe
857 00:24:42.443908 ddr clk to 1584MHz
858 00:24:42.451004 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 00:24:42.488904
860 00:24:42.489370 dmc_version 0001
861 00:24:42.494892 Check phy result
862 00:24:42.500861 INFO : End of CA training
863 00:24:42.501328 INFO : End of initialization
864 00:24:42.506395 INFO : Training has run successfully!
865 00:24:42.506856 Check phy result
866 00:24:42.512005 INFO : End of initialization
867 00:24:42.512475 INFO : End of read enable training
868 00:24:42.517625 INFO : End of fine write leveling
869 00:24:42.523227 INFO : End of Write leveling coarse delay
870 00:24:42.523683 INFO : Training has run successfully!
871 00:24:42.524137 Check phy result
872 00:24:42.528876 INFO : End of initialization
873 00:24:42.529334 INFO : End of read dq deskew training
874 00:24:42.534416 INFO : End of MPR read delay center optimization
875 00:24:42.540009 INFO : End of write delay center optimization
876 00:24:42.545583 INFO : End of read delay center optimization
877 00:24:42.546041 INFO : End of max read latency training
878 00:24:42.551221 INFO : Training has run successfully!
879 00:24:42.551680 1D training succeed
880 00:24:42.559412 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 00:24:42.607040 Check phy result
882 00:24:42.607543 INFO : End of initialization
883 00:24:42.628781 INFO : End of 2D read delay Voltage center optimization
884 00:24:42.649012 INFO : End of 2D read delay Voltage center optimization
885 00:24:42.701019 INFO : End of 2D write delay Voltage center optimization
886 00:24:42.751250 INFO : End of 2D write delay Voltage center optimization
887 00:24:42.756875 INFO : Training has run successfully!
888 00:24:42.757339
889 00:24:42.757751 channel==0
890 00:24:42.762491 RxClkDly_Margin_A0==88 ps 9
891 00:24:42.762955 TxDqDly_Margin_A0==98 ps 10
892 00:24:42.765832 RxClkDly_Margin_A1==88 ps 9
893 00:24:42.766292 TxDqDly_Margin_A1==98 ps 10
894 00:24:42.771406 TrainedVREFDQ_A0==74
895 00:24:42.771880 TrainedVREFDQ_A1==76
896 00:24:42.772353 VrefDac_Margin_A0==25
897 00:24:42.777043 DeviceVref_Margin_A0==40
898 00:24:42.777525 VrefDac_Margin_A1==25
899 00:24:42.782624 DeviceVref_Margin_A1==38
900 00:24:42.783111
901 00:24:42.783504
902 00:24:42.783886 channel==1
903 00:24:42.784303 RxClkDly_Margin_A0==98 ps 10
904 00:24:42.785897 TxDqDly_Margin_A0==88 ps 9
905 00:24:42.791348 RxClkDly_Margin_A1==88 ps 9
906 00:24:42.791796 TxDqDly_Margin_A1==88 ps 9
907 00:24:42.792227 TrainedVREFDQ_A0==77
908 00:24:42.796958 TrainedVREFDQ_A1==77
909 00:24:42.797408 VrefDac_Margin_A0==22
910 00:24:42.802514 DeviceVref_Margin_A0==37
911 00:24:42.802957 VrefDac_Margin_A1==24
912 00:24:42.803340 DeviceVref_Margin_A1==37
913 00:24:42.803721
914 00:24:42.808132 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 00:24:42.808584
916 00:24:42.841723 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 00:24:42.842220 2D training succeed
918 00:24:42.847339 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 00:24:42.853011 auto size-- 65535DDR cs0 size: 2048MB
920 00:24:42.853462 DDR cs1 size: 2048MB
921 00:24:42.858506 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 00:24:42.858957 cs0 DataBus test pass
923 00:24:42.859342 cs1 DataBus test pass
924 00:24:42.864178 cs0 AddrBus test pass
925 00:24:42.864629 cs1 AddrBus test pass
926 00:24:42.865015
927 00:24:42.869713 100bdlr_step_size ps== 420
928 00:24:42.870184 result report
929 00:24:42.870570 boot times 0Enable ddr reg access
930 00:24:42.879680 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 00:24:42.893278 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 00:24:43.466777 0.0;M3 CHK:0;cm4_sp_mode 0
933 00:24:43.467334 MVN_1=0x00000000
934 00:24:43.472285 MVN_2=0x00000000
935 00:24:43.478052 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 00:24:43.478503 OPS=0x10
937 00:24:43.478920 ring efuse init
938 00:24:43.479324 chipver efuse init
939 00:24:43.486626 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 00:24:43.487086 [0.018961 Inits done]
941 00:24:43.492872 secure task start!
942 00:24:43.493321 high task start!
943 00:24:43.493729 low task start!
944 00:24:43.494133 run into bl31
945 00:24:43.500533 NOTICE: BL31: v1.3(release):4fc40b1
946 00:24:43.508305 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 00:24:43.508760 NOTICE: BL31: G12A normal boot!
948 00:24:43.533650 NOTICE: BL31: BL33 decompress pass
949 00:24:43.538470 ERROR: Error initializing runtime service opteed_fast
950 00:24:44.772209
951 00:24:44.772803
952 00:24:44.780578 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 00:24:44.781044
954 00:24:44.781459 Model: Libre Computer AML-A311D-CC Alta
955 00:24:44.989085 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 00:24:45.012564 DRAM: 2 GiB (effective 3.8 GiB)
957 00:24:45.155454 Core: 408 devices, 31 uclasses, devicetree: separate
958 00:24:45.161335 WDT: Not starting watchdog@f0d0
959 00:24:45.193547 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 00:24:45.206007 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 00:24:45.210957 ** Bad device specification mmc 0 **
962 00:24:45.221331 Card did not respond to voltage select! : -110
963 00:24:45.229000 ** Bad device specification mmc 0 **
964 00:24:45.229501 Couldn't find partition mmc 0
965 00:24:45.237300 Card did not respond to voltage select! : -110
966 00:24:45.242831 ** Bad device specification mmc 0 **
967 00:24:45.243273 Couldn't find partition mmc 0
968 00:24:45.247864 Error: could not access storage.
969 00:24:45.590383 Net: eth0: ethernet@ff3f0000
970 00:24:45.590973 starting USB...
971 00:24:45.842278 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 00:24:45.842868 Starting the controller
973 00:24:45.849138 USB XHCI 1.10
974 00:24:47.710781 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 00:24:47.711374 bl2_stage_init 0x01
976 00:24:47.711801 bl2_stage_init 0x81
977 00:24:47.716407 hw id: 0x0000 - pwm id 0x01
978 00:24:47.716864 bl2_stage_init 0xc1
979 00:24:47.717277 bl2_stage_init 0x02
980 00:24:47.717678
981 00:24:47.721936 L0:00000000
982 00:24:47.722383 L1:20000703
983 00:24:47.722791 L2:00008067
984 00:24:47.723194 L3:14000000
985 00:24:47.727504 B2:00402000
986 00:24:47.727945 B1:e0f83180
987 00:24:47.728392
988 00:24:47.728803 TE: 58124
989 00:24:47.729203
990 00:24:47.733173 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 00:24:47.733616
992 00:24:47.734023 Board ID = 1
993 00:24:47.738798 Set A53 clk to 24M
994 00:24:47.739233 Set A73 clk to 24M
995 00:24:47.739633 Set clk81 to 24M
996 00:24:47.744330 A53 clk: 1200 MHz
997 00:24:47.744773 A73 clk: 1200 MHz
998 00:24:47.745372 CLK81: 166.6M
999 00:24:47.745810 smccc: 00012a91
1000 00:24:47.749932 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 00:24:47.755529 board id: 1
1002 00:24:47.760580 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 00:24:47.772186 fw parse done
1004 00:24:47.778077 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 00:24:47.820602 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 00:24:47.831529 PIEI prepare done
1007 00:24:47.832058 fastboot data load
1008 00:24:47.832462 fastboot data verify
1009 00:24:47.837158 verify result: 266
1010 00:24:47.842783 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 00:24:47.843221 LPDDR4 probe
1012 00:24:47.843613 ddr clk to 1584MHz
1013 00:24:47.850770 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 00:24:47.887819
1015 00:24:47.888337 dmc_version 0001
1016 00:24:47.894716 Check phy result
1017 00:24:47.900525 INFO : End of CA training
1018 00:24:47.900976 INFO : End of initialization
1019 00:24:47.906161 INFO : Training has run successfully!
1020 00:24:47.906669 Check phy result
1021 00:24:47.911725 INFO : End of initialization
1022 00:24:47.912222 INFO : End of read enable training
1023 00:24:47.917320 INFO : End of fine write leveling
1024 00:24:47.922960 INFO : End of Write leveling coarse delay
1025 00:24:47.923432 INFO : Training has run successfully!
1026 00:24:47.923843 Check phy result
1027 00:24:47.928504 INFO : End of initialization
1028 00:24:47.928963 INFO : End of read dq deskew training
1029 00:24:47.934129 INFO : End of MPR read delay center optimization
1030 00:24:47.939733 INFO : End of write delay center optimization
1031 00:24:47.945334 INFO : End of read delay center optimization
1032 00:24:47.945797 INFO : End of max read latency training
1033 00:24:47.950917 INFO : Training has run successfully!
1034 00:24:47.951375 1D training succeed
1035 00:24:47.960160 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 00:24:48.007688 Check phy result
1037 00:24:48.008196 INFO : End of initialization
1038 00:24:48.029447 INFO : End of 2D read delay Voltage center optimization
1039 00:24:48.049683 INFO : End of 2D read delay Voltage center optimization
1040 00:24:48.101757 INFO : End of 2D write delay Voltage center optimization
1041 00:24:48.151088 INFO : End of 2D write delay Voltage center optimization
1042 00:24:48.156642 INFO : Training has run successfully!
1043 00:24:48.157122
1044 00:24:48.157539 channel==0
1045 00:24:48.162207 RxClkDly_Margin_A0==88 ps 9
1046 00:24:48.162662 TxDqDly_Margin_A0==98 ps 10
1047 00:24:48.165576 RxClkDly_Margin_A1==88 ps 9
1048 00:24:48.166023 TxDqDly_Margin_A1==98 ps 10
1049 00:24:48.171185 TrainedVREFDQ_A0==74
1050 00:24:48.171669 TrainedVREFDQ_A1==74
1051 00:24:48.172112 VrefDac_Margin_A0==25
1052 00:24:48.176734 DeviceVref_Margin_A0==40
1053 00:24:48.177201 VrefDac_Margin_A1==25
1054 00:24:48.182350 DeviceVref_Margin_A1==40
1055 00:24:48.182814
1056 00:24:48.183224
1057 00:24:48.183628 channel==1
1058 00:24:48.184055 RxClkDly_Margin_A0==98 ps 10
1059 00:24:48.187914 TxDqDly_Margin_A0==88 ps 9
1060 00:24:48.188397 RxClkDly_Margin_A1==88 ps 9
1061 00:24:48.193572 TxDqDly_Margin_A1==88 ps 9
1062 00:24:48.194035 TrainedVREFDQ_A0==77
1063 00:24:48.194442 TrainedVREFDQ_A1==77
1064 00:24:48.199160 VrefDac_Margin_A0==22
1065 00:24:48.199618 DeviceVref_Margin_A0==37
1066 00:24:48.204738 VrefDac_Margin_A1==24
1067 00:24:48.205193 DeviceVref_Margin_A1==37
1068 00:24:48.205596
1069 00:24:48.210363 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 00:24:48.210816
1071 00:24:48.238343 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 00:24:48.243965 2D training succeed
1073 00:24:48.249571 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 00:24:48.250058 auto size-- 65535DDR cs0 size: 2048MB
1075 00:24:48.255130 DDR cs1 size: 2048MB
1076 00:24:48.255599 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 00:24:48.260739 cs0 DataBus test pass
1078 00:24:48.261194 cs1 DataBus test pass
1079 00:24:48.261601 cs0 AddrBus test pass
1080 00:24:48.266348 cs1 AddrBus test pass
1081 00:24:48.266794
1082 00:24:48.267201 100bdlr_step_size ps== 420
1083 00:24:48.267611 result report
1084 00:24:48.271945 boot times 0Enable ddr reg access
1085 00:24:48.279536 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 00:24:48.293036 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 00:24:48.866970 0.0;M3 CHK:0;cm4_sp_mode 0
1088 00:24:48.867407 MVN_1=0x00000000
1089 00:24:48.872179 MVN_2=0x00000000
1090 00:24:48.877987 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 00:24:48.878500 OPS=0x10
1092 00:24:48.878965 ring efuse init
1093 00:24:48.879422 chipver efuse init
1094 00:24:48.883496 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 00:24:48.889084 [0.018961 Inits done]
1096 00:24:48.889599 secure task start!
1097 00:24:48.890059 high task start!
1098 00:24:48.893657 low task start!
1099 00:24:48.894157 run into bl31
1100 00:24:48.900363 NOTICE: BL31: v1.3(release):4fc40b1
1101 00:24:48.908118 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 00:24:48.908632 NOTICE: BL31: G12A normal boot!
1103 00:24:48.933503 NOTICE: BL31: BL33 decompress pass
1104 00:24:48.939184 ERROR: Error initializing runtime service opteed_fast
1105 00:24:50.172153
1106 00:24:50.172818
1107 00:24:50.180494 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 00:24:50.181004
1109 00:24:50.181470 Model: Libre Computer AML-A311D-CC Alta
1110 00:24:50.388852 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 00:24:50.412311 DRAM: 2 GiB (effective 3.8 GiB)
1112 00:24:50.555343 Core: 408 devices, 31 uclasses, devicetree: separate
1113 00:24:50.561155 WDT: Not starting watchdog@f0d0
1114 00:24:50.593485 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 00:24:50.605950 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 00:24:50.610844 ** Bad device specification mmc 0 **
1117 00:24:50.621353 Card did not respond to voltage select! : -110
1118 00:24:50.628833 ** Bad device specification mmc 0 **
1119 00:24:50.629346 Couldn't find partition mmc 0
1120 00:24:50.637299 Card did not respond to voltage select! : -110
1121 00:24:50.642684 ** Bad device specification mmc 0 **
1122 00:24:50.643187 Couldn't find partition mmc 0
1123 00:24:50.647767 Error: could not access storage.
1124 00:24:50.990269 Net: eth0: ethernet@ff3f0000
1125 00:24:50.990864 starting USB...
1126 00:24:51.242083 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 00:24:51.242642 Starting the controller
1128 00:24:51.249021 USB XHCI 1.10
1129 00:24:52.803095 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 00:24:52.811480 scanning usb for storage devices... 0 Storage Device(s) found
1132 00:24:52.863233 Hit any key to stop autoboot: 1
1133 00:24:52.864181 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 00:24:52.864817 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 00:24:52.865320 Setting prompt string to ['=>']
1136 00:24:52.865831 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 00:24:52.878973 0
1138 00:24:52.879956 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 00:24:52.880522 Sending with 10 millisecond of delay
1141 00:24:54.015904 => setenv autoload no
1142 00:24:54.026785 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 00:24:54.032131 setenv autoload no
1144 00:24:54.032927 Sending with 10 millisecond of delay
1146 00:24:55.830483 => setenv initrd_high 0xffffffff
1147 00:24:55.841314 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 00:24:55.842248 setenv initrd_high 0xffffffff
1149 00:24:55.843015 Sending with 10 millisecond of delay
1151 00:24:57.459659 => setenv fdt_high 0xffffffff
1152 00:24:57.470506 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 00:24:57.471426 setenv fdt_high 0xffffffff
1154 00:24:57.472194 Sending with 10 millisecond of delay
1156 00:24:57.764267 => dhcp
1157 00:24:57.775083 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 00:24:57.776028 dhcp
1159 00:24:57.776514 Speed: 1000, full duplex
1160 00:24:57.776971 BOOTP broadcast 1
1161 00:24:57.977710 DHCP client bound to address 192.168.6.33 (202 ms)
1162 00:24:57.978669 Sending with 10 millisecond of delay
1164 00:24:59.655892 => setenv serverip 192.168.6.2
1165 00:24:59.666732 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 00:24:59.667611 setenv serverip 192.168.6.2
1167 00:24:59.668405 Sending with 10 millisecond of delay
1169 00:25:03.392883 => tftpboot 0x01080000 713216/tftp-deploy-p1jqj5ld/kernel/uImage
1170 00:25:03.403727 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 00:25:03.404754 tftpboot 0x01080000 713216/tftp-deploy-p1jqj5ld/kernel/uImage
1172 00:25:03.405227 Speed: 1000, full duplex
1173 00:25:03.405669 Using ethernet@ff3f0000 device
1174 00:25:03.406502 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1175 00:25:03.412014 Filename '713216/tftp-deploy-p1jqj5ld/kernel/uImage'.
1176 00:25:03.415912 Load address: 0x1080000
1177 00:25:05.771182 Loading: *################################################## 35.7 MiB
1178 00:25:05.771830 15.1 MiB/s
1179 00:25:05.772413 done
1180 00:25:05.775588 Bytes transferred = 37407296 (23aca40 hex)
1181 00:25:05.776400 Sending with 10 millisecond of delay
1183 00:25:10.471053 => tftpboot 0x08000000 713216/tftp-deploy-p1jqj5ld/ramdisk/ramdisk.cpio.gz.uboot
1184 00:25:10.481869 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 00:25:10.482800 tftpboot 0x08000000 713216/tftp-deploy-p1jqj5ld/ramdisk/ramdisk.cpio.gz.uboot
1186 00:25:10.483272 Speed: 1000, full duplex
1187 00:25:10.483711 Using ethernet@ff3f0000 device
1188 00:25:10.484542 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1189 00:25:10.496252 Filename '713216/tftp-deploy-p1jqj5ld/ramdisk/ramdisk.cpio.gz.uboot'.
1190 00:25:10.496813 Load address: 0x8000000
1191 00:25:14.237350 Loading: *## UDP wrong checksum 000000ff 00002e21
1192 00:25:14.245281 UDP wrong checksum 000000ff 0000c213
1193 00:25:17.211598 T ############################################### UDP wrong checksum 00000005 00000f9f
1194 00:25:22.214291 T UDP wrong checksum 00000005 00000f9f
1195 00:25:32.216155 T T UDP wrong checksum 00000005 00000f9f
1196 00:25:52.220178 T T T T UDP wrong checksum 00000005 00000f9f
1197 00:26:07.224377 T T
1198 00:26:07.225028 Retry count exceeded; starting again
1200 00:26:07.226582 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1203 00:26:07.228755 end: 2.4 uboot-commands (duration 00:01:52) [common]
1205 00:26:07.230475 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 00:26:07.231596 end: 2 uboot-action (duration 00:01:52) [common]
1209 00:26:07.233311 Cleaning after the job
1210 00:26:07.233894 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/ramdisk
1211 00:26:07.235118 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/kernel
1212 00:26:07.277186 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/dtb
1213 00:26:07.278384 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/nfsrootfs
1214 00:26:07.443545 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/713216/tftp-deploy-p1jqj5ld/modules
1215 00:26:07.466827 start: 4.1 power-off (timeout 00:00:30) [common]
1216 00:26:07.467530 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 00:26:07.504259 >> OK - accepted request
1218 00:26:07.506263 Returned 0 in 0 seconds
1219 00:26:07.607055 end: 4.1 power-off (duration 00:00:00) [common]
1221 00:26:07.608080 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 00:26:07.608750 Listened to connection for namespace 'common' for up to 1s
1223 00:26:08.609659 Finalising connection for namespace 'common'
1224 00:26:08.610103 Disconnecting from shell: Finalise
1225 00:26:08.610427 =>
1226 00:26:08.711194 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 00:26:08.711914 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/713216
1228 00:26:11.598202 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/713216
1229 00:26:11.598815 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.