Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:40:57.105865 lava-dispatcher, installed at version: 2024.01
2 09:40:57.106960 start: 0 validate
3 09:40:57.107711 Start time: 2024-09-01 09:40:57.107651+00:00 (UTC)
4 09:40:57.108541 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:40:57.109325 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:40:57.154165 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:40:57.154936 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 09:40:57.183611 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:40:57.184300 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 09:40:58.229496 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:40:58.229997 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 09:40:58.265262 validate duration: 1.16
14 09:40:58.266106 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:40:58.266439 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:40:58.266732 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:40:58.267309 Not decompressing ramdisk as can be used compressed.
18 09:40:58.267730 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:40:58.268015 saving as /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/ramdisk/rootfs.cpio.gz
20 09:40:58.268298 total size: 8181887 (7 MB)
21 09:40:58.305611 progress 0 % (0 MB)
22 09:40:58.316891 progress 5 % (0 MB)
23 09:40:58.327551 progress 10 % (0 MB)
24 09:40:58.335597 progress 15 % (1 MB)
25 09:40:58.340975 progress 20 % (1 MB)
26 09:40:58.346738 progress 25 % (1 MB)
27 09:40:58.352122 progress 30 % (2 MB)
28 09:40:58.357858 progress 35 % (2 MB)
29 09:40:58.363148 progress 40 % (3 MB)
30 09:40:58.368947 progress 45 % (3 MB)
31 09:40:58.374274 progress 50 % (3 MB)
32 09:40:58.380050 progress 55 % (4 MB)
33 09:40:58.385343 progress 60 % (4 MB)
34 09:40:58.391053 progress 65 % (5 MB)
35 09:40:58.396514 progress 70 % (5 MB)
36 09:40:58.402210 progress 75 % (5 MB)
37 09:40:58.407475 progress 80 % (6 MB)
38 09:40:58.413194 progress 85 % (6 MB)
39 09:40:58.418517 progress 90 % (7 MB)
40 09:40:58.424274 progress 95 % (7 MB)
41 09:40:58.429218 progress 100 % (7 MB)
42 09:40:58.429876 7 MB downloaded in 0.16 s (48.30 MB/s)
43 09:40:58.430436 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:40:58.431317 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:40:58.431611 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:40:58.431886 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:40:58.432414 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 09:40:58.432671 saving as /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/kernel/Image
50 09:40:58.432880 total size: 66032128 (62 MB)
51 09:40:58.433094 No compression specified
52 09:40:58.469405 progress 0 % (0 MB)
53 09:40:58.511167 progress 5 % (3 MB)
54 09:40:58.554082 progress 10 % (6 MB)
55 09:40:58.594923 progress 15 % (9 MB)
56 09:40:58.635587 progress 20 % (12 MB)
57 09:40:58.675955 progress 25 % (15 MB)
58 09:40:58.716755 progress 30 % (18 MB)
59 09:40:58.757740 progress 35 % (22 MB)
60 09:40:58.798448 progress 40 % (25 MB)
61 09:40:58.838547 progress 45 % (28 MB)
62 09:40:58.879095 progress 50 % (31 MB)
63 09:40:58.919580 progress 55 % (34 MB)
64 09:40:58.960738 progress 60 % (37 MB)
65 09:40:59.001134 progress 65 % (40 MB)
66 09:40:59.041980 progress 70 % (44 MB)
67 09:40:59.082805 progress 75 % (47 MB)
68 09:40:59.123349 progress 80 % (50 MB)
69 09:40:59.163599 progress 85 % (53 MB)
70 09:40:59.204803 progress 90 % (56 MB)
71 09:40:59.245239 progress 95 % (59 MB)
72 09:40:59.285422 progress 100 % (62 MB)
73 09:40:59.285990 62 MB downloaded in 0.85 s (73.82 MB/s)
74 09:40:59.286477 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:40:59.287301 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:40:59.287583 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:40:59.287850 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:40:59.288343 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 09:40:59.288626 saving as /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 09:40:59.288837 total size: 53173 (0 MB)
82 09:40:59.289049 No compression specified
83 09:40:59.328024 progress 61 % (0 MB)
84 09:40:59.328860 progress 100 % (0 MB)
85 09:40:59.329393 0 MB downloaded in 0.04 s (1.25 MB/s)
86 09:40:59.329875 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:40:59.330687 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:40:59.330952 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:40:59.331219 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:40:59.331670 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 09:40:59.331910 saving as /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/modules/modules.tar
93 09:40:59.332212 total size: 16062372 (15 MB)
94 09:40:59.332432 Using unxz to decompress xz
95 09:40:59.366287 progress 0 % (0 MB)
96 09:40:59.466086 progress 5 % (0 MB)
97 09:40:59.585999 progress 10 % (1 MB)
98 09:40:59.715217 progress 15 % (2 MB)
99 09:40:59.854057 progress 20 % (3 MB)
100 09:40:59.984568 progress 25 % (3 MB)
101 09:41:00.119056 progress 30 % (4 MB)
102 09:41:00.246267 progress 35 % (5 MB)
103 09:41:00.372475 progress 40 % (6 MB)
104 09:41:00.502237 progress 45 % (6 MB)
105 09:41:00.633593 progress 50 % (7 MB)
106 09:41:00.762017 progress 55 % (8 MB)
107 09:41:00.900808 progress 60 % (9 MB)
108 09:41:01.031699 progress 65 % (9 MB)
109 09:41:01.153978 progress 70 % (10 MB)
110 09:41:01.291976 progress 75 % (11 MB)
111 09:41:01.441551 progress 80 % (12 MB)
112 09:41:01.560043 progress 85 % (13 MB)
113 09:41:01.688997 progress 90 % (13 MB)
114 09:41:01.800708 progress 95 % (14 MB)
115 09:41:01.932290 progress 100 % (15 MB)
116 09:41:01.943976 15 MB downloaded in 2.61 s (5.87 MB/s)
117 09:41:01.944968 end: 1.4.1 http-download (duration 00:00:03) [common]
119 09:41:01.946606 end: 1.4 download-retry (duration 00:00:03) [common]
120 09:41:01.947149 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 09:41:01.947684 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 09:41:01.948224 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:41:01.948743 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 09:41:01.949717 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4
125 09:41:01.950641 makedir: /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin
126 09:41:01.951313 makedir: /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/tests
127 09:41:01.951948 makedir: /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/results
128 09:41:01.952604 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-add-keys
129 09:41:01.953561 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-add-sources
130 09:41:01.954509 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-background-process-start
131 09:41:01.955482 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-background-process-stop
132 09:41:01.956462 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-common-functions
133 09:41:01.957107 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-echo-ipv4
134 09:41:01.957654 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-install-packages
135 09:41:01.958183 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-installed-packages
136 09:41:01.958703 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-os-build
137 09:41:01.959228 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-probe-channel
138 09:41:01.959754 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-probe-ip
139 09:41:01.960531 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-target-ip
140 09:41:01.961477 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-target-mac
141 09:41:01.962428 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-target-storage
142 09:41:01.963365 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-test-case
143 09:41:01.964323 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-test-event
144 09:41:01.965261 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-test-feedback
145 09:41:01.966220 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-test-raise
146 09:41:01.967163 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-test-reference
147 09:41:01.968120 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-test-runner
148 09:41:01.969052 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-test-set
149 09:41:01.969989 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-test-shell
150 09:41:01.970961 Updating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-install-packages (oe)
151 09:41:01.972024 Updating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/bin/lava-installed-packages (oe)
152 09:41:01.972931 Creating /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/environment
153 09:41:01.973689 LAVA metadata
154 09:41:01.974196 - LAVA_JOB_ID=684937
155 09:41:01.974631 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:41:01.975305 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 09:41:01.977157 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:41:01.977763 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 09:41:01.978183 skipped lava-vland-overlay
160 09:41:01.978677 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:41:01.979190 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 09:41:01.979630 skipped lava-multinode-overlay
163 09:41:01.980166 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:41:01.980684 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 09:41:01.981172 Loading test definitions
166 09:41:01.981726 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 09:41:01.982175 Using /lava-684937 at stage 0
168 09:41:01.984325 uuid=684937_1.5.2.4.1 testdef=None
169 09:41:01.984663 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:41:01.984946 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 09:41:01.986856 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:41:01.987675 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 09:41:01.990031 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:41:01.990877 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 09:41:01.993206 runner path: /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/0/tests/0_dmesg test_uuid 684937_1.5.2.4.1
178 09:41:01.993793 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:41:01.994576 Creating lava-test-runner.conf files
181 09:41:01.994786 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/684937/lava-overlay-e28ficq4/lava-684937/0 for stage 0
182 09:41:01.995143 - 0_dmesg
183 09:41:01.995511 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:41:01.995804 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 09:41:02.020697 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:41:02.021105 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 09:41:02.021378 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:41:02.021651 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:41:02.021920 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 09:41:02.969410 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:41:02.970181 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 09:41:02.970697 extracting modules file /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/modules/modules.tar to /var/lib/lava/dispatcher/tmp/684937/extract-overlay-ramdisk-7ict9hmp/ramdisk
193 09:41:04.585820 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 09:41:04.586317 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 09:41:04.586639 [common] Applying overlay /var/lib/lava/dispatcher/tmp/684937/compress-overlay-efwlw_d8/overlay-1.5.2.5.tar.gz to ramdisk
196 09:41:04.586896 [common] Applying overlay /var/lib/lava/dispatcher/tmp/684937/compress-overlay-efwlw_d8/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/684937/extract-overlay-ramdisk-7ict9hmp/ramdisk
197 09:41:04.620275 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:41:04.620711 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 09:41:04.621031 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 09:41:04.621301 Converting downloaded kernel to a uImage
201 09:41:04.621664 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/kernel/Image /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/kernel/uImage
202 09:41:05.367464 output: Image Name:
203 09:41:05.367900 output: Created: Sun Sep 1 09:41:04 2024
204 09:41:05.368155 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:41:05.368364 output: Data Size: 66032128 Bytes = 64484.50 KiB = 62.97 MiB
206 09:41:05.368566 output: Load Address: 01080000
207 09:41:05.368764 output: Entry Point: 01080000
208 09:41:05.368965 output:
209 09:41:05.369302 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 09:41:05.369566 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 09:41:05.369836 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 09:41:05.370088 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:41:05.370344 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 09:41:05.370636 Building ramdisk /var/lib/lava/dispatcher/tmp/684937/extract-overlay-ramdisk-7ict9hmp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/684937/extract-overlay-ramdisk-7ict9hmp/ramdisk
215 09:41:08.609228 >> 255202 blocks
216 09:41:19.561991 Adding RAMdisk u-boot header.
217 09:41:19.562427 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/684937/extract-overlay-ramdisk-7ict9hmp/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/684937/extract-overlay-ramdisk-7ict9hmp/ramdisk.cpio.gz.uboot
218 09:41:19.909997 output: Image Name:
219 09:41:19.910445 output: Created: Sun Sep 1 09:41:19 2024
220 09:41:19.910936 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:41:19.911395 output: Data Size: 33530217 Bytes = 32744.35 KiB = 31.98 MiB
222 09:41:19.911868 output: Load Address: 00000000
223 09:41:19.912368 output: Entry Point: 00000000
224 09:41:19.912814 output:
225 09:41:19.914063 rename /var/lib/lava/dispatcher/tmp/684937/extract-overlay-ramdisk-7ict9hmp/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/ramdisk/ramdisk.cpio.gz.uboot
226 09:41:19.914844 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 09:41:19.915456 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
228 09:41:19.916119 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 09:41:19.916644 No LXC device requested
230 09:41:19.917213 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:41:19.917780 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 09:41:19.918336 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:41:19.918794 Checking files for TFTP limit of 4294967296 bytes.
234 09:41:19.921749 end: 1 tftp-deploy (duration 00:00:22) [common]
235 09:41:19.922388 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:41:19.922973 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:41:19.923528 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:41:19.924115 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:41:19.924708 Using kernel file from prepare-kernel: 684937/tftp-deploy-f2jol341/kernel/uImage
240 09:41:19.925384 substitutions:
241 09:41:19.925843 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:41:19.926297 - {DTB_ADDR}: 0x01070000
243 09:41:19.926745 - {DTB}: 684937/tftp-deploy-f2jol341/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 09:41:19.927194 - {INITRD}: 684937/tftp-deploy-f2jol341/ramdisk/ramdisk.cpio.gz.uboot
245 09:41:19.927637 - {KERNEL_ADDR}: 0x01080000
246 09:41:19.928105 - {KERNEL}: 684937/tftp-deploy-f2jol341/kernel/uImage
247 09:41:19.928556 - {LAVA_MAC}: None
248 09:41:19.929044 - {PRESEED_CONFIG}: None
249 09:41:19.929522 - {PRESEED_LOCAL}: None
250 09:41:19.929981 - {RAMDISK_ADDR}: 0x08000000
251 09:41:19.930421 - {RAMDISK}: 684937/tftp-deploy-f2jol341/ramdisk/ramdisk.cpio.gz.uboot
252 09:41:19.930863 - {ROOT_PART}: None
253 09:41:19.931300 - {ROOT}: None
254 09:41:19.931731 - {SERVER_IP}: 192.168.6.2
255 09:41:19.932208 - {TEE_ADDR}: 0x83000000
256 09:41:19.932648 - {TEE}: None
257 09:41:19.933087 Parsed boot commands:
258 09:41:19.933555 - setenv autoload no
259 09:41:19.934016 - setenv initrd_high 0xffffffff
260 09:41:19.934456 - setenv fdt_high 0xffffffff
261 09:41:19.934893 - dhcp
262 09:41:19.935329 - setenv serverip 192.168.6.2
263 09:41:19.935766 - tftpboot 0x01080000 684937/tftp-deploy-f2jol341/kernel/uImage
264 09:41:19.936239 - tftpboot 0x08000000 684937/tftp-deploy-f2jol341/ramdisk/ramdisk.cpio.gz.uboot
265 09:41:19.936682 - tftpboot 0x01070000 684937/tftp-deploy-f2jol341/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 09:41:19.937123 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:41:19.937567 - bootm 0x01080000 0x08000000 0x01070000
268 09:41:19.938129 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:41:19.939789 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:41:19.940320 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 09:41:19.955913 Setting prompt string to ['lava-test: # ']
273 09:41:19.957567 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:41:19.959017 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:41:19.959745 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:41:19.960417 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:41:19.961748 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 09:41:20.002448 >> OK - accepted request
279 09:41:20.004578 Returned 0 in 0 seconds
280 09:41:20.105835 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:41:20.107678 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:41:20.108377 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:41:20.108955 Setting prompt string to ['Hit any key to stop autoboot']
285 09:41:20.109461 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:41:20.111205 Trying 192.168.56.21...
287 09:41:20.111748 Connected to conserv1.
288 09:41:20.112254 Escape character is '^]'.
289 09:41:20.112737
290 09:41:20.113259 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 09:41:20.113770
292 09:41:27.825078 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 09:41:27.825491 bl2_stage_init 0x01
294 09:41:27.825721 bl2_stage_init 0x81
295 09:41:27.830544 hw id: 0x0000 - pwm id 0x01
296 09:41:27.830945 bl2_stage_init 0xc1
297 09:41:27.834708 bl2_stage_init 0x02
298 09:41:27.835083
299 09:41:27.835408 L0:00000000
300 09:41:27.835732 L1:00000703
301 09:41:27.840183 L2:00008067
302 09:41:27.840458 L3:15000000
303 09:41:27.840671 S1:00000000
304 09:41:27.840874 B2:20282000
305 09:41:27.841072 B1:a0f83180
306 09:41:27.841269
307 09:41:27.845704 TE: 70393
308 09:41:27.846106
309 09:41:27.851400 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 09:41:27.851787
311 09:41:27.852153 Board ID = 1
312 09:41:27.852843 Set cpu clk to 24M
313 09:41:27.857093 Set clk81 to 24M
314 09:41:27.857650 Use GP1_pll as DSU clk.
315 09:41:27.858178 DSU clk: 1200 Mhz
316 09:41:27.862659 CPU clk: 1200 MHz
317 09:41:27.863217 Set clk81 to 166.6M
318 09:41:27.868149 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 09:41:27.868613 board id: 1
320 09:41:27.876994 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:41:27.887545 fw parse done
322 09:41:27.893558 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:41:27.936272 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:41:27.947152 PIEI prepare done
325 09:41:27.947618 fastboot data load
326 09:41:27.948050 fastboot data verify
327 09:41:27.952727 verify result: 266
328 09:41:27.958356 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 09:41:27.958821 LPDDR4 probe
330 09:41:27.959237 ddr clk to 1584MHz
331 09:41:27.966343 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:41:28.003683
333 09:41:28.004267 dmc_version 0001
334 09:41:28.010280 Check phy result
335 09:41:28.016185 INFO : End of CA training
336 09:41:28.016639 INFO : End of initialization
337 09:41:28.021755 INFO : Training has run successfully!
338 09:41:28.022240 Check phy result
339 09:41:28.027391 INFO : End of initialization
340 09:41:28.027842 INFO : End of read enable training
341 09:41:28.033008 INFO : End of fine write leveling
342 09:41:28.038597 INFO : End of Write leveling coarse delay
343 09:41:28.039039 INFO : Training has run successfully!
344 09:41:28.039433 Check phy result
345 09:41:28.044160 INFO : End of initialization
346 09:41:28.044595 INFO : End of read dq deskew training
347 09:41:28.049810 INFO : End of MPR read delay center optimization
348 09:41:28.055374 INFO : End of write delay center optimization
349 09:41:28.061020 INFO : End of read delay center optimization
350 09:41:28.061489 INFO : End of max read latency training
351 09:41:28.066490 INFO : Training has run successfully!
352 09:41:28.066935 1D training succeed
353 09:41:28.075824 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:41:28.123351 Check phy result
355 09:41:28.123822 INFO : End of initialization
356 09:41:28.145701 INFO : End of 2D read delay Voltage center optimization
357 09:41:28.164899 INFO : End of 2D read delay Voltage center optimization
358 09:41:28.216864 INFO : End of 2D write delay Voltage center optimization
359 09:41:28.266091 INFO : End of 2D write delay Voltage center optimization
360 09:41:28.271498 INFO : Training has run successfully!
361 09:41:28.271945
362 09:41:28.272379 channel==0
363 09:41:28.277080 RxClkDly_Margin_A0==88 ps 9
364 09:41:28.277527 TxDqDly_Margin_A0==98 ps 10
365 09:41:28.280406 RxClkDly_Margin_A1==88 ps 9
366 09:41:28.280844 TxDqDly_Margin_A1==98 ps 10
367 09:41:28.286039 TrainedVREFDQ_A0==74
368 09:41:28.286479 TrainedVREFDQ_A1==75
369 09:41:28.291554 VrefDac_Margin_A0==24
370 09:41:28.292009 DeviceVref_Margin_A0==40
371 09:41:28.292409 VrefDac_Margin_A1==23
372 09:41:28.297187 DeviceVref_Margin_A1==39
373 09:41:28.297630
374 09:41:28.298026
375 09:41:28.298416 channel==1
376 09:41:28.298803 RxClkDly_Margin_A0==78 ps 8
377 09:41:28.302865 TxDqDly_Margin_A0==98 ps 10
378 09:41:28.303302 RxClkDly_Margin_A1==78 ps 8
379 09:41:28.308440 TxDqDly_Margin_A1==88 ps 9
380 09:41:28.308887 TrainedVREFDQ_A0==78
381 09:41:28.309284 TrainedVREFDQ_A1==75
382 09:41:28.314063 VrefDac_Margin_A0==22
383 09:41:28.314498 DeviceVref_Margin_A0==36
384 09:41:28.319538 VrefDac_Margin_A1==22
385 09:41:28.319971 DeviceVref_Margin_A1==39
386 09:41:28.320404
387 09:41:28.325131 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:41:28.325571
389 09:41:28.353144 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000016 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 09:41:28.358820 2D training succeed
391 09:41:28.364310 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:41:28.364761 auto size-- 65535DDR cs0 size: 2048MB
393 09:41:28.370129 DDR cs1 size: 2048MB
394 09:41:28.370611 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:41:28.375568 cs0 DataBus test pass
396 09:41:28.376053 cs1 DataBus test pass
397 09:41:28.376454 cs0 AddrBus test pass
398 09:41:28.381144 cs1 AddrBus test pass
399 09:41:28.381585
400 09:41:28.381978 100bdlr_step_size ps== 478
401 09:41:28.382376 result report
402 09:41:28.386940 boot times 0Enable ddr reg access
403 09:41:28.393485 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:41:28.408201 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 09:41:29.062112 bl2z: ptr: 05129330, size: 00001e40
406 09:41:29.069175 0.0;M3 CHK:0;cm4_sp_mode 0
407 09:41:29.069442 MVN_1=0x00000000
408 09:41:29.069652 MVN_2=0x00000000
409 09:41:29.080700 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 09:41:29.081196 OPS=0x04
411 09:41:29.081406 ring efuse init
412 09:41:29.086325 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 09:41:29.086905 [0.017310 Inits done]
414 09:41:29.087114 secure task start!
415 09:41:29.094228 high task start!
416 09:41:29.094468 low task start!
417 09:41:29.094670 run into bl31
418 09:41:29.102814 NOTICE: BL31: v1.3(release):4fc40b1
419 09:41:29.110614 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 09:41:29.110883 NOTICE: BL31: G12A normal boot!
421 09:41:29.126167 NOTICE: BL31: BL33 decompress pass
422 09:41:29.131859 ERROR: Error initializing runtime service opteed_fast
423 09:41:30.374778 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 09:41:30.375201 bl2_stage_init 0x01
425 09:41:30.375429 bl2_stage_init 0x81
426 09:41:30.380462 hw id: 0x0000 - pwm id 0x01
427 09:41:30.380753 bl2_stage_init 0xc1
428 09:41:30.380962 bl2_stage_init 0x02
429 09:41:30.381161
430 09:41:30.386067 L0:00000000
431 09:41:30.386326 L1:00000703
432 09:41:30.386532 L2:00008067
433 09:41:30.386729 L3:15000000
434 09:41:30.386926 S1:00000000
435 09:41:30.391619 B2:20282000
436 09:41:30.391889 B1:a0f83180
437 09:41:30.392143
438 09:41:30.392348 TE: 69305
439 09:41:30.392545
440 09:41:30.397230 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 09:41:30.397487
442 09:41:30.402853 Board ID = 1
443 09:41:30.403117 Set cpu clk to 24M
444 09:41:30.403321 Set clk81 to 24M
445 09:41:30.408413 Use GP1_pll as DSU clk.
446 09:41:30.408836 DSU clk: 1200 Mhz
447 09:41:30.409168 CPU clk: 1200 MHz
448 09:41:30.409483 Set clk81 to 166.6M
449 09:41:30.419573 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 09:41:30.419969 board id: 1
451 09:41:30.426054 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 09:41:30.437150 fw parse done
453 09:41:30.442191 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 09:41:30.486027 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 09:41:30.497070 PIEI prepare done
456 09:41:30.497387 fastboot data load
457 09:41:30.497606 fastboot data verify
458 09:41:30.502658 verify result: 266
459 09:41:30.508248 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 09:41:30.508668 LPDDR4 probe
461 09:41:30.509002 ddr clk to 1584MHz
462 09:41:30.517177 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 09:41:31.875399 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
464 09:41:31.875841 bl2_stage_init 0x01
465 09:41:31.876157 bl2_stage_init 0x81
466 09:41:31.880917 hw id: 0x0000 - pwm id 0x01
467 09:41:31.881374 bl2_stage_init 0xc1
468 09:41:31.886524 bl2_stage_init 0x02
469 09:41:31.886992
470 09:41:31.887402 L0:00000000
471 09:41:31.887697 L1:00000703
472 09:41:31.887942 L2:00008067
473 09:41:31.888212 L3:15000000
474 09:41:31.892074 S1:00000000
475 09:41:31.892403 B2:20282000
476 09:41:31.892658 B1:a0f83180
477 09:41:31.892897
478 09:41:31.893123 TE: 70810
479 09:41:31.893348
480 09:41:31.897692 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
481 09:41:31.898185
482 09:41:31.903297 Board ID = 1
483 09:41:31.903777 Set cpu clk to 24M
484 09:41:31.904218 Set clk81 to 24M
485 09:41:31.908893 Use GP1_pll as DSU clk.
486 09:41:31.909374 DSU clk: 1200 Mhz
487 09:41:31.909931 CPU clk: 1200 MHz
488 09:41:31.914521 Set clk81 to 166.6M
489 09:41:31.920156 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
490 09:41:31.920494 board id: 1
491 09:41:31.927464 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
492 09:41:31.938226 fw parse done
493 09:41:31.943461 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
494 09:41:31.987393 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
495 09:41:31.998502 PIEI prepare done
496 09:41:31.999116 fastboot data load
497 09:41:31.999571 fastboot data verify
498 09:41:32.004078 verify result: 266
499 09:41:32.009736 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
500 09:41:32.010335 LPDDR4 probe
501 09:41:32.010821 ddr clk to 1584MHz
502 09:41:32.017770 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 09:41:32.054553
504 09:41:32.055200 dmc_version 0001
505 09:41:32.062554 Check phy result
506 09:41:32.068426 INFO : End of CA training
507 09:41:32.069050 INFO : End of initialization
508 09:41:32.074054 INFO : Training has run successfully!
509 09:41:32.074655 Check phy result
510 09:41:32.079714 INFO : End of initialization
511 09:41:32.080339 INFO : End of read enable training
512 09:41:32.085248 INFO : End of fine write leveling
513 09:41:32.090819 INFO : End of Write leveling coarse delay
514 09:41:32.091438 INFO : Training has run successfully!
515 09:41:32.091925 Check phy result
516 09:41:32.096473 INFO : End of initialization
517 09:41:32.097054 INFO : End of read dq deskew training
518 09:41:32.102023 INFO : End of MPR read delay center optimization
519 09:41:32.107649 INFO : End of write delay center optimization
520 09:41:32.113237 INFO : End of read delay center optimization
521 09:41:32.113846 INFO : End of max read latency training
522 09:41:32.118815 INFO : Training has run successfully!
523 09:41:32.119391 1D training succeed
524 09:41:32.128085 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
525 09:41:32.176378 Check phy result
526 09:41:32.177012 INFO : End of initialization
527 09:41:32.203791 INFO : End of 2D read delay Voltage center optimization
528 09:41:32.227889 INFO : End of 2D read delay Voltage center optimization
529 09:41:32.284636 INFO : End of 2D write delay Voltage center optimization
530 09:41:32.338664 INFO : End of 2D write delay Voltage center optimization
531 09:41:32.344207 INFO : Training has run successfully!
532 09:41:32.344796
533 09:41:32.345276 channel==0
534 09:41:32.349763 RxClkDly_Margin_A0==78 ps 8
535 09:41:32.350326 TxDqDly_Margin_A0==98 ps 10
536 09:41:32.355353 RxClkDly_Margin_A1==88 ps 9
537 09:41:32.355921 TxDqDly_Margin_A1==98 ps 10
538 09:41:32.356471 TrainedVREFDQ_A0==74
539 09:41:32.360995 TrainedVREFDQ_A1==75
540 09:41:32.361593 VrefDac_Margin_A0==24
541 09:41:32.362063 DeviceVref_Margin_A0==40
542 09:41:32.366563 VrefDac_Margin_A1==22
543 09:41:32.367124 DeviceVref_Margin_A1==39
544 09:41:32.367590
545 09:41:32.368090
546 09:41:32.372156 channel==1
547 09:41:32.372719 RxClkDly_Margin_A0==88 ps 9
548 09:41:32.373186 TxDqDly_Margin_A0==98 ps 10
549 09:41:32.377763 RxClkDly_Margin_A1==88 ps 9
550 09:41:32.378321 TxDqDly_Margin_A1==78 ps 8
551 09:41:32.383375 TrainedVREFDQ_A0==77
552 09:41:32.383950 TrainedVREFDQ_A1==75
553 09:41:32.384471 VrefDac_Margin_A0==23
554 09:41:32.388964 DeviceVref_Margin_A0==37
555 09:41:32.389532 VrefDac_Margin_A1==22
556 09:41:32.394557 DeviceVref_Margin_A1==39
557 09:41:32.395116
558 09:41:32.395579 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
559 09:41:32.396060
560 09:41:32.428154 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000015 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000062
561 09:41:32.428780 2D training succeed
562 09:41:32.433877 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
563 09:41:32.439359 auto size-- 65535DDR cs0 size: 2048MB
564 09:41:32.439927 DDR cs1 size: 2048MB
565 09:41:32.444994 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
566 09:41:32.445565 cs0 DataBus test pass
567 09:41:32.450561 cs1 DataBus test pass
568 09:41:32.451117 cs0 AddrBus test pass
569 09:41:32.451585 cs1 AddrBus test pass
570 09:41:32.452074
571 09:41:32.456158 100bdlr_step_size ps== 471
572 09:41:32.456726 result report
573 09:41:32.461739 boot times 0Enable ddr reg access
574 09:41:32.466083 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
575 09:41:32.481004 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
576 09:41:33.140105 bl2z: ptr: 05129330, size: 00001e40
577 09:41:33.149577 0.0;M3 CHK:0;cm4_sp_mode 0
578 09:41:33.150222 MVN_1=0x00000000
579 09:41:33.150458 MVN_2=0x00000000
580 09:41:33.160688 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
581 09:41:33.161278 OPS=0x04
582 09:41:33.161622 ring efuse init
583 09:41:33.166146 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
584 09:41:33.166499 [0.017354 Inits done]
585 09:41:33.166720 secure task start!
586 09:41:33.173363 high task start!
587 09:41:33.173907 low task start!
588 09:41:33.174246 run into bl31
589 09:41:33.182037 NOTICE: BL31: v1.3(release):4fc40b1
590 09:41:33.189932 NOTICE: BL31: Built : 15:57:33, May 22 2019
591 09:41:33.190360 NOTICE: BL31: G12A normal boot!
592 09:41:33.205522 NOTICE: BL31: BL33 decompress pass
593 09:41:33.211418 ERROR: Error initializing runtime service opteed_fast
594 09:41:34.426462 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
595 09:41:34.427130 bl2_stage_init 0x01
596 09:41:34.427612 bl2_stage_init 0x81
597 09:41:34.431860 hw id: 0x0000 - pwm id 0x01
598 09:41:34.432396 bl2_stage_init 0xc1
599 09:41:34.436228 bl2_stage_init 0x02
600 09:41:34.436720
601 09:41:34.437182 L0:00000000
602 09:41:34.437629 L1:00000703
603 09:41:34.438070 L2:00008067
604 09:41:34.441871 L3:15000000
605 09:41:34.442355 S1:00000000
606 09:41:34.442806 B2:20282000
607 09:41:34.443246 B1:a0f83180
608 09:41:34.443682
609 09:41:34.444164 TE: 71188
610 09:41:34.444617
611 09:41:34.453033 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
612 09:41:34.453545
613 09:41:34.454002 Board ID = 1
614 09:41:34.454443 Set cpu clk to 24M
615 09:41:34.454881 Set clk81 to 24M
616 09:41:34.458622 Use GP1_pll as DSU clk.
617 09:41:34.459113 DSU clk: 1200 Mhz
618 09:41:34.459563 CPU clk: 1200 MHz
619 09:41:34.464073 Set clk81 to 166.6M
620 09:41:34.469681 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
621 09:41:34.470170 board id: 1
622 09:41:34.478092 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
623 09:41:34.488985 fw parse done
624 09:41:34.494902 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
625 09:41:34.537996 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
626 09:41:34.549190 PIEI prepare done
627 09:41:34.549710 fastboot data load
628 09:41:34.550171 fastboot data verify
629 09:41:34.554791 verify result: 266
630 09:41:34.560299 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
631 09:41:34.560793 LPDDR4 probe
632 09:41:34.561246 ddr clk to 1584MHz
633 09:41:34.568317 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
634 09:41:34.606092
635 09:41:34.606613 dmc_version 0001
636 09:41:34.613091 Check phy result
637 09:41:34.619042 INFO : End of CA training
638 09:41:34.619528 INFO : End of initialization
639 09:41:34.624688 INFO : Training has run successfully!
640 09:41:34.625241 Check phy result
641 09:41:34.630401 INFO : End of initialization
642 09:41:34.630913 INFO : End of read enable training
643 09:41:34.633779 INFO : End of fine write leveling
644 09:41:34.639353 INFO : End of Write leveling coarse delay
645 09:41:34.644965 INFO : Training has run successfully!
646 09:41:34.645462 Check phy result
647 09:41:34.645908 INFO : End of initialization
648 09:41:34.650530 INFO : End of read dq deskew training
649 09:41:34.656169 INFO : End of MPR read delay center optimization
650 09:41:34.656654 INFO : End of write delay center optimization
651 09:41:34.661713 INFO : End of read delay center optimization
652 09:41:34.667346 INFO : End of max read latency training
653 09:41:34.667837 INFO : Training has run successfully!
654 09:41:34.672959 1D training succeed
655 09:41:34.678675 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
656 09:41:34.727263 Check phy result
657 09:41:34.727838 INFO : End of initialization
658 09:41:34.754543 INFO : End of 2D read delay Voltage center optimization
659 09:41:34.778762 INFO : End of 2D read delay Voltage center optimization
660 09:41:34.835417 INFO : End of 2D write delay Voltage center optimization
661 09:41:34.889486 INFO : End of 2D write delay Voltage center optimization
662 09:41:34.895176 INFO : Training has run successfully!
663 09:41:34.895674
664 09:41:34.896170 channel==0
665 09:41:34.900620 RxClkDly_Margin_A0==78 ps 8
666 09:41:34.901108 TxDqDly_Margin_A0==98 ps 10
667 09:41:34.906197 RxClkDly_Margin_A1==88 ps 9
668 09:41:34.906679 TxDqDly_Margin_A1==98 ps 10
669 09:41:34.907131 TrainedVREFDQ_A0==74
670 09:41:34.911729 TrainedVREFDQ_A1==74
671 09:41:34.912254 VrefDac_Margin_A0==23
672 09:41:34.912711 DeviceVref_Margin_A0==40
673 09:41:34.917365 VrefDac_Margin_A1==23
674 09:41:34.917843 DeviceVref_Margin_A1==40
675 09:41:34.918287
676 09:41:34.918728
677 09:41:34.923097 channel==1
678 09:41:34.923576 RxClkDly_Margin_A0==78 ps 8
679 09:41:34.924049 TxDqDly_Margin_A0==98 ps 10
680 09:41:34.928627 RxClkDly_Margin_A1==78 ps 8
681 09:41:34.929192 TxDqDly_Margin_A1==78 ps 8
682 09:41:34.934157 TrainedVREFDQ_A0==78
683 09:41:34.934672 TrainedVREFDQ_A1==75
684 09:41:34.935129 VrefDac_Margin_A0==22
685 09:41:34.939829 DeviceVref_Margin_A0==36
686 09:41:34.940385 VrefDac_Margin_A1==22
687 09:41:34.945423 DeviceVref_Margin_A1==38
688 09:41:34.945916
689 09:41:34.946361 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
690 09:41:34.946803
691 09:41:34.978995 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000014 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
692 09:41:34.979641 2D training succeed
693 09:41:34.984390 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
694 09:41:34.989994 auto size-- 65535DDR cs0 size: 2048MB
695 09:41:34.990496 DDR cs1 size: 2048MB
696 09:41:34.995613 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
697 09:41:34.996146 cs0 DataBus test pass
698 09:41:35.001231 cs1 DataBus test pass
699 09:41:35.001793 cs0 AddrBus test pass
700 09:41:35.002246 cs1 AddrBus test pass
701 09:41:35.002687
702 09:41:35.006797 100bdlr_step_size ps== 471
703 09:41:35.007320 result report
704 09:41:35.012364 boot times 0Enable ddr reg access
705 09:41:35.017645 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
706 09:41:35.031551 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
707 09:41:35.690646 bl2z: ptr: 05129330, size: 00001e40
708 09:41:35.699630 0.0;M3 CHK:0;cm4_sp_mode 0
709 09:41:35.700277 MVN_1=0x00000000
710 09:41:35.700723 MVN_2=0x00000000
711 09:41:35.711159 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
712 09:41:35.711724 OPS=0x04
713 09:41:35.712207 ring efuse init
714 09:41:35.714029 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
715 09:41:35.720401 [0.017354 Inits done]
716 09:41:35.720867 secure task start!
717 09:41:35.721296 high task start!
718 09:41:35.721719 low task start!
719 09:41:35.724684 run into bl31
720 09:41:35.733419 NOTICE: BL31: v1.3(release):4fc40b1
721 09:41:35.741134 NOTICE: BL31: Built : 15:57:33, May 22 2019
722 09:41:35.741612 NOTICE: BL31: G12A normal boot!
723 09:41:35.756757 NOTICE: BL31: BL33 decompress pass
724 09:41:35.762449 ERROR: Error initializing runtime service opteed_fast
725 09:41:36.557955
726 09:41:36.558585
727 09:41:36.563208 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
728 09:41:36.563715
729 09:41:36.566704 Model: Libre Computer AML-S905D3-CC Solitude
730 09:41:36.958781 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
731 09:41:36.959202 DRAM: 2 GiB (effective 3.8 GiB)
732 09:41:36.959423 Core: 406 devices, 33 uclasses, devicetree: separate
733 09:41:36.959633 WDT: Not starting watchdog@f0d0
734 09:41:36.959836 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
735 09:41:36.960114 Loading Environment from FAT... Card did not respond to voltage select! : -110
736 09:41:36.960329 ** Bad device specification mmc 0 **
737 09:41:36.960557 Card did not respond to voltage select! : -110
738 09:41:36.960761 ** Bad device specification mmc 0 **
739 09:41:36.960963 Couldn't find partition mmc 0
740 09:41:36.961173 Card did not respond to voltage select! : -110
741 09:41:36.961373 ** Bad device specification mmc 0 **
742 09:41:36.961570 Couldn't find partition mmc 0
743 09:41:36.962153 Error: could not access storage.
744 09:41:37.211419 Net: eth0: ethernet@ff3f0000
745 09:41:37.212029 starting USB...
746 09:41:37.456221 Bus usb@ff500000: Register 3000140 NbrPorts 3
747 09:41:37.456780 Starting the controller
748 09:41:37.462947 USB XHCI 1.10
749 09:41:39.019167 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
750 09:41:39.027464 scanning usb for storage devices... 0 Storage Device(s) found
752 09:41:39.078590 Hit any key to stop autoboot: 1
753 09:41:39.079343 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
754 09:41:39.079795 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
755 09:41:39.080103 Setting prompt string to ['=>']
756 09:41:39.080373 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
757 09:41:39.094249 0
758 09:41:39.094905 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
760 09:41:39.195739 => setenv autoload no
761 09:41:39.196482 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
762 09:41:39.200585 setenv autoload no
764 09:41:39.301660 => setenv initrd_high 0xffffffff
765 09:41:39.302358 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
766 09:41:39.306328 setenv initrd_high 0xffffffff
768 09:41:39.407389 => setenv fdt_high 0xffffffff
769 09:41:39.408141 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
770 09:41:39.412085 setenv fdt_high 0xffffffff
772 09:41:39.513210 => dhcp
773 09:41:39.513882 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
774 09:41:39.517901 dhcp
775 09:41:40.023540 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
776 09:41:40.024171 Speed: 1000, full duplex
777 09:41:40.024615 BOOTP broadcast 1
778 09:41:40.271811 BOOTP broadcast 2
779 09:41:40.772783 BOOTP broadcast 3
780 09:41:41.773739 BOOTP broadcast 4
781 09:41:43.774764 BOOTP broadcast 5
782 09:41:43.786774 DHCP client bound to address 192.168.6.12 (3762 ms)
784 09:41:43.888326 => setenv serverip 192.168.6.2
785 09:41:43.889037 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
786 09:41:43.893652 setenv serverip 192.168.6.2
788 09:41:43.995187 => tftpboot 0x01080000 684937/tftp-deploy-f2jol341/kernel/uImage
789 09:41:43.996034 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
790 09:41:44.002820 tftpboot 0x01080000 684937/tftp-deploy-f2jol341/kernel/uImage
791 09:41:44.003290 Speed: 1000, full duplex
792 09:41:44.003712 Using ethernet@ff3f0000 device
793 09:41:44.008286 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
794 09:41:44.013904 Filename '684937/tftp-deploy-f2jol341/kernel/uImage'.
795 09:41:44.017770 Load address: 0x1080000
796 09:41:44.419240 Loading: *#### UDP wrong checksum 000000ff 0000259d
797 09:41:44.459002 UDP wrong checksum 000000ff 0000ae8f
798 09:41:48.201958 ############################################## 63 MiB
799 09:41:48.202370 15 MiB/s
800 09:41:48.202586 done
801 09:41:48.206018 Bytes transferred = 66032192 (3ef9240 hex)
803 09:41:48.307186 => tftpboot 0x08000000 684937/tftp-deploy-f2jol341/ramdisk/ramdisk.cpio.gz.uboot
804 09:41:48.307724 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
805 09:41:48.314446 tftpboot 0x08000000 684937/tftp-deploy-f2jol341/ramdisk/ramdisk.cpio.gz.uboot
806 09:41:48.314783 Speed: 1000, full duplex
807 09:41:48.315007 Using ethernet@ff3f0000 device
808 09:41:48.320045 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
809 09:41:48.329873 Filename '684937/tftp-deploy-f2jol341/ramdisk/ramdisk.cpio.gz.uboot'.
810 09:41:48.330240 Load address: 0x8000000
811 09:41:55.508545 Loading: *#################T ################################ UDP wrong checksum 00000007 00002dbd
812 09:42:00.508670 T UDP wrong checksum 00000007 00002dbd
813 09:42:01.270241 UDP wrong checksum 000000ff 0000459f
814 09:42:01.303158 UDP wrong checksum 000000ff 0000cc91
815 09:42:10.510602 T T UDP wrong checksum 00000007 00002dbd
816 09:42:30.512351 T T T UDP wrong checksum 00000007 00002dbd
817 09:42:45.518312 T T T
818 09:42:45.518749 Retry count exceeded; starting again
820 09:42:45.519676 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
823 09:42:45.520756 end: 2.4 uboot-commands (duration 00:01:26) [common]
825 09:42:45.521538 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
827 09:42:45.522191 end: 2 uboot-action (duration 00:01:26) [common]
829 09:42:45.523098 Cleaning after the job
830 09:42:45.523446 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/ramdisk
831 09:42:45.524507 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/kernel
832 09:42:45.534224 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/dtb
833 09:42:45.535097 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684937/tftp-deploy-f2jol341/modules
834 09:42:45.561465 start: 4.1 power-off (timeout 00:00:30) [common]
835 09:42:45.562185 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
836 09:42:45.595456 >> OK - accepted request
837 09:42:45.597998 Returned 0 in 0 seconds
838 09:42:45.698826 end: 4.1 power-off (duration 00:00:00) [common]
840 09:42:45.699931 start: 4.2 read-feedback (timeout 00:10:00) [common]
841 09:42:45.700697 Listened to connection for namespace 'common' for up to 1s
842 09:42:46.701686 Finalising connection for namespace 'common'
843 09:42:46.702416 Disconnecting from shell: Finalise
844 09:42:46.702957 =>
845 09:42:46.804020 end: 4.2 read-feedback (duration 00:00:01) [common]
846 09:42:46.804740 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/684937
847 09:42:47.093147 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/684937
848 09:42:47.093765 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.