Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:08:16.161432 lava-dispatcher, installed at version: 2024.01
2 09:08:16.162358 start: 0 validate
3 09:08:16.162934 Start time: 2024-09-01 09:08:16.162897+00:00 (UTC)
4 09:08:16.163626 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:08:16.164327 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:08:16.204052 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:08:16.204643 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:08:16.232009 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:08:16.232688 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:08:16.264781 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:08:16.265331 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:08:16.300622 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 09:08:16.301133 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 09:08:16.337506 validate duration: 0.17
16 09:08:16.338476 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:08:16.338887 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:08:16.339311 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:08:16.339961 Not decompressing ramdisk as can be used compressed.
20 09:08:16.340435 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:08:16.340791 saving as /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/ramdisk/initrd.cpio.gz
22 09:08:16.341061 total size: 5628169 (5 MB)
23 09:08:16.378268 progress 0 % (0 MB)
24 09:08:16.382848 progress 5 % (0 MB)
25 09:08:16.387152 progress 10 % (0 MB)
26 09:08:16.390949 progress 15 % (0 MB)
27 09:08:16.395012 progress 20 % (1 MB)
28 09:08:16.398734 progress 25 % (1 MB)
29 09:08:16.402947 progress 30 % (1 MB)
30 09:08:16.407177 progress 35 % (1 MB)
31 09:08:16.411052 progress 40 % (2 MB)
32 09:08:16.415350 progress 45 % (2 MB)
33 09:08:16.419164 progress 50 % (2 MB)
34 09:08:16.423381 progress 55 % (2 MB)
35 09:08:16.427614 progress 60 % (3 MB)
36 09:08:16.431461 progress 65 % (3 MB)
37 09:08:16.435567 progress 70 % (3 MB)
38 09:08:16.439255 progress 75 % (4 MB)
39 09:08:16.443092 progress 80 % (4 MB)
40 09:08:16.446492 progress 85 % (4 MB)
41 09:08:16.450361 progress 90 % (4 MB)
42 09:08:16.454095 progress 95 % (5 MB)
43 09:08:16.457459 progress 100 % (5 MB)
44 09:08:16.458142 5 MB downloaded in 0.12 s (45.85 MB/s)
45 09:08:16.458702 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:08:16.459659 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:08:16.459974 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:08:16.460288 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:08:16.460789 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig/gcc-12/kernel/Image
51 09:08:16.461055 saving as /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/kernel/Image
52 09:08:16.461274 total size: 45308416 (43 MB)
53 09:08:16.461496 No compression specified
54 09:08:16.494870 progress 0 % (0 MB)
55 09:08:16.523394 progress 5 % (2 MB)
56 09:08:16.551925 progress 10 % (4 MB)
57 09:08:16.578580 progress 15 % (6 MB)
58 09:08:16.605483 progress 20 % (8 MB)
59 09:08:16.632446 progress 25 % (10 MB)
60 09:08:16.658819 progress 30 % (12 MB)
61 09:08:16.685149 progress 35 % (15 MB)
62 09:08:16.712123 progress 40 % (17 MB)
63 09:08:16.738739 progress 45 % (19 MB)
64 09:08:16.765614 progress 50 % (21 MB)
65 09:08:16.792392 progress 55 % (23 MB)
66 09:08:16.820758 progress 60 % (25 MB)
67 09:08:16.848026 progress 65 % (28 MB)
68 09:08:16.875039 progress 70 % (30 MB)
69 09:08:16.902542 progress 75 % (32 MB)
70 09:08:16.930034 progress 80 % (34 MB)
71 09:08:16.957426 progress 85 % (36 MB)
72 09:08:16.985139 progress 90 % (38 MB)
73 09:08:17.012913 progress 95 % (41 MB)
74 09:08:17.039728 progress 100 % (43 MB)
75 09:08:17.040514 43 MB downloaded in 0.58 s (74.60 MB/s)
76 09:08:17.041058 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:08:17.041887 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:08:17.042164 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:08:17.042431 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:08:17.042987 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 09:08:17.043248 saving as /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/dtb/meson-g12b-a311d-libretech-cc.dtb
83 09:08:17.043456 total size: 54667 (0 MB)
84 09:08:17.043682 No compression specified
85 09:08:17.077401 progress 59 % (0 MB)
86 09:08:17.078326 progress 100 % (0 MB)
87 09:08:17.078927 0 MB downloaded in 0.04 s (1.47 MB/s)
88 09:08:17.079427 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:08:17.080344 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:08:17.080618 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:08:17.080885 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:08:17.081361 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:08:17.081604 saving as /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/nfsrootfs/full.rootfs.tar
95 09:08:17.081810 total size: 120894716 (115 MB)
96 09:08:17.082022 Using unxz to decompress xz
97 09:08:17.117112 progress 0 % (0 MB)
98 09:08:17.966503 progress 5 % (5 MB)
99 09:08:18.816883 progress 10 % (11 MB)
100 09:08:19.616097 progress 15 % (17 MB)
101 09:08:20.360236 progress 20 % (23 MB)
102 09:08:20.961439 progress 25 % (28 MB)
103 09:08:21.789341 progress 30 % (34 MB)
104 09:08:22.598921 progress 35 % (40 MB)
105 09:08:22.948219 progress 40 % (46 MB)
106 09:08:23.323206 progress 45 % (51 MB)
107 09:08:24.072656 progress 50 % (57 MB)
108 09:08:24.976102 progress 55 % (63 MB)
109 09:08:25.781920 progress 60 % (69 MB)
110 09:08:26.559952 progress 65 % (74 MB)
111 09:08:27.346668 progress 70 % (80 MB)
112 09:08:28.189790 progress 75 % (86 MB)
113 09:08:28.997208 progress 80 % (92 MB)
114 09:08:29.803241 progress 85 % (98 MB)
115 09:08:30.689109 progress 90 % (103 MB)
116 09:08:31.522894 progress 95 % (109 MB)
117 09:08:32.414134 progress 100 % (115 MB)
118 09:08:32.427762 115 MB downloaded in 15.35 s (7.51 MB/s)
119 09:08:32.428485 end: 1.4.1 http-download (duration 00:00:15) [common]
121 09:08:32.429371 end: 1.4 download-retry (duration 00:00:15) [common]
122 09:08:32.429650 start: 1.5 download-retry (timeout 00:09:44) [common]
123 09:08:32.429934 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 09:08:32.430467 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig/gcc-12/modules.tar.xz
125 09:08:32.430766 saving as /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/modules/modules.tar
126 09:08:32.430984 total size: 11499436 (10 MB)
127 09:08:32.431212 Using unxz to decompress xz
128 09:08:32.493687 progress 0 % (0 MB)
129 09:08:32.572589 progress 5 % (0 MB)
130 09:08:32.660150 progress 10 % (1 MB)
131 09:08:32.751321 progress 15 % (1 MB)
132 09:08:32.847023 progress 20 % (2 MB)
133 09:08:32.925239 progress 25 % (2 MB)
134 09:08:33.006165 progress 30 % (3 MB)
135 09:08:33.078522 progress 35 % (3 MB)
136 09:08:33.158055 progress 40 % (4 MB)
137 09:08:33.235801 progress 45 % (4 MB)
138 09:08:33.316219 progress 50 % (5 MB)
139 09:08:33.400562 progress 55 % (6 MB)
140 09:08:33.473659 progress 60 % (6 MB)
141 09:08:33.559273 progress 65 % (7 MB)
142 09:08:33.636489 progress 70 % (7 MB)
143 09:08:33.720104 progress 75 % (8 MB)
144 09:08:33.811134 progress 80 % (8 MB)
145 09:08:33.910648 progress 85 % (9 MB)
146 09:08:33.984072 progress 90 % (9 MB)
147 09:08:34.066190 progress 95 % (10 MB)
148 09:08:34.142587 progress 100 % (10 MB)
149 09:08:34.158661 10 MB downloaded in 1.73 s (6.35 MB/s)
150 09:08:34.159301 end: 1.5.1 http-download (duration 00:00:02) [common]
152 09:08:34.160251 end: 1.5 download-retry (duration 00:00:02) [common]
153 09:08:34.160557 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 09:08:34.160860 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 09:08:52.256698 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/684540/extract-nfsrootfs-442_d5wm
156 09:08:52.257312 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 09:08:52.257628 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 09:08:52.260781 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3
159 09:08:52.261421 makedir: /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin
160 09:08:52.261869 makedir: /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/tests
161 09:08:52.262623 makedir: /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/results
162 09:08:52.263044 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-add-keys
163 09:08:52.263727 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-add-sources
164 09:08:52.264429 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-background-process-start
165 09:08:52.265012 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-background-process-stop
166 09:08:52.265631 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-common-functions
167 09:08:52.266189 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-echo-ipv4
168 09:08:52.266797 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-install-packages
169 09:08:52.267363 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-installed-packages
170 09:08:52.268195 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-os-build
171 09:08:52.268783 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-probe-channel
172 09:08:52.270159 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-probe-ip
173 09:08:52.270781 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-target-ip
174 09:08:52.271336 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-target-mac
175 09:08:52.271846 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-target-storage
176 09:08:52.272436 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-test-case
177 09:08:52.272968 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-test-event
178 09:08:52.273498 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-test-feedback
179 09:08:52.274034 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-test-raise
180 09:08:52.274854 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-test-reference
181 09:08:52.275448 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-test-runner
182 09:08:52.276766 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-test-set
183 09:08:52.277574 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-test-shell
184 09:08:52.278228 Updating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-add-keys (debian)
185 09:08:52.281978 Updating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-add-sources (debian)
186 09:08:52.285091 Updating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-install-packages (debian)
187 09:08:52.285886 Updating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-installed-packages (debian)
188 09:08:52.286925 Updating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/bin/lava-os-build (debian)
189 09:08:52.287455 Creating /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/environment
190 09:08:52.287882 LAVA metadata
191 09:08:52.288243 - LAVA_JOB_ID=684540
192 09:08:52.288480 - LAVA_DISPATCHER_IP=192.168.6.2
193 09:08:52.288876 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 09:08:52.290711 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 09:08:52.291102 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 09:08:52.291347 skipped lava-vland-overlay
197 09:08:52.291626 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 09:08:52.291899 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 09:08:52.292160 skipped lava-multinode-overlay
200 09:08:52.292418 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 09:08:52.292713 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 09:08:52.293003 Loading test definitions
203 09:08:52.293305 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 09:08:52.293548 Using /lava-684540 at stage 0
205 09:08:52.297215 uuid=684540_1.6.2.4.1 testdef=None
206 09:08:52.297572 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 09:08:52.297846 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 09:08:52.299571 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 09:08:52.300468 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 09:08:52.302668 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 09:08:52.304472 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 09:08:52.308710 runner path: /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/0/tests/0_timesync-off test_uuid 684540_1.6.2.4.1
215 09:08:52.311144 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 09:08:52.312178 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 09:08:52.312463 Using /lava-684540 at stage 0
219 09:08:52.312861 Fetching tests from https://github.com/kernelci/test-definitions.git
220 09:08:52.313213 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/0/tests/1_kselftest-dt'
221 09:08:55.831313 Running '/usr/bin/git checkout kernelci.org
222 09:08:56.284745 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 09:08:56.286262 uuid=684540_1.6.2.4.5 testdef=None
224 09:08:56.286638 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 09:08:56.287417 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
227 09:08:56.290576 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 09:08:56.291421 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
230 09:08:56.295289 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 09:08:56.296218 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
233 09:08:56.299997 runner path: /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/0/tests/1_kselftest-dt test_uuid 684540_1.6.2.4.5
234 09:08:56.300312 BOARD='meson-g12b-a311d-libretech-cc'
235 09:08:56.300518 BRANCH='mainline'
236 09:08:56.300739 SKIPFILE='/dev/null'
237 09:08:56.300961 SKIP_INSTALL='True'
238 09:08:56.301176 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 09:08:56.301383 TST_CASENAME=''
240 09:08:56.301581 TST_CMDFILES='dt'
241 09:08:56.302197 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 09:08:56.303008 Creating lava-test-runner.conf files
244 09:08:56.303215 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/684540/lava-overlay-wmqwz1l3/lava-684540/0 for stage 0
245 09:08:56.303692 - 0_timesync-off
246 09:08:56.303959 - 1_kselftest-dt
247 09:08:56.304332 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 09:08:56.304622 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
249 09:09:19.719342 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 09:09:19.719777 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 09:09:19.720069 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 09:09:19.720349 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 09:09:19.720617 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 09:09:20.348963 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 09:09:20.349427 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 09:09:20.349683 extracting modules file /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/684540/extract-nfsrootfs-442_d5wm
257 09:09:21.728959 extracting modules file /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/684540/extract-overlay-ramdisk-x__me7mf/ramdisk
258 09:09:23.146547 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 09:09:23.147015 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 09:09:23.147295 [common] Applying overlay to NFS
261 09:09:23.147511 [common] Applying overlay /var/lib/lava/dispatcher/tmp/684540/compress-overlay-8bj1drlh/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/684540/extract-nfsrootfs-442_d5wm
262 09:09:25.879208 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 09:09:25.879671 start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
264 09:09:25.879944 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
265 09:09:25.880199 Converting downloaded kernel to a uImage
266 09:09:25.880510 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/kernel/Image /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/kernel/uImage
267 09:09:26.393382 output: Image Name:
268 09:09:26.393811 output: Created: Sun Sep 1 09:09:25 2024
269 09:09:26.394023 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 09:09:26.394227 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
271 09:09:26.394428 output: Load Address: 01080000
272 09:09:26.394627 output: Entry Point: 01080000
273 09:09:26.394825 output:
274 09:09:26.395160 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 09:09:26.395427 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 09:09:26.395692 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 09:09:26.395949 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 09:09:26.396263 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 09:09:26.396527 Building ramdisk /var/lib/lava/dispatcher/tmp/684540/extract-overlay-ramdisk-x__me7mf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/684540/extract-overlay-ramdisk-x__me7mf/ramdisk
280 09:09:28.760080 >> 165160 blocks
281 09:09:36.934602 Adding RAMdisk u-boot header.
282 09:09:36.935048 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/684540/extract-overlay-ramdisk-x__me7mf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/684540/extract-overlay-ramdisk-x__me7mf/ramdisk.cpio.gz.uboot
283 09:09:37.176868 output: Image Name:
284 09:09:37.177437 output: Created: Sun Sep 1 09:09:36 2024
285 09:09:37.177805 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 09:09:37.178518 output: Data Size: 23259469 Bytes = 22714.33 KiB = 22.18 MiB
287 09:09:37.178920 output: Load Address: 00000000
288 09:09:37.179272 output: Entry Point: 00000000
289 09:09:37.179620 output:
290 09:09:37.180730 rename /var/lib/lava/dispatcher/tmp/684540/extract-overlay-ramdisk-x__me7mf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/ramdisk/ramdisk.cpio.gz.uboot
291 09:09:37.181373 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 09:09:37.182319 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 09:09:37.182766 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:39) [common]
294 09:09:37.183209 No LXC device requested
295 09:09:37.183660 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 09:09:37.184491 start: 1.8 deploy-device-env (timeout 00:08:39) [common]
297 09:09:37.185329 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 09:09:37.185701 Checking files for TFTP limit of 4294967296 bytes.
299 09:09:37.188045 end: 1 tftp-deploy (duration 00:01:21) [common]
300 09:09:37.188525 start: 2 uboot-action (timeout 00:05:00) [common]
301 09:09:37.188997 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 09:09:37.189442 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 09:09:37.189887 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 09:09:37.190345 Using kernel file from prepare-kernel: 684540/tftp-deploy-ysqxeve5/kernel/uImage
305 09:09:37.190887 substitutions:
306 09:09:37.191233 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 09:09:37.191578 - {DTB_ADDR}: 0x01070000
308 09:09:37.191922 - {DTB}: 684540/tftp-deploy-ysqxeve5/dtb/meson-g12b-a311d-libretech-cc.dtb
309 09:09:37.192291 - {INITRD}: 684540/tftp-deploy-ysqxeve5/ramdisk/ramdisk.cpio.gz.uboot
310 09:09:37.192664 - {KERNEL_ADDR}: 0x01080000
311 09:09:37.192976 - {KERNEL}: 684540/tftp-deploy-ysqxeve5/kernel/uImage
312 09:09:37.193290 - {LAVA_MAC}: None
313 09:09:37.193689 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/684540/extract-nfsrootfs-442_d5wm
314 09:09:37.194024 - {NFS_SERVER_IP}: 192.168.6.2
315 09:09:37.194334 - {PRESEED_CONFIG}: None
316 09:09:37.194677 - {PRESEED_LOCAL}: None
317 09:09:37.195013 - {RAMDISK_ADDR}: 0x08000000
318 09:09:37.195349 - {RAMDISK}: 684540/tftp-deploy-ysqxeve5/ramdisk/ramdisk.cpio.gz.uboot
319 09:09:37.195688 - {ROOT_PART}: None
320 09:09:37.196041 - {ROOT}: None
321 09:09:37.196384 - {SERVER_IP}: 192.168.6.2
322 09:09:37.196690 - {TEE_ADDR}: 0x83000000
323 09:09:37.197031 - {TEE}: None
324 09:09:37.197371 Parsed boot commands:
325 09:09:37.197701 - setenv autoload no
326 09:09:37.198037 - setenv initrd_high 0xffffffff
327 09:09:37.198353 - setenv fdt_high 0xffffffff
328 09:09:37.198688 - dhcp
329 09:09:37.199026 - setenv serverip 192.168.6.2
330 09:09:37.199365 - tftpboot 0x01080000 684540/tftp-deploy-ysqxeve5/kernel/uImage
331 09:09:37.199711 - tftpboot 0x08000000 684540/tftp-deploy-ysqxeve5/ramdisk/ramdisk.cpio.gz.uboot
332 09:09:37.200068 - tftpboot 0x01070000 684540/tftp-deploy-ysqxeve5/dtb/meson-g12b-a311d-libretech-cc.dtb
333 09:09:37.200413 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/684540/extract-nfsrootfs-442_d5wm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 09:09:37.200752 - bootm 0x01080000 0x08000000 0x01070000
335 09:09:37.201196 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 09:09:37.202387 start: 2.3 connect-device (timeout 00:05:00) [common]
338 09:09:37.202743 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 09:09:37.215257 Setting prompt string to ['lava-test: # ']
340 09:09:37.216543 end: 2.3 connect-device (duration 00:00:00) [common]
341 09:09:37.217097 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 09:09:37.217618 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 09:09:37.218101 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 09:09:37.219043 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 09:09:37.253110 >> OK - accepted request
346 09:09:37.255420 Returned 0 in 0 seconds
347 09:09:37.356483 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 09:09:37.357518 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 09:09:37.357873 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 09:09:37.358181 Setting prompt string to ['Hit any key to stop autoboot']
352 09:09:37.358443 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 09:09:37.359411 Trying 192.168.56.21...
354 09:09:37.359698 Connected to conserv1.
355 09:09:37.359930 Escape character is '^]'.
356 09:09:37.360209
357 09:09:37.360445 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 09:09:37.360680
359 09:09:48.618287 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 09:09:48.618925 bl2_stage_init 0x01
361 09:09:48.619351 bl2_stage_init 0x81
362 09:09:48.624000 hw id: 0x0000 - pwm id 0x01
363 09:09:48.624295 bl2_stage_init 0xc1
364 09:09:48.624504 bl2_stage_init 0x02
365 09:09:48.624713
366 09:09:48.629372 L0:00000000
367 09:09:48.629650 L1:20000703
368 09:09:48.629860 L2:00008067
369 09:09:48.630062 L3:14000000
370 09:09:48.632410 B2:00402000
371 09:09:48.632887 B1:e0f83180
372 09:09:48.633276
373 09:09:48.633664 TE: 58158
374 09:09:48.634050
375 09:09:48.643370 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 09:09:48.643883
377 09:09:48.644319 Board ID = 1
378 09:09:48.644706 Set A53 clk to 24M
379 09:09:48.645089 Set A73 clk to 24M
380 09:09:48.649092 Set clk81 to 24M
381 09:09:48.649562 A53 clk: 1200 MHz
382 09:09:48.649956 A73 clk: 1200 MHz
383 09:09:48.652670 CLK81: 166.6M
384 09:09:48.653127 smccc: 00012ab5
385 09:09:48.658269 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 09:09:48.663873 board id: 1
387 09:09:48.669110 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 09:09:48.679457 fw parse done
389 09:09:48.685434 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 09:09:48.728022 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 09:09:48.738914 PIEI prepare done
392 09:09:48.739382 fastboot data load
393 09:09:48.739777 fastboot data verify
394 09:09:48.744490 verify result: 266
395 09:09:48.750132 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 09:09:48.750616 LPDDR4 probe
397 09:09:48.751008 ddr clk to 1584MHz
398 09:09:48.758049 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 09:09:48.795378
400 09:09:48.795870 dmc_version 0001
401 09:09:48.802119 Check phy result
402 09:09:48.807920 INFO : End of CA training
403 09:09:48.808418 INFO : End of initialization
404 09:09:48.813565 INFO : Training has run successfully!
405 09:09:48.814028 Check phy result
406 09:09:48.819224 INFO : End of initialization
407 09:09:48.819698 INFO : End of read enable training
408 09:09:48.824701 INFO : End of fine write leveling
409 09:09:48.830406 INFO : End of Write leveling coarse delay
410 09:09:48.830880 INFO : Training has run successfully!
411 09:09:48.831279 Check phy result
412 09:09:48.835947 INFO : End of initialization
413 09:09:48.836466 INFO : End of read dq deskew training
414 09:09:48.841532 INFO : End of MPR read delay center optimization
415 09:09:48.847151 INFO : End of write delay center optimization
416 09:09:48.852718 INFO : End of read delay center optimization
417 09:09:48.853207 INFO : End of max read latency training
418 09:09:48.858372 INFO : Training has run successfully!
419 09:09:48.858838 1D training succeed
420 09:09:48.867544 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 09:09:48.915143 Check phy result
422 09:09:48.915667 INFO : End of initialization
423 09:09:48.936858 INFO : End of 2D read delay Voltage center optimization
424 09:09:48.956282 INFO : End of 2D read delay Voltage center optimization
425 09:09:49.008308 INFO : End of 2D write delay Voltage center optimization
426 09:09:49.057675 INFO : End of 2D write delay Voltage center optimization
427 09:09:49.063226 INFO : Training has run successfully!
428 09:09:49.063711
429 09:09:49.064183 channel==0
430 09:09:49.069016 RxClkDly_Margin_A0==88 ps 9
431 09:09:49.069494 TxDqDly_Margin_A0==98 ps 10
432 09:09:49.072185 RxClkDly_Margin_A1==88 ps 9
433 09:09:49.072660 TxDqDly_Margin_A1==98 ps 10
434 09:09:49.077728 TrainedVREFDQ_A0==74
435 09:09:49.078214 TrainedVREFDQ_A1==74
436 09:09:49.083321 VrefDac_Margin_A0==25
437 09:09:49.083818 DeviceVref_Margin_A0==40
438 09:09:49.084265 VrefDac_Margin_A1==25
439 09:09:49.089029 DeviceVref_Margin_A1==40
440 09:09:49.089522
441 09:09:49.089937
442 09:09:49.090341 channel==1
443 09:09:49.090735 RxClkDly_Margin_A0==98 ps 10
444 09:09:49.094543 TxDqDly_Margin_A0==98 ps 10
445 09:09:49.095045 RxClkDly_Margin_A1==88 ps 9
446 09:09:49.100162 TxDqDly_Margin_A1==98 ps 10
447 09:09:49.100674 TrainedVREFDQ_A0==77
448 09:09:49.101088 TrainedVREFDQ_A1==77
449 09:09:49.105721 VrefDac_Margin_A0==23
450 09:09:49.106236 DeviceVref_Margin_A0==37
451 09:09:49.111392 VrefDac_Margin_A1==23
452 09:09:49.111903 DeviceVref_Margin_A1==37
453 09:09:49.112359
454 09:09:49.116927 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 09:09:49.117434
456 09:09:49.144861 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000017 00000019 00000018 00000018 00000018 00000019 0000001a 00000017 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 09:09:49.150455 2D training succeed
458 09:09:49.156127 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 09:09:49.156634 auto size-- 65535DDR cs0 size: 2048MB
460 09:09:49.161665 DDR cs1 size: 2048MB
461 09:09:49.162140 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 09:09:49.167302 cs0 DataBus test pass
463 09:09:49.167781 cs1 DataBus test pass
464 09:09:49.168240 cs0 AddrBus test pass
465 09:09:49.174795 cs1 AddrBus test pass
466 09:09:49.175280
467 09:09:49.175692 100bdlr_step_size ps== 426
468 09:09:49.176145 result report
469 09:09:49.178430 boot times 0Enable ddr reg access
470 09:09:49.186326 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 09:09:49.198729 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 09:09:49.773563 0.0;M3 CHK:0;cm4_sp_mode 0
473 09:09:49.776162 MVN_1=0x00000000
474 09:09:49.779525 MVN_2=0x00000000
475 09:09:49.784774 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 09:09:49.788410 OPS=0x10
477 09:09:49.788855 ring efuse init
478 09:09:49.789268 chipver efuse init
479 09:09:49.791276 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 09:09:49.796228 [0.018961 Inits done]
481 09:09:49.796809 secure task start!
482 09:09:49.797261 high task start!
483 09:09:49.800608 low task start!
484 09:09:49.801092 run into bl31
485 09:09:49.807125 NOTICE: BL31: v1.3(release):4fc40b1
486 09:09:49.815076 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 09:09:49.815569 NOTICE: BL31: G12A normal boot!
488 09:09:49.840202 NOTICE: BL31: BL33 decompress pass
489 09:09:49.846046 ERROR: Error initializing runtime service opteed_fast
490 09:09:51.078776
491 09:09:51.079183
492 09:09:51.087183 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 09:09:51.087483
494 09:09:51.087708 Model: Libre Computer AML-A311D-CC Alta
495 09:09:51.295646 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 09:09:51.319087 DRAM: 2 GiB (effective 3.8 GiB)
497 09:09:51.462179 Core: 408 devices, 31 uclasses, devicetree: separate
498 09:09:51.466907 WDT: Not starting watchdog@f0d0
499 09:09:51.500262 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 09:09:51.512736 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 09:09:51.516795 ** Bad device specification mmc 0 **
502 09:09:51.527886 Card did not respond to voltage select! : -110
503 09:09:51.535452 ** Bad device specification mmc 0 **
504 09:09:51.535780 Couldn't find partition mmc 0
505 09:09:51.543753 Card did not respond to voltage select! : -110
506 09:09:51.549239 ** Bad device specification mmc 0 **
507 09:09:51.549574 Couldn't find partition mmc 0
508 09:09:51.554319 Error: could not access storage.
509 09:09:52.818674 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
510 09:09:52.819351 bl2_stage_init 0x81
511 09:09:52.824149 hw id: 0x0000 - pwm id 0x01
512 09:09:52.824469 bl2_stage_init 0xc1
513 09:09:52.824679 bl2_stage_init 0x02
514 09:09:52.824880
515 09:09:52.829763 L0:00000000
516 09:09:52.830022 L1:20000703
517 09:09:52.830223 L2:00008067
518 09:09:52.830419 L3:14000000
519 09:09:52.830615 B2:00402000
520 09:09:52.835293 B1:e0f83180
521 09:09:52.835801
522 09:09:52.836283 TE: 58150
523 09:09:52.836723
524 09:09:52.840998 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 09:09:52.841505
526 09:09:52.841947 Board ID = 1
527 09:09:52.846578 Set A53 clk to 24M
528 09:09:52.847081 Set A73 clk to 24M
529 09:09:52.847516 Set clk81 to 24M
530 09:09:52.852224 A53 clk: 1200 MHz
531 09:09:52.852714 A73 clk: 1200 MHz
532 09:09:52.853150 CLK81: 166.6M
533 09:09:52.853585 smccc: 00012aac
534 09:09:52.857850 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 09:09:52.863384 board id: 1
536 09:09:52.869317 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 09:09:52.879823 fw parse done
538 09:09:52.885762 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 09:09:52.928547 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 09:09:52.939323 PIEI prepare done
541 09:09:52.939809 fastboot data load
542 09:09:52.940296 fastboot data verify
543 09:09:52.944923 verify result: 266
544 09:09:52.950615 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 09:09:52.951095 LPDDR4 probe
546 09:09:52.951531 ddr clk to 1584MHz
547 09:09:52.958568 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 09:09:52.995891
549 09:09:52.996525 dmc_version 0001
550 09:09:53.002541 Check phy result
551 09:09:53.008559 INFO : End of CA training
552 09:09:53.009036 INFO : End of initialization
553 09:09:53.014003 INFO : Training has run successfully!
554 09:09:53.014472 Check phy result
555 09:09:53.019597 INFO : End of initialization
556 09:09:53.020095 INFO : End of read enable training
557 09:09:53.025221 INFO : End of fine write leveling
558 09:09:53.030856 INFO : End of Write leveling coarse delay
559 09:09:53.031321 INFO : Training has run successfully!
560 09:09:53.031754 Check phy result
561 09:09:53.036426 INFO : End of initialization
562 09:09:53.036702 INFO : End of read dq deskew training
563 09:09:53.041973 INFO : End of MPR read delay center optimization
564 09:09:53.047565 INFO : End of write delay center optimization
565 09:09:53.053203 INFO : End of read delay center optimization
566 09:09:53.053507 INFO : End of max read latency training
567 09:09:53.058801 INFO : Training has run successfully!
568 09:09:53.059124 1D training succeed
569 09:09:53.068077 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 09:09:53.114603 Check phy result
571 09:09:53.114981 INFO : End of initialization
572 09:09:53.137394 INFO : End of 2D read delay Voltage center optimization
573 09:09:53.156616 INFO : End of 2D read delay Voltage center optimization
574 09:09:53.209610 INFO : End of 2D write delay Voltage center optimization
575 09:09:53.259027 INFO : End of 2D write delay Voltage center optimization
576 09:09:53.264573 INFO : Training has run successfully!
577 09:09:53.265159
578 09:09:53.265615 channel==0
579 09:09:53.270116 RxClkDly_Margin_A0==78 ps 8
580 09:09:53.270685 TxDqDly_Margin_A0==98 ps 10
581 09:09:53.273502 RxClkDly_Margin_A1==88 ps 9
582 09:09:53.274090 TxDqDly_Margin_A1==88 ps 9
583 09:09:53.279069 TrainedVREFDQ_A0==74
584 09:09:53.279618 TrainedVREFDQ_A1==74
585 09:09:53.280099 VrefDac_Margin_A0==25
586 09:09:53.284663 DeviceVref_Margin_A0==40
587 09:09:53.285209 VrefDac_Margin_A1==25
588 09:09:53.290341 DeviceVref_Margin_A1==40
589 09:09:53.290883
590 09:09:53.291332
591 09:09:53.291810 channel==1
592 09:09:53.292324 RxClkDly_Margin_A0==98 ps 10
593 09:09:53.293557 TxDqDly_Margin_A0==88 ps 9
594 09:09:53.299067 RxClkDly_Margin_A1==98 ps 10
595 09:09:53.299599 TxDqDly_Margin_A1==88 ps 9
596 09:09:53.300100 TrainedVREFDQ_A0==74
597 09:09:53.304684 TrainedVREFDQ_A1==77
598 09:09:53.305012 VrefDac_Margin_A0==22
599 09:09:53.310317 DeviceVref_Margin_A0==40
600 09:09:53.310681 VrefDac_Margin_A1==22
601 09:09:53.310893 DeviceVref_Margin_A1==37
602 09:09:53.311096
603 09:09:53.319226 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 09:09:53.319536
605 09:09:53.344955 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
606 09:09:53.350570 2D training succeed
607 09:09:53.356188 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 09:09:53.361706 auto size-- 65535DDR cs0 size: 2048MB
609 09:09:53.362063 DDR cs1 size: 2048MB
610 09:09:53.367466 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 09:09:53.367791 cs0 DataBus test pass
612 09:09:53.368055 cs1 DataBus test pass
613 09:09:53.372962 cs0 AddrBus test pass
614 09:09:53.373554 cs1 AddrBus test pass
615 09:09:53.373835
616 09:09:53.374079 100bdlr_step_size ps== 420
617 09:09:53.378586 result report
618 09:09:53.378917 boot times 0Enable ddr reg access
619 09:09:53.386400 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 09:09:53.400025 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 09:09:53.974506 0.0;M3 CHK:0;cm4_sp_mode 0
622 09:09:53.975226 MVN_1=0x00000000
623 09:09:53.980080 MVN_2=0x00000000
624 09:09:53.985831 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 09:09:53.986404 OPS=0x10
626 09:09:53.986903 ring efuse init
627 09:09:53.987381 chipver efuse init
628 09:09:53.994020 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 09:09:53.994592 [0.018960 Inits done]
630 09:09:54.001527 secure task start!
631 09:09:54.002040 high task start!
632 09:09:54.002479 low task start!
633 09:09:54.002912 run into bl31
634 09:09:54.008233 NOTICE: BL31: v1.3(release):4fc40b1
635 09:09:54.016115 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 09:09:54.016704 NOTICE: BL31: G12A normal boot!
637 09:09:54.041404 NOTICE: BL31: BL33 decompress pass
638 09:09:54.047083 ERROR: Error initializing runtime service opteed_fast
639 09:09:55.279963
640 09:09:55.280660
641 09:09:55.288323 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 09:09:55.288859
643 09:09:55.289309 Model: Libre Computer AML-A311D-CC Alta
644 09:09:55.497903 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 09:09:55.520208 DRAM: 2 GiB (effective 3.8 GiB)
646 09:09:55.663248 Core: 408 devices, 31 uclasses, devicetree: separate
647 09:09:55.668998 WDT: Not starting watchdog@f0d0
648 09:09:55.701249 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 09:09:55.713715 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 09:09:55.718731 ** Bad device specification mmc 0 **
651 09:09:55.729078 Card did not respond to voltage select! : -110
652 09:09:55.737413 ** Bad device specification mmc 0 **
653 09:09:55.738111 Couldn't find partition mmc 0
654 09:09:55.745891 Card did not respond to voltage select! : -110
655 09:09:55.750666 ** Bad device specification mmc 0 **
656 09:09:55.751264 Couldn't find partition mmc 0
657 09:09:55.760247 Error: could not access storage.
658 09:09:56.098102 Net: eth0: ethernet@ff3f0000
659 09:09:56.098560 starting USB...
660 09:09:56.350123 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 09:09:56.350554 Starting the controller
662 09:09:56.356793 USB XHCI 1.10
663 09:09:58.067416 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 09:09:58.067857 bl2_stage_init 0x01
665 09:09:58.068119 bl2_stage_init 0x81
666 09:09:58.072990 hw id: 0x0000 - pwm id 0x01
667 09:09:58.073347 bl2_stage_init 0xc1
668 09:09:58.073584 bl2_stage_init 0x02
669 09:09:58.073810
670 09:09:58.078613 L0:00000000
671 09:09:58.078963 L1:20000703
672 09:09:58.079193 L2:00008067
673 09:09:58.079411 L3:14000000
674 09:09:58.084333 B2:00402000
675 09:09:58.084687 B1:e0f83180
676 09:09:58.084910
677 09:09:58.085119 TE: 58159
678 09:09:58.085322
679 09:09:58.089833 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 09:09:58.090182
681 09:09:58.090406 Board ID = 1
682 09:09:58.095579 Set A53 clk to 24M
683 09:09:58.095955 Set A73 clk to 24M
684 09:09:58.096212 Set clk81 to 24M
685 09:09:58.101057 A53 clk: 1200 MHz
686 09:09:58.101468 A73 clk: 1200 MHz
687 09:09:58.101698 CLK81: 166.6M
688 09:09:58.101907 smccc: 00012ab5
689 09:09:58.106790 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 09:09:58.112204 board id: 1
691 09:09:58.117959 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 09:09:58.128757 fw parse done
693 09:09:58.134178 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 09:09:58.176508 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 09:09:58.188314 PIEI prepare done
696 09:09:58.188902 fastboot data load
697 09:09:58.189213 fastboot data verify
698 09:09:58.193875 verify result: 266
699 09:09:58.199704 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 09:09:58.200142 LPDDR4 probe
701 09:09:58.200394 ddr clk to 1584MHz
702 09:09:58.207919 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 09:09:58.244980
704 09:09:58.245417 dmc_version 0001
705 09:09:58.251049 Check phy result
706 09:09:58.257342 INFO : End of CA training
707 09:09:58.257739 INFO : End of initialization
708 09:09:58.262834 INFO : Training has run successfully!
709 09:09:58.263244 Check phy result
710 09:09:58.268487 INFO : End of initialization
711 09:09:58.268880 INFO : End of read enable training
712 09:09:58.274097 INFO : End of fine write leveling
713 09:09:58.279765 INFO : End of Write leveling coarse delay
714 09:09:58.280432 INFO : Training has run successfully!
715 09:09:58.280843 Check phy result
716 09:09:58.285320 INFO : End of initialization
717 09:09:58.285938 INFO : End of read dq deskew training
718 09:09:58.290923 INFO : End of MPR read delay center optimization
719 09:09:58.296540 INFO : End of write delay center optimization
720 09:09:58.302115 INFO : End of read delay center optimization
721 09:09:58.302532 INFO : End of max read latency training
722 09:09:58.307797 INFO : Training has run successfully!
723 09:09:58.308250 1D training succeed
724 09:09:58.316439 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 09:09:58.364486 Check phy result
726 09:09:58.364909 INFO : End of initialization
727 09:09:58.386682 INFO : End of 2D read delay Voltage center optimization
728 09:09:58.406517 INFO : End of 2D read delay Voltage center optimization
729 09:09:58.458992 INFO : End of 2D write delay Voltage center optimization
730 09:09:58.508900 INFO : End of 2D write delay Voltage center optimization
731 09:09:58.514280 INFO : Training has run successfully!
732 09:09:58.514613
733 09:09:58.514824 channel==0
734 09:09:58.519867 RxClkDly_Margin_A0==88 ps 9
735 09:09:58.520246 TxDqDly_Margin_A0==98 ps 10
736 09:09:58.525469 RxClkDly_Margin_A1==88 ps 9
737 09:09:58.525828 TxDqDly_Margin_A1==98 ps 10
738 09:09:58.526077 TrainedVREFDQ_A0==74
739 09:09:58.531203 TrainedVREFDQ_A1==74
740 09:09:58.531750 VrefDac_Margin_A0==24
741 09:09:58.532258 DeviceVref_Margin_A0==40
742 09:09:58.536685 VrefDac_Margin_A1==25
743 09:09:58.537185 DeviceVref_Margin_A1==40
744 09:09:58.537639
745 09:09:58.538156
746 09:09:58.542283 channel==1
747 09:09:58.542815 RxClkDly_Margin_A0==98 ps 10
748 09:09:58.543274 TxDqDly_Margin_A0==88 ps 9
749 09:09:58.547849 RxClkDly_Margin_A1==88 ps 9
750 09:09:58.548393 TxDqDly_Margin_A1==88 ps 9
751 09:09:58.553414 TrainedVREFDQ_A0==75
752 09:09:58.553914 TrainedVREFDQ_A1==77
753 09:09:58.554370 VrefDac_Margin_A0==22
754 09:09:58.559115 DeviceVref_Margin_A0==39
755 09:09:58.559609 VrefDac_Margin_A1==24
756 09:09:58.564832 DeviceVref_Margin_A1==37
757 09:09:58.565328
758 09:09:58.565782 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 09:09:58.566232
760 09:09:58.598280 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
761 09:09:58.598876 2D training succeed
762 09:09:58.603934 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 09:09:58.609406 auto size-- 65535DDR cs0 size: 2048MB
764 09:09:58.609763 DDR cs1 size: 2048MB
765 09:09:58.615095 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 09:09:58.615426 cs0 DataBus test pass
767 09:09:58.620677 cs1 DataBus test pass
768 09:09:58.621041 cs0 AddrBus test pass
769 09:09:58.621298 cs1 AddrBus test pass
770 09:09:58.621539
771 09:09:58.626200 100bdlr_step_size ps== 420
772 09:09:58.626543 result report
773 09:09:58.631811 boot times 0Enable ddr reg access
774 09:09:58.637066 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 09:09:58.649867 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 09:09:59.224277 0.0;M3 CHK:0;cm4_sp_mode 0
777 09:09:59.224983 MVN_1=0x00000000
778 09:09:59.229805 MVN_2=0x00000000
779 09:09:59.235559 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 09:09:59.236211 OPS=0x10
781 09:09:59.236683 ring efuse init
782 09:09:59.237121 chipver efuse init
783 09:09:59.241130 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 09:09:59.246691 [0.018961 Inits done]
785 09:09:59.247191 secure task start!
786 09:09:59.247630 high task start!
787 09:09:59.250664 low task start!
788 09:09:59.251232 run into bl31
789 09:09:59.257969 NOTICE: BL31: v1.3(release):4fc40b1
790 09:09:59.265127 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 09:09:59.265637 NOTICE: BL31: G12A normal boot!
792 09:09:59.291717 NOTICE: BL31: BL33 decompress pass
793 09:09:59.296643 ERROR: Error initializing runtime service opteed_fast
794 09:10:00.530035
795 09:10:00.530457
796 09:10:00.537738 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 09:10:00.538074
798 09:10:00.538286 Model: Libre Computer AML-A311D-CC Alta
799 09:10:00.928319 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 09:10:00.928935 DRAM: 2 GiB (effective 3.8 GiB)
801 09:10:00.930090 Core: 408 devices, 31 uclasses, devicetree: separate
802 09:10:00.930569 WDT: Not starting watchdog@f0d0
803 09:10:00.951534 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 09:10:00.964316 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 09:10:00.967927 ** Bad device specification mmc 0 **
806 09:10:00.979287 Card did not respond to voltage select! : -110
807 09:10:00.986813 ** Bad device specification mmc 0 **
808 09:10:00.987336 Couldn't find partition mmc 0
809 09:10:00.995228 Card did not respond to voltage select! : -110
810 09:10:01.000717 ** Bad device specification mmc 0 **
811 09:10:01.001247 Couldn't find partition mmc 0
812 09:10:01.004819 Error: could not access storage.
813 09:10:01.348328 Net: eth0: ethernet@ff3f0000
814 09:10:01.348765 starting USB...
815 09:10:01.600120 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 09:10:01.600544 Starting the controller
817 09:10:01.606280 USB XHCI 1.10
818 09:10:03.768765 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 09:10:03.769220 bl2_stage_init 0x01
820 09:10:03.769539 bl2_stage_init 0x81
821 09:10:03.773949 hw id: 0x0000 - pwm id 0x01
822 09:10:03.774337 bl2_stage_init 0xc1
823 09:10:03.774580 bl2_stage_init 0x02
824 09:10:03.774807
825 09:10:03.779550 L0:00000000
826 09:10:03.779924 L1:20000703
827 09:10:03.780214 L2:00008067
828 09:10:03.780444 L3:14000000
829 09:10:03.782367 B2:00402000
830 09:10:03.782691 B1:e0f83180
831 09:10:03.782952
832 09:10:03.783241 TE: 58159
833 09:10:03.783517
834 09:10:03.793605 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 09:10:03.794209
836 09:10:03.794646 Board ID = 1
837 09:10:03.794924 Set A53 clk to 24M
838 09:10:03.795153 Set A73 clk to 24M
839 09:10:03.799166 Set clk81 to 24M
840 09:10:03.799683 A53 clk: 1200 MHz
841 09:10:03.799955 A73 clk: 1200 MHz
842 09:10:03.803022 CLK81: 166.6M
843 09:10:03.803508 smccc: 00012ab5
844 09:10:03.808335 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 09:10:03.814052 board id: 1
846 09:10:03.818574 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 09:10:03.829438 fw parse done
848 09:10:03.835832 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 09:10:03.878346 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 09:10:03.889259 PIEI prepare done
851 09:10:03.889901 fastboot data load
852 09:10:03.890406 fastboot data verify
853 09:10:03.895106 verify result: 266
854 09:10:03.900489 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 09:10:03.901080 LPDDR4 probe
856 09:10:03.901592 ddr clk to 1584MHz
857 09:10:03.908486 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 09:10:03.944705
859 09:10:03.945338 dmc_version 0001
860 09:10:03.951415 Check phy result
861 09:10:03.958186 INFO : End of CA training
862 09:10:03.958756 INFO : End of initialization
863 09:10:03.963777 INFO : Training has run successfully!
864 09:10:03.964358 Check phy result
865 09:10:03.969368 INFO : End of initialization
866 09:10:03.969922 INFO : End of read enable training
867 09:10:03.974961 INFO : End of fine write leveling
868 09:10:03.980590 INFO : End of Write leveling coarse delay
869 09:10:03.981196 INFO : Training has run successfully!
870 09:10:03.981679 Check phy result
871 09:10:03.986178 INFO : End of initialization
872 09:10:03.986825 INFO : End of read dq deskew training
873 09:10:03.991804 INFO : End of MPR read delay center optimization
874 09:10:03.997376 INFO : End of write delay center optimization
875 09:10:04.002983 INFO : End of read delay center optimization
876 09:10:04.003571 INFO : End of max read latency training
877 09:10:04.008542 INFO : Training has run successfully!
878 09:10:04.009116 1D training succeed
879 09:10:04.017732 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 09:10:04.065311 Check phy result
881 09:10:04.065971 INFO : End of initialization
882 09:10:04.087953 INFO : End of 2D read delay Voltage center optimization
883 09:10:04.106983 INFO : End of 2D read delay Voltage center optimization
884 09:10:04.158976 INFO : End of 2D write delay Voltage center optimization
885 09:10:04.209174 INFO : End of 2D write delay Voltage center optimization
886 09:10:04.214826 INFO : Training has run successfully!
887 09:10:04.215414
888 09:10:04.215927 channel==0
889 09:10:04.220607 RxClkDly_Margin_A0==88 ps 9
890 09:10:04.221616 TxDqDly_Margin_A0==98 ps 10
891 09:10:04.225920 RxClkDly_Margin_A1==88 ps 9
892 09:10:04.226503 TxDqDly_Margin_A1==98 ps 10
893 09:10:04.226960 TrainedVREFDQ_A0==74
894 09:10:04.231602 TrainedVREFDQ_A1==74
895 09:10:04.232590 VrefDac_Margin_A0==24
896 09:10:04.233609 DeviceVref_Margin_A0==40
897 09:10:04.237183 VrefDac_Margin_A1==24
898 09:10:04.238259 DeviceVref_Margin_A1==40
899 09:10:04.239063
900 09:10:04.239847
901 09:10:04.242793 channel==1
902 09:10:04.244178 RxClkDly_Margin_A0==88 ps 9
903 09:10:04.245374 TxDqDly_Margin_A0==98 ps 10
904 09:10:04.248462 RxClkDly_Margin_A1==98 ps 10
905 09:10:04.249353 TxDqDly_Margin_A1==88 ps 9
906 09:10:04.254330 TrainedVREFDQ_A0==77
907 09:10:04.255749 TrainedVREFDQ_A1==77
908 09:10:04.256835 VrefDac_Margin_A0==22
909 09:10:04.259437 DeviceVref_Margin_A0==37
910 09:10:04.260026 VrefDac_Margin_A1==22
911 09:10:04.264954 DeviceVref_Margin_A1==37
912 09:10:04.265492
913 09:10:04.265913 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 09:10:04.266446
915 09:10:04.298880 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
916 09:10:04.299778 2D training succeed
917 09:10:04.304405 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 09:10:04.310077 auto size-- 65535DDR cs0 size: 2048MB
919 09:10:04.310729 DDR cs1 size: 2048MB
920 09:10:04.315567 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 09:10:04.316227 cs0 DataBus test pass
922 09:10:04.320929 cs1 DataBus test pass
923 09:10:04.321271 cs0 AddrBus test pass
924 09:10:04.321476 cs1 AddrBus test pass
925 09:10:04.321675
926 09:10:04.326473 100bdlr_step_size ps== 420
927 09:10:04.326822 result report
928 09:10:04.332072 boot times 0Enable ddr reg access
929 09:10:04.336655 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 09:10:04.351101 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 09:10:04.923010 0.0;M3 CHK:0;cm4_sp_mode 0
932 09:10:04.923792 MVN_1=0x00000000
933 09:10:04.928507 MVN_2=0x00000000
934 09:10:04.934211 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 09:10:04.934748 OPS=0x10
936 09:10:04.935303 ring efuse init
937 09:10:04.935761 chipver efuse init
938 09:10:04.939781 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 09:10:04.945382 [0.018960 Inits done]
940 09:10:04.945891 secure task start!
941 09:10:04.946347 high task start!
942 09:10:04.949939 low task start!
943 09:10:04.950451 run into bl31
944 09:10:04.956582 NOTICE: BL31: v1.3(release):4fc40b1
945 09:10:04.963558 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 09:10:04.964119 NOTICE: BL31: G12A normal boot!
947 09:10:04.989871 NOTICE: BL31: BL33 decompress pass
948 09:10:04.995581 ERROR: Error initializing runtime service opteed_fast
949 09:10:06.228246
950 09:10:06.228978
951 09:10:06.236693 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 09:10:06.237394
953 09:10:06.237961 Model: Libre Computer AML-A311D-CC Alta
954 09:10:06.444495 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 09:10:06.468496 DRAM: 2 GiB (effective 3.8 GiB)
956 09:10:06.611736 Core: 408 devices, 31 uclasses, devicetree: separate
957 09:10:06.616564 WDT: Not starting watchdog@f0d0
958 09:10:06.649766 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 09:10:06.662050 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 09:10:06.667125 ** Bad device specification mmc 0 **
961 09:10:06.677344 Card did not respond to voltage select! : -110
962 09:10:06.685019 ** Bad device specification mmc 0 **
963 09:10:06.685286 Couldn't find partition mmc 0
964 09:10:06.693331 Card did not respond to voltage select! : -110
965 09:10:06.699129 ** Bad device specification mmc 0 **
966 09:10:06.699862 Couldn't find partition mmc 0
967 09:10:06.704095 Error: could not access storage.
968 09:10:07.046393 Net: eth0: ethernet@ff3f0000
969 09:10:07.046825 starting USB...
970 09:10:07.298241 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 09:10:07.298643 Starting the controller
972 09:10:07.305150 USB XHCI 1.10
973 09:10:09.167295 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
974 09:10:09.167942 bl2_stage_init 0x81
975 09:10:09.172861 hw id: 0x0000 - pwm id 0x01
976 09:10:09.173320 bl2_stage_init 0xc1
977 09:10:09.173730 bl2_stage_init 0x02
978 09:10:09.174136
979 09:10:09.178555 L0:00000000
980 09:10:09.178999 L1:20000703
981 09:10:09.179403 L2:00008067
982 09:10:09.179798 L3:14000000
983 09:10:09.180235 B2:00402000
984 09:10:09.183958 B1:e0f83180
985 09:10:09.184587
986 09:10:09.184996 TE: 58150
987 09:10:09.185398
988 09:10:09.189527 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
989 09:10:09.189982
990 09:10:09.190386 Board ID = 1
991 09:10:09.195222 Set A53 clk to 24M
992 09:10:09.195664 Set A73 clk to 24M
993 09:10:09.196099 Set clk81 to 24M
994 09:10:09.200896 A53 clk: 1200 MHz
995 09:10:09.201349 A73 clk: 1200 MHz
996 09:10:09.201752 CLK81: 166.6M
997 09:10:09.202145 smccc: 00012aab
998 09:10:09.206647 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
999 09:10:09.212030 board id: 1
1000 09:10:09.217791 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1001 09:10:09.228567 fw parse done
1002 09:10:09.234395 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1003 09:10:09.276831 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1004 09:10:09.287744 PIEI prepare done
1005 09:10:09.288292 fastboot data load
1006 09:10:09.288694 fastboot data verify
1007 09:10:09.293551 verify result: 266
1008 09:10:09.299044 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1009 09:10:09.299484 LPDDR4 probe
1010 09:10:09.299872 ddr clk to 1584MHz
1011 09:10:09.307128 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1012 09:10:09.344417
1013 09:10:09.345003 dmc_version 0001
1014 09:10:09.350979 Check phy result
1015 09:10:09.356902 INFO : End of CA training
1016 09:10:09.357379 INFO : End of initialization
1017 09:10:09.362682 INFO : Training has run successfully!
1018 09:10:09.363112 Check phy result
1019 09:10:09.368142 INFO : End of initialization
1020 09:10:09.368666 INFO : End of read enable training
1021 09:10:09.373692 INFO : End of fine write leveling
1022 09:10:09.379297 INFO : End of Write leveling coarse delay
1023 09:10:09.379843 INFO : Training has run successfully!
1024 09:10:09.380302 Check phy result
1025 09:10:09.384889 INFO : End of initialization
1026 09:10:09.385376 INFO : End of read dq deskew training
1027 09:10:09.390512 INFO : End of MPR read delay center optimization
1028 09:10:09.396043 INFO : End of write delay center optimization
1029 09:10:09.401631 INFO : End of read delay center optimization
1030 09:10:09.402129 INFO : End of max read latency training
1031 09:10:09.407227 INFO : Training has run successfully!
1032 09:10:09.407700 1D training succeed
1033 09:10:09.416525 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1034 09:10:09.464158 Check phy result
1035 09:10:09.464739 INFO : End of initialization
1036 09:10:09.485863 INFO : End of 2D read delay Voltage center optimization
1037 09:10:09.506161 INFO : End of 2D read delay Voltage center optimization
1038 09:10:09.558136 INFO : End of 2D write delay Voltage center optimization
1039 09:10:09.607620 INFO : End of 2D write delay Voltage center optimization
1040 09:10:09.613003 INFO : Training has run successfully!
1041 09:10:09.613475
1042 09:10:09.613893 channel==0
1043 09:10:09.618653 RxClkDly_Margin_A0==88 ps 9
1044 09:10:09.619115 TxDqDly_Margin_A0==98 ps 10
1045 09:10:09.624354 RxClkDly_Margin_A1==88 ps 9
1046 09:10:09.624789 TxDqDly_Margin_A1==98 ps 10
1047 09:10:09.625188 TrainedVREFDQ_A0==74
1048 09:10:09.629871 TrainedVREFDQ_A1==74
1049 09:10:09.630322 VrefDac_Margin_A0==25
1050 09:10:09.630718 DeviceVref_Margin_A0==40
1051 09:10:09.635511 VrefDac_Margin_A1==25
1052 09:10:09.635935 DeviceVref_Margin_A1==40
1053 09:10:09.636366
1054 09:10:09.636757
1055 09:10:09.641056 channel==1
1056 09:10:09.641476 RxClkDly_Margin_A0==98 ps 10
1057 09:10:09.641870 TxDqDly_Margin_A0==98 ps 10
1058 09:10:09.646646 RxClkDly_Margin_A1==98 ps 10
1059 09:10:09.647073 TxDqDly_Margin_A1==88 ps 9
1060 09:10:09.652313 TrainedVREFDQ_A0==77
1061 09:10:09.652825 TrainedVREFDQ_A1==77
1062 09:10:09.653239 VrefDac_Margin_A0==22
1063 09:10:09.657886 DeviceVref_Margin_A0==37
1064 09:10:09.658367 VrefDac_Margin_A1==22
1065 09:10:09.663518 DeviceVref_Margin_A1==37
1066 09:10:09.663966
1067 09:10:09.664403 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1068 09:10:09.669115
1069 09:10:09.697068 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1070 09:10:09.697675 2D training succeed
1071 09:10:09.702662 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1072 09:10:09.708376 auto size-- 65535DDR cs0 size: 2048MB
1073 09:10:09.708818 DDR cs1 size: 2048MB
1074 09:10:09.713760 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1075 09:10:09.714108 cs0 DataBus test pass
1076 09:10:09.719669 cs1 DataBus test pass
1077 09:10:09.720206 cs0 AddrBus test pass
1078 09:10:09.720631 cs1 AddrBus test pass
1079 09:10:09.721021
1080 09:10:09.725072 100bdlr_step_size ps== 420
1081 09:10:09.725516 result report
1082 09:10:09.730684 boot times 0Enable ddr reg access
1083 09:10:09.736125 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1084 09:10:09.749547 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1085 09:10:10.323307 0.0;M3 CHK:0;cm4_sp_mode 0
1086 09:10:10.324024 MVN_1=0x00000000
1087 09:10:10.328700 MVN_2=0x00000000
1088 09:10:10.334935 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1089 09:10:10.335495 OPS=0x10
1090 09:10:10.335936 ring efuse init
1091 09:10:10.336437 chipver efuse init
1092 09:10:10.340059 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1093 09:10:10.345670 [0.018961 Inits done]
1094 09:10:10.346220 secure task start!
1095 09:10:10.346640 high task start!
1096 09:10:10.350231 low task start!
1097 09:10:10.350669 run into bl31
1098 09:10:10.356839 NOTICE: BL31: v1.3(release):4fc40b1
1099 09:10:10.364619 NOTICE: BL31: Built : 15:58:17, May 22 2019
1100 09:10:10.365072 NOTICE: BL31: G12A normal boot!
1101 09:10:10.390106 NOTICE: BL31: BL33 decompress pass
1102 09:10:10.395749 ERROR: Error initializing runtime service opteed_fast
1103 09:10:11.628548
1104 09:10:11.629138
1105 09:10:11.636905 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1106 09:10:11.637374
1107 09:10:11.637791 Model: Libre Computer AML-A311D-CC Alta
1108 09:10:11.845362 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1109 09:10:11.868765 DRAM: 2 GiB (effective 3.8 GiB)
1110 09:10:12.011801 Core: 408 devices, 31 uclasses, devicetree: separate
1111 09:10:12.017713 WDT: Not starting watchdog@f0d0
1112 09:10:12.049954 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1113 09:10:12.062395 Loading Environment from FAT... Card did not respond to voltage select! : -110
1114 09:10:12.067339 ** Bad device specification mmc 0 **
1115 09:10:12.077720 Card did not respond to voltage select! : -110
1116 09:10:12.085338 ** Bad device specification mmc 0 **
1117 09:10:12.085950 Couldn't find partition mmc 0
1118 09:10:12.093744 Card did not respond to voltage select! : -110
1119 09:10:12.099150 ** Bad device specification mmc 0 **
1120 09:10:12.099489 Couldn't find partition mmc 0
1121 09:10:12.104195 Error: could not access storage.
1122 09:10:12.446841 Net: eth0: ethernet@ff3f0000
1123 09:10:12.447272 starting USB...
1124 09:10:12.698574 Bus usb@ff500000: Register 3000140 NbrPorts 3
1125 09:10:12.699109 Starting the controller
1126 09:10:12.705489 USB XHCI 1.10
1127 09:10:14.259838 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1128 09:10:14.267573 scanning usb for storage devices... 0 Storage Device(s) found
1130 09:10:14.319448 Hit any key to stop autoboot: 1
1131 09:10:14.320346 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1132 09:10:14.321006 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1133 09:10:14.321514 Setting prompt string to ['=>']
1134 09:10:14.322021 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1135 09:10:14.335557 0
1136 09:10:14.336567 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1137 09:10:14.337109 Sending with 10 millisecond of delay
1139 09:10:15.471901 => setenv autoload no
1140 09:10:15.482787 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1141 09:10:15.488268 setenv autoload no
1142 09:10:15.489066 Sending with 10 millisecond of delay
1144 09:10:17.288894 => setenv initrd_high 0xffffffff
1145 09:10:17.299696 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1146 09:10:17.300593 setenv initrd_high 0xffffffff
1147 09:10:17.301303 Sending with 10 millisecond of delay
1149 09:10:18.922515 => setenv fdt_high 0xffffffff
1150 09:10:18.933320 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1151 09:10:18.933961 setenv fdt_high 0xffffffff
1152 09:10:18.934500 Sending with 10 millisecond of delay
1154 09:10:19.226710 => dhcp
1155 09:10:19.237592 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1156 09:10:19.238671 dhcp
1157 09:10:19.239186 Speed: 1000, full duplex
1158 09:10:19.239679 BOOTP broadcast 1
1159 09:10:19.486244 BOOTP broadcast 2
1160 09:10:19.497995 DHCP client bound to address 192.168.6.33 (260 ms)
1161 09:10:19.498527 Sending with 10 millisecond of delay
1163 09:10:21.175195 => setenv serverip 192.168.6.2
1164 09:10:21.185990 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1165 09:10:21.186861 setenv serverip 192.168.6.2
1166 09:10:21.187564 Sending with 10 millisecond of delay
1168 09:10:24.910832 => tftpboot 0x01080000 684540/tftp-deploy-ysqxeve5/kernel/uImage
1169 09:10:24.921405 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1170 09:10:24.921986 tftpboot 0x01080000 684540/tftp-deploy-ysqxeve5/kernel/uImage
1171 09:10:24.922233 Speed: 1000, full duplex
1172 09:10:24.922446 Using ethernet@ff3f0000 device
1173 09:10:24.924148 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1174 09:10:24.929635 Filename '684540/tftp-deploy-ysqxeve5/kernel/uImage'.
1175 09:10:24.933555 Load address: 0x1080000
1176 09:10:25.875528 Loading: *################ UDP wrong checksum 000000ff 00002a17
1177 09:10:25.885439 UDP wrong checksum 000000ff 0000d471
1178 09:10:25.892548 UDP wrong checksum 000000ff 0000ad09
1179 09:10:25.900728 # UDP wrong checksum 000000ff 00005864
1180 09:10:28.037504 ################################# 43.2 MiB
1181 09:10:28.038190 13.9 MiB/s
1182 09:10:28.038665 done
1183 09:10:28.041820 Bytes transferred = 45308480 (2b35a40 hex)
1184 09:10:28.042648 Sending with 10 millisecond of delay
1186 09:10:32.730872 => tftpboot 0x08000000 684540/tftp-deploy-ysqxeve5/ramdisk/ramdisk.cpio.gz.uboot
1187 09:10:32.741775 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1188 09:10:32.742484 tftpboot 0x08000000 684540/tftp-deploy-ysqxeve5/ramdisk/ramdisk.cpio.gz.uboot
1189 09:10:32.742710 Speed: 1000, full duplex
1190 09:10:32.742910 Using ethernet@ff3f0000 device
1191 09:10:32.744473 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1192 09:10:32.756369 Filename '684540/tftp-deploy-ysqxeve5/ramdisk/ramdisk.cpio.gz.uboot'.
1193 09:10:32.756972 Load address: 0x8000000
1194 09:10:39.480606 Loading: *############T ##################################### UDP wrong checksum 00000005 0000244c
1195 09:10:44.480507 T UDP wrong checksum 00000005 0000244c
1196 09:10:54.482559 T T UDP wrong checksum 00000005 0000244c
1197 09:11:14.486758 T T T T UDP wrong checksum 00000005 0000244c
1198 09:11:29.490363 T T
1199 09:11:29.490796 Retry count exceeded; starting again
1201 09:11:29.491691 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1204 09:11:29.492711 end: 2.4 uboot-commands (duration 00:01:52) [common]
1206 09:11:29.493434 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1208 09:11:29.494253 end: 2 uboot-action (duration 00:01:52) [common]
1210 09:11:29.495140 Cleaning after the job
1211 09:11:29.495476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/ramdisk
1212 09:11:29.496350 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/kernel
1213 09:11:29.510633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/dtb
1214 09:11:29.511472 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/nfsrootfs
1215 09:11:29.541994 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684540/tftp-deploy-ysqxeve5/modules
1216 09:11:29.548359 start: 4.1 power-off (timeout 00:00:30) [common]
1217 09:11:29.549019 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1218 09:11:29.581508 >> OK - accepted request
1219 09:11:29.583876 Returned 0 in 0 seconds
1220 09:11:29.684736 end: 4.1 power-off (duration 00:00:00) [common]
1222 09:11:29.685744 start: 4.2 read-feedback (timeout 00:10:00) [common]
1223 09:11:29.686413 Listened to connection for namespace 'common' for up to 1s
1224 09:11:30.687327 Finalising connection for namespace 'common'
1225 09:11:30.687866 Disconnecting from shell: Finalise
1226 09:11:30.688227 =>
1227 09:11:30.788908 end: 4.2 read-feedback (duration 00:00:01) [common]
1228 09:11:30.789370 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/684540
1229 09:11:33.947965 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/684540
1230 09:11:33.948559 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.