Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:38:36.990903 lava-dispatcher, installed at version: 2024.01
2 09:38:36.991677 start: 0 validate
3 09:38:36.992154 Start time: 2024-09-01 09:38:36.992124+00:00 (UTC)
4 09:38:36.992722 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:38:36.993262 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:38:37.034867 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:38:37.035408 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:38:37.067370 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:38:37.068018 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:38:37.106901 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:38:37.107724 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:38:37.139541 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 09:38:37.140078 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.11-rc6%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 09:38:37.183602 validate duration: 0.19
16 09:38:37.185134 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:38:37.185734 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:38:37.186326 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:38:37.187259 Not decompressing ramdisk as can be used compressed.
20 09:38:37.188026 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 09:38:37.188547 saving as /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/ramdisk/initrd.cpio.gz
22 09:38:37.189064 total size: 5628140 (5 MB)
23 09:38:37.233828 progress 0 % (0 MB)
24 09:38:37.241609 progress 5 % (0 MB)
25 09:38:37.250164 progress 10 % (0 MB)
26 09:38:37.257693 progress 15 % (0 MB)
27 09:38:37.263600 progress 20 % (1 MB)
28 09:38:37.267570 progress 25 % (1 MB)
29 09:38:37.271556 progress 30 % (1 MB)
30 09:38:37.275491 progress 35 % (1 MB)
31 09:38:37.278963 progress 40 % (2 MB)
32 09:38:37.282929 progress 45 % (2 MB)
33 09:38:37.286484 progress 50 % (2 MB)
34 09:38:37.290406 progress 55 % (2 MB)
35 09:38:37.294344 progress 60 % (3 MB)
36 09:38:37.297926 progress 65 % (3 MB)
37 09:38:37.301894 progress 70 % (3 MB)
38 09:38:37.305403 progress 75 % (4 MB)
39 09:38:37.309293 progress 80 % (4 MB)
40 09:38:37.312789 progress 85 % (4 MB)
41 09:38:37.316540 progress 90 % (4 MB)
42 09:38:37.320164 progress 95 % (5 MB)
43 09:38:37.323368 progress 100 % (5 MB)
44 09:38:37.324020 5 MB downloaded in 0.13 s (39.78 MB/s)
45 09:38:37.324569 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:38:37.325443 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:38:37.325732 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:38:37.326003 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:38:37.326480 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig/gcc-12/kernel/Image
51 09:38:37.326720 saving as /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/kernel/Image
52 09:38:37.326930 total size: 45308416 (43 MB)
53 09:38:37.327142 No compression specified
54 09:38:37.359322 progress 0 % (0 MB)
55 09:38:37.391605 progress 5 % (2 MB)
56 09:38:37.420160 progress 10 % (4 MB)
57 09:38:37.448542 progress 15 % (6 MB)
58 09:38:37.477960 progress 20 % (8 MB)
59 09:38:37.508285 progress 25 % (10 MB)
60 09:38:37.537531 progress 30 % (12 MB)
61 09:38:37.566647 progress 35 % (15 MB)
62 09:38:37.595364 progress 40 % (17 MB)
63 09:38:37.624136 progress 45 % (19 MB)
64 09:38:37.654101 progress 50 % (21 MB)
65 09:38:37.682429 progress 55 % (23 MB)
66 09:38:37.711462 progress 60 % (25 MB)
67 09:38:37.740333 progress 65 % (28 MB)
68 09:38:37.769571 progress 70 % (30 MB)
69 09:38:37.798863 progress 75 % (32 MB)
70 09:38:37.827274 progress 80 % (34 MB)
71 09:38:37.855795 progress 85 % (36 MB)
72 09:38:37.884318 progress 90 % (38 MB)
73 09:38:37.912732 progress 95 % (41 MB)
74 09:38:37.940589 progress 100 % (43 MB)
75 09:38:37.941326 43 MB downloaded in 0.61 s (70.33 MB/s)
76 09:38:37.941811 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:38:37.942643 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:38:37.942923 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:38:37.943192 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:38:37.943673 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 09:38:37.943920 saving as /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/dtb/meson-g12b-a311d-libretech-cc.dtb
83 09:38:37.944158 total size: 54667 (0 MB)
84 09:38:37.944371 No compression specified
85 09:38:37.984399 progress 59 % (0 MB)
86 09:38:37.985290 progress 100 % (0 MB)
87 09:38:37.985881 0 MB downloaded in 0.04 s (1.25 MB/s)
88 09:38:37.986381 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:38:37.987273 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:38:37.987568 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:38:37.987858 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:38:37.988462 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 09:38:37.988738 saving as /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/nfsrootfs/full.rootfs.tar
95 09:38:37.988957 total size: 474398908 (452 MB)
96 09:38:37.989180 Using unxz to decompress xz
97 09:38:38.022255 progress 0 % (0 MB)
98 09:38:39.135138 progress 5 % (22 MB)
99 09:38:40.647721 progress 10 % (45 MB)
100 09:38:41.143812 progress 15 % (67 MB)
101 09:38:41.964304 progress 20 % (90 MB)
102 09:38:42.500395 progress 25 % (113 MB)
103 09:38:42.902968 progress 30 % (135 MB)
104 09:38:43.556025 progress 35 % (158 MB)
105 09:38:44.456778 progress 40 % (181 MB)
106 09:38:45.309255 progress 45 % (203 MB)
107 09:38:45.880229 progress 50 % (226 MB)
108 09:38:46.530406 progress 55 % (248 MB)
109 09:38:47.729820 progress 60 % (271 MB)
110 09:38:49.179131 progress 65 % (294 MB)
111 09:38:50.759732 progress 70 % (316 MB)
112 09:38:54.003816 progress 75 % (339 MB)
113 09:38:56.505701 progress 80 % (361 MB)
114 09:38:59.553023 progress 85 % (384 MB)
115 09:39:03.172024 progress 90 % (407 MB)
116 09:39:06.379727 progress 95 % (429 MB)
117 09:39:09.547346 progress 100 % (452 MB)
118 09:39:09.560301 452 MB downloaded in 31.57 s (14.33 MB/s)
119 09:39:09.561293 end: 1.4.1 http-download (duration 00:00:32) [common]
121 09:39:09.563039 end: 1.4 download-retry (duration 00:00:32) [common]
122 09:39:09.563611 start: 1.5 download-retry (timeout 00:09:28) [common]
123 09:39:09.564221 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 09:39:09.565107 downloading http://storage.kernelci.org/mainline/master/v6.11-rc6/arm64/defconfig/gcc-12/modules.tar.xz
125 09:39:09.565627 saving as /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/modules/modules.tar
126 09:39:09.566074 total size: 11499436 (10 MB)
127 09:39:09.566530 Using unxz to decompress xz
128 09:39:09.608914 progress 0 % (0 MB)
129 09:39:09.694231 progress 5 % (0 MB)
130 09:39:09.797696 progress 10 % (1 MB)
131 09:39:09.901172 progress 15 % (1 MB)
132 09:39:10.014995 progress 20 % (2 MB)
133 09:39:10.108114 progress 25 % (2 MB)
134 09:39:10.211921 progress 30 % (3 MB)
135 09:39:10.303631 progress 35 % (3 MB)
136 09:39:10.408910 progress 40 % (4 MB)
137 09:39:10.510948 progress 45 % (4 MB)
138 09:39:10.616482 progress 50 % (5 MB)
139 09:39:10.728389 progress 55 % (6 MB)
140 09:39:10.825323 progress 60 % (6 MB)
141 09:39:10.937382 progress 65 % (7 MB)
142 09:39:11.035868 progress 70 % (7 MB)
143 09:39:11.144849 progress 75 % (8 MB)
144 09:39:11.265641 progress 80 % (8 MB)
145 09:39:11.379628 progress 85 % (9 MB)
146 09:39:11.450316 progress 90 % (9 MB)
147 09:39:11.529919 progress 95 % (10 MB)
148 09:39:11.601754 progress 100 % (10 MB)
149 09:39:11.616493 10 MB downloaded in 2.05 s (5.35 MB/s)
150 09:39:11.617442 end: 1.5.1 http-download (duration 00:00:02) [common]
152 09:39:11.619139 end: 1.5 download-retry (duration 00:00:02) [common]
153 09:39:11.619712 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 09:39:11.620342 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 09:39:27.642975 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/684617/extract-nfsrootfs-ebwf44tk
156 09:39:27.643579 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 09:39:27.643891 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 09:39:27.644814 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf
159 09:39:27.645437 makedir: /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin
160 09:39:27.645857 makedir: /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/tests
161 09:39:27.646271 makedir: /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/results
162 09:39:27.646683 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-add-keys
163 09:39:27.647373 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-add-sources
164 09:39:27.648046 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-background-process-start
165 09:39:27.648744 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-background-process-stop
166 09:39:27.649480 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-common-functions
167 09:39:27.651634 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-echo-ipv4
168 09:39:27.652704 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-install-packages
169 09:39:27.653344 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-installed-packages
170 09:39:27.654056 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-os-build
171 09:39:27.654738 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-probe-channel
172 09:39:27.655333 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-probe-ip
173 09:39:27.656181 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-target-ip
174 09:39:27.656824 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-target-mac
175 09:39:27.658280 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-target-storage
176 09:39:27.658926 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-test-case
177 09:39:27.659579 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-test-event
178 09:39:27.661403 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-test-feedback
179 09:39:27.663029 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-test-raise
180 09:39:27.663669 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-test-reference
181 09:39:27.664635 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-test-runner
182 09:39:27.665702 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-test-set
183 09:39:27.669983 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-test-shell
184 09:39:27.670651 Updating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-install-packages (oe)
185 09:39:27.671316 Updating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/bin/lava-installed-packages (oe)
186 09:39:27.671908 Creating /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/environment
187 09:39:27.672414 LAVA metadata
188 09:39:27.672707 - LAVA_JOB_ID=684617
189 09:39:27.672931 - LAVA_DISPATCHER_IP=192.168.6.2
190 09:39:27.673334 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 09:39:27.674438 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 09:39:27.674818 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 09:39:27.675036 skipped lava-vland-overlay
194 09:39:27.675284 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 09:39:27.675548 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 09:39:27.675776 skipped lava-multinode-overlay
197 09:39:27.676052 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 09:39:27.676359 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 09:39:27.676646 Loading test definitions
200 09:39:27.676943 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 09:39:27.677171 Using /lava-684617 at stage 0
202 09:39:27.678607 uuid=684617_1.6.2.4.1 testdef=None
203 09:39:27.678987 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 09:39:27.679268 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 09:39:27.681235 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 09:39:27.682133 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 09:39:27.684599 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 09:39:27.685504 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:09) [common]
211 09:39:27.687973 runner path: /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 684617_1.6.2.4.1
212 09:39:27.688766 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 09:39:27.689577 Creating lava-test-runner.conf files
215 09:39:27.689786 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/684617/lava-overlay-vtk788zf/lava-684617/0 for stage 0
216 09:39:27.690172 - 0_v4l2-decoder-conformance-h265
217 09:39:27.690595 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 09:39:27.690896 start: 1.6.2.5 compress-overlay (timeout 00:09:09) [common]
219 09:39:27.714745 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 09:39:27.715189 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:09) [common]
221 09:39:27.715482 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 09:39:27.715776 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 09:39:27.716085 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:09) [common]
224 09:39:28.564844 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 09:39:28.565309 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
226 09:39:28.565586 extracting modules file /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/684617/extract-nfsrootfs-ebwf44tk
227 09:39:30.075686 extracting modules file /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/684617/extract-overlay-ramdisk-5uec4vzc/ramdisk
228 09:39:31.486426 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 09:39:31.486870 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 09:39:31.487149 [common] Applying overlay to NFS
231 09:39:31.487363 [common] Applying overlay /var/lib/lava/dispatcher/tmp/684617/compress-overlay-foqfkyle/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/684617/extract-nfsrootfs-ebwf44tk
232 09:39:31.517130 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 09:39:31.517502 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 09:39:31.517772 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 09:39:31.518000 Converting downloaded kernel to a uImage
236 09:39:31.518313 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/kernel/Image /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/kernel/uImage
237 09:39:32.047129 output: Image Name:
238 09:39:32.047529 output: Created: Sun Sep 1 09:39:31 2024
239 09:39:32.047740 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 09:39:32.047946 output: Data Size: 45308416 Bytes = 44246.50 KiB = 43.21 MiB
241 09:39:32.048183 output: Load Address: 01080000
242 09:39:32.048386 output: Entry Point: 01080000
243 09:39:32.048587 output:
244 09:39:32.048924 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 09:39:32.049192 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 09:39:32.049461 start: 1.6.7 configure-preseed-file (timeout 00:09:05) [common]
247 09:39:32.049713 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 09:39:32.049970 start: 1.6.8 compress-ramdisk (timeout 00:09:05) [common]
249 09:39:32.050224 Building ramdisk /var/lib/lava/dispatcher/tmp/684617/extract-overlay-ramdisk-5uec4vzc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/684617/extract-overlay-ramdisk-5uec4vzc/ramdisk
250 09:39:34.739246 >> 165160 blocks
251 09:39:42.360097 Adding RAMdisk u-boot header.
252 09:39:42.360593 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/684617/extract-overlay-ramdisk-5uec4vzc/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/684617/extract-overlay-ramdisk-5uec4vzc/ramdisk.cpio.gz.uboot
253 09:39:42.604335 output: Image Name:
254 09:39:42.604721 output: Created: Sun Sep 1 09:39:42 2024
255 09:39:42.604937 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 09:39:42.605144 output: Data Size: 23256617 Bytes = 22711.54 KiB = 22.18 MiB
257 09:39:42.605346 output: Load Address: 00000000
258 09:39:42.605547 output: Entry Point: 00000000
259 09:39:42.605746 output:
260 09:39:42.606408 rename /var/lib/lava/dispatcher/tmp/684617/extract-overlay-ramdisk-5uec4vzc/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/ramdisk/ramdisk.cpio.gz.uboot
261 09:39:42.606838 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 09:39:42.607129 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 09:39:42.607403 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:55) [common]
264 09:39:42.607652 No LXC device requested
265 09:39:42.607911 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 09:39:42.608494 start: 1.8 deploy-device-env (timeout 00:08:55) [common]
267 09:39:42.609072 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 09:39:42.609534 Checking files for TFTP limit of 4294967296 bytes.
269 09:39:42.612463 end: 1 tftp-deploy (duration 00:01:05) [common]
270 09:39:42.613097 start: 2 uboot-action (timeout 00:05:00) [common]
271 09:39:42.613674 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 09:39:42.614221 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 09:39:42.614769 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 09:39:42.615340 Using kernel file from prepare-kernel: 684617/tftp-deploy-jn0_54y8/kernel/uImage
275 09:39:42.616055 substitutions:
276 09:39:42.616508 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 09:39:42.616949 - {DTB_ADDR}: 0x01070000
278 09:39:42.617388 - {DTB}: 684617/tftp-deploy-jn0_54y8/dtb/meson-g12b-a311d-libretech-cc.dtb
279 09:39:42.617824 - {INITRD}: 684617/tftp-deploy-jn0_54y8/ramdisk/ramdisk.cpio.gz.uboot
280 09:39:42.618258 - {KERNEL_ADDR}: 0x01080000
281 09:39:42.618688 - {KERNEL}: 684617/tftp-deploy-jn0_54y8/kernel/uImage
282 09:39:42.619123 - {LAVA_MAC}: None
283 09:39:42.619593 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/684617/extract-nfsrootfs-ebwf44tk
284 09:39:42.620054 - {NFS_SERVER_IP}: 192.168.6.2
285 09:39:42.620486 - {PRESEED_CONFIG}: None
286 09:39:42.620914 - {PRESEED_LOCAL}: None
287 09:39:42.621341 - {RAMDISK_ADDR}: 0x08000000
288 09:39:42.621762 - {RAMDISK}: 684617/tftp-deploy-jn0_54y8/ramdisk/ramdisk.cpio.gz.uboot
289 09:39:42.622188 - {ROOT_PART}: None
290 09:39:42.622614 - {ROOT}: None
291 09:39:42.623038 - {SERVER_IP}: 192.168.6.2
292 09:39:42.623461 - {TEE_ADDR}: 0x83000000
293 09:39:42.623884 - {TEE}: None
294 09:39:42.624378 Parsed boot commands:
295 09:39:42.624797 - setenv autoload no
296 09:39:42.625221 - setenv initrd_high 0xffffffff
297 09:39:42.625645 - setenv fdt_high 0xffffffff
298 09:39:42.626067 - dhcp
299 09:39:42.626487 - setenv serverip 192.168.6.2
300 09:39:42.626906 - tftpboot 0x01080000 684617/tftp-deploy-jn0_54y8/kernel/uImage
301 09:39:42.627328 - tftpboot 0x08000000 684617/tftp-deploy-jn0_54y8/ramdisk/ramdisk.cpio.gz.uboot
302 09:39:42.627750 - tftpboot 0x01070000 684617/tftp-deploy-jn0_54y8/dtb/meson-g12b-a311d-libretech-cc.dtb
303 09:39:42.628204 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/684617/extract-nfsrootfs-ebwf44tk,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 09:39:42.628641 - bootm 0x01080000 0x08000000 0x01070000
305 09:39:42.629181 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 09:39:42.630796 start: 2.3 connect-device (timeout 00:05:00) [common]
308 09:39:42.631250 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 09:39:42.646430 Setting prompt string to ['lava-test: # ']
310 09:39:42.648035 end: 2.3 connect-device (duration 00:00:00) [common]
311 09:39:42.648700 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 09:39:42.649320 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 09:39:42.649910 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 09:39:42.651104 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 09:39:42.686153 >> OK - accepted request
316 09:39:42.688018 Returned 0 in 0 seconds
317 09:39:42.789196 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 09:39:42.790883 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 09:39:42.791500 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 09:39:42.792115 Setting prompt string to ['Hit any key to stop autoboot']
322 09:39:42.792629 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 09:39:42.794285 Trying 192.168.56.21...
324 09:39:42.794794 Connected to conserv1.
325 09:39:42.795248 Escape character is '^]'.
326 09:39:42.795706
327 09:39:42.796207 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 09:39:42.796666
329 09:39:54.277331 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 09:39:54.277978 bl2_stage_init 0x01
331 09:39:54.278427 bl2_stage_init 0x81
332 09:39:54.282860 hw id: 0x0000 - pwm id 0x01
333 09:39:54.283361 bl2_stage_init 0xc1
334 09:39:54.283798 bl2_stage_init 0x02
335 09:39:54.284290
336 09:39:54.288461 L0:00000000
337 09:39:54.288942 L1:20000703
338 09:39:54.289377 L2:00008067
339 09:39:54.289800 L3:14000000
340 09:39:54.294038 B2:00402000
341 09:39:54.294506 B1:e0f83180
342 09:39:54.294934
343 09:39:54.295365 TE: 58124
344 09:39:54.295793
345 09:39:54.299610 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 09:39:54.300104
347 09:39:54.300542 Board ID = 1
348 09:39:54.305331 Set A53 clk to 24M
349 09:39:54.305795 Set A73 clk to 24M
350 09:39:54.306228 Set clk81 to 24M
351 09:39:54.310874 A53 clk: 1200 MHz
352 09:39:54.311330 A73 clk: 1200 MHz
353 09:39:54.311757 CLK81: 166.6M
354 09:39:54.312219 smccc: 00012a92
355 09:39:54.316489 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 09:39:54.322065 board id: 1
357 09:39:54.327927 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 09:39:54.338624 fw parse done
359 09:39:54.344555 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 09:39:54.387297 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 09:39:54.398122 PIEI prepare done
362 09:39:54.398579 fastboot data load
363 09:39:54.399011 fastboot data verify
364 09:39:54.403828 verify result: 266
365 09:39:54.409355 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 09:39:54.409808 LPDDR4 probe
367 09:39:54.410233 ddr clk to 1584MHz
368 09:39:54.417431 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 09:39:54.454622
370 09:39:54.455099 dmc_version 0001
371 09:39:54.461383 Check phy result
372 09:39:54.467141 INFO : End of CA training
373 09:39:54.467603 INFO : End of initialization
374 09:39:54.472744 INFO : Training has run successfully!
375 09:39:54.473205 Check phy result
376 09:39:54.478316 INFO : End of initialization
377 09:39:54.478775 INFO : End of read enable training
378 09:39:54.483949 INFO : End of fine write leveling
379 09:39:54.489464 INFO : End of Write leveling coarse delay
380 09:39:54.489921 INFO : Training has run successfully!
381 09:39:54.490353 Check phy result
382 09:39:54.495074 INFO : End of initialization
383 09:39:54.495529 INFO : End of read dq deskew training
384 09:39:54.500713 INFO : End of MPR read delay center optimization
385 09:39:54.506360 INFO : End of write delay center optimization
386 09:39:54.511917 INFO : End of read delay center optimization
387 09:39:54.512417 INFO : End of max read latency training
388 09:39:54.517515 INFO : Training has run successfully!
389 09:39:54.517967 1D training succeed
390 09:39:54.526703 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 09:39:54.574576 Check phy result
392 09:39:54.575151 INFO : End of initialization
393 09:39:54.596045 INFO : End of 2D read delay Voltage center optimization
394 09:39:54.616130 INFO : End of 2D read delay Voltage center optimization
395 09:39:54.668070 INFO : End of 2D write delay Voltage center optimization
396 09:39:54.717266 INFO : End of 2D write delay Voltage center optimization
397 09:39:54.722768 INFO : Training has run successfully!
398 09:39:54.723507
399 09:39:54.723727 channel==0
400 09:39:54.728417 RxClkDly_Margin_A0==88 ps 9
401 09:39:54.728932 TxDqDly_Margin_A0==98 ps 10
402 09:39:54.734018 RxClkDly_Margin_A1==88 ps 9
403 09:39:54.734577 TxDqDly_Margin_A1==88 ps 9
404 09:39:54.734789 TrainedVREFDQ_A0==74
405 09:39:54.739609 TrainedVREFDQ_A1==74
406 09:39:54.740184 VrefDac_Margin_A0==25
407 09:39:54.740397 DeviceVref_Margin_A0==40
408 09:39:54.745215 VrefDac_Margin_A1==25
409 09:39:54.745803 DeviceVref_Margin_A1==40
410 09:39:54.746013
411 09:39:54.746246
412 09:39:54.746706 channel==1
413 09:39:54.750803 RxClkDly_Margin_A0==98 ps 10
414 09:39:54.751375 TxDqDly_Margin_A0==98 ps 10
415 09:39:54.756392 RxClkDly_Margin_A1==88 ps 9
416 09:39:54.756940 TxDqDly_Margin_A1==88 ps 9
417 09:39:54.761962 TrainedVREFDQ_A0==77
418 09:39:54.762258 TrainedVREFDQ_A1==77
419 09:39:54.762467 VrefDac_Margin_A0==22
420 09:39:54.767632 DeviceVref_Margin_A0==37
421 09:39:54.768263 VrefDac_Margin_A1==24
422 09:39:54.773093 DeviceVref_Margin_A1==37
423 09:39:54.773382
424 09:39:54.773591 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 09:39:54.774129
426 09:39:54.806734 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 09:39:54.807131 2D training succeed
428 09:39:54.812346 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 09:39:54.817971 auto size-- 65535DDR cs0 size: 2048MB
430 09:39:54.818292 DDR cs1 size: 2048MB
431 09:39:54.823547 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 09:39:54.823860 cs0 DataBus test pass
433 09:39:54.829141 cs1 DataBus test pass
434 09:39:54.829461 cs0 AddrBus test pass
435 09:39:54.829681 cs1 AddrBus test pass
436 09:39:54.829890
437 09:39:54.834731 100bdlr_step_size ps== 420
438 09:39:54.835066 result report
439 09:39:54.840342 boot times 0Enable ddr reg access
440 09:39:54.845597 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 09:39:54.859088 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 09:39:55.431179 0.0;M3 CHK:0;cm4_sp_mode 0
443 09:39:55.431620 MVN_1=0x00000000
444 09:39:55.436615 MVN_2=0x00000000
445 09:39:55.442448 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 09:39:55.442800 OPS=0x10
447 09:39:55.443088 ring efuse init
448 09:39:55.443364 chipver efuse init
449 09:39:55.450683 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 09:39:55.451053 [0.018961 Inits done]
451 09:39:55.451335 secure task start!
452 09:39:55.458160 high task start!
453 09:39:55.458539 low task start!
454 09:39:55.458815 run into bl31
455 09:39:55.464829 NOTICE: BL31: v1.3(release):4fc40b1
456 09:39:55.472638 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 09:39:55.473254 NOTICE: BL31: G12A normal boot!
458 09:39:55.498105 NOTICE: BL31: BL33 decompress pass
459 09:39:55.503694 ERROR: Error initializing runtime service opteed_fast
460 09:39:56.736490
461 09:39:56.736914
462 09:39:56.744968 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 09:39:56.745343
464 09:39:56.745615 Model: Libre Computer AML-A311D-CC Alta
465 09:39:56.953341 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 09:39:56.975868 DRAM: 2 GiB (effective 3.8 GiB)
467 09:39:57.119779 Core: 408 devices, 31 uclasses, devicetree: separate
468 09:39:57.125678 WDT: Not starting watchdog@f0d0
469 09:39:57.157908 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 09:39:57.170328 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 09:39:57.175336 ** Bad device specification mmc 0 **
472 09:39:57.185684 Card did not respond to voltage select! : -110
473 09:39:57.192521 ** Bad device specification mmc 0 **
474 09:39:57.193025 Couldn't find partition mmc 0
475 09:39:57.201725 Card did not respond to voltage select! : -110
476 09:39:57.207119 ** Bad device specification mmc 0 **
477 09:39:57.207596 Couldn't find partition mmc 0
478 09:39:57.212178 Error: could not access storage.
479 09:39:58.477746 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 09:39:58.478152 bl2_stage_init 0x01
481 09:39:58.478387 bl2_stage_init 0x81
482 09:39:58.483439 hw id: 0x0000 - pwm id 0x01
483 09:39:58.483753 bl2_stage_init 0xc1
484 09:39:58.484057 bl2_stage_init 0x02
485 09:39:58.484508
486 09:39:58.488883 L0:00000000
487 09:39:58.489161 L1:20000703
488 09:39:58.489389 L2:00008067
489 09:39:58.489611 L3:14000000
490 09:39:58.491919 B2:00402000
491 09:39:58.492223 B1:e0f83180
492 09:39:58.492458
493 09:39:58.492688 TE: 58159
494 09:39:58.492914
495 09:39:58.502986 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 09:39:58.503286
497 09:39:58.503525 Board ID = 1
498 09:39:58.503751 Set A53 clk to 24M
499 09:39:58.503972 Set A73 clk to 24M
500 09:39:58.508601 Set clk81 to 24M
501 09:39:58.508887 A53 clk: 1200 MHz
502 09:39:58.509121 A73 clk: 1200 MHz
503 09:39:58.512135 CLK81: 166.6M
504 09:39:58.512408 smccc: 00012ab4
505 09:39:58.517899 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 09:39:58.523373 board id: 1
507 09:39:58.528358 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 09:39:58.539231 fw parse done
509 09:39:58.544598 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 09:39:58.587610 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 09:39:58.598632 PIEI prepare done
512 09:39:58.599231 fastboot data load
513 09:39:58.599691 fastboot data verify
514 09:39:58.604470 verify result: 266
515 09:39:58.609727 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 09:39:58.610262 LPDDR4 probe
517 09:39:58.610730 ddr clk to 1584MHz
518 09:39:58.617801 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 09:39:58.654237
520 09:39:58.654844 dmc_version 0001
521 09:39:58.661566 Check phy result
522 09:39:58.667576 INFO : End of CA training
523 09:39:58.668130 INFO : End of initialization
524 09:39:58.673145 INFO : Training has run successfully!
525 09:39:58.673725 Check phy result
526 09:39:58.678710 INFO : End of initialization
527 09:39:58.679261 INFO : End of read enable training
528 09:39:58.684371 INFO : End of fine write leveling
529 09:39:58.689991 INFO : End of Write leveling coarse delay
530 09:39:58.690569 INFO : Training has run successfully!
531 09:39:58.691313 Check phy result
532 09:39:58.695652 INFO : End of initialization
533 09:39:58.696271 INFO : End of read dq deskew training
534 09:39:58.701080 INFO : End of MPR read delay center optimization
535 09:39:58.706681 INFO : End of write delay center optimization
536 09:39:58.712327 INFO : End of read delay center optimization
537 09:39:58.712907 INFO : End of max read latency training
538 09:39:58.717956 INFO : Training has run successfully!
539 09:39:58.718520 1D training succeed
540 09:39:58.727110 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 09:39:58.773769 Check phy result
542 09:39:58.774400 INFO : End of initialization
543 09:39:58.796513 INFO : End of 2D read delay Voltage center optimization
544 09:39:58.816792 INFO : End of 2D read delay Voltage center optimization
545 09:39:58.868062 INFO : End of 2D write delay Voltage center optimization
546 09:39:58.918308 INFO : End of 2D write delay Voltage center optimization
547 09:39:58.923696 INFO : Training has run successfully!
548 09:39:58.924308
549 09:39:58.924800 channel==0
550 09:39:58.929319 RxClkDly_Margin_A0==88 ps 9
551 09:39:58.929903 TxDqDly_Margin_A0==98 ps 10
552 09:39:58.932608 RxClkDly_Margin_A1==88 ps 9
553 09:39:58.933165 TxDqDly_Margin_A1==98 ps 10
554 09:39:58.938125 TrainedVREFDQ_A0==74
555 09:39:58.938692 TrainedVREFDQ_A1==74
556 09:39:58.939171 VrefDac_Margin_A0==25
557 09:39:58.943743 DeviceVref_Margin_A0==40
558 09:39:58.944445 VrefDac_Margin_A1==25
559 09:39:58.949416 DeviceVref_Margin_A1==40
560 09:39:58.949993
561 09:39:58.950470
562 09:39:58.950909 channel==1
563 09:39:58.951357 RxClkDly_Margin_A0==98 ps 10
564 09:39:58.952653 TxDqDly_Margin_A0==98 ps 10
565 09:39:58.958329 RxClkDly_Margin_A1==88 ps 9
566 09:39:58.958919 TxDqDly_Margin_A1==88 ps 9
567 09:39:58.959409 TrainedVREFDQ_A0==77
568 09:39:58.963895 TrainedVREFDQ_A1==77
569 09:39:58.964490 VrefDac_Margin_A0==22
570 09:39:58.969489 DeviceVref_Margin_A0==37
571 09:39:58.970037 VrefDac_Margin_A1==24
572 09:39:58.970516 DeviceVref_Margin_A1==37
573 09:39:58.971046
574 09:39:58.975073 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 09:39:58.975663
576 09:39:59.008624 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 09:39:59.009220 2D training succeed
578 09:39:59.014187 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 09:39:59.019757 auto size-- 65535DDR cs0 size: 2048MB
580 09:39:59.020330 DDR cs1 size: 2048MB
581 09:39:59.025358 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 09:39:59.025867 cs0 DataBus test pass
583 09:39:59.026324 cs1 DataBus test pass
584 09:39:59.031001 cs0 AddrBus test pass
585 09:39:59.031575 cs1 AddrBus test pass
586 09:39:59.032148
587 09:39:59.036575 100bdlr_step_size ps== 420
588 09:39:59.037128 result report
589 09:39:59.037579 boot times 0Enable ddr reg access
590 09:39:59.046363 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 09:39:59.060082 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 09:39:59.633747 0.0;M3 CHK:0;cm4_sp_mode 0
593 09:39:59.634378 MVN_1=0x00000000
594 09:39:59.639187 MVN_2=0x00000000
595 09:39:59.644996 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 09:39:59.645542 OPS=0x10
597 09:39:59.646001 ring efuse init
598 09:39:59.646452 chipver efuse init
599 09:39:59.650695 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 09:39:59.656266 [0.018961 Inits done]
601 09:39:59.656783 secure task start!
602 09:39:59.657220 high task start!
603 09:39:59.659761 low task start!
604 09:39:59.660275 run into bl31
605 09:39:59.667410 NOTICE: BL31: v1.3(release):4fc40b1
606 09:39:59.675218 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 09:39:59.675790 NOTICE: BL31: G12A normal boot!
608 09:39:59.700635 NOTICE: BL31: BL33 decompress pass
609 09:39:59.706310 ERROR: Error initializing runtime service opteed_fast
610 09:40:00.939344
611 09:40:00.940057
612 09:40:00.947712 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 09:40:00.948308
614 09:40:00.948783 Model: Libre Computer AML-A311D-CC Alta
615 09:40:01.155790 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 09:40:01.179442 DRAM: 2 GiB (effective 3.8 GiB)
617 09:40:01.322811 Core: 408 devices, 31 uclasses, devicetree: separate
618 09:40:01.328350 WDT: Not starting watchdog@f0d0
619 09:40:01.360666 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 09:40:01.373004 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 09:40:01.378005 ** Bad device specification mmc 0 **
622 09:40:01.388326 Card did not respond to voltage select! : -110
623 09:40:01.395126 ** Bad device specification mmc 0 **
624 09:40:01.395605 Couldn't find partition mmc 0
625 09:40:01.404352 Card did not respond to voltage select! : -110
626 09:40:01.409906 ** Bad device specification mmc 0 **
627 09:40:01.410429 Couldn't find partition mmc 0
628 09:40:01.414886 Error: could not access storage.
629 09:40:01.757591 Net: eth0: ethernet@ff3f0000
630 09:40:01.758188 starting USB...
631 09:40:02.009209 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 09:40:02.009743 Starting the controller
633 09:40:02.016206 USB XHCI 1.10
634 09:40:03.727941 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 09:40:03.728628 bl2_stage_init 0x01
636 09:40:03.729103 bl2_stage_init 0x81
637 09:40:03.733550 hw id: 0x0000 - pwm id 0x01
638 09:40:03.734040 bl2_stage_init 0xc1
639 09:40:03.734494 bl2_stage_init 0x02
640 09:40:03.734940
641 09:40:03.739103 L0:00000000
642 09:40:03.739582 L1:20000703
643 09:40:03.740071 L2:00008067
644 09:40:03.740524 L3:14000000
645 09:40:03.744731 B2:00402000
646 09:40:03.745207 B1:e0f83180
647 09:40:03.745651
648 09:40:03.746087 TE: 58167
649 09:40:03.746525
650 09:40:03.750285 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 09:40:03.750771
652 09:40:03.751226 Board ID = 1
653 09:40:03.755894 Set A53 clk to 24M
654 09:40:03.756400 Set A73 clk to 24M
655 09:40:03.756842 Set clk81 to 24M
656 09:40:03.761545 A53 clk: 1200 MHz
657 09:40:03.762011 A73 clk: 1200 MHz
658 09:40:03.762450 CLK81: 166.6M
659 09:40:03.762885 smccc: 00012abe
660 09:40:03.767077 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 09:40:03.772982 board id: 1
662 09:40:03.777875 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 09:40:03.789157 fw parse done
664 09:40:03.795242 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 09:40:03.837582 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 09:40:03.848601 PIEI prepare done
667 09:40:03.849080 fastboot data load
668 09:40:03.849532 fastboot data verify
669 09:40:03.854289 verify result: 266
670 09:40:03.859846 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 09:40:03.860367 LPDDR4 probe
672 09:40:03.860816 ddr clk to 1584MHz
673 09:40:03.866973 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 09:40:03.905114
675 09:40:03.905627 dmc_version 0001
676 09:40:03.911736 Check phy result
677 09:40:03.917700 INFO : End of CA training
678 09:40:03.918171 INFO : End of initialization
679 09:40:03.923231 INFO : Training has run successfully!
680 09:40:03.923702 Check phy result
681 09:40:03.928821 INFO : End of initialization
682 09:40:03.929294 INFO : End of read enable training
683 09:40:03.932183 INFO : End of fine write leveling
684 09:40:03.937749 INFO : End of Write leveling coarse delay
685 09:40:03.943437 INFO : Training has run successfully!
686 09:40:03.943910 Check phy result
687 09:40:03.944390 INFO : End of initialization
688 09:40:03.948970 INFO : End of read dq deskew training
689 09:40:03.954558 INFO : End of MPR read delay center optimization
690 09:40:03.955026 INFO : End of write delay center optimization
691 09:40:03.960179 INFO : End of read delay center optimization
692 09:40:03.965767 INFO : End of max read latency training
693 09:40:03.966238 INFO : Training has run successfully!
694 09:40:03.971334 1D training succeed
695 09:40:03.976436 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 09:40:04.024906 Check phy result
697 09:40:04.025424 INFO : End of initialization
698 09:40:04.046501 INFO : End of 2D read delay Voltage center optimization
699 09:40:04.065830 INFO : End of 2D read delay Voltage center optimization
700 09:40:04.117622 INFO : End of 2D write delay Voltage center optimization
701 09:40:04.167768 INFO : End of 2D write delay Voltage center optimization
702 09:40:04.173319 INFO : Training has run successfully!
703 09:40:04.173831
704 09:40:04.174294 channel==0
705 09:40:04.178897 RxClkDly_Margin_A0==88 ps 9
706 09:40:04.179399 TxDqDly_Margin_A0==98 ps 10
707 09:40:04.182271 RxClkDly_Margin_A1==88 ps 9
708 09:40:04.182769 TxDqDly_Margin_A1==98 ps 10
709 09:40:04.187874 TrainedVREFDQ_A0==74
710 09:40:04.188410 TrainedVREFDQ_A1==74
711 09:40:04.188885 VrefDac_Margin_A0==25
712 09:40:04.193448 DeviceVref_Margin_A0==40
713 09:40:04.193957 VrefDac_Margin_A1==25
714 09:40:04.199046 DeviceVref_Margin_A1==40
715 09:40:04.199582
716 09:40:04.200086
717 09:40:04.200535 channel==1
718 09:40:04.200970 RxClkDly_Margin_A0==98 ps 10
719 09:40:04.202372 TxDqDly_Margin_A0==98 ps 10
720 09:40:04.207841 RxClkDly_Margin_A1==88 ps 9
721 09:40:04.208414 TxDqDly_Margin_A1==88 ps 9
722 09:40:04.208904 TrainedVREFDQ_A0==77
723 09:40:04.213456 TrainedVREFDQ_A1==77
724 09:40:04.213971 VrefDac_Margin_A0==22
725 09:40:04.219079 DeviceVref_Margin_A0==37
726 09:40:04.219609 VrefDac_Margin_A1==24
727 09:40:04.220122 DeviceVref_Margin_A1==37
728 09:40:04.220594
729 09:40:04.224701 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 09:40:04.225209
731 09:40:04.258268 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
732 09:40:04.258837 2D training succeed
733 09:40:04.263879 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 09:40:04.269453 auto size-- 65535DDR cs0 size: 2048MB
735 09:40:04.269932 DDR cs1 size: 2048MB
736 09:40:04.275049 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 09:40:04.275515 cs0 DataBus test pass
738 09:40:04.275964 cs1 DataBus test pass
739 09:40:04.280649 cs0 AddrBus test pass
740 09:40:04.281151 cs1 AddrBus test pass
741 09:40:04.281620
742 09:40:04.286296 100bdlr_step_size ps== 420
743 09:40:04.286831 result report
744 09:40:04.287284 boot times 0Enable ddr reg access
745 09:40:04.295655 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 09:40:04.309728 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 09:40:04.881954 0.0;M3 CHK:0;cm4_sp_mode 0
748 09:40:04.882612 MVN_1=0x00000000
749 09:40:04.887265 MVN_2=0x00000000
750 09:40:04.893004 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 09:40:04.893549 OPS=0x10
752 09:40:04.893992 ring efuse init
753 09:40:04.894426 chipver efuse init
754 09:40:04.898703 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 09:40:04.904210 [0.018961 Inits done]
756 09:40:04.904714 secure task start!
757 09:40:04.905153 high task start!
758 09:40:04.907845 low task start!
759 09:40:04.908450 run into bl31
760 09:40:04.915389 NOTICE: BL31: v1.3(release):4fc40b1
761 09:40:04.923234 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 09:40:04.923722 NOTICE: BL31: G12A normal boot!
763 09:40:04.948525 NOTICE: BL31: BL33 decompress pass
764 09:40:04.954208 ERROR: Error initializing runtime service opteed_fast
765 09:40:06.187070
766 09:40:06.187677
767 09:40:06.195466 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 09:40:06.195954
769 09:40:06.196593 Model: Libre Computer AML-A311D-CC Alta
770 09:40:06.657937 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 09:40:06.658514 DRAM: 2 GiB (effective 3.8 GiB)
772 09:40:06.658949 Core: 408 devices, 31 uclasses, devicetree: separate
773 09:40:06.659370 WDT: Not starting watchdog@f0d0
774 09:40:06.659775 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 09:40:06.660232 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 09:40:06.660644 ** Bad device specification mmc 0 **
777 09:40:06.661054 Card did not respond to voltage select! : -110
778 09:40:06.661450 ** Bad device specification mmc 0 **
779 09:40:06.661852 Couldn't find partition mmc 0
780 09:40:06.662244 Card did not respond to voltage select! : -110
781 09:40:06.662809 ** Bad device specification mmc 0 **
782 09:40:06.663285 Couldn't find partition mmc 0
783 09:40:06.664213 Error: could not access storage.
784 09:40:07.006223 Net: eth0: ethernet@ff3f0000
785 09:40:07.006815 starting USB...
786 09:40:07.257973 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 09:40:07.258548 Starting the controller
788 09:40:07.263963 USB XHCI 1.10
789 09:40:09.429540 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 09:40:09.430155 bl2_stage_init 0x01
791 09:40:09.430588 bl2_stage_init 0x81
792 09:40:09.434966 hw id: 0x0000 - pwm id 0x01
793 09:40:09.435418 bl2_stage_init 0xc1
794 09:40:09.435837 bl2_stage_init 0x02
795 09:40:09.436297
796 09:40:09.440618 L0:00000000
797 09:40:09.441061 L1:20000703
798 09:40:09.441473 L2:00008067
799 09:40:09.441877 L3:14000000
800 09:40:09.446259 B2:00402000
801 09:40:09.446698 B1:e0f83180
802 09:40:09.447103
803 09:40:09.447508 TE: 58167
804 09:40:09.447909
805 09:40:09.451867 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 09:40:09.452351
807 09:40:09.452768 Board ID = 1
808 09:40:09.457439 Set A53 clk to 24M
809 09:40:09.457917 Set A73 clk to 24M
810 09:40:09.458324 Set clk81 to 24M
811 09:40:09.463021 A53 clk: 1200 MHz
812 09:40:09.463465 A73 clk: 1200 MHz
813 09:40:09.463872 CLK81: 166.6M
814 09:40:09.464311 smccc: 00012abe
815 09:40:09.468686 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 09:40:09.474267 board id: 1
817 09:40:09.480149 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 09:40:09.490675 fw parse done
819 09:40:09.496724 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 09:40:09.539336 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 09:40:09.550235 PIEI prepare done
822 09:40:09.550684 fastboot data load
823 09:40:09.551100 fastboot data verify
824 09:40:09.555842 verify result: 266
825 09:40:09.561430 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 09:40:09.561866 LPDDR4 probe
827 09:40:09.562274 ddr clk to 1584MHz
828 09:40:09.569463 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 09:40:09.606728
830 09:40:09.607199 dmc_version 0001
831 09:40:09.613400 Check phy result
832 09:40:09.619321 INFO : End of CA training
833 09:40:09.619799 INFO : End of initialization
834 09:40:09.624830 INFO : Training has run successfully!
835 09:40:09.625298 Check phy result
836 09:40:09.630465 INFO : End of initialization
837 09:40:09.630957 INFO : End of read enable training
838 09:40:09.633759 INFO : End of fine write leveling
839 09:40:09.639326 INFO : End of Write leveling coarse delay
840 09:40:09.644988 INFO : Training has run successfully!
841 09:40:09.645460 Check phy result
842 09:40:09.645872 INFO : End of initialization
843 09:40:09.650501 INFO : End of read dq deskew training
844 09:40:09.656146 INFO : End of MPR read delay center optimization
845 09:40:09.656612 INFO : End of write delay center optimization
846 09:40:09.661937 INFO : End of read delay center optimization
847 09:40:09.667348 INFO : End of max read latency training
848 09:40:09.667804 INFO : Training has run successfully!
849 09:40:09.672919 1D training succeed
850 09:40:09.678871 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 09:40:09.726515 Check phy result
852 09:40:09.726994 INFO : End of initialization
853 09:40:09.748114 INFO : End of 2D read delay Voltage center optimization
854 09:40:09.768231 INFO : End of 2D read delay Voltage center optimization
855 09:40:09.820079 INFO : End of 2D write delay Voltage center optimization
856 09:40:09.869406 INFO : End of 2D write delay Voltage center optimization
857 09:40:09.874847 INFO : Training has run successfully!
858 09:40:09.875276
859 09:40:09.875683 channel==0
860 09:40:09.880521 RxClkDly_Margin_A0==88 ps 9
861 09:40:09.880952 TxDqDly_Margin_A0==98 ps 10
862 09:40:09.883837 RxClkDly_Margin_A1==88 ps 9
863 09:40:09.884298 TxDqDly_Margin_A1==98 ps 10
864 09:40:09.889434 TrainedVREFDQ_A0==74
865 09:40:09.889924 TrainedVREFDQ_A1==74
866 09:40:09.894925 VrefDac_Margin_A0==25
867 09:40:09.895395 DeviceVref_Margin_A0==40
868 09:40:09.895783 VrefDac_Margin_A1==25
869 09:40:09.900588 DeviceVref_Margin_A1==40
870 09:40:09.901001
871 09:40:09.901385
872 09:40:09.901766 channel==1
873 09:40:09.902143 RxClkDly_Margin_A0==98 ps 10
874 09:40:09.904117 TxDqDly_Margin_A0==98 ps 10
875 09:40:09.909674 RxClkDly_Margin_A1==98 ps 10
876 09:40:09.910084 TxDqDly_Margin_A1==88 ps 9
877 09:40:09.910472 TrainedVREFDQ_A0==77
878 09:40:09.915202 TrainedVREFDQ_A1==77
879 09:40:09.915630 VrefDac_Margin_A0==22
880 09:40:09.920858 DeviceVref_Margin_A0==37
881 09:40:09.921273 VrefDac_Margin_A1==22
882 09:40:09.921657 DeviceVref_Margin_A1==37
883 09:40:09.922035
884 09:40:09.930112 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 09:40:09.930526
886 09:40:09.958145 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 09:40:09.958628 2D training succeed
888 09:40:09.963511 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 09:40:09.969123 auto size-- 65535DDR cs0 size: 2048MB
890 09:40:09.969537 DDR cs1 size: 2048MB
891 09:40:09.974717 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 09:40:09.975129 cs0 DataBus test pass
893 09:40:09.980363 cs1 DataBus test pass
894 09:40:09.980772 cs0 AddrBus test pass
895 09:40:09.985943 cs1 AddrBus test pass
896 09:40:09.986354
897 09:40:09.986740 100bdlr_step_size ps== 432
898 09:40:09.987130 result report
899 09:40:09.991538 boot times 0Enable ddr reg access
900 09:40:09.997787 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 09:40:10.011323 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 09:40:10.583170 0.0;M3 CHK:0;cm4_sp_mode 0
903 09:40:10.583593 MVN_1=0x00000000
904 09:40:10.588859 MVN_2=0x00000000
905 09:40:10.594604 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 09:40:10.595105 OPS=0x10
907 09:40:10.595534 ring efuse init
908 09:40:10.595950 chipver efuse init
909 09:40:10.600233 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 09:40:10.605801 [0.018960 Inits done]
911 09:40:10.606294 secure task start!
912 09:40:10.606714 high task start!
913 09:40:10.610503 low task start!
914 09:40:10.610988 run into bl31
915 09:40:10.617044 NOTICE: BL31: v1.3(release):4fc40b1
916 09:40:10.624890 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 09:40:10.625437 NOTICE: BL31: G12A normal boot!
918 09:40:10.650176 NOTICE: BL31: BL33 decompress pass
919 09:40:10.655866 ERROR: Error initializing runtime service opteed_fast
920 09:40:11.888689
921 09:40:11.889322
922 09:40:11.897108 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 09:40:11.897606
924 09:40:11.898039 Model: Libre Computer AML-A311D-CC Alta
925 09:40:12.105576 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 09:40:12.128890 DRAM: 2 GiB (effective 3.8 GiB)
927 09:40:12.271796 Core: 408 devices, 31 uclasses, devicetree: separate
928 09:40:12.277668 WDT: Not starting watchdog@f0d0
929 09:40:12.309973 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 09:40:12.322359 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 09:40:12.326403 ** Bad device specification mmc 0 **
932 09:40:12.337678 Card did not respond to voltage select! : -110
933 09:40:12.345339 ** Bad device specification mmc 0 **
934 09:40:12.345606 Couldn't find partition mmc 0
935 09:40:12.353691 Card did not respond to voltage select! : -110
936 09:40:12.359177 ** Bad device specification mmc 0 **
937 09:40:12.359438 Couldn't find partition mmc 0
938 09:40:12.364262 Error: could not access storage.
939 09:40:12.706771 Net: eth0: ethernet@ff3f0000
940 09:40:12.707147 starting USB...
941 09:40:12.958555 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 09:40:12.958911 Starting the controller
943 09:40:12.965622 USB XHCI 1.10
944 09:40:14.829476 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 09:40:14.829867 bl2_stage_init 0x01
946 09:40:14.830078 bl2_stage_init 0x81
947 09:40:14.835113 hw id: 0x0000 - pwm id 0x01
948 09:40:14.835692 bl2_stage_init 0xc1
949 09:40:14.836271 bl2_stage_init 0x02
950 09:40:14.836754
951 09:40:14.840666 L0:00000000
952 09:40:14.841367 L1:20000703
953 09:40:14.841859 L2:00008067
954 09:40:14.842315 L3:14000000
955 09:40:14.846272 B2:00402000
956 09:40:14.846749 B1:e0f83180
957 09:40:14.847197
958 09:40:14.847642 TE: 58159
959 09:40:14.848127
960 09:40:14.851859 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 09:40:14.852368
962 09:40:14.852822 Board ID = 1
963 09:40:14.857479 Set A53 clk to 24M
964 09:40:14.857958 Set A73 clk to 24M
965 09:40:14.858406 Set clk81 to 24M
966 09:40:14.863056 A53 clk: 1200 MHz
967 09:40:14.863534 A73 clk: 1200 MHz
968 09:40:14.863974 CLK81: 166.6M
969 09:40:14.864619 smccc: 00012ab5
970 09:40:14.868643 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 09:40:14.874228 board id: 1
972 09:40:14.880120 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 09:40:14.890844 fw parse done
974 09:40:14.896764 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 09:40:14.939403 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 09:40:14.950271 PIEI prepare done
977 09:40:14.950703 fastboot data load
978 09:40:14.951101 fastboot data verify
979 09:40:14.955947 verify result: 266
980 09:40:14.961654 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 09:40:14.962079 LPDDR4 probe
982 09:40:14.962465 ddr clk to 1584MHz
983 09:40:14.969678 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 09:40:15.006921
985 09:40:15.007345 dmc_version 0001
986 09:40:15.013616 Check phy result
987 09:40:15.019368 INFO : End of CA training
988 09:40:15.019786 INFO : End of initialization
989 09:40:15.025026 INFO : Training has run successfully!
990 09:40:15.025442 Check phy result
991 09:40:15.030556 INFO : End of initialization
992 09:40:15.030976 INFO : End of read enable training
993 09:40:15.036181 INFO : End of fine write leveling
994 09:40:15.041789 INFO : End of Write leveling coarse delay
995 09:40:15.042242 INFO : Training has run successfully!
996 09:40:15.042652 Check phy result
997 09:40:15.047444 INFO : End of initialization
998 09:40:15.047891 INFO : End of read dq deskew training
999 09:40:15.053038 INFO : End of MPR read delay center optimization
1000 09:40:15.058720 INFO : End of write delay center optimization
1001 09:40:15.064142 INFO : End of read delay center optimization
1002 09:40:15.064582 INFO : End of max read latency training
1003 09:40:15.069733 INFO : Training has run successfully!
1004 09:40:15.070172 1D training succeed
1005 09:40:15.079031 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 09:40:15.126571 Check phy result
1007 09:40:15.127024 INFO : End of initialization
1008 09:40:15.148374 INFO : End of 2D read delay Voltage center optimization
1009 09:40:15.168683 INFO : End of 2D read delay Voltage center optimization
1010 09:40:15.220735 INFO : End of 2D write delay Voltage center optimization
1011 09:40:15.270169 INFO : End of 2D write delay Voltage center optimization
1012 09:40:15.275699 INFO : Training has run successfully!
1013 09:40:15.276185
1014 09:40:15.276602 channel==0
1015 09:40:15.281269 RxClkDly_Margin_A0==88 ps 9
1016 09:40:15.281709 TxDqDly_Margin_A0==98 ps 10
1017 09:40:15.284640 RxClkDly_Margin_A1==88 ps 9
1018 09:40:15.285078 TxDqDly_Margin_A1==98 ps 10
1019 09:40:15.290196 TrainedVREFDQ_A0==74
1020 09:40:15.290642 TrainedVREFDQ_A1==74
1021 09:40:15.291059 VrefDac_Margin_A0==25
1022 09:40:15.295794 DeviceVref_Margin_A0==40
1023 09:40:15.296257 VrefDac_Margin_A1==25
1024 09:40:15.301436 DeviceVref_Margin_A1==40
1025 09:40:15.301875
1026 09:40:15.302285
1027 09:40:15.302686 channel==1
1028 09:40:15.303081 RxClkDly_Margin_A0==98 ps 10
1029 09:40:15.304877 TxDqDly_Margin_A0==98 ps 10
1030 09:40:15.310349 RxClkDly_Margin_A1==88 ps 9
1031 09:40:15.310784 TxDqDly_Margin_A1==88 ps 9
1032 09:40:15.311191 TrainedVREFDQ_A0==77
1033 09:40:15.316014 TrainedVREFDQ_A1==77
1034 09:40:15.316455 VrefDac_Margin_A0==22
1035 09:40:15.321590 DeviceVref_Margin_A0==37
1036 09:40:15.322033 VrefDac_Margin_A1==24
1037 09:40:15.322444 DeviceVref_Margin_A1==37
1038 09:40:15.322841
1039 09:40:15.327179 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 09:40:15.327619
1041 09:40:15.360807 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
1042 09:40:15.361278 2D training succeed
1043 09:40:15.366433 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 09:40:15.371886 auto size-- 65535DDR cs0 size: 2048MB
1045 09:40:15.372349 DDR cs1 size: 2048MB
1046 09:40:15.377480 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 09:40:15.377921 cs0 DataBus test pass
1048 09:40:15.378327 cs1 DataBus test pass
1049 09:40:15.383119 cs0 AddrBus test pass
1050 09:40:15.383552 cs1 AddrBus test pass
1051 09:40:15.383955
1052 09:40:15.388700 100bdlr_step_size ps== 420
1053 09:40:15.389146 result report
1054 09:40:15.389549 boot times 0Enable ddr reg access
1055 09:40:15.398499 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 09:40:15.412148 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 09:40:15.985616 0.0;M3 CHK:0;cm4_sp_mode 0
1058 09:40:15.985950 MVN_1=0x00000000
1059 09:40:15.991104 MVN_2=0x00000000
1060 09:40:15.996913 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 09:40:15.997368 OPS=0x10
1062 09:40:15.997781 ring efuse init
1063 09:40:15.998182 chipver efuse init
1064 09:40:16.002517 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 09:40:16.008155 [0.018961 Inits done]
1066 09:40:16.008597 secure task start!
1067 09:40:16.009004 high task start!
1068 09:40:16.012693 low task start!
1069 09:40:16.013131 run into bl31
1070 09:40:16.019346 NOTICE: BL31: v1.3(release):4fc40b1
1071 09:40:16.027168 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 09:40:16.027620 NOTICE: BL31: G12A normal boot!
1073 09:40:16.052565 NOTICE: BL31: BL33 decompress pass
1074 09:40:16.058270 ERROR: Error initializing runtime service opteed_fast
1075 09:40:17.291145
1076 09:40:17.291737
1077 09:40:17.298555 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 09:40:17.299020
1079 09:40:17.299441 Model: Libre Computer AML-A311D-CC Alta
1080 09:40:17.508062 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 09:40:17.531375 DRAM: 2 GiB (effective 3.8 GiB)
1082 09:40:17.674448 Core: 408 devices, 31 uclasses, devicetree: separate
1083 09:40:17.679969 WDT: Not starting watchdog@f0d0
1084 09:40:17.712468 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 09:40:17.724998 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 09:40:17.729644 ** Bad device specification mmc 0 **
1087 09:40:17.740480 Card did not respond to voltage select! : -110
1088 09:40:17.747365 ** Bad device specification mmc 0 **
1089 09:40:17.747895 Couldn't find partition mmc 0
1090 09:40:17.756406 Card did not respond to voltage select! : -110
1091 09:40:17.761791 ** Bad device specification mmc 0 **
1092 09:40:17.762306 Couldn't find partition mmc 0
1093 09:40:17.766141 Error: could not access storage.
1094 09:40:18.108767 Net: eth0: ethernet@ff3f0000
1095 09:40:18.109381 starting USB...
1096 09:40:18.361197 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 09:40:18.361829 Starting the controller
1098 09:40:18.367756 USB XHCI 1.10
1099 09:40:19.925354 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 09:40:19.933883 scanning usb for storage devices... 0 Storage Device(s) found
1102 09:40:19.985429 Hit any key to stop autoboot: 1
1103 09:40:19.986211 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 09:40:19.986951 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 09:40:19.987416 Setting prompt string to ['=>']
1106 09:40:19.987885 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 09:40:20.000217 0
1108 09:40:20.001126 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 09:40:20.001614 Sending with 10 millisecond of delay
1111 09:40:21.136352 => setenv autoload no
1112 09:40:21.147290 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 09:40:21.149950 setenv autoload no
1114 09:40:21.150453 Sending with 10 millisecond of delay
1116 09:40:22.947192 => setenv initrd_high 0xffffffff
1117 09:40:22.957805 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 09:40:22.958513 setenv initrd_high 0xffffffff
1119 09:40:22.959099 Sending with 10 millisecond of delay
1121 09:40:24.576493 => setenv fdt_high 0xffffffff
1122 09:40:24.587283 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 09:40:24.588152 setenv fdt_high 0xffffffff
1124 09:40:24.588864 Sending with 10 millisecond of delay
1126 09:40:24.880639 => dhcp
1127 09:40:24.891357 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 09:40:24.892226 dhcp
1129 09:40:24.892666 Speed: 1000, full duplex
1130 09:40:24.893079 BOOTP broadcast 1
1131 09:40:25.139858 BOOTP broadcast 2
1132 09:40:25.343510 DHCP client bound to address 192.168.6.33 (452 ms)
1133 09:40:25.344409 Sending with 10 millisecond of delay
1135 09:40:27.020937 => setenv serverip 192.168.6.2
1136 09:40:27.031722 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1137 09:40:27.032601 setenv serverip 192.168.6.2
1138 09:40:27.033308 Sending with 10 millisecond of delay
1140 09:40:30.757414 => tftpboot 0x01080000 684617/tftp-deploy-jn0_54y8/kernel/uImage
1141 09:40:30.768195 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1142 09:40:30.768708 tftpboot 0x01080000 684617/tftp-deploy-jn0_54y8/kernel/uImage
1143 09:40:30.768943 Speed: 1000, full duplex
1144 09:40:30.769146 Using ethernet@ff3f0000 device
1145 09:40:30.771101 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 09:40:30.776764 Filename '684617/tftp-deploy-jn0_54y8/kernel/uImage'.
1147 09:40:30.780624 Load address: 0x1080000
1148 09:40:33.649852 Loading: *################################################## 43.2 MiB
1149 09:40:33.650486 15 MiB/s
1150 09:40:33.650917 done
1151 09:40:33.654141 Bytes transferred = 45308480 (2b35a40 hex)
1152 09:40:33.654864 Sending with 10 millisecond of delay
1154 09:40:38.341376 => tftpboot 0x08000000 684617/tftp-deploy-jn0_54y8/ramdisk/ramdisk.cpio.gz.uboot
1155 09:40:38.352177 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1156 09:40:38.353055 tftpboot 0x08000000 684617/tftp-deploy-jn0_54y8/ramdisk/ramdisk.cpio.gz.uboot
1157 09:40:38.353479 Speed: 1000, full duplex
1158 09:40:38.353875 Using ethernet@ff3f0000 device
1159 09:40:38.354825 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 09:40:38.366620 Filename '684617/tftp-deploy-jn0_54y8/ramdisk/ramdisk.cpio.gz.uboot'.
1161 09:40:38.366949 Load address: 0x8000000
1162 09:40:45.251272 Loading: *#####################T ############################ UDP wrong checksum 00000005 0000c385
1163 09:40:47.460163 UDP wrong checksum 000000ff 00003069
1164 09:40:47.470191 UDP wrong checksum 000000ff 0000b35b
1165 09:40:50.253222 T UDP wrong checksum 00000005 0000c385
1166 09:41:00.255047 T T UDP wrong checksum 00000005 0000c385
1167 09:41:20.258933 T T T T UDP wrong checksum 00000005 0000c385
1168 09:41:30.876976 T T UDP wrong checksum 000000ff 0000a9ef
1169 09:41:30.895720 UDP wrong checksum 000000ff 00003de2
1170 09:41:35.262976
1171 09:41:35.263592 Retry count exceeded; starting again
1173 09:41:35.265032 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1176 09:41:35.266819 end: 2.4 uboot-commands (duration 00:01:53) [common]
1178 09:41:35.268206 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1180 09:41:35.269245 end: 2 uboot-action (duration 00:01:53) [common]
1182 09:41:35.270770 Cleaning after the job
1183 09:41:35.271328 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/ramdisk
1184 09:41:35.272626 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/kernel
1185 09:41:35.307247 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/dtb
1186 09:41:35.308620 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/nfsrootfs
1187 09:41:35.507902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/684617/tftp-deploy-jn0_54y8/modules
1188 09:41:35.531254 start: 4.1 power-off (timeout 00:00:30) [common]
1189 09:41:35.531912 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1190 09:41:35.562984 >> OK - accepted request
1191 09:41:35.565046 Returned 0 in 0 seconds
1192 09:41:35.665793 end: 4.1 power-off (duration 00:00:00) [common]
1194 09:41:35.666751 start: 4.2 read-feedback (timeout 00:10:00) [common]
1195 09:41:35.667403 Listened to connection for namespace 'common' for up to 1s
1196 09:41:36.667355 Finalising connection for namespace 'common'
1197 09:41:36.667851 Disconnecting from shell: Finalise
1198 09:41:36.668194 =>
1199 09:41:36.768870 end: 4.2 read-feedback (duration 00:00:01) [common]
1200 09:41:36.769344 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/684617
1201 09:41:39.414734 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/684617
1202 09:41:39.415311 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.