Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:44:06.442025 lava-dispatcher, installed at version: 2024.01
2 21:44:06.442851 start: 0 validate
3 21:44:06.443347 Start time: 2024-10-02 21:44:06.443316+00:00 (UTC)
4 21:44:06.443919 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:44:06.444496 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:44:06.482105 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:44:06.482677 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fkernel%2FImage exists
8 21:44:06.510722 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:44:06.511364 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 21:44:12.583013 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:44:12.583514 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fmodules.tar.xz exists
12 21:44:14.632313 validate duration: 8.19
14 21:44:14.633226 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:44:14.633537 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:44:14.633823 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:44:14.634416 Not decompressing ramdisk as can be used compressed.
18 21:44:14.634830 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:44:14.635084 saving as /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/ramdisk/rootfs.cpio.gz
20 21:44:14.635344 total size: 8181887 (7 MB)
21 21:44:14.674785 progress 0 % (0 MB)
22 21:44:14.686349 progress 5 % (0 MB)
23 21:44:14.698520 progress 10 % (0 MB)
24 21:44:14.709306 progress 15 % (1 MB)
25 21:44:14.714718 progress 20 % (1 MB)
26 21:44:14.720548 progress 25 % (1 MB)
27 21:44:14.725958 progress 30 % (2 MB)
28 21:44:14.731764 progress 35 % (2 MB)
29 21:44:14.737209 progress 40 % (3 MB)
30 21:44:14.743016 progress 45 % (3 MB)
31 21:44:14.748380 progress 50 % (3 MB)
32 21:44:14.754197 progress 55 % (4 MB)
33 21:44:14.759506 progress 60 % (4 MB)
34 21:44:14.765183 progress 65 % (5 MB)
35 21:44:14.770531 progress 70 % (5 MB)
36 21:44:14.776303 progress 75 % (5 MB)
37 21:44:14.781990 progress 80 % (6 MB)
38 21:44:14.788445 progress 85 % (6 MB)
39 21:44:14.793870 progress 90 % (7 MB)
40 21:44:14.799710 progress 95 % (7 MB)
41 21:44:14.804719 progress 100 % (7 MB)
42 21:44:14.805419 7 MB downloaded in 0.17 s (45.88 MB/s)
43 21:44:14.805964 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:44:14.806831 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:44:14.807118 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:44:14.807384 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:44:14.807865 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/kernel/Image
49 21:44:14.808169 saving as /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/kernel/Image
50 21:44:14.808380 total size: 39424512 (37 MB)
51 21:44:14.808591 No compression specified
52 21:44:14.889778 progress 0 % (0 MB)
53 21:44:14.914993 progress 5 % (1 MB)
54 21:44:14.940132 progress 10 % (3 MB)
55 21:44:14.965549 progress 15 % (5 MB)
56 21:44:14.990349 progress 20 % (7 MB)
57 21:44:15.014908 progress 25 % (9 MB)
58 21:44:15.040261 progress 30 % (11 MB)
59 21:44:15.065933 progress 35 % (13 MB)
60 21:44:15.090674 progress 40 % (15 MB)
61 21:44:15.115679 progress 45 % (16 MB)
62 21:44:15.140773 progress 50 % (18 MB)
63 21:44:15.165118 progress 55 % (20 MB)
64 21:44:15.190063 progress 60 % (22 MB)
65 21:44:15.215395 progress 65 % (24 MB)
66 21:44:15.240323 progress 70 % (26 MB)
67 21:44:15.265814 progress 75 % (28 MB)
68 21:44:15.292068 progress 80 % (30 MB)
69 21:44:15.317057 progress 85 % (31 MB)
70 21:44:15.342799 progress 90 % (33 MB)
71 21:44:15.368330 progress 95 % (35 MB)
72 21:44:15.394834 progress 100 % (37 MB)
73 21:44:15.395495 37 MB downloaded in 0.59 s (64.04 MB/s)
74 21:44:15.396055 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:44:15.396979 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:44:15.397323 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:44:15.397643 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:44:15.398209 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 21:44:15.398541 saving as /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 21:44:15.398752 total size: 53209 (0 MB)
82 21:44:15.398968 No compression specified
83 21:44:15.434168 progress 61 % (0 MB)
84 21:44:15.435011 progress 100 % (0 MB)
85 21:44:15.435558 0 MB downloaded in 0.04 s (1.38 MB/s)
86 21:44:15.436058 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:44:15.436908 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:44:15.437168 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:44:15.437426 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:44:15.437917 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/modules.tar.xz
92 21:44:15.438210 saving as /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/modules/modules.tar
93 21:44:15.438434 total size: 11755936 (11 MB)
94 21:44:15.438661 Using unxz to decompress xz
95 21:44:15.485425 progress 0 % (0 MB)
96 21:44:15.562880 progress 5 % (0 MB)
97 21:44:15.645586 progress 10 % (1 MB)
98 21:44:15.740035 progress 15 % (1 MB)
99 21:44:15.847654 progress 20 % (2 MB)
100 21:44:15.932955 progress 25 % (2 MB)
101 21:44:16.015576 progress 30 % (3 MB)
102 21:44:16.097611 progress 35 % (3 MB)
103 21:44:16.181603 progress 40 % (4 MB)
104 21:44:16.261255 progress 45 % (5 MB)
105 21:44:16.342399 progress 50 % (5 MB)
106 21:44:16.421975 progress 55 % (6 MB)
107 21:44:16.509479 progress 60 % (6 MB)
108 21:44:16.598477 progress 65 % (7 MB)
109 21:44:16.686233 progress 70 % (7 MB)
110 21:44:16.782981 progress 75 % (8 MB)
111 21:44:16.880832 progress 80 % (9 MB)
112 21:44:16.959627 progress 85 % (9 MB)
113 21:44:17.037852 progress 90 % (10 MB)
114 21:44:17.118668 progress 95 % (10 MB)
115 21:44:17.197162 progress 100 % (11 MB)
116 21:44:17.211999 11 MB downloaded in 1.77 s (6.32 MB/s)
117 21:44:17.213090 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:44:17.214836 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:44:17.215411 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:44:17.215975 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:44:17.216549 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:44:17.217091 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:44:17.218137 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx
125 21:44:17.219077 makedir: /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin
126 21:44:17.219773 makedir: /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/tests
127 21:44:17.220495 makedir: /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/results
128 21:44:17.221162 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-add-keys
129 21:44:17.222203 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-add-sources
130 21:44:17.223212 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-background-process-start
131 21:44:17.224271 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-background-process-stop
132 21:44:17.225346 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-common-functions
133 21:44:17.226358 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-echo-ipv4
134 21:44:17.227353 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-install-packages
135 21:44:17.228366 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-installed-packages
136 21:44:17.229355 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-os-build
137 21:44:17.230338 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-probe-channel
138 21:44:17.231304 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-probe-ip
139 21:44:17.232312 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-target-ip
140 21:44:17.233301 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-target-mac
141 21:44:17.234390 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-target-storage
142 21:44:17.235439 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-test-case
143 21:44:17.236497 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-test-event
144 21:44:17.237502 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-test-feedback
145 21:44:17.238487 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-test-raise
146 21:44:17.239473 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-test-reference
147 21:44:17.240507 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-test-runner
148 21:44:17.241512 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-test-set
149 21:44:17.242489 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-test-shell
150 21:44:17.243499 Updating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-install-packages (oe)
151 21:44:17.244873 Updating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/bin/lava-installed-packages (oe)
152 21:44:17.245954 Creating /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/environment
153 21:44:17.246793 LAVA metadata
154 21:44:17.247335 - LAVA_JOB_ID=795087
155 21:44:17.247814 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:44:17.248617 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:44:17.250615 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:44:17.251270 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:44:17.251725 skipped lava-vland-overlay
160 21:44:17.252350 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:44:17.252913 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:44:17.253382 skipped lava-multinode-overlay
163 21:44:17.253916 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:44:17.254462 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:44:17.254987 Loading test definitions
166 21:44:17.255582 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:44:17.256106 Using /lava-795087 at stage 0
168 21:44:17.258584 uuid=795087_1.5.2.4.1 testdef=None
169 21:44:17.259243 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:44:17.259818 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:44:17.263787 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:44:17.265538 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:44:17.270216 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:44:17.271840 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:44:17.274210 runner path: /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/0/tests/0_dmesg test_uuid 795087_1.5.2.4.1
178 21:44:17.274809 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:44:17.275584 Creating lava-test-runner.conf files
181 21:44:17.275788 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795087/lava-overlay-zahrjgwx/lava-795087/0 for stage 0
182 21:44:17.276165 - 0_dmesg
183 21:44:17.276535 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:44:17.276817 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:44:17.301224 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:44:17.301687 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:44:17.301968 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:44:17.302249 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:44:17.302529 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:44:18.291063 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:44:18.291789 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:44:18.292318 extracting modules file /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795087/extract-overlay-ramdisk-ebwkmrl1/ramdisk
193 21:44:19.722541 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:44:19.723026 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:44:19.723300 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795087/compress-overlay-bldz16o7/overlay-1.5.2.5.tar.gz to ramdisk
196 21:44:19.723515 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795087/compress-overlay-bldz16o7/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795087/extract-overlay-ramdisk-ebwkmrl1/ramdisk
197 21:44:19.754279 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:44:19.754734 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:44:19.755004 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:44:19.755233 Converting downloaded kernel to a uImage
201 21:44:19.755542 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/kernel/Image /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/kernel/uImage
202 21:44:20.162375 output: Image Name:
203 21:44:20.162799 output: Created: Wed Oct 2 21:44:19 2024
204 21:44:20.163005 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:44:20.163204 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
206 21:44:20.163404 output: Load Address: 01080000
207 21:44:20.163600 output: Entry Point: 01080000
208 21:44:20.163795 output:
209 21:44:20.164155 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 21:44:20.164424 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 21:44:20.164689 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 21:44:20.164938 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:44:20.165189 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 21:44:20.165444 Building ramdisk /var/lib/lava/dispatcher/tmp/795087/extract-overlay-ramdisk-ebwkmrl1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795087/extract-overlay-ramdisk-ebwkmrl1/ramdisk
215 21:44:23.082213 >> 188209 blocks
216 21:44:31.435519 Adding RAMdisk u-boot header.
217 21:44:31.436222 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795087/extract-overlay-ramdisk-ebwkmrl1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795087/extract-overlay-ramdisk-ebwkmrl1/ramdisk.cpio.gz.uboot
218 21:44:31.712972 output: Image Name:
219 21:44:31.713374 output: Created: Wed Oct 2 21:44:31 2024
220 21:44:31.713581 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:44:31.713782 output: Data Size: 26751169 Bytes = 26124.19 KiB = 25.51 MiB
222 21:44:31.713981 output: Load Address: 00000000
223 21:44:31.714178 output: Entry Point: 00000000
224 21:44:31.714373 output:
225 21:44:31.714869 rename /var/lib/lava/dispatcher/tmp/795087/extract-overlay-ramdisk-ebwkmrl1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/ramdisk/ramdisk.cpio.gz.uboot
226 21:44:31.715259 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 21:44:31.715535 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 21:44:31.715799 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:44:31.716319 No LXC device requested
230 21:44:31.716913 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:44:31.717495 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:44:31.718029 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:44:31.718474 Checking files for TFTP limit of 4294967296 bytes.
234 21:44:31.721402 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:44:31.722016 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:44:31.722581 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:44:31.723118 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:44:31.723659 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:44:31.724268 Using kernel file from prepare-kernel: 795087/tftp-deploy-qp884h8o/kernel/uImage
240 21:44:31.724950 substitutions:
241 21:44:31.725398 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:44:31.725837 - {DTB_ADDR}: 0x01070000
243 21:44:31.726269 - {DTB}: 795087/tftp-deploy-qp884h8o/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 21:44:31.726705 - {INITRD}: 795087/tftp-deploy-qp884h8o/ramdisk/ramdisk.cpio.gz.uboot
245 21:44:31.727138 - {KERNEL_ADDR}: 0x01080000
246 21:44:31.727568 - {KERNEL}: 795087/tftp-deploy-qp884h8o/kernel/uImage
247 21:44:31.728027 - {LAVA_MAC}: None
248 21:44:31.728503 - {PRESEED_CONFIG}: None
249 21:44:31.728936 - {PRESEED_LOCAL}: None
250 21:44:31.729363 - {RAMDISK_ADDR}: 0x08000000
251 21:44:31.729788 - {RAMDISK}: 795087/tftp-deploy-qp884h8o/ramdisk/ramdisk.cpio.gz.uboot
252 21:44:31.730217 - {ROOT_PART}: None
253 21:44:31.730643 - {ROOT}: None
254 21:44:31.731070 - {SERVER_IP}: 192.168.6.2
255 21:44:31.731502 - {TEE_ADDR}: 0x83000000
256 21:44:31.731927 - {TEE}: None
257 21:44:31.732378 Parsed boot commands:
258 21:44:31.732792 - setenv autoload no
259 21:44:31.733215 - setenv initrd_high 0xffffffff
260 21:44:31.733639 - setenv fdt_high 0xffffffff
261 21:44:31.734063 - dhcp
262 21:44:31.734486 - setenv serverip 192.168.6.2
263 21:44:31.734907 - tftpboot 0x01080000 795087/tftp-deploy-qp884h8o/kernel/uImage
264 21:44:31.735332 - tftpboot 0x08000000 795087/tftp-deploy-qp884h8o/ramdisk/ramdisk.cpio.gz.uboot
265 21:44:31.735757 - tftpboot 0x01070000 795087/tftp-deploy-qp884h8o/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 21:44:31.736209 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:44:31.736641 - bootm 0x01080000 0x08000000 0x01070000
268 21:44:31.737174 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:44:31.738781 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:44:31.739255 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 21:44:31.753860 Setting prompt string to ['lava-test: # ']
273 21:44:31.755452 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:44:31.756121 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:44:31.756714 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:44:31.757417 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:44:31.758648 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 21:44:31.793816 >> OK - accepted request
279 21:44:31.796197 Returned 0 in 0 seconds
280 21:44:31.897453 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:44:31.899263 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:44:31.899879 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:44:31.900486 Setting prompt string to ['Hit any key to stop autoboot']
285 21:44:31.900983 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:44:31.902751 Trying 192.168.56.21...
287 21:44:31.903309 Connected to conserv1.
288 21:44:31.903767 Escape character is '^]'.
289 21:44:31.904268
290 21:44:31.904730 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 21:44:31.905192
292 21:44:40.572473 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 21:44:40.572866 bl2_stage_init 0x01
294 21:44:40.573085 bl2_stage_init 0x81
295 21:44:40.578152 hw id: 0x0000 - pwm id 0x01
296 21:44:40.578399 bl2_stage_init 0xc1
297 21:44:40.583158 bl2_stage_init 0x02
298 21:44:40.583384
299 21:44:40.583593 L0:00000000
300 21:44:40.583798 L1:00000703
301 21:44:40.584025 L2:00008067
302 21:44:40.584225 L3:15000000
303 21:44:40.588851 S1:00000000
304 21:44:40.589084 B2:20282000
305 21:44:40.589282 B1:a0f83180
306 21:44:40.589478
307 21:44:40.589673 TE: 68597
308 21:44:40.589868
309 21:44:40.594312 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 21:44:40.594540
311 21:44:40.599917 Board ID = 1
312 21:44:40.600155 Set cpu clk to 24M
313 21:44:40.600353 Set clk81 to 24M
314 21:44:40.605653 Use GP1_pll as DSU clk.
315 21:44:40.606145 DSU clk: 1200 Mhz
316 21:44:40.606577 CPU clk: 1200 MHz
317 21:44:40.611167 Set clk81 to 166.6M
318 21:44:40.616915 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 21:44:40.617428 board id: 1
320 21:44:40.624020 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:44:40.634924 fw parse done
322 21:44:40.640877 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:44:40.683977 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:44:40.695104 PIEI prepare done
325 21:44:40.695625 fastboot data load
326 21:44:40.696116 fastboot data verify
327 21:44:40.700668 verify result: 266
328 21:44:40.706255 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 21:44:40.706761 LPDDR4 probe
330 21:44:40.707205 ddr clk to 1584MHz
331 21:44:40.714258 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:44:40.752101
333 21:44:40.752656 dmc_version 0001
334 21:44:40.759060 Check phy result
335 21:44:40.765057 INFO : End of CA training
336 21:44:40.765543 INFO : End of initialization
337 21:44:40.770585 INFO : Training has run successfully!
338 21:44:40.771046 Check phy result
339 21:44:40.776223 INFO : End of initialization
340 21:44:40.776703 INFO : End of read enable training
341 21:44:40.779588 INFO : End of fine write leveling
342 21:44:40.784970 INFO : End of Write leveling coarse delay
343 21:44:40.790661 INFO : Training has run successfully!
344 21:44:40.791121 Check phy result
345 21:44:40.791553 INFO : End of initialization
346 21:44:40.796209 INFO : End of read dq deskew training
347 21:44:40.799631 INFO : End of MPR read delay center optimization
348 21:44:40.805163 INFO : End of write delay center optimization
349 21:44:40.810801 INFO : End of read delay center optimization
350 21:44:40.811264 INFO : End of max read latency training
351 21:44:40.816446 INFO : Training has run successfully!
352 21:44:40.816934 1D training succeed
353 21:44:40.824627 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:44:40.872919 Check phy result
355 21:44:40.873454 INFO : End of initialization
356 21:44:40.900344 INFO : End of 2D read delay Voltage center optimization
357 21:44:40.924517 INFO : End of 2D read delay Voltage center optimization
358 21:44:40.981205 INFO : End of 2D write delay Voltage center optimization
359 21:44:41.035272 INFO : End of 2D write delay Voltage center optimization
360 21:44:41.040726 INFO : Training has run successfully!
361 21:44:41.041251
362 21:44:41.041694 channel==0
363 21:44:41.046377 RxClkDly_Margin_A0==69 ps 7
364 21:44:41.046837 TxDqDly_Margin_A0==98 ps 10
365 21:44:41.052123 RxClkDly_Margin_A1==88 ps 9
366 21:44:41.052635 TxDqDly_Margin_A1==98 ps 10
367 21:44:41.053082 TrainedVREFDQ_A0==74
368 21:44:41.057539 TrainedVREFDQ_A1==74
369 21:44:41.058001 VrefDac_Margin_A0==24
370 21:44:41.058434 DeviceVref_Margin_A0==40
371 21:44:41.063202 VrefDac_Margin_A1==23
372 21:44:41.063733 DeviceVref_Margin_A1==40
373 21:44:41.064239
374 21:44:41.064683
375 21:44:41.068787 channel==1
376 21:44:41.069259 RxClkDly_Margin_A0==78 ps 8
377 21:44:41.069695 TxDqDly_Margin_A0==88 ps 9
378 21:44:41.074383 RxClkDly_Margin_A1==88 ps 9
379 21:44:41.074852 TxDqDly_Margin_A1==88 ps 9
380 21:44:41.080087 TrainedVREFDQ_A0==75
381 21:44:41.080556 TrainedVREFDQ_A1==77
382 21:44:41.080995 VrefDac_Margin_A0==20
383 21:44:41.085570 DeviceVref_Margin_A0==39
384 21:44:41.086035 VrefDac_Margin_A1==22
385 21:44:41.091127 DeviceVref_Margin_A1==37
386 21:44:41.091585
387 21:44:41.092056 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:44:41.092492
389 21:44:41.124691 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 21:44:41.125292 2D training succeed
391 21:44:41.130347 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:44:41.135969 auto size-- 65535DDR cs0 size: 2048MB
393 21:44:41.136495 DDR cs1 size: 2048MB
394 21:44:41.141597 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:44:41.142173 cs0 DataBus test pass
396 21:44:41.147198 cs1 DataBus test pass
397 21:44:41.147759 cs0 AddrBus test pass
398 21:44:41.148291 cs1 AddrBus test pass
399 21:44:41.148753
400 21:44:41.155654 100bdlr_step_size ps== 471
401 21:44:41.156082 result report
402 21:44:41.160962 boot times 0Enable ddr reg access
403 21:44:41.164457 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:44:41.179000 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 21:44:41.836654 bl2z: ptr: 05129330, size: 00001e40
406 21:44:41.846053 0.0;M3 CHK:0;cm4_sp_mode 0
407 21:44:41.846591 MVN_1=0x00000000
408 21:44:41.847023 MVN_2=0x00000000
409 21:44:41.857365 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 21:44:41.857905 OPS=0x04
411 21:44:41.858309 ring efuse init
412 21:44:41.862959 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 21:44:41.863414 [0.017354 Inits done]
414 21:44:41.863811 secure task start!
415 21:44:41.870832 high task start!
416 21:44:41.871273 low task start!
417 21:44:41.871667 run into bl31
418 21:44:41.879509 NOTICE: BL31: v1.3(release):4fc40b1
419 21:44:41.887356 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 21:44:41.887824 NOTICE: BL31: G12A normal boot!
421 21:44:41.903043 NOTICE: BL31: BL33 decompress pass
422 21:44:41.908620 ERROR: Error initializing runtime service opteed_fast
423 21:44:44.616264 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 21:44:44.616904 bl2_stage_init 0x01
425 21:44:44.617336 bl2_stage_init 0x81
426 21:44:44.621671 hw id: 0x0000 - pwm id 0x01
427 21:44:44.622127 bl2_stage_init 0xc1
428 21:44:44.625935 bl2_stage_init 0x02
429 21:44:44.626391
430 21:44:44.626809 L0:00000000
431 21:44:44.627214 L1:00000703
432 21:44:44.627611 L2:00008067
433 21:44:44.631459 L3:15000000
434 21:44:44.631910 S1:00000000
435 21:44:44.632362 B2:20282000
436 21:44:44.632768 B1:a0f83180
437 21:44:44.633166
438 21:44:44.633562 TE: 72836
439 21:44:44.637138
440 21:44:44.642643 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 21:44:44.643117
442 21:44:44.643542 Board ID = 1
443 21:44:44.643958 Set cpu clk to 24M
444 21:44:44.648367 Set clk81 to 24M
445 21:44:44.648822 Use GP1_pll as DSU clk.
446 21:44:44.649233 DSU clk: 1200 Mhz
447 21:44:44.649636 CPU clk: 1200 MHz
448 21:44:44.653892 Set clk81 to 166.6M
449 21:44:44.659436 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 21:44:44.659884 board id: 1
451 21:44:44.668085 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 21:44:44.678958 fw parse done
453 21:44:44.684893 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 21:44:44.727679 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 21:44:44.739367 PIEI prepare done
456 21:44:44.739881 fastboot data load
457 21:44:44.740366 fastboot data verify
458 21:44:44.745053 verify result: 266
459 21:44:44.750536 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 21:44:44.751036 LPDDR4 probe
461 21:44:44.751450 ddr clk to 1584MHz
462 21:44:44.757362 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 21:44:44.795301
464 21:44:44.795849 dmc_version 0001
465 21:44:44.802375 Check phy result
466 21:44:44.809094 INFO : End of CA training
467 21:44:44.809579 INFO : End of initialization
468 21:44:44.814661 INFO : Training has run successfully!
469 21:44:44.815105 Check phy result
470 21:44:44.820404 INFO : End of initialization
471 21:44:44.820843 INFO : End of read enable training
472 21:44:44.823561 INFO : End of fine write leveling
473 21:44:44.829193 INFO : End of Write leveling coarse delay
474 21:44:44.834712 INFO : Training has run successfully!
475 21:44:44.835148 Check phy result
476 21:44:44.835555 INFO : End of initialization
477 21:44:44.840431 INFO : End of read dq deskew training
478 21:44:44.845924 INFO : End of MPR read delay center optimization
479 21:44:44.846354 INFO : End of write delay center optimization
480 21:44:44.851562 INFO : End of read delay center optimization
481 21:44:44.857162 INFO : End of max read latency training
482 21:44:44.857601 INFO : Training has run successfully!
483 21:44:44.862727 1D training succeed
484 21:44:44.868694 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 21:44:44.916927 Check phy result
486 21:44:44.917395 INFO : End of initialization
487 21:44:44.944369 INFO : End of 2D read delay Voltage center optimization
488 21:44:44.968502 INFO : End of 2D read delay Voltage center optimization
489 21:44:45.025260 INFO : End of 2D write delay Voltage center optimization
490 21:44:45.079350 INFO : End of 2D write delay Voltage center optimization
491 21:44:45.084794 INFO : Training has run successfully!
492 21:44:45.085283
493 21:44:45.085698 channel==0
494 21:44:45.090463 RxClkDly_Margin_A0==78 ps 8
495 21:44:45.090898 TxDqDly_Margin_A0==88 ps 9
496 21:44:45.095954 RxClkDly_Margin_A1==88 ps 9
497 21:44:45.096433 TxDqDly_Margin_A1==98 ps 10
498 21:44:45.096847 TrainedVREFDQ_A0==74
499 21:44:45.101570 TrainedVREFDQ_A1==74
500 21:44:45.102004 VrefDac_Margin_A0==23
501 21:44:45.102407 DeviceVref_Margin_A0==40
502 21:44:45.107190 VrefDac_Margin_A1==23
503 21:44:45.107619 DeviceVref_Margin_A1==40
504 21:44:45.108056
505 21:44:45.108476
506 21:44:45.108884 channel==1
507 21:44:45.112924 RxClkDly_Margin_A0==88 ps 9
508 21:44:45.113358 TxDqDly_Margin_A0==88 ps 9
509 21:44:45.118485 RxClkDly_Margin_A1==88 ps 9
510 21:44:45.118924 TxDqDly_Margin_A1==88 ps 9
511 21:44:45.124030 TrainedVREFDQ_A0==75
512 21:44:45.124467 TrainedVREFDQ_A1==77
513 21:44:45.124875 VrefDac_Margin_A0==22
514 21:44:45.129611 DeviceVref_Margin_A0==39
515 21:44:45.130043 VrefDac_Margin_A1==22
516 21:44:45.130448 DeviceVref_Margin_A1==37
517 21:44:45.135208
518 21:44:45.135676 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 21:44:45.136122
520 21:44:45.168780 soc_vref_reg_value 0x 0000001a 00000019 00000018 00000017 00000019 00000016 00000018 00000016 00000018 00000017 00000017 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 21:44:45.169295 2D training succeed
522 21:44:45.174478 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 21:44:45.180003 auto size-- 65535DDR cs0 size: 2048MB
524 21:44:45.180444 DDR cs1 size: 2048MB
525 21:44:45.185649 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 21:44:45.186109 cs0 DataBus test pass
527 21:44:45.191282 cs1 DataBus test pass
528 21:44:45.191715 cs0 AddrBus test pass
529 21:44:45.192157 cs1 AddrBus test pass
530 21:44:45.192559
531 21:44:45.196783 100bdlr_step_size ps== 478
532 21:44:45.197223 result report
533 21:44:45.202478 boot times 0Enable ddr reg access
534 21:44:45.207551 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 21:44:45.221355 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 21:44:45.880800 bl2z: ptr: 05129330, size: 00001e40
537 21:44:45.890001 0.0;M3 CHK:0;cm4_sp_mode 0
538 21:44:45.890487 MVN_1=0x00000000
539 21:44:45.890897 MVN_2=0x00000000
540 21:44:45.901287 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 21:44:45.901748 OPS=0x04
542 21:44:45.902167 ring efuse init
543 21:44:45.904214 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 21:44:45.909769 [0.017354 Inits done]
545 21:44:45.910216 secure task start!
546 21:44:45.910622 high task start!
547 21:44:45.911022 low task start!
548 21:44:45.913980 run into bl31
549 21:44:45.923543 NOTICE: BL31: v1.3(release):4fc40b1
550 21:44:45.931317 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 21:44:45.931768 NOTICE: BL31: G12A normal boot!
552 21:44:45.946990 NOTICE: BL31: BL33 decompress pass
553 21:44:45.952631 ERROR: Error initializing runtime service opteed_fast
554 21:44:47.314140 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 21:44:47.314794 bl2_stage_init 0x01
556 21:44:47.315214 bl2_stage_init 0x81
557 21:44:47.320098 hw id: 0x0000 - pwm id 0x01
558 21:44:47.320669 bl2_stage_init 0xc1
559 21:44:47.324496 bl2_stage_init 0x02
560 21:44:47.325219
561 21:44:47.325743 L0:00000000
562 21:44:47.326253 L1:00000703
563 21:44:47.326755 L2:00008067
564 21:44:47.329987 L3:15000000
565 21:44:47.330603 S1:00000000
566 21:44:47.331111 B2:20282000
567 21:44:47.331616 B1:a0f83180
568 21:44:47.332179
569 21:44:47.332708 TE: 70471
570 21:44:47.333237
571 21:44:47.336379 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 21:44:47.337011
573 21:44:47.342135 Board ID = 1
574 21:44:47.342658 Set cpu clk to 24M
575 21:44:47.343051 Set clk81 to 24M
576 21:44:47.347688 Use GP1_pll as DSU clk.
577 21:44:47.348233 DSU clk: 1200 Mhz
578 21:44:47.348630 CPU clk: 1200 MHz
579 21:44:47.353135 Set clk81 to 166.6M
580 21:44:47.358818 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 21:44:47.359327 board id: 1
582 21:44:47.366157 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 21:44:47.377081 fw parse done
584 21:44:47.382874 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 21:44:47.426047 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 21:44:47.437227 PIEI prepare done
587 21:44:47.437804 fastboot data load
588 21:44:47.438209 fastboot data verify
589 21:44:47.442752 verify result: 266
590 21:44:47.448543 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 21:44:47.449143 LPDDR4 probe
592 21:44:47.449555 ddr clk to 1584MHz
593 21:44:47.456418 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 21:44:47.494218
595 21:44:47.494841 dmc_version 0001
596 21:44:47.501087 Check phy result
597 21:44:47.506986 INFO : End of CA training
598 21:44:47.507529 INFO : End of initialization
599 21:44:47.512595 INFO : Training has run successfully!
600 21:44:47.513112 Check phy result
601 21:44:47.518303 INFO : End of initialization
602 21:44:47.518817 INFO : End of read enable training
603 21:44:47.521549 INFO : End of fine write leveling
604 21:44:47.527135 INFO : End of Write leveling coarse delay
605 21:44:47.532675 INFO : Training has run successfully!
606 21:44:47.533227 Check phy result
607 21:44:47.533654 INFO : End of initialization
608 21:44:47.538281 INFO : End of read dq deskew training
609 21:44:47.544104 INFO : End of MPR read delay center optimization
610 21:44:47.544679 INFO : End of write delay center optimization
611 21:44:47.549586 INFO : End of read delay center optimization
612 21:44:47.555142 INFO : End of max read latency training
613 21:44:47.555709 INFO : Training has run successfully!
614 21:44:47.560740 1D training succeed
615 21:44:47.566682 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 21:44:47.615147 Check phy result
617 21:44:47.615788 INFO : End of initialization
618 21:44:47.644312 INFO : End of 2D read delay Voltage center optimization
619 21:44:47.666596 INFO : End of 2D read delay Voltage center optimization
620 21:44:47.723339 INFO : End of 2D write delay Voltage center optimization
621 21:44:47.777191 INFO : End of 2D write delay Voltage center optimization
622 21:44:47.782912 INFO : Training has run successfully!
623 21:44:47.783388
624 21:44:47.783817 channel==0
625 21:44:47.788459 RxClkDly_Margin_A0==88 ps 9
626 21:44:47.788947 TxDqDly_Margin_A0==98 ps 10
627 21:44:47.791618 RxClkDly_Margin_A1==88 ps 9
628 21:44:47.792115 TxDqDly_Margin_A1==98 ps 10
629 21:44:47.797453 TrainedVREFDQ_A0==74
630 21:44:47.797918 TrainedVREFDQ_A1==75
631 21:44:47.802876 VrefDac_Margin_A0==24
632 21:44:47.803332 DeviceVref_Margin_A0==40
633 21:44:47.803741 VrefDac_Margin_A1==23
634 21:44:47.808401 DeviceVref_Margin_A1==39
635 21:44:47.808858
636 21:44:47.809268
637 21:44:47.809665 channel==1
638 21:44:47.810059 RxClkDly_Margin_A0==88 ps 9
639 21:44:47.811850 TxDqDly_Margin_A0==88 ps 9
640 21:44:47.817579 RxClkDly_Margin_A1==88 ps 9
641 21:44:47.818036 TxDqDly_Margin_A1==98 ps 10
642 21:44:47.818448 TrainedVREFDQ_A0==75
643 21:44:47.822941 TrainedVREFDQ_A1==78
644 21:44:47.823398 VrefDac_Margin_A0==22
645 21:44:47.828365 DeviceVref_Margin_A0==38
646 21:44:47.828817 VrefDac_Margin_A1==22
647 21:44:47.829216 DeviceVref_Margin_A1==36
648 21:44:47.829613
649 21:44:47.837660 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 21:44:47.838122
651 21:44:47.863301 soc_vref_reg_value 0x 0000001a 00000019 00000019 00000017 00000019 00000015 00000018 00000016 00000018 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000061
652 21:44:47.869007 2D training succeed
653 21:44:47.874527 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 21:44:47.874984 auto size-- 65535DDR cs0 size: 2048MB
655 21:44:47.880176 DDR cs1 size: 2048MB
656 21:44:47.880628 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 21:44:47.885732 cs0 DataBus test pass
658 21:44:47.886184 cs1 DataBus test pass
659 21:44:47.891391 cs0 AddrBus test pass
660 21:44:47.891868 cs1 AddrBus test pass
661 21:44:47.892326
662 21:44:47.892734 100bdlr_step_size ps== 471
663 21:44:47.897029 result report
664 21:44:47.897482 boot times 0Enable ddr reg access
665 21:44:47.904577 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 21:44:47.918258 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 21:44:48.577947 bl2z: ptr: 05129330, size: 00001e40
668 21:44:48.585912 0.0;M3 CHK:0;cm4_sp_mode 0
669 21:44:48.586398 MVN_1=0x00000000
670 21:44:48.586815 MVN_2=0x00000000
671 21:44:48.597409 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 21:44:48.597904 OPS=0x04
673 21:44:48.598322 ring efuse init
674 21:44:48.603060 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 21:44:48.603518 [0.017354 Inits done]
676 21:44:48.603926 secure task start!
677 21:44:48.610221 high task start!
678 21:44:48.610662 low task start!
679 21:44:48.611069 run into bl31
680 21:44:48.619749 NOTICE: BL31: v1.3(release):4fc40b1
681 21:44:48.626591 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 21:44:48.627044 NOTICE: BL31: G12A normal boot!
683 21:44:48.643194 NOTICE: BL31: BL33 decompress pass
684 21:44:48.648887 ERROR: Error initializing runtime service opteed_fast
685 21:44:49.442977
686 21:44:49.443557
687 21:44:49.448365 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 21:44:49.448843
689 21:44:49.451887 Model: Libre Computer AML-S905D3-CC Solitude
690 21:44:49.598793 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 21:44:49.614137 DRAM: 2 GiB (effective 3.8 GiB)
692 21:44:49.715098 Core: 406 devices, 33 uclasses, devicetree: separate
693 21:44:49.720952 WDT: Not starting watchdog@f0d0
694 21:44:49.746063 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 21:44:49.758230 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 21:44:49.763242 ** Bad device specification mmc 0 **
697 21:44:49.773349 Card did not respond to voltage select! : -110
698 21:44:49.780931 ** Bad device specification mmc 0 **
699 21:44:49.781372 Couldn't find partition mmc 0
700 21:44:49.789250 Card did not respond to voltage select! : -110
701 21:44:49.794757 ** Bad device specification mmc 0 **
702 21:44:49.795192 Couldn't find partition mmc 0
703 21:44:49.799872 Error: could not access storage.
704 21:44:50.096231 Net: eth0: ethernet@ff3f0000
705 21:44:50.096769 starting USB...
706 21:44:50.341022 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 21:44:50.341583 Starting the controller
708 21:44:50.347861 USB XHCI 1.10
709 21:44:51.901644 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 21:44:51.909685 scanning usb for storage devices... 0 Storage Device(s) found
712 21:44:51.961199 Hit any key to stop autoboot: 1
713 21:44:51.962041 end: 2.4.2 bootloader-interrupt (duration 00:00:20) [common]
714 21:44:51.962625 start: 2.4.3 bootloader-commands (timeout 00:04:40) [common]
715 21:44:51.963101 Setting prompt string to ['=>']
716 21:44:51.963577 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:40)
717 21:44:51.975751 0
718 21:44:51.976652 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 21:44:52.077847 => setenv autoload no
721 21:44:52.078529 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 21:44:52.083270 setenv autoload no
724 21:44:52.184759 => setenv initrd_high 0xffffffff
725 21:44:52.185466 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 21:44:52.189795 setenv initrd_high 0xffffffff
728 21:44:52.291612 => setenv fdt_high 0xffffffff
729 21:44:52.292383 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
730 21:44:52.296614 setenv fdt_high 0xffffffff
732 21:44:52.398063 => dhcp
733 21:44:52.398736 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
734 21:44:52.402776 dhcp
735 21:44:53.008424 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 21:44:53.009004 Speed: 1000, full duplex
737 21:44:53.009449 BOOTP broadcast 1
738 21:44:53.256047 BOOTP broadcast 2
739 21:44:53.758070 BOOTP broadcast 3
740 21:44:54.759034 BOOTP broadcast 4
741 21:44:56.760055 BOOTP broadcast 5
742 21:44:56.772469 DHCP client bound to address 192.168.6.12 (3764 ms)
744 21:44:56.873920 => setenv serverip 192.168.6.2
745 21:44:56.874607 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
746 21:44:56.878865 setenv serverip 192.168.6.2
748 21:44:56.980364 => tftpboot 0x01080000 795087/tftp-deploy-qp884h8o/kernel/uImage
749 21:44:56.981045 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
750 21:44:56.987510 tftpboot 0x01080000 795087/tftp-deploy-qp884h8o/kernel/uImage
751 21:44:56.987965 Speed: 1000, full duplex
752 21:44:56.988441 Using ethernet@ff3f0000 device
753 21:44:56.993039 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 21:44:56.998525 Filename '795087/tftp-deploy-qp884h8o/kernel/uImage'.
755 21:44:57.002413 Load address: 0x1080000
756 21:44:59.880809 Loading: *################################################## 37.6 MiB
757 21:44:59.881406 13.1 MiB/s
758 21:44:59.881836 done
759 21:44:59.885117 Bytes transferred = 39424576 (2599240 hex)
761 21:44:59.986769 => tftpboot 0x08000000 795087/tftp-deploy-qp884h8o/ramdisk/ramdisk.cpio.gz.uboot
762 21:44:59.987428 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
763 21:44:59.994017 tftpboot 0x08000000 795087/tftp-deploy-qp884h8o/ramdisk/ramdisk.cpio.gz.uboot
764 21:44:59.994472 Speed: 1000, full duplex
765 21:44:59.994868 Using ethernet@ff3f0000 device
766 21:44:59.999511 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 21:45:00.009338 Filename '795087/tftp-deploy-qp884h8o/ramdisk/ramdisk.cpio.gz.uboot'.
768 21:45:00.009667 Load address: 0x8000000
769 21:45:01.972813 Loading: *################################################# UDP wrong checksum 00000005 0000c02d
770 21:45:06.974090 T UDP wrong checksum 00000005 0000c02d
771 21:45:16.975453 T T UDP wrong checksum 00000005 0000c02d
772 21:45:36.980146 T T T T UDP wrong checksum 00000005 0000c02d
773 21:45:50.194004 T T UDP wrong checksum 000000ff 0000c247
774 21:45:50.213748 UDP wrong checksum 000000ff 0000573a
775 21:45:56.984652 T
776 21:45:56.985325 Retry count exceeded; starting again
778 21:45:56.986928 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
781 21:45:56.989061 end: 2.4 uboot-commands (duration 00:01:25) [common]
783 21:45:56.990550 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
785 21:45:56.991662 end: 2 uboot-action (duration 00:01:25) [common]
787 21:45:56.993472 Cleaning after the job
788 21:45:56.994096 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/ramdisk
789 21:45:56.995353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/kernel
790 21:45:57.040803 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/dtb
791 21:45:57.041653 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795087/tftp-deploy-qp884h8o/modules
792 21:45:57.064007 start: 4.1 power-off (timeout 00:00:30) [common]
793 21:45:57.064694 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
794 21:45:57.096146 >> OK - accepted request
795 21:45:57.098223 Returned 0 in 0 seconds
796 21:45:57.199035 end: 4.1 power-off (duration 00:00:00) [common]
798 21:45:57.200065 start: 4.2 read-feedback (timeout 00:10:00) [common]
799 21:45:57.200739 Listened to connection for namespace 'common' for up to 1s
800 21:45:58.201727 Finalising connection for namespace 'common'
801 21:45:58.202522 Disconnecting from shell: Finalise
802 21:45:58.203120 =>
803 21:45:58.304185 end: 4.2 read-feedback (duration 00:00:01) [common]
804 21:45:58.304865 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795087
805 21:45:58.624247 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795087
806 21:45:58.624849 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.