Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:46:26.261208 lava-dispatcher, installed at version: 2024.01
2 21:46:26.261973 start: 0 validate
3 21:46:26.262463 Start time: 2024-10-02 21:46:26.262434+00:00 (UTC)
4 21:46:26.263015 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:46:26.263543 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 21:46:26.298237 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:46:26.298859 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fkernel%2FImage exists
8 21:46:26.327948 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:46:26.328657 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:46:26.358113 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:46:26.358671 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 21:46:26.393841 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 21:46:26.394338 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fmodules.tar.xz exists
14 21:46:26.435066 validate duration: 0.17
16 21:46:26.435916 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:46:26.436278 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:46:26.436603 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:46:26.437194 Not decompressing ramdisk as can be used compressed.
20 21:46:26.437637 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 21:46:26.437918 saving as /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/ramdisk/initrd.cpio.gz
22 21:46:26.438193 total size: 5628182 (5 MB)
23 21:46:26.473103 progress 0 % (0 MB)
24 21:46:26.477881 progress 5 % (0 MB)
25 21:46:26.485531 progress 10 % (0 MB)
26 21:46:26.492450 progress 15 % (0 MB)
27 21:46:26.498156 progress 20 % (1 MB)
28 21:46:26.501755 progress 25 % (1 MB)
29 21:46:26.505748 progress 30 % (1 MB)
30 21:46:26.509759 progress 35 % (1 MB)
31 21:46:26.513306 progress 40 % (2 MB)
32 21:46:26.517324 progress 45 % (2 MB)
33 21:46:26.520886 progress 50 % (2 MB)
34 21:46:26.524806 progress 55 % (2 MB)
35 21:46:26.528739 progress 60 % (3 MB)
36 21:46:26.532221 progress 65 % (3 MB)
37 21:46:26.536135 progress 70 % (3 MB)
38 21:46:26.539647 progress 75 % (4 MB)
39 21:46:26.543606 progress 80 % (4 MB)
40 21:46:26.547153 progress 85 % (4 MB)
41 21:46:26.551096 progress 90 % (4 MB)
42 21:46:26.554920 progress 95 % (5 MB)
43 21:46:26.558218 progress 100 % (5 MB)
44 21:46:26.558885 5 MB downloaded in 0.12 s (44.48 MB/s)
45 21:46:26.559421 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:46:26.560348 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:46:26.560650 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:46:26.560920 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:46:26.561392 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/kernel/Image
51 21:46:26.561664 saving as /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/kernel/Image
52 21:46:26.561873 total size: 39424512 (37 MB)
53 21:46:26.562084 No compression specified
54 21:46:26.596199 progress 0 % (0 MB)
55 21:46:26.624019 progress 5 % (1 MB)
56 21:46:26.651319 progress 10 % (3 MB)
57 21:46:26.678615 progress 15 % (5 MB)
58 21:46:26.703603 progress 20 % (7 MB)
59 21:46:26.728971 progress 25 % (9 MB)
60 21:46:26.753805 progress 30 % (11 MB)
61 21:46:26.779723 progress 35 % (13 MB)
62 21:46:26.805189 progress 40 % (15 MB)
63 21:46:26.830745 progress 45 % (16 MB)
64 21:46:26.855910 progress 50 % (18 MB)
65 21:46:26.881274 progress 55 % (20 MB)
66 21:46:26.906744 progress 60 % (22 MB)
67 21:46:26.932579 progress 65 % (24 MB)
68 21:46:26.957980 progress 70 % (26 MB)
69 21:46:26.983215 progress 75 % (28 MB)
70 21:46:27.008535 progress 80 % (30 MB)
71 21:46:27.033947 progress 85 % (31 MB)
72 21:46:27.059308 progress 90 % (33 MB)
73 21:46:27.084739 progress 95 % (35 MB)
74 21:46:27.109817 progress 100 % (37 MB)
75 21:46:27.110384 37 MB downloaded in 0.55 s (68.55 MB/s)
76 21:46:27.110885 end: 1.2.1 http-download (duration 00:00:01) [common]
78 21:46:27.111725 end: 1.2 download-retry (duration 00:00:01) [common]
79 21:46:27.112042 start: 1.3 download-retry (timeout 00:09:59) [common]
80 21:46:27.112333 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 21:46:27.112830 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 21:46:27.113089 saving as /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/dtb/meson-g12b-a311d-libretech-cc.dtb
83 21:46:27.113302 total size: 54703 (0 MB)
84 21:46:27.113516 No compression specified
85 21:46:27.146165 progress 59 % (0 MB)
86 21:46:27.147041 progress 100 % (0 MB)
87 21:46:27.147619 0 MB downloaded in 0.03 s (1.52 MB/s)
88 21:46:27.148146 end: 1.3.1 http-download (duration 00:00:00) [common]
90 21:46:27.149032 end: 1.3 download-retry (duration 00:00:00) [common]
91 21:46:27.149314 start: 1.4 download-retry (timeout 00:09:59) [common]
92 21:46:27.149592 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 21:46:27.150100 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 21:46:27.150367 saving as /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/nfsrootfs/full.rootfs.tar
95 21:46:27.150577 total size: 107552908 (102 MB)
96 21:46:27.150798 Using unxz to decompress xz
97 21:46:27.184980 progress 0 % (0 MB)
98 21:46:27.840547 progress 5 % (5 MB)
99 21:46:28.567651 progress 10 % (10 MB)
100 21:46:29.307087 progress 15 % (15 MB)
101 21:46:30.089504 progress 20 % (20 MB)
102 21:46:30.680656 progress 25 % (25 MB)
103 21:46:31.309356 progress 30 % (30 MB)
104 21:46:32.062840 progress 35 % (35 MB)
105 21:46:32.413590 progress 40 % (41 MB)
106 21:46:32.844734 progress 45 % (46 MB)
107 21:46:33.553277 progress 50 % (51 MB)
108 21:46:34.273952 progress 55 % (56 MB)
109 21:46:35.049307 progress 60 % (61 MB)
110 21:46:35.832460 progress 65 % (66 MB)
111 21:46:36.603947 progress 70 % (71 MB)
112 21:46:37.409006 progress 75 % (76 MB)
113 21:46:38.098626 progress 80 % (82 MB)
114 21:46:38.809195 progress 85 % (87 MB)
115 21:46:39.551469 progress 90 % (92 MB)
116 21:46:40.281334 progress 95 % (97 MB)
117 21:46:41.049248 progress 100 % (102 MB)
118 21:46:41.062306 102 MB downloaded in 13.91 s (7.37 MB/s)
119 21:46:41.062971 end: 1.4.1 http-download (duration 00:00:14) [common]
121 21:46:41.063802 end: 1.4 download-retry (duration 00:00:14) [common]
122 21:46:41.064105 start: 1.5 download-retry (timeout 00:09:45) [common]
123 21:46:41.064406 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 21:46:41.064961 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/modules.tar.xz
125 21:46:41.065235 saving as /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/modules/modules.tar
126 21:46:41.065452 total size: 11755936 (11 MB)
127 21:46:41.065674 Using unxz to decompress xz
128 21:46:41.101682 progress 0 % (0 MB)
129 21:46:41.174896 progress 5 % (0 MB)
130 21:46:41.259301 progress 10 % (1 MB)
131 21:46:41.351375 progress 15 % (1 MB)
132 21:46:41.433777 progress 20 % (2 MB)
133 21:46:41.519048 progress 25 % (2 MB)
134 21:46:41.601994 progress 30 % (3 MB)
135 21:46:41.684527 progress 35 % (3 MB)
136 21:46:41.764849 progress 40 % (4 MB)
137 21:46:41.846653 progress 45 % (5 MB)
138 21:46:41.929652 progress 50 % (5 MB)
139 21:46:42.009446 progress 55 % (6 MB)
140 21:46:42.096700 progress 60 % (6 MB)
141 21:46:42.184495 progress 65 % (7 MB)
142 21:46:42.268811 progress 70 % (7 MB)
143 21:46:42.364615 progress 75 % (8 MB)
144 21:46:42.460883 progress 80 % (9 MB)
145 21:46:42.538968 progress 85 % (9 MB)
146 21:46:42.616789 progress 90 % (10 MB)
147 21:46:42.696612 progress 95 % (10 MB)
148 21:46:42.774588 progress 100 % (11 MB)
149 21:46:42.787796 11 MB downloaded in 1.72 s (6.51 MB/s)
150 21:46:42.788724 end: 1.5.1 http-download (duration 00:00:02) [common]
152 21:46:42.790335 end: 1.5 download-retry (duration 00:00:02) [common]
153 21:46:42.790850 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 21:46:42.791365 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 21:46:54.475934 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/795082/extract-nfsrootfs-ly_kivq7
156 21:46:54.476572 end: 1.6.1 extract-nfsrootfs (duration 00:00:12) [common]
157 21:46:54.476895 start: 1.6.2 lava-overlay (timeout 00:09:32) [common]
158 21:46:54.477523 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_
159 21:46:54.478016 makedir: /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin
160 21:46:54.478390 makedir: /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/tests
161 21:46:54.478824 makedir: /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/results
162 21:46:54.479234 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-add-keys
163 21:46:54.479852 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-add-sources
164 21:46:54.480543 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-background-process-start
165 21:46:54.481212 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-background-process-stop
166 21:46:54.481913 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-common-functions
167 21:46:54.482626 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-echo-ipv4
168 21:46:54.483240 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-install-packages
169 21:46:54.483831 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-installed-packages
170 21:46:54.484415 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-os-build
171 21:46:54.484945 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-probe-channel
172 21:46:54.485453 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-probe-ip
173 21:46:54.485952 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-target-ip
174 21:46:54.486454 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-target-mac
175 21:46:54.486945 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-target-storage
176 21:46:54.487461 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-test-case
177 21:46:54.487972 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-test-event
178 21:46:54.488532 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-test-feedback
179 21:46:54.489046 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-test-raise
180 21:46:54.489582 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-test-reference
181 21:46:54.490089 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-test-runner
182 21:46:54.490617 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-test-set
183 21:46:54.491126 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-test-shell
184 21:46:54.491648 Updating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-install-packages (oe)
185 21:46:54.492353 Updating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/bin/lava-installed-packages (oe)
186 21:46:54.492935 Creating /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/environment
187 21:46:54.493384 LAVA metadata
188 21:46:54.493681 - LAVA_JOB_ID=795082
189 21:46:54.493922 - LAVA_DISPATCHER_IP=192.168.6.2
190 21:46:54.494344 start: 1.6.2.1 ssh-authorize (timeout 00:09:32) [common]
191 21:46:54.495594 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 21:46:54.495947 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:32) [common]
193 21:46:54.496224 skipped lava-vland-overlay
194 21:46:54.496512 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 21:46:54.496798 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:32) [common]
196 21:46:54.497042 skipped lava-multinode-overlay
197 21:46:54.497312 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 21:46:54.497587 start: 1.6.2.4 test-definition (timeout 00:09:32) [common]
199 21:46:54.497868 Loading test definitions
200 21:46:54.498165 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:32) [common]
201 21:46:54.498407 Using /lava-795082 at stage 0
202 21:46:54.499716 uuid=795082_1.6.2.4.1 testdef=None
203 21:46:54.500072 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 21:46:54.500352 start: 1.6.2.4.2 test-overlay (timeout 00:09:32) [common]
205 21:46:54.502321 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 21:46:54.503129 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:32) [common]
208 21:46:54.505509 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 21:46:54.506367 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:32) [common]
211 21:46:54.508702 runner path: /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/0/tests/0_dmesg test_uuid 795082_1.6.2.4.1
212 21:46:54.509314 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 21:46:54.510075 Creating lava-test-runner.conf files
215 21:46:54.510276 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795082/lava-overlay-155mnrm_/lava-795082/0 for stage 0
216 21:46:54.510636 - 0_dmesg
217 21:46:54.510988 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 21:46:54.511268 start: 1.6.2.5 compress-overlay (timeout 00:09:32) [common]
219 21:46:54.534829 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 21:46:54.535279 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:32) [common]
221 21:46:54.535555 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 21:46:54.535843 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 21:46:54.536157 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
224 21:46:55.221373 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 21:46:55.221875 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
226 21:46:55.222185 extracting modules file /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795082/extract-nfsrootfs-ly_kivq7
227 21:46:56.727375 extracting modules file /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795082/extract-overlay-ramdisk-7cdi0rdw/ramdisk
228 21:46:58.236850 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 21:46:58.237362 start: 1.6.5 apply-overlay-tftp (timeout 00:09:28) [common]
230 21:46:58.237696 [common] Applying overlay to NFS
231 21:46:58.237961 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795082/compress-overlay-j3tsqtzf/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795082/extract-nfsrootfs-ly_kivq7
232 21:46:58.272819 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 21:46:58.273320 start: 1.6.6 prepare-kernel (timeout 00:09:28) [common]
234 21:46:58.273649 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:28) [common]
235 21:46:58.273918 Converting downloaded kernel to a uImage
236 21:46:58.274312 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/kernel/Image /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/kernel/uImage
237 21:46:58.694856 output: Image Name:
238 21:46:58.695277 output: Created: Wed Oct 2 21:46:58 2024
239 21:46:58.695493 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 21:46:58.695698 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
241 21:46:58.695900 output: Load Address: 01080000
242 21:46:58.696145 output: Entry Point: 01080000
243 21:46:58.696347 output:
244 21:46:58.696775 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 21:46:58.697055 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 21:46:58.697323 start: 1.6.7 configure-preseed-file (timeout 00:09:28) [common]
247 21:46:58.697579 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 21:46:58.697838 start: 1.6.8 compress-ramdisk (timeout 00:09:28) [common]
249 21:46:58.698097 Building ramdisk /var/lib/lava/dispatcher/tmp/795082/extract-overlay-ramdisk-7cdi0rdw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795082/extract-overlay-ramdisk-7cdi0rdw/ramdisk
250 21:47:01.285041 >> 173426 blocks
251 21:47:09.216153 Adding RAMdisk u-boot header.
252 21:47:09.216612 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795082/extract-overlay-ramdisk-7cdi0rdw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795082/extract-overlay-ramdisk-7cdi0rdw/ramdisk.cpio.gz.uboot
253 21:47:09.462854 output: Image Name:
254 21:47:09.463284 output: Created: Wed Oct 2 21:47:09 2024
255 21:47:09.463501 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 21:47:09.463707 output: Data Size: 24126053 Bytes = 23560.60 KiB = 23.01 MiB
257 21:47:09.463907 output: Load Address: 00000000
258 21:47:09.464262 output: Entry Point: 00000000
259 21:47:09.464661 output:
260 21:47:09.465757 rename /var/lib/lava/dispatcher/tmp/795082/extract-overlay-ramdisk-7cdi0rdw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/ramdisk/ramdisk.cpio.gz.uboot
261 21:47:09.466486 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 21:47:09.467035 end: 1.6 prepare-tftp-overlay (duration 00:00:27) [common]
263 21:47:09.467563 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
264 21:47:09.468051 No LXC device requested
265 21:47:09.468567 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 21:47:09.469078 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
267 21:47:09.469570 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 21:47:09.469979 Checking files for TFTP limit of 4294967296 bytes.
269 21:47:09.472785 end: 1 tftp-deploy (duration 00:00:43) [common]
270 21:47:09.473397 start: 2 uboot-action (timeout 00:05:00) [common]
271 21:47:09.473923 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 21:47:09.474418 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 21:47:09.474920 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 21:47:09.475444 Using kernel file from prepare-kernel: 795082/tftp-deploy-7ran1pv0/kernel/uImage
275 21:47:09.476092 substitutions:
276 21:47:09.476508 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 21:47:09.476909 - {DTB_ADDR}: 0x01070000
278 21:47:09.477302 - {DTB}: 795082/tftp-deploy-7ran1pv0/dtb/meson-g12b-a311d-libretech-cc.dtb
279 21:47:09.477696 - {INITRD}: 795082/tftp-deploy-7ran1pv0/ramdisk/ramdisk.cpio.gz.uboot
280 21:47:09.478086 - {KERNEL_ADDR}: 0x01080000
281 21:47:09.478475 - {KERNEL}: 795082/tftp-deploy-7ran1pv0/kernel/uImage
282 21:47:09.478865 - {LAVA_MAC}: None
283 21:47:09.479295 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/795082/extract-nfsrootfs-ly_kivq7
284 21:47:09.479690 - {NFS_SERVER_IP}: 192.168.6.2
285 21:47:09.480104 - {PRESEED_CONFIG}: None
286 21:47:09.480495 - {PRESEED_LOCAL}: None
287 21:47:09.480878 - {RAMDISK_ADDR}: 0x08000000
288 21:47:09.481261 - {RAMDISK}: 795082/tftp-deploy-7ran1pv0/ramdisk/ramdisk.cpio.gz.uboot
289 21:47:09.481644 - {ROOT_PART}: None
290 21:47:09.482031 - {ROOT}: None
291 21:47:09.482419 - {SERVER_IP}: 192.168.6.2
292 21:47:09.482805 - {TEE_ADDR}: 0x83000000
293 21:47:09.483186 - {TEE}: None
294 21:47:09.483572 Parsed boot commands:
295 21:47:09.483946 - setenv autoload no
296 21:47:09.484360 - setenv initrd_high 0xffffffff
297 21:47:09.484743 - setenv fdt_high 0xffffffff
298 21:47:09.485123 - dhcp
299 21:47:09.485505 - setenv serverip 192.168.6.2
300 21:47:09.485887 - tftpboot 0x01080000 795082/tftp-deploy-7ran1pv0/kernel/uImage
301 21:47:09.486270 - tftpboot 0x08000000 795082/tftp-deploy-7ran1pv0/ramdisk/ramdisk.cpio.gz.uboot
302 21:47:09.486652 - tftpboot 0x01070000 795082/tftp-deploy-7ran1pv0/dtb/meson-g12b-a311d-libretech-cc.dtb
303 21:47:09.487036 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/795082/extract-nfsrootfs-ly_kivq7,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 21:47:09.487431 - bootm 0x01080000 0x08000000 0x01070000
305 21:47:09.487938 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 21:47:09.489448 start: 2.3 connect-device (timeout 00:05:00) [common]
308 21:47:09.489863 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 21:47:09.503349 Setting prompt string to ['lava-test: # ']
310 21:47:09.504333 end: 2.3 connect-device (duration 00:00:00) [common]
311 21:47:09.504745 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 21:47:09.505086 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 21:47:09.505393 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 21:47:09.506032 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 21:47:09.539789 >> OK - accepted request
316 21:47:09.541903 Returned 0 in 0 seconds
317 21:47:09.642955 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 21:47:09.643955 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 21:47:09.644357 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 21:47:09.644651 Setting prompt string to ['Hit any key to stop autoboot']
322 21:47:09.644909 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 21:47:09.645829 Trying 192.168.56.21...
324 21:47:09.646109 Connected to conserv1.
325 21:47:09.646338 Escape character is '^]'.
326 21:47:09.646566
327 21:47:09.646796 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 21:47:09.647023
329 21:47:20.609926 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 21:47:20.610364 bl2_stage_init 0x81
331 21:47:20.615410 hw id: 0x0000 - pwm id 0x01
332 21:47:20.615745 bl2_stage_init 0xc1
333 21:47:20.615974 bl2_stage_init 0x02
334 21:47:20.616227
335 21:47:20.620950 L0:00000000
336 21:47:20.621234 L1:20000703
337 21:47:20.621444 L2:00008067
338 21:47:20.621648 L3:14000000
339 21:47:20.621850 B2:00402000
340 21:47:20.626638 B1:e0f83180
341 21:47:20.626963
342 21:47:20.627178 TE: 58150
343 21:47:20.627386
344 21:47:20.632154 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 21:47:20.632446
346 21:47:20.632665 Board ID = 1
347 21:47:20.637734 Set A53 clk to 24M
348 21:47:20.638021 Set A73 clk to 24M
349 21:47:20.638231 Set clk81 to 24M
350 21:47:20.643362 A53 clk: 1200 MHz
351 21:47:20.643668 A73 clk: 1200 MHz
352 21:47:20.643879 CLK81: 166.6M
353 21:47:20.644115 smccc: 00012aab
354 21:47:20.648923 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 21:47:20.654624 board id: 1
356 21:47:20.660357 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 21:47:20.671037 fw parse done
358 21:47:20.675953 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 21:47:20.719561 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 21:47:20.730547 PIEI prepare done
361 21:47:20.730854 fastboot data load
362 21:47:20.731059 fastboot data verify
363 21:47:20.736147 verify result: 266
364 21:47:20.741853 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 21:47:20.742164 LPDDR4 probe
366 21:47:20.742370 ddr clk to 1584MHz
367 21:47:20.748913 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 21:47:20.787023
369 21:47:20.787380 dmc_version 0001
370 21:47:20.793677 Check phy result
371 21:47:20.799571 INFO : End of CA training
372 21:47:20.799822 INFO : End of initialization
373 21:47:20.805166 INFO : Training has run successfully!
374 21:47:20.805440 Check phy result
375 21:47:20.810728 INFO : End of initialization
376 21:47:20.810982 INFO : End of read enable training
377 21:47:20.816388 INFO : End of fine write leveling
378 21:47:20.821901 INFO : End of Write leveling coarse delay
379 21:47:20.822154 INFO : Training has run successfully!
380 21:47:20.822364 Check phy result
381 21:47:20.827573 INFO : End of initialization
382 21:47:20.827824 INFO : End of read dq deskew training
383 21:47:20.833152 INFO : End of MPR read delay center optimization
384 21:47:20.838746 INFO : End of write delay center optimization
385 21:47:20.844333 INFO : End of read delay center optimization
386 21:47:20.844625 INFO : End of max read latency training
387 21:47:20.849968 INFO : Training has run successfully!
388 21:47:20.850241 1D training succeed
389 21:47:20.858112 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 21:47:20.906796 Check phy result
391 21:47:20.907216 INFO : End of initialization
392 21:47:20.927498 INFO : End of 2D read delay Voltage center optimization
393 21:47:20.948559 INFO : End of 2D read delay Voltage center optimization
394 21:47:21.000441 INFO : End of 2D write delay Voltage center optimization
395 21:47:21.049785 INFO : End of 2D write delay Voltage center optimization
396 21:47:21.055159 INFO : Training has run successfully!
397 21:47:21.055430
398 21:47:21.055639 channel==0
399 21:47:21.060777 RxClkDly_Margin_A0==88 ps 9
400 21:47:21.061022 TxDqDly_Margin_A0==98 ps 10
401 21:47:21.066369 RxClkDly_Margin_A1==88 ps 9
402 21:47:21.066629 TxDqDly_Margin_A1==88 ps 9
403 21:47:21.066838 TrainedVREFDQ_A0==74
404 21:47:21.072011 TrainedVREFDQ_A1==74
405 21:47:21.072272 VrefDac_Margin_A0==25
406 21:47:21.072480 DeviceVref_Margin_A0==40
407 21:47:21.077617 VrefDac_Margin_A1==25
408 21:47:21.077881 DeviceVref_Margin_A1==40
409 21:47:21.078087
410 21:47:21.078291
411 21:47:21.078495 channel==1
412 21:47:21.083214 RxClkDly_Margin_A0==98 ps 10
413 21:47:21.083461 TxDqDly_Margin_A0==98 ps 10
414 21:47:21.088758 RxClkDly_Margin_A1==98 ps 10
415 21:47:21.089038 TxDqDly_Margin_A1==88 ps 9
416 21:47:21.094366 TrainedVREFDQ_A0==77
417 21:47:21.094617 TrainedVREFDQ_A1==77
418 21:47:21.094824 VrefDac_Margin_A0==22
419 21:47:21.100002 DeviceVref_Margin_A0==37
420 21:47:21.100262 VrefDac_Margin_A1==22
421 21:47:21.105635 DeviceVref_Margin_A1==37
422 21:47:21.105895
423 21:47:21.106104 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 21:47:21.106308
425 21:47:21.139140 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
426 21:47:21.139553 2D training succeed
427 21:47:21.144809 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 21:47:21.150475 auto size-- 65535DDR cs0 size: 2048MB
429 21:47:21.150844 DDR cs1 size: 2048MB
430 21:47:21.155977 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 21:47:21.156331 cs0 DataBus test pass
432 21:47:21.161685 cs1 DataBus test pass
433 21:47:21.161984 cs0 AddrBus test pass
434 21:47:21.162195 cs1 AddrBus test pass
435 21:47:21.162396
436 21:47:21.167182 100bdlr_step_size ps== 420
437 21:47:21.167478 result report
438 21:47:21.172757 boot times 0Enable ddr reg access
439 21:47:21.178096 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 21:47:21.191517 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 21:47:21.763592 0.0;M3 CHK:0;cm4_sp_mode 0
442 21:47:21.764030 MVN_1=0x00000000
443 21:47:21.769112 MVN_2=0x00000000
444 21:47:21.774855 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 21:47:21.775129 OPS=0x10
446 21:47:21.775345 ring efuse init
447 21:47:21.775564 chipver efuse init
448 21:47:21.783016 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 21:47:21.783288 [0.018961 Inits done]
450 21:47:21.789729 secure task start!
451 21:47:21.789982 high task start!
452 21:47:21.790183 low task start!
453 21:47:21.790380 run into bl31
454 21:47:21.797254 NOTICE: BL31: v1.3(release):4fc40b1
455 21:47:21.805066 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 21:47:21.805344 NOTICE: BL31: G12A normal boot!
457 21:47:21.830513 NOTICE: BL31: BL33 decompress pass
458 21:47:21.835191 ERROR: Error initializing runtime service opteed_fast
459 21:47:23.069632
460 21:47:23.070062
461 21:47:23.077289 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 21:47:23.077676
463 21:47:23.077991 Model: Libre Computer AML-A311D-CC Alta
464 21:47:23.286056 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 21:47:23.309347 DRAM: 2 GiB (effective 3.8 GiB)
466 21:47:23.452263 Core: 408 devices, 31 uclasses, devicetree: separate
467 21:47:23.458246 WDT: Not starting watchdog@f0d0
468 21:47:23.490386 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 21:47:23.502899 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 21:47:23.507935 ** Bad device specification mmc 0 **
471 21:47:23.518194 Card did not respond to voltage select! : -110
472 21:47:23.525849 ** Bad device specification mmc 0 **
473 21:47:23.526134 Couldn't find partition mmc 0
474 21:47:23.534146 Card did not respond to voltage select! : -110
475 21:47:23.539711 ** Bad device specification mmc 0 **
476 21:47:23.540123 Couldn't find partition mmc 0
477 21:47:23.544721 Error: could not access storage.
478 21:47:24.810693 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
479 21:47:24.811084 bl2_stage_init 0x01
480 21:47:24.811319 bl2_stage_init 0x81
481 21:47:24.815872 hw id: 0x0000 - pwm id 0x01
482 21:47:24.816144 bl2_stage_init 0xc1
483 21:47:24.816356 bl2_stage_init 0x02
484 21:47:24.816561
485 21:47:24.821723 L0:00000000
486 21:47:24.821988 L1:20000703
487 21:47:24.822189 L2:00008067
488 21:47:24.822396 L3:14000000
489 21:47:24.824522 B2:00402000
490 21:47:24.824759 B1:e0f83180
491 21:47:24.824961
492 21:47:24.825166 TE: 58124
493 21:47:24.825371
494 21:47:24.835773 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 21:47:24.836076
496 21:47:24.836303 Board ID = 1
497 21:47:24.836517 Set A53 clk to 24M
498 21:47:24.836726 Set A73 clk to 24M
499 21:47:24.841087 Set clk81 to 24M
500 21:47:24.841339 A53 clk: 1200 MHz
501 21:47:24.841552 A73 clk: 1200 MHz
502 21:47:24.845215 CLK81: 166.6M
503 21:47:24.845470 smccc: 00012a92
504 21:47:24.850777 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 21:47:24.851049 board id: 1
506 21:47:24.859949 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 21:47:24.871720 fw parse done
508 21:47:24.876525 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 21:47:24.919149 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 21:47:24.930953 PIEI prepare done
511 21:47:24.931238 fastboot data load
512 21:47:24.931451 fastboot data verify
513 21:47:24.936523 verify result: 266
514 21:47:24.942124 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 21:47:24.942391 LPDDR4 probe
516 21:47:24.942603 ddr clk to 1584MHz
517 21:47:24.950091 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 21:47:24.987416
519 21:47:24.987750 dmc_version 0001
520 21:47:24.993654 Check phy result
521 21:47:24.999915 INFO : End of CA training
522 21:47:25.000220 INFO : End of initialization
523 21:47:25.005483 INFO : Training has run successfully!
524 21:47:25.005754 Check phy result
525 21:47:25.011212 INFO : End of initialization
526 21:47:25.011573 INFO : End of read enable training
527 21:47:25.014509 INFO : End of fine write leveling
528 21:47:25.020023 INFO : End of Write leveling coarse delay
529 21:47:25.025671 INFO : Training has run successfully!
530 21:47:25.025934 Check phy result
531 21:47:25.026139 INFO : End of initialization
532 21:47:25.031255 INFO : End of read dq deskew training
533 21:47:25.036841 INFO : End of MPR read delay center optimization
534 21:47:25.037106 INFO : End of write delay center optimization
535 21:47:25.042432 INFO : End of read delay center optimization
536 21:47:25.048067 INFO : End of max read latency training
537 21:47:25.048334 INFO : Training has run successfully!
538 21:47:25.053651 1D training succeed
539 21:47:25.059512 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 21:47:25.107046 Check phy result
541 21:47:25.107372 INFO : End of initialization
542 21:47:25.129510 INFO : End of 2D read delay Voltage center optimization
543 21:47:25.149637 INFO : End of 2D read delay Voltage center optimization
544 21:47:25.201530 INFO : End of 2D write delay Voltage center optimization
545 21:47:25.250868 INFO : End of 2D write delay Voltage center optimization
546 21:47:25.256343 INFO : Training has run successfully!
547 21:47:25.256635
548 21:47:25.256860 channel==0
549 21:47:25.261938 RxClkDly_Margin_A0==88 ps 9
550 21:47:25.262210 TxDqDly_Margin_A0==98 ps 10
551 21:47:25.267570 RxClkDly_Margin_A1==88 ps 9
552 21:47:25.267917 TxDqDly_Margin_A1==98 ps 10
553 21:47:25.268217 TrainedVREFDQ_A0==74
554 21:47:25.273207 TrainedVREFDQ_A1==75
555 21:47:25.273533 VrefDac_Margin_A0==25
556 21:47:25.273745 DeviceVref_Margin_A0==40
557 21:47:25.278778 VrefDac_Margin_A1==25
558 21:47:25.279086 DeviceVref_Margin_A1==39
559 21:47:25.279307
560 21:47:25.279522
561 21:47:25.284409 channel==1
562 21:47:25.284688 RxClkDly_Margin_A0==98 ps 10
563 21:47:25.284903 TxDqDly_Margin_A0==98 ps 10
564 21:47:25.289979 RxClkDly_Margin_A1==98 ps 10
565 21:47:25.290269 TxDqDly_Margin_A1==88 ps 9
566 21:47:25.295620 TrainedVREFDQ_A0==77
567 21:47:25.295909 TrainedVREFDQ_A1==77
568 21:47:25.296152 VrefDac_Margin_A0==22
569 21:47:25.301254 DeviceVref_Margin_A0==37
570 21:47:25.301562 VrefDac_Margin_A1==22
571 21:47:25.306789 DeviceVref_Margin_A1==37
572 21:47:25.307085
573 21:47:25.307302 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 21:47:25.312447
575 21:47:25.340384 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 21:47:25.340742 2D training succeed
577 21:47:25.346001 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 21:47:25.351571 auto size-- 65535DDR cs0 size: 2048MB
579 21:47:25.351878 DDR cs1 size: 2048MB
580 21:47:25.357238 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 21:47:25.357550 cs0 DataBus test pass
582 21:47:25.362771 cs1 DataBus test pass
583 21:47:25.363078 cs0 AddrBus test pass
584 21:47:25.363289 cs1 AddrBus test pass
585 21:47:25.363489
586 21:47:25.368492 100bdlr_step_size ps== 420
587 21:47:25.368839 result report
588 21:47:25.373914 boot times 0Enable ddr reg access
589 21:47:25.379439 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 21:47:25.392918 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 21:47:25.965002 0.0;M3 CHK:0;cm4_sp_mode 0
592 21:47:25.965638 MVN_1=0x00000000
593 21:47:25.970466 MVN_2=0x00000000
594 21:47:25.976266 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 21:47:25.976754 OPS=0x10
596 21:47:25.977107 ring efuse init
597 21:47:25.977439 chipver efuse init
598 21:47:25.981798 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 21:47:25.987458 [0.018961 Inits done]
600 21:47:25.987889 secure task start!
601 21:47:25.988280 high task start!
602 21:47:25.991957 low task start!
603 21:47:25.992396 run into bl31
604 21:47:25.998608 NOTICE: BL31: v1.3(release):4fc40b1
605 21:47:26.005600 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 21:47:26.006064 NOTICE: BL31: G12A normal boot!
607 21:47:26.031815 NOTICE: BL31: BL33 decompress pass
608 21:47:26.037372 ERROR: Error initializing runtime service opteed_fast
609 21:47:27.270281
610 21:47:27.270719
611 21:47:27.278759 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 21:47:27.279120
613 21:47:27.279354 Model: Libre Computer AML-A311D-CC Alta
614 21:47:27.487168 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 21:47:27.510558 DRAM: 2 GiB (effective 3.8 GiB)
616 21:47:27.653616 Core: 408 devices, 31 uclasses, devicetree: separate
617 21:47:27.659435 WDT: Not starting watchdog@f0d0
618 21:47:27.691779 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 21:47:27.704096 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 21:47:27.709068 ** Bad device specification mmc 0 **
621 21:47:27.719432 Card did not respond to voltage select! : -110
622 21:47:27.727041 ** Bad device specification mmc 0 **
623 21:47:27.727340 Couldn't find partition mmc 0
624 21:47:27.735404 Card did not respond to voltage select! : -110
625 21:47:27.740931 ** Bad device specification mmc 0 **
626 21:47:27.741226 Couldn't find partition mmc 0
627 21:47:27.745962 Error: could not access storage.
628 21:47:28.088588 Net: eth0: ethernet@ff3f0000
629 21:47:28.089179 starting USB...
630 21:47:28.340310 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 21:47:28.340733 Starting the controller
632 21:47:28.347230 USB XHCI 1.10
633 21:47:30.058749 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 21:47:30.059160 bl2_stage_init 0x01
635 21:47:30.059374 bl2_stage_init 0x81
636 21:47:30.064319 hw id: 0x0000 - pwm id 0x01
637 21:47:30.064683 bl2_stage_init 0xc1
638 21:47:30.064986 bl2_stage_init 0x02
639 21:47:30.065276
640 21:47:30.069862 L0:00000000
641 21:47:30.070146 L1:20000703
642 21:47:30.070352 L2:00008067
643 21:47:30.070548 L3:14000000
644 21:47:30.075422 B2:00402000
645 21:47:30.075767 B1:e0f83180
646 21:47:30.076112
647 21:47:30.076645 TE: 58124
648 21:47:30.077070
649 21:47:30.081839 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 21:47:30.082304
651 21:47:30.082724 Board ID = 1
652 21:47:30.086668 Set A53 clk to 24M
653 21:47:30.087124 Set A73 clk to 24M
654 21:47:30.087534 Set clk81 to 24M
655 21:47:30.092265 A53 clk: 1200 MHz
656 21:47:30.092726 A73 clk: 1200 MHz
657 21:47:30.093141 CLK81: 166.6M
658 21:47:30.093547 smccc: 00012a92
659 21:47:30.097816 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 21:47:30.103462 board id: 1
661 21:47:30.109452 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 21:47:30.119973 fw parse done
663 21:47:30.126015 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 21:47:30.168504 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 21:47:30.179401 PIEI prepare done
666 21:47:30.179869 fastboot data load
667 21:47:30.180357 fastboot data verify
668 21:47:30.185090 verify result: 266
669 21:47:30.190661 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 21:47:30.191124 LPDDR4 probe
671 21:47:30.191536 ddr clk to 1584MHz
672 21:47:30.198643 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 21:47:30.235909
674 21:47:30.236417 dmc_version 0001
675 21:47:30.242692 Check phy result
676 21:47:30.248452 INFO : End of CA training
677 21:47:30.248925 INFO : End of initialization
678 21:47:30.254070 INFO : Training has run successfully!
679 21:47:30.254539 Check phy result
680 21:47:30.259657 INFO : End of initialization
681 21:47:30.260198 INFO : End of read enable training
682 21:47:30.265291 INFO : End of fine write leveling
683 21:47:30.270851 INFO : End of Write leveling coarse delay
684 21:47:30.271307 INFO : Training has run successfully!
685 21:47:30.271722 Check phy result
686 21:47:30.276493 INFO : End of initialization
687 21:47:30.276957 INFO : End of read dq deskew training
688 21:47:30.282095 INFO : End of MPR read delay center optimization
689 21:47:30.287652 INFO : End of write delay center optimization
690 21:47:30.293259 INFO : End of read delay center optimization
691 21:47:30.293735 INFO : End of max read latency training
692 21:47:30.298848 INFO : Training has run successfully!
693 21:47:30.299298 1D training succeed
694 21:47:30.308059 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 21:47:30.355643 Check phy result
696 21:47:30.356143 INFO : End of initialization
697 21:47:30.378082 INFO : End of 2D read delay Voltage center optimization
698 21:47:30.398219 INFO : End of 2D read delay Voltage center optimization
699 21:47:30.450143 INFO : End of 2D write delay Voltage center optimization
700 21:47:30.499404 INFO : End of 2D write delay Voltage center optimization
701 21:47:30.505030 INFO : Training has run successfully!
702 21:47:30.505482
703 21:47:30.505899 channel==0
704 21:47:30.510443 RxClkDly_Margin_A0==88 ps 9
705 21:47:30.510893 TxDqDly_Margin_A0==98 ps 10
706 21:47:30.513790 RxClkDly_Margin_A1==88 ps 9
707 21:47:30.514239 TxDqDly_Margin_A1==98 ps 10
708 21:47:30.519379 TrainedVREFDQ_A0==74
709 21:47:30.519838 TrainedVREFDQ_A1==75
710 21:47:30.524966 VrefDac_Margin_A0==25
711 21:47:30.525417 DeviceVref_Margin_A0==40
712 21:47:30.525826 VrefDac_Margin_A1==25
713 21:47:30.530682 DeviceVref_Margin_A1==39
714 21:47:30.531134
715 21:47:30.531541
716 21:47:30.531940 channel==1
717 21:47:30.532376 RxClkDly_Margin_A0==98 ps 10
718 21:47:30.534009 TxDqDly_Margin_A0==98 ps 10
719 21:47:30.539569 RxClkDly_Margin_A1==98 ps 10
720 21:47:30.540034 TxDqDly_Margin_A1==108 ps 11
721 21:47:30.545212 TrainedVREFDQ_A0==77
722 21:47:30.545671 TrainedVREFDQ_A1==78
723 21:47:30.546083 VrefDac_Margin_A0==23
724 21:47:30.550701 DeviceVref_Margin_A0==37
725 21:47:30.551157 VrefDac_Margin_A1==24
726 21:47:30.551556 DeviceVref_Margin_A1==36
727 21:47:30.551949
728 21:47:30.559766 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 21:47:30.560259
730 21:47:30.585584 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
731 21:47:30.591257 2D training succeed
732 21:47:30.594699 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 21:47:30.600122 auto size-- 65535DDR cs0 size: 2048MB
734 21:47:30.600611 DDR cs1 size: 2048MB
735 21:47:30.605697 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 21:47:30.606181 cs0 DataBus test pass
737 21:47:30.611351 cs1 DataBus test pass
738 21:47:30.611828 cs0 AddrBus test pass
739 21:47:30.612341 cs1 AddrBus test pass
740 21:47:30.612761
741 21:47:30.614852 100bdlr_step_size ps== 420
742 21:47:30.615328 result report
743 21:47:30.620380 boot times 0Enable ddr reg access
744 21:47:30.628091 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 21:47:30.640594 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 21:47:31.213478 0.0;M3 CHK:0;cm4_sp_mode 0
747 21:47:31.213926 MVN_1=0x00000000
748 21:47:31.218947 MVN_2=0x00000000
749 21:47:31.224741 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 21:47:31.225075 OPS=0x10
751 21:47:31.225334 ring efuse init
752 21:47:31.225584 chipver efuse init
753 21:47:31.232925 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 21:47:31.233273 [0.018961 Inits done]
755 21:47:31.239610 secure task start!
756 21:47:31.239949 high task start!
757 21:47:31.240256 low task start!
758 21:47:31.240507 run into bl31
759 21:47:31.247180 NOTICE: BL31: v1.3(release):4fc40b1
760 21:47:31.254520 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 21:47:31.254879 NOTICE: BL31: G12A normal boot!
762 21:47:31.280496 NOTICE: BL31: BL33 decompress pass
763 21:47:31.285354 ERROR: Error initializing runtime service opteed_fast
764 21:47:32.518898
765 21:47:32.519325
766 21:47:32.526451 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 21:47:32.526761
768 21:47:32.526986 Model: Libre Computer AML-A311D-CC Alta
769 21:47:32.734789 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 21:47:32.758243 DRAM: 2 GiB (effective 3.8 GiB)
771 21:47:32.902147 Core: 408 devices, 31 uclasses, devicetree: separate
772 21:47:32.907133 WDT: Not starting watchdog@f0d0
773 21:47:32.940318 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 21:47:32.952801 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 21:47:32.956789 ** Bad device specification mmc 0 **
776 21:47:32.968121 Card did not respond to voltage select! : -110
777 21:47:32.974869 ** Bad device specification mmc 0 **
778 21:47:32.975245 Couldn't find partition mmc 0
779 21:47:32.984147 Card did not respond to voltage select! : -110
780 21:47:32.989560 ** Bad device specification mmc 0 **
781 21:47:32.990071 Couldn't find partition mmc 0
782 21:47:32.993813 Error: could not access storage.
783 21:47:33.337105 Net: eth0: ethernet@ff3f0000
784 21:47:33.337539 starting USB...
785 21:47:33.589384 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 21:47:33.590473 Starting the controller
787 21:47:33.596812 USB XHCI 1.10
788 21:47:35.679074 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 21:47:35.679498 bl2_stage_init 0x01
790 21:47:35.679729 bl2_stage_init 0x81
791 21:47:35.684528 hw id: 0x0000 - pwm id 0x01
792 21:47:35.684932 bl2_stage_init 0xc1
793 21:47:35.685263 bl2_stage_init 0x02
794 21:47:35.685705
795 21:47:35.691292 L0:00000000
796 21:47:35.691925 L1:20000703
797 21:47:35.692422 L2:00008067
798 21:47:35.692867 L3:14000000
799 21:47:35.693510 B2:00402000
800 21:47:35.693770 B1:e0f83180
801 21:47:35.693991
802 21:47:35.694432 TE: 58124
803 21:47:35.694940
804 21:47:35.704327 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 21:47:35.704917
806 21:47:35.705241 Board ID = 1
807 21:47:35.705458 Set A53 clk to 24M
808 21:47:35.705666 Set A73 clk to 24M
809 21:47:35.709858 Set clk81 to 24M
810 21:47:35.710189 A53 clk: 1200 MHz
811 21:47:35.710434 A73 clk: 1200 MHz
812 21:47:35.715452 CLK81: 166.6M
813 21:47:35.716069 smccc: 00012a92
814 21:47:35.721039 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 21:47:35.721566 board id: 1
816 21:47:35.728624 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 21:47:35.740210 fw parse done
818 21:47:35.745807 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 21:47:35.787965 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 21:47:35.803733 PIEI prepare done
821 21:47:35.804350 fastboot data load
822 21:47:35.805296 fastboot data verify
823 21:47:35.806536 verify result: 266
824 21:47:35.810947 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 21:47:35.811320 LPDDR4 probe
826 21:47:35.811569 ddr clk to 1584MHz
827 21:47:35.818994 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 21:47:35.856155
829 21:47:35.856585 dmc_version 0001
830 21:47:35.861865 Check phy result
831 21:47:35.868692 INFO : End of CA training
832 21:47:35.869233 INFO : End of initialization
833 21:47:35.874264 INFO : Training has run successfully!
834 21:47:35.874645 Check phy result
835 21:47:35.880017 INFO : End of initialization
836 21:47:35.880542 INFO : End of read enable training
837 21:47:35.885514 INFO : End of fine write leveling
838 21:47:35.891071 INFO : End of Write leveling coarse delay
839 21:47:35.891443 INFO : Training has run successfully!
840 21:47:35.891677 Check phy result
841 21:47:35.896697 INFO : End of initialization
842 21:47:35.897064 INFO : End of read dq deskew training
843 21:47:35.902300 INFO : End of MPR read delay center optimization
844 21:47:35.907937 INFO : End of write delay center optimization
845 21:47:35.913661 INFO : End of read delay center optimization
846 21:47:35.914049 INFO : End of max read latency training
847 21:47:35.919117 INFO : Training has run successfully!
848 21:47:35.919546 1D training succeed
849 21:47:35.927876 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 21:47:35.975107 Check phy result
851 21:47:35.975706 INFO : End of initialization
852 21:47:35.996863 INFO : End of 2D read delay Voltage center optimization
853 21:47:36.017534 INFO : End of 2D read delay Voltage center optimization
854 21:47:36.068982 INFO : End of 2D write delay Voltage center optimization
855 21:47:36.119331 INFO : End of 2D write delay Voltage center optimization
856 21:47:36.124887 INFO : Training has run successfully!
857 21:47:36.125321
858 21:47:36.125613 channel==0
859 21:47:36.130452 RxClkDly_Margin_A0==88 ps 9
860 21:47:36.130967 TxDqDly_Margin_A0==98 ps 10
861 21:47:36.136091 RxClkDly_Margin_A1==88 ps 9
862 21:47:36.136575 TxDqDly_Margin_A1==98 ps 10
863 21:47:36.136946 TrainedVREFDQ_A0==74
864 21:47:36.141665 TrainedVREFDQ_A1==74
865 21:47:36.142026 VrefDac_Margin_A0==25
866 21:47:36.142276 DeviceVref_Margin_A0==40
867 21:47:36.147197 VrefDac_Margin_A1==25
868 21:47:36.147822 DeviceVref_Margin_A1==40
869 21:47:36.148275
870 21:47:36.148680
871 21:47:36.152938 channel==1
872 21:47:36.153488 RxClkDly_Margin_A0==98 ps 10
873 21:47:36.153902 TxDqDly_Margin_A0==98 ps 10
874 21:47:36.158501 RxClkDly_Margin_A1==98 ps 10
875 21:47:36.159029 TxDqDly_Margin_A1==88 ps 9
876 21:47:36.164081 TrainedVREFDQ_A0==77
877 21:47:36.164631 TrainedVREFDQ_A1==77
878 21:47:36.165036 VrefDac_Margin_A0==22
879 21:47:36.169707 DeviceVref_Margin_A0==37
880 21:47:36.170238 VrefDac_Margin_A1==22
881 21:47:36.175290 DeviceVref_Margin_A1==37
882 21:47:36.175804
883 21:47:36.176259 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 21:47:36.180968
885 21:47:36.208849 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
886 21:47:36.209459 2D training succeed
887 21:47:36.214451 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 21:47:36.219921 auto size-- 65535DDR cs0 size: 2048MB
889 21:47:36.220302 DDR cs1 size: 2048MB
890 21:47:36.225647 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 21:47:36.226187 cs0 DataBus test pass
892 21:47:36.231268 cs1 DataBus test pass
893 21:47:36.231792 cs0 AddrBus test pass
894 21:47:36.232227 cs1 AddrBus test pass
895 21:47:36.232623
896 21:47:36.236807 100bdlr_step_size ps== 420
897 21:47:36.237304 result report
898 21:47:36.242429 boot times 0Enable ddr reg access
899 21:47:36.246940 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 21:47:36.260307 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 21:47:36.834155 0.0;M3 CHK:0;cm4_sp_mode 0
902 21:47:36.834608 MVN_1=0x00000000
903 21:47:36.839690 MVN_2=0x00000000
904 21:47:36.845448 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 21:47:36.845784 OPS=0x10
906 21:47:36.846012 ring efuse init
907 21:47:36.846223 chipver efuse init
908 21:47:36.851058 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 21:47:36.856619 [0.018961 Inits done]
910 21:47:36.856940 secure task start!
911 21:47:36.857152 high task start!
912 21:47:36.860368 low task start!
913 21:47:36.860677 run into bl31
914 21:47:36.867944 NOTICE: BL31: v1.3(release):4fc40b1
915 21:47:36.874957 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 21:47:36.875288 NOTICE: BL31: G12A normal boot!
917 21:47:36.901123 NOTICE: BL31: BL33 decompress pass
918 21:47:36.906449 ERROR: Error initializing runtime service opteed_fast
919 21:47:38.139584
920 21:47:38.140192
921 21:47:38.147183 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 21:47:38.147511
923 21:47:38.147739 Model: Libre Computer AML-A311D-CC Alta
924 21:47:38.356466 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 21:47:38.379146 DRAM: 2 GiB (effective 3.8 GiB)
926 21:47:38.522798 Core: 408 devices, 31 uclasses, devicetree: separate
927 21:47:38.527707 WDT: Not starting watchdog@f0d0
928 21:47:38.560969 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 21:47:38.573420 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 21:47:38.577891 ** Bad device specification mmc 0 **
931 21:47:38.588745 Card did not respond to voltage select! : -110
932 21:47:38.595630 ** Bad device specification mmc 0 **
933 21:47:38.595938 Couldn't find partition mmc 0
934 21:47:38.604728 Card did not respond to voltage select! : -110
935 21:47:38.610211 ** Bad device specification mmc 0 **
936 21:47:38.610503 Couldn't find partition mmc 0
937 21:47:38.614872 Error: could not access storage.
938 21:47:38.956831 Net: eth0: ethernet@ff3f0000
939 21:47:38.957270 starting USB...
940 21:47:39.209545 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 21:47:39.209963 Starting the controller
942 21:47:39.216382 USB XHCI 1.10
943 21:47:41.078627 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
944 21:47:41.079068 bl2_stage_init 0x81
945 21:47:41.084170 hw id: 0x0000 - pwm id 0x01
946 21:47:41.084583 bl2_stage_init 0xc1
947 21:47:41.084904 bl2_stage_init 0x02
948 21:47:41.085209
949 21:47:41.089717 L0:00000000
950 21:47:41.090004 L1:20000703
951 21:47:41.090218 L2:00008067
952 21:47:41.090421 L3:14000000
953 21:47:41.090620 B2:00402000
954 21:47:41.092485 B1:e0f83180
955 21:47:41.092863
956 21:47:41.093186 TE: 58150
957 21:47:41.093497
958 21:47:41.103675 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 21:47:41.104140
960 21:47:41.104472 Board ID = 1
961 21:47:41.104781 Set A53 clk to 24M
962 21:47:41.105086 Set A73 clk to 24M
963 21:47:41.109385 Set clk81 to 24M
964 21:47:41.109691 A53 clk: 1200 MHz
965 21:47:41.109911 A73 clk: 1200 MHz
966 21:47:41.114930 CLK81: 166.6M
967 21:47:41.115334 smccc: 00012aac
968 21:47:41.120548 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 21:47:41.120965 board id: 1
970 21:47:41.128197 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 21:47:41.139788 fw parse done
972 21:47:41.145122 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 21:47:41.187490 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 21:47:41.199289 PIEI prepare done
975 21:47:41.199606 fastboot data load
976 21:47:41.199820 fastboot data verify
977 21:47:41.205257 verify result: 266
978 21:47:41.210298 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 21:47:41.210606 LPDDR4 probe
980 21:47:41.212905 ddr clk to 1584MHz
981 21:47:41.217820 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 21:47:41.255086
983 21:47:41.255454 dmc_version 0001
984 21:47:41.261761 Check phy result
985 21:47:41.268423 INFO : End of CA training
986 21:47:41.268706 INFO : End of initialization
987 21:47:41.274045 INFO : Training has run successfully!
988 21:47:41.274314 Check phy result
989 21:47:41.279849 INFO : End of initialization
990 21:47:41.280164 INFO : End of read enable training
991 21:47:41.285231 INFO : End of fine write leveling
992 21:47:41.290747 INFO : End of Write leveling coarse delay
993 21:47:41.291009 INFO : Training has run successfully!
994 21:47:41.291213 Check phy result
995 21:47:41.296401 INFO : End of initialization
996 21:47:41.296666 INFO : End of read dq deskew training
997 21:47:41.301964 INFO : End of MPR read delay center optimization
998 21:47:41.307585 INFO : End of write delay center optimization
999 21:47:41.313086 INFO : End of read delay center optimization
1000 21:47:41.313350 INFO : End of max read latency training
1001 21:47:41.318739 INFO : Training has run successfully!
1002 21:47:41.319004 1D training succeed
1003 21:47:41.326986 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 21:47:41.374721 Check phy result
1005 21:47:41.375122 INFO : End of initialization
1006 21:47:41.396279 INFO : End of 2D read delay Voltage center optimization
1007 21:47:41.416473 INFO : End of 2D read delay Voltage center optimization
1008 21:47:41.468351 INFO : End of 2D write delay Voltage center optimization
1009 21:47:41.518520 INFO : End of 2D write delay Voltage center optimization
1010 21:47:41.524015 INFO : Training has run successfully!
1011 21:47:41.524290
1012 21:47:41.524495 channel==0
1013 21:47:41.529645 RxClkDly_Margin_A0==88 ps 9
1014 21:47:41.530027 TxDqDly_Margin_A0==98 ps 10
1015 21:47:41.532860 RxClkDly_Margin_A1==88 ps 9
1016 21:47:41.533232 TxDqDly_Margin_A1==98 ps 10
1017 21:47:41.538435 TrainedVREFDQ_A0==74
1018 21:47:41.538815 TrainedVREFDQ_A1==74
1019 21:47:41.544107 VrefDac_Margin_A0==25
1020 21:47:41.544408 DeviceVref_Margin_A0==40
1021 21:47:41.544624 VrefDac_Margin_A1==25
1022 21:47:41.549586 DeviceVref_Margin_A1==40
1023 21:47:41.549961
1024 21:47:41.550274
1025 21:47:41.550573 channel==1
1026 21:47:41.550867 RxClkDly_Margin_A0==88 ps 9
1027 21:47:41.553119 TxDqDly_Margin_A0==98 ps 10
1028 21:47:41.558648 RxClkDly_Margin_A1==98 ps 10
1029 21:47:41.558907 TxDqDly_Margin_A1==88 ps 9
1030 21:47:41.559114 TrainedVREFDQ_A0==77
1031 21:47:41.564277 TrainedVREFDQ_A1==77
1032 21:47:41.564641 VrefDac_Margin_A0==23
1033 21:47:41.569876 DeviceVref_Margin_A0==37
1034 21:47:41.570237 VrefDac_Margin_A1==24
1035 21:47:41.570551 DeviceVref_Margin_A1==37
1036 21:47:41.570774
1037 21:47:41.575499 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 21:47:41.575772
1039 21:47:41.608924 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1040 21:47:41.609241 2D training succeed
1041 21:47:41.614568 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 21:47:41.620330 auto size-- 65535DDR cs0 size: 2048MB
1043 21:47:41.620811 DDR cs1 size: 2048MB
1044 21:47:41.625894 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 21:47:41.626278 cs0 DataBus test pass
1046 21:47:41.626496 cs1 DataBus test pass
1047 21:47:41.636141 cs0 AddrBus test pass
1048 21:47:41.636883 cs1 AddrBus test pass
1049 21:47:41.637303
1050 21:47:41.637960 100bdlr_step_size ps== 420
1051 21:47:41.638392 result report
1052 21:47:41.638640 boot times 0Enable ddr reg access
1053 21:47:41.646556 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 21:47:41.659354 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 21:47:42.232261 0.0;M3 CHK:0;cm4_sp_mode 0
1056 21:47:42.232668 MVN_1=0x00000000
1057 21:47:42.237788 MVN_2=0x00000000
1058 21:47:42.243639 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 21:47:42.244128 OPS=0x10
1060 21:47:42.244411 ring efuse init
1061 21:47:42.244629 chipver efuse init
1062 21:47:42.251789 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 21:47:42.252283 [0.018961 Inits done]
1064 21:47:42.259248 secure task start!
1065 21:47:42.259682 high task start!
1066 21:47:42.260102 low task start!
1067 21:47:42.260463 run into bl31
1068 21:47:42.265988 NOTICE: BL31: v1.3(release):4fc40b1
1069 21:47:42.273297 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 21:47:42.273736 NOTICE: BL31: G12A normal boot!
1071 21:47:42.299133 NOTICE: BL31: BL33 decompress pass
1072 21:47:42.304576 ERROR: Error initializing runtime service opteed_fast
1073 21:47:43.537680
1074 21:47:43.538108
1075 21:47:43.545208 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 21:47:43.545558
1077 21:47:43.545778 Model: Libre Computer AML-A311D-CC Alta
1078 21:47:43.753556 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 21:47:43.776977 DRAM: 2 GiB (effective 3.8 GiB)
1080 21:47:43.920934 Core: 408 devices, 31 uclasses, devicetree: separate
1081 21:47:43.925995 WDT: Not starting watchdog@f0d0
1082 21:47:43.959001 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 21:47:43.971370 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 21:47:43.976018 ** Bad device specification mmc 0 **
1085 21:47:43.986734 Card did not respond to voltage select! : -110
1086 21:47:43.994081 ** Bad device specification mmc 0 **
1087 21:47:43.994412 Couldn't find partition mmc 0
1088 21:47:44.002766 Card did not respond to voltage select! : -110
1089 21:47:44.008203 ** Bad device specification mmc 0 **
1090 21:47:44.008632 Couldn't find partition mmc 0
1091 21:47:44.012309 Error: could not access storage.
1092 21:47:44.354858 Net: eth0: ethernet@ff3f0000
1093 21:47:44.355273 starting USB...
1094 21:47:44.607597 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 21:47:44.608176 Starting the controller
1096 21:47:44.614438 USB XHCI 1.10
1097 21:47:46.168894 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 21:47:46.176328 scanning usb for storage devices... 0 Storage Device(s) found
1100 21:47:46.228131 Hit any key to stop autoboot: 1
1101 21:47:46.228971 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1102 21:47:46.229638 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1103 21:47:46.230175 Setting prompt string to ['=>']
1104 21:47:46.230706 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1105 21:47:46.233598 0
1106 21:47:46.234542 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 21:47:46.235107 Sending with 10 millisecond of delay
1109 21:47:47.369993 => setenv autoload no
1110 21:47:47.380784 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1111 21:47:47.386126 setenv autoload no
1112 21:47:47.386909 Sending with 10 millisecond of delay
1114 21:47:49.183816 => setenv initrd_high 0xffffffff
1115 21:47:49.194685 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1116 21:47:49.195608 setenv initrd_high 0xffffffff
1117 21:47:49.196422 Sending with 10 millisecond of delay
1119 21:47:50.813101 => setenv fdt_high 0xffffffff
1120 21:47:50.823951 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1121 21:47:50.824899 setenv fdt_high 0xffffffff
1122 21:47:50.825780 Sending with 10 millisecond of delay
1124 21:47:51.117723 => dhcp
1125 21:47:51.128456 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1126 21:47:51.129323 dhcp
1127 21:47:51.129801 Speed: 1000, full duplex
1128 21:47:51.130249 BOOTP broadcast 1
1129 21:47:51.375236 BOOTP broadcast 2
1130 21:47:51.387735 DHCP client bound to address 192.168.6.33 (260 ms)
1131 21:47:51.388671 Sending with 10 millisecond of delay
1133 21:47:53.065307 => setenv serverip 192.168.6.2
1134 21:47:53.076136 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 21:47:53.077015 setenv serverip 192.168.6.2
1136 21:47:53.077777 Sending with 10 millisecond of delay
1138 21:47:56.801455 => tftpboot 0x01080000 795082/tftp-deploy-7ran1pv0/kernel/uImage
1139 21:47:56.813177 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1140 21:47:56.813743 tftpboot 0x01080000 795082/tftp-deploy-7ran1pv0/kernel/uImage
1141 21:47:56.813994 Speed: 1000, full duplex
1142 21:47:56.814202 Using ethernet@ff3f0000 device
1143 21:47:56.816878 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1144 21:47:56.822400 Filename '795082/tftp-deploy-7ran1pv0/kernel/uImage'.
1145 21:47:56.826254 Load address: 0x1080000
1146 21:47:59.566177 Loading: *###################################### UDP wrong checksum 000000ff 00006bac
1147 21:47:59.586066 # UDP wrong checksum 000000ff 0000089f
1148 21:48:00.274240 ########### 37.6 MiB
1149 21:48:00.277898 10.9 MiB/s
1150 21:48:00.278163 done
1151 21:48:00.278382 Bytes transferred = 39424576 (2599240 hex)
1152 21:48:00.278838 Sending with 10 millisecond of delay
1154 21:48:04.966029 => tftpboot 0x08000000 795082/tftp-deploy-7ran1pv0/ramdisk/ramdisk.cpio.gz.uboot
1155 21:48:04.977210 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1156 21:48:04.978161 tftpboot 0x08000000 795082/tftp-deploy-7ran1pv0/ramdisk/ramdisk.cpio.gz.uboot
1157 21:48:04.978624 Speed: 1000, full duplex
1158 21:48:04.979058 Using ethernet@ff3f0000 device
1159 21:48:04.979591 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 21:48:04.987886 Filename '795082/tftp-deploy-7ran1pv0/ramdisk/ramdisk.cpio.gz.uboot'.
1161 21:48:04.988481 Load address: 0x8000000
1162 21:48:06.920742 Loading: *################################################# UDP wrong checksum 00000005 0000544f
1163 21:48:11.585933 UDP wrong checksum 000000ff 0000bfb5
1164 21:48:11.594205 UDP wrong checksum 000000ff 000056a8
1165 21:48:11.921691 T UDP wrong checksum 00000005 0000544f
1166 21:48:21.924445 T T UDP wrong checksum 00000005 0000544f
1167 21:48:23.665990 UDP wrong checksum 000000ff 00000c69
1168 21:48:23.672499 UDP wrong checksum 000000ff 0000a05b
1169 21:48:41.927875 T T T T UDP wrong checksum 00000005 0000544f
1170 21:48:42.259312 UDP wrong checksum 000000ff 00002331
1171 21:48:42.289181 UDP wrong checksum 000000ff 0000b823
1172 21:48:43.081966 UDP wrong checksum 000000ff 0000b264
1173 21:48:43.090282 UDP wrong checksum 000000ff 00003c57
1174 21:49:01.932831 T T T
1175 21:49:01.933224 Retry count exceeded; starting again
1177 21:49:01.934083 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1180 21:49:01.935004 end: 2.4 uboot-commands (duration 00:01:52) [common]
1182 21:49:01.935721 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1184 21:49:01.936313 end: 2 uboot-action (duration 00:01:52) [common]
1186 21:49:01.937139 Cleaning after the job
1187 21:49:01.937455 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/ramdisk
1188 21:49:01.938242 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/kernel
1189 21:49:01.960813 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/dtb
1190 21:49:01.961733 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/nfsrootfs
1191 21:49:01.998943 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795082/tftp-deploy-7ran1pv0/modules
1192 21:49:02.006183 start: 4.1 power-off (timeout 00:00:30) [common]
1193 21:49:02.006770 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1194 21:49:02.037164 >> OK - accepted request
1195 21:49:02.039054 Returned 0 in 0 seconds
1196 21:49:02.139754 end: 4.1 power-off (duration 00:00:00) [common]
1198 21:49:02.140681 start: 4.2 read-feedback (timeout 00:10:00) [common]
1199 21:49:02.141343 Listened to connection for namespace 'common' for up to 1s
1200 21:49:03.142298 Finalising connection for namespace 'common'
1201 21:49:03.142866 Disconnecting from shell: Finalise
1202 21:49:03.143191 =>
1203 21:49:03.243966 end: 4.2 read-feedback (duration 00:00:01) [common]
1204 21:49:03.244670 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795082
1205 21:49:04.951242 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795082
1206 21:49:04.951829 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.