Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:06:04.152542 lava-dispatcher, installed at version: 2024.01
2 21:06:04.153377 start: 0 validate
3 21:06:04.153819 Start time: 2024-10-02 21:06:04.153791+00:00 (UTC)
4 21:06:04.154373 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:06:04.154876 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64be%2Frootfs.cpio.gz exists
6 21:06:04.198147 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:06:04.199064 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_CPU_BIG_ENDIAN%3Dy%2Fgcc-12%2Fkernel%2FImage exists
8 21:06:05.241210 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:06:05.241839 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_CPU_BIG_ENDIAN%3Dy%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 21:06:10.311841 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:06:10.312472 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2BCONFIG_CPU_BIG_ENDIAN%3Dy%2Fgcc-12%2Fmodules.tar.xz exists
12 21:06:11.372896 validate duration: 7.22
14 21:06:11.373753 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:06:11.374093 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:06:11.374417 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:06:11.375025 Not decompressing ramdisk as can be used compressed.
18 21:06:11.375465 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64be/rootfs.cpio.gz
19 21:06:11.375749 saving as /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/ramdisk/rootfs.cpio.gz
20 21:06:11.376065 total size: 8083589 (7 MB)
21 21:06:11.419789 progress 0 % (0 MB)
22 21:06:11.432088 progress 5 % (0 MB)
23 21:06:11.443598 progress 10 % (0 MB)
24 21:06:11.455478 progress 15 % (1 MB)
25 21:06:11.462990 progress 20 % (1 MB)
26 21:06:11.468395 progress 25 % (1 MB)
27 21:06:11.474464 progress 30 % (2 MB)
28 21:06:11.479840 progress 35 % (2 MB)
29 21:06:11.485293 progress 40 % (3 MB)
30 21:06:11.491016 progress 45 % (3 MB)
31 21:06:11.496315 progress 50 % (3 MB)
32 21:06:11.501710 progress 55 % (4 MB)
33 21:06:11.507401 progress 60 % (4 MB)
34 21:06:11.514063 progress 65 % (5 MB)
35 21:06:11.519835 progress 70 % (5 MB)
36 21:06:11.525729 progress 75 % (5 MB)
37 21:06:11.531140 progress 80 % (6 MB)
38 21:06:11.536538 progress 85 % (6 MB)
39 21:06:11.542346 progress 90 % (6 MB)
40 21:06:11.547723 progress 95 % (7 MB)
41 21:06:11.552802 progress 100 % (7 MB)
42 21:06:11.553526 7 MB downloaded in 0.18 s (43.45 MB/s)
43 21:06:11.554126 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:06:11.555101 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:06:11.555440 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:06:11.555751 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:06:11.556296 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-12/kernel/Image
49 21:06:11.556624 saving as /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/kernel/Image
50 21:06:11.556855 total size: 44136456 (42 MB)
51 21:06:11.557082 No compression specified
52 21:06:11.596558 progress 0 % (0 MB)
53 21:06:11.623776 progress 5 % (2 MB)
54 21:06:11.650912 progress 10 % (4 MB)
55 21:06:11.678405 progress 15 % (6 MB)
56 21:06:11.705909 progress 20 % (8 MB)
57 21:06:11.732775 progress 25 % (10 MB)
58 21:06:11.760030 progress 30 % (12 MB)
59 21:06:11.786720 progress 35 % (14 MB)
60 21:06:11.813345 progress 40 % (16 MB)
61 21:06:11.840456 progress 45 % (18 MB)
62 21:06:11.867254 progress 50 % (21 MB)
63 21:06:11.893986 progress 55 % (23 MB)
64 21:06:11.921652 progress 60 % (25 MB)
65 21:06:11.948288 progress 65 % (27 MB)
66 21:06:11.975462 progress 70 % (29 MB)
67 21:06:12.002415 progress 75 % (31 MB)
68 21:06:12.028780 progress 80 % (33 MB)
69 21:06:12.055175 progress 85 % (35 MB)
70 21:06:12.081794 progress 90 % (37 MB)
71 21:06:12.108697 progress 95 % (40 MB)
72 21:06:12.137581 progress 100 % (42 MB)
73 21:06:12.138395 42 MB downloaded in 0.58 s (72.38 MB/s)
74 21:06:12.138922 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:06:12.139746 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:06:12.140047 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:06:12.140320 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:06:12.140804 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 21:06:12.141086 saving as /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 21:06:12.141296 total size: 53209 (0 MB)
82 21:06:12.141507 No compression specified
83 21:06:12.184284 progress 61 % (0 MB)
84 21:06:12.185200 progress 100 % (0 MB)
85 21:06:12.185800 0 MB downloaded in 0.04 s (1.14 MB/s)
86 21:06:12.186324 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:06:12.187224 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:06:12.187521 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:06:12.187829 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:06:12.188375 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+CONFIG_CPU_BIG_ENDIAN=y/gcc-12/modules.tar.xz
92 21:06:12.188667 saving as /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/modules/modules.tar
93 21:06:12.188890 total size: 11441952 (10 MB)
94 21:06:12.189114 Using unxz to decompress xz
95 21:06:12.236474 progress 0 % (0 MB)
96 21:06:12.308571 progress 5 % (0 MB)
97 21:06:12.384761 progress 10 % (1 MB)
98 21:06:12.474889 progress 15 % (1 MB)
99 21:06:12.552266 progress 20 % (2 MB)
100 21:06:12.636695 progress 25 % (2 MB)
101 21:06:12.713592 progress 30 % (3 MB)
102 21:06:12.794386 progress 35 % (3 MB)
103 21:06:12.869886 progress 40 % (4 MB)
104 21:06:12.946744 progress 45 % (4 MB)
105 21:06:13.022102 progress 50 % (5 MB)
106 21:06:13.098549 progress 55 % (6 MB)
107 21:06:13.178566 progress 60 % (6 MB)
108 21:06:13.306966 progress 65 % (7 MB)
109 21:06:13.390143 progress 70 % (7 MB)
110 21:06:13.486482 progress 75 % (8 MB)
111 21:06:13.583028 progress 80 % (8 MB)
112 21:06:13.659920 progress 85 % (9 MB)
113 21:06:13.736198 progress 90 % (9 MB)
114 21:06:13.808761 progress 95 % (10 MB)
115 21:06:13.887268 progress 100 % (10 MB)
116 21:06:13.898491 10 MB downloaded in 1.71 s (6.38 MB/s)
117 21:06:13.899082 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:06:13.899912 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:06:13.900659 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:06:13.901276 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:06:13.901828 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:06:13.902382 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:06:13.903428 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj
125 21:06:13.904402 makedir: /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin
126 21:06:13.905111 makedir: /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/tests
127 21:06:13.905788 makedir: /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/results
128 21:06:13.906450 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-add-keys
129 21:06:13.907465 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-add-sources
130 21:06:13.908512 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-background-process-start
131 21:06:13.909601 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-background-process-stop
132 21:06:13.910669 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-common-functions
133 21:06:13.911657 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-echo-ipv4
134 21:06:13.912690 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-install-packages
135 21:06:13.913671 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-installed-packages
136 21:06:13.914640 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-os-build
137 21:06:13.915616 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-probe-channel
138 21:06:13.916646 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-probe-ip
139 21:06:13.917683 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-target-ip
140 21:06:13.918705 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-target-mac
141 21:06:13.919721 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-target-storage
142 21:06:13.920782 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-test-case
143 21:06:13.921890 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-test-event
144 21:06:13.922894 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-test-feedback
145 21:06:13.923874 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-test-raise
146 21:06:13.924896 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-test-reference
147 21:06:13.925885 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-test-runner
148 21:06:13.926868 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-test-set
149 21:06:13.927841 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-test-shell
150 21:06:13.928891 Updating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-install-packages (oe)
151 21:06:13.929982 Updating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/bin/lava-installed-packages (oe)
152 21:06:13.930908 Creating /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/environment
153 21:06:13.931708 LAVA metadata
154 21:06:13.932294 - LAVA_JOB_ID=794744
155 21:06:13.932771 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:06:13.933493 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:06:13.935451 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:06:13.936157 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:06:13.936593 skipped lava-vland-overlay
160 21:06:13.937084 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:06:13.937590 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:06:13.938017 skipped lava-multinode-overlay
163 21:06:13.938497 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:06:13.938993 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:06:13.939472 Loading test definitions
166 21:06:13.940038 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:06:13.940293 Using /lava-794744 at stage 0
168 21:06:13.941551 uuid=794744_1.5.2.4.1 testdef=None
169 21:06:13.941906 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:06:13.942182 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:06:13.944041 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:06:13.944882 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:06:13.947198 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:06:13.948097 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:06:13.950331 runner path: /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/0/tests/0_dmesg test_uuid 794744_1.5.2.4.1
178 21:06:13.950937 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:06:13.951745 Creating lava-test-runner.conf files
181 21:06:13.951951 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/794744/lava-overlay-rvjykcwj/lava-794744/0 for stage 0
182 21:06:13.952331 - 0_dmesg
183 21:06:13.952710 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:06:13.953005 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:06:13.977603 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:06:13.978034 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:06:13.978310 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:06:13.978579 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:06:13.978846 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:06:14.899089 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:06:14.899557 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:06:14.899832 extracting modules file /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/794744/extract-overlay-ramdisk-t4he0jto/ramdisk
193 21:06:16.212919 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:06:16.213403 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:06:16.213703 [common] Applying overlay /var/lib/lava/dispatcher/tmp/794744/compress-overlay-numdqc80/overlay-1.5.2.5.tar.gz to ramdisk
196 21:06:16.213947 [common] Applying overlay /var/lib/lava/dispatcher/tmp/794744/compress-overlay-numdqc80/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/794744/extract-overlay-ramdisk-t4he0jto/ramdisk
197 21:06:16.244023 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:06:16.244420 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:06:16.244687 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:06:16.244911 Converting downloaded kernel to a uImage
201 21:06:16.245211 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/kernel/Image /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/kernel/uImage
202 21:06:16.704175 output: Image Name:
203 21:06:16.704632 output: Created: Wed Oct 2 21:06:16 2024
204 21:06:16.704848 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:06:16.705051 output: Data Size: 44136456 Bytes = 43102.01 KiB = 42.09 MiB
206 21:06:16.705254 output: Load Address: 01080000
207 21:06:16.705451 output: Entry Point: 01080000
208 21:06:16.705649 output:
209 21:06:16.705988 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 21:06:16.706256 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 21:06:16.706525 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 21:06:16.706777 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:06:16.707029 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 21:06:16.707288 Building ramdisk /var/lib/lava/dispatcher/tmp/794744/extract-overlay-ramdisk-t4he0jto/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/794744/extract-overlay-ramdisk-t4he0jto/ramdisk
215 21:06:19.067738 >> 179559 blocks
216 21:06:28.332003 Adding RAMdisk u-boot header.
217 21:06:28.332448 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/794744/extract-overlay-ramdisk-t4he0jto/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/794744/extract-overlay-ramdisk-t4he0jto/ramdisk.cpio.gz.uboot
218 21:06:28.607592 output: Image Name:
219 21:06:28.608067 output: Created: Wed Oct 2 21:06:28 2024
220 21:06:28.608539 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:06:28.609007 output: Data Size: 26113375 Bytes = 25501.34 KiB = 24.90 MiB
222 21:06:28.609458 output: Load Address: 00000000
223 21:06:28.609903 output: Entry Point: 00000000
224 21:06:28.610338 output:
225 21:06:28.611341 rename /var/lib/lava/dispatcher/tmp/794744/extract-overlay-ramdisk-t4he0jto/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/ramdisk/ramdisk.cpio.gz.uboot
226 21:06:28.612130 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 21:06:28.612742 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 21:06:28.613334 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:06:28.613847 No LXC device requested
230 21:06:28.614403 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:06:28.614972 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:06:28.615521 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:06:28.616011 Checking files for TFTP limit of 4294967296 bytes.
234 21:06:28.618947 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:06:28.619576 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:06:28.620207 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:06:28.620777 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:06:28.621339 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:06:28.621928 Using kernel file from prepare-kernel: 794744/tftp-deploy-4g8wfq9l/kernel/uImage
240 21:06:28.622610 substitutions:
241 21:06:28.623066 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:06:28.623517 - {DTB_ADDR}: 0x01070000
243 21:06:28.623958 - {DTB}: 794744/tftp-deploy-4g8wfq9l/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 21:06:28.624447 - {INITRD}: 794744/tftp-deploy-4g8wfq9l/ramdisk/ramdisk.cpio.gz.uboot
245 21:06:28.624894 - {KERNEL_ADDR}: 0x01080000
246 21:06:28.625333 - {KERNEL}: 794744/tftp-deploy-4g8wfq9l/kernel/uImage
247 21:06:28.625774 - {LAVA_MAC}: None
248 21:06:28.626259 - {PRESEED_CONFIG}: None
249 21:06:28.626698 - {PRESEED_LOCAL}: None
250 21:06:28.627133 - {RAMDISK_ADDR}: 0x08000000
251 21:06:28.627564 - {RAMDISK}: 794744/tftp-deploy-4g8wfq9l/ramdisk/ramdisk.cpio.gz.uboot
252 21:06:28.628021 - {ROOT_PART}: None
253 21:06:28.628465 - {ROOT}: None
254 21:06:28.628900 - {SERVER_IP}: 192.168.6.2
255 21:06:28.629337 - {TEE_ADDR}: 0x83000000
256 21:06:28.629770 - {TEE}: None
257 21:06:28.630202 Parsed boot commands:
258 21:06:28.630625 - setenv autoload no
259 21:06:28.631054 - setenv initrd_high 0xffffffff
260 21:06:28.631483 - setenv fdt_high 0xffffffff
261 21:06:28.631913 - dhcp
262 21:06:28.632388 - setenv serverip 192.168.6.2
263 21:06:28.632824 - tftpboot 0x01080000 794744/tftp-deploy-4g8wfq9l/kernel/uImage
264 21:06:28.633259 - tftpboot 0x08000000 794744/tftp-deploy-4g8wfq9l/ramdisk/ramdisk.cpio.gz.uboot
265 21:06:28.633697 - tftpboot 0x01070000 794744/tftp-deploy-4g8wfq9l/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 21:06:28.634128 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:06:28.634567 - bootm 0x01080000 0x08000000 0x01070000
268 21:06:28.635126 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:06:28.636832 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:06:28.637336 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 21:06:28.653138 Setting prompt string to ['lava-test: # ']
273 21:06:28.654988 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:06:28.655753 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:06:28.656480 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:06:28.657061 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:06:28.658320 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 21:06:28.695600 >> OK - accepted request
279 21:06:28.697541 Returned 0 in 0 seconds
280 21:06:28.798732 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:06:28.800857 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:06:28.801469 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:06:28.802017 Setting prompt string to ['Hit any key to stop autoboot']
285 21:06:28.802503 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:06:28.804275 Trying 192.168.56.21...
287 21:06:28.804823 Connected to conserv1.
288 21:06:28.805283 Escape character is '^]'.
289 21:06:28.805748
290 21:06:28.806216 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 21:06:28.806691
292 21:06:36.254667 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 21:06:36.255342 bl2_stage_init 0x01
294 21:06:36.255814 bl2_stage_init 0x81
295 21:06:36.260228 hw id: 0x0000 - pwm id 0x01
296 21:06:36.260725 bl2_stage_init 0xc1
297 21:06:36.261184 bl2_stage_init 0x02
298 21:06:36.261632
299 21:06:36.265831 L0:00000000
300 21:06:36.266337 L1:00000703
301 21:06:36.266807 L2:00008067
302 21:06:36.267254 L3:15000000
303 21:06:36.267691 S1:00000000
304 21:06:36.271414 B2:20282000
305 21:06:36.271892 B1:a0f83180
306 21:06:36.272359
307 21:06:36.272795 TE: 72726
308 21:06:36.273228
309 21:06:36.276905 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 21:06:36.277372
311 21:06:36.282554 Board ID = 1
312 21:06:36.283012 Set cpu clk to 24M
313 21:06:36.283440 Set clk81 to 24M
314 21:06:36.288182 Use GP1_pll as DSU clk.
315 21:06:36.288648 DSU clk: 1200 Mhz
316 21:06:36.289080 CPU clk: 1200 MHz
317 21:06:36.289513 Set clk81 to 166.6M
318 21:06:36.299361 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 21:06:36.299831 board id: 1
320 21:06:36.305516 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:06:36.316433 fw parse done
322 21:06:36.322509 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:06:36.365022 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:06:36.375887 PIEI prepare done
325 21:06:36.376450 fastboot data load
326 21:06:36.376890 fastboot data verify
327 21:06:36.381469 verify result: 266
328 21:06:36.387114 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 21:06:36.387672 LPDDR4 probe
330 21:06:36.388181 ddr clk to 1584MHz
331 21:06:36.395114 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:06:36.432366
333 21:06:36.432888 dmc_version 0001
334 21:06:36.439032 Check phy result
335 21:06:36.444962 INFO : End of CA training
336 21:06:36.445474 INFO : End of initialization
337 21:06:36.450557 INFO : Training has run successfully!
338 21:06:36.451061 Check phy result
339 21:06:36.456215 INFO : End of initialization
340 21:06:36.456730 INFO : End of read enable training
341 21:06:36.459471 INFO : End of fine write leveling
342 21:06:36.464995 INFO : End of Write leveling coarse delay
343 21:06:36.470587 INFO : Training has run successfully!
344 21:06:36.471095 Check phy result
345 21:06:36.471539 INFO : End of initialization
346 21:06:36.476281 INFO : End of read dq deskew training
347 21:06:36.481786 INFO : End of MPR read delay center optimization
348 21:06:36.482299 INFO : End of write delay center optimization
349 21:06:36.487383 INFO : End of read delay center optimization
350 21:06:36.492997 INFO : End of max read latency training
351 21:06:36.493516 INFO : Training has run successfully!
352 21:06:36.498588 1D training succeed
353 21:06:36.504545 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:06:36.552127 Check phy result
355 21:06:36.552657 INFO : End of initialization
356 21:06:36.574500 INFO : End of 2D read delay Voltage center optimization
357 21:06:36.593607 INFO : End of 2D read delay Voltage center optimization
358 21:06:36.645516 INFO : End of 2D write delay Voltage center optimization
359 21:06:36.694726 INFO : End of 2D write delay Voltage center optimization
360 21:06:36.700323 INFO : Training has run successfully!
361 21:06:36.700844
362 21:06:36.701286 channel==0
363 21:06:36.705847 RxClkDly_Margin_A0==78 ps 8
364 21:06:36.706361 TxDqDly_Margin_A0==98 ps 10
365 21:06:36.711475 RxClkDly_Margin_A1==88 ps 9
366 21:06:36.712026 TxDqDly_Margin_A1==88 ps 9
367 21:06:36.712479 TrainedVREFDQ_A0==74
368 21:06:36.717058 TrainedVREFDQ_A1==74
369 21:06:36.717583 VrefDac_Margin_A0==22
370 21:06:36.718020 DeviceVref_Margin_A0==40
371 21:06:36.722666 VrefDac_Margin_A1==23
372 21:06:36.723185 DeviceVref_Margin_A1==40
373 21:06:36.723626
374 21:06:36.724097
375 21:06:36.724534 channel==1
376 21:06:36.728341 RxClkDly_Margin_A0==78 ps 8
377 21:06:36.728890 TxDqDly_Margin_A0==98 ps 10
378 21:06:36.733863 RxClkDly_Margin_A1==88 ps 9
379 21:06:36.734419 TxDqDly_Margin_A1==88 ps 9
380 21:06:36.739522 TrainedVREFDQ_A0==78
381 21:06:36.740107 TrainedVREFDQ_A1==75
382 21:06:36.740557 VrefDac_Margin_A0==22
383 21:06:36.745085 DeviceVref_Margin_A0==36
384 21:06:36.745650 VrefDac_Margin_A1==20
385 21:06:36.750657 DeviceVref_Margin_A1==39
386 21:06:36.751209
387 21:06:36.751678 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:06:36.752159
389 21:06:36.784291 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 21:06:36.784932 2D training succeed
391 21:06:36.789868 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:06:36.795511 auto size-- 65535DDR cs0 size: 2048MB
393 21:06:36.796108 DDR cs1 size: 2048MB
394 21:06:36.801073 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:06:36.801622 cs0 DataBus test pass
396 21:06:36.806655 cs1 DataBus test pass
397 21:06:36.807194 cs0 AddrBus test pass
398 21:06:36.807663 cs1 AddrBus test pass
399 21:06:36.808144
400 21:06:36.812322 100bdlr_step_size ps== 478
401 21:06:36.812895 result report
402 21:06:36.817881 boot times 0Enable ddr reg access
403 21:06:36.823038 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:06:36.836834 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 21:06:37.491434 bl2z: ptr: 05129330, size: 00001e40
406 21:06:37.498598 0.0;M3 CHK:0;cm4_sp_mode 0
407 21:06:37.499174 MVN_1=0x00000000
408 21:06:37.499646 MVN_2=0x00000000
409 21:06:37.510049 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 21:06:37.510592 OPS=0x04
411 21:06:37.511061 ring efuse init
412 21:06:37.515686 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 21:06:37.516240 [0.017319 Inits done]
414 21:06:37.516699 secure task start!
415 21:06:37.523586 high task start!
416 21:06:37.524119 low task start!
417 21:06:37.524580 run into bl31
418 21:06:37.532170 NOTICE: BL31: v1.3(release):4fc40b1
419 21:06:37.539951 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 21:06:37.540496 NOTICE: BL31: G12A normal boot!
421 21:06:37.555442 NOTICE: BL31: BL33 decompress pass
422 21:06:37.561127 ERROR: Error initializing runtime service opteed_fast
423 21:06:40.297734 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 21:06:40.298420 bl2_stage_init 0x01
425 21:06:40.298909 bl2_stage_init 0x81
426 21:06:40.303284 hw id: 0x0000 - pwm id 0x01
427 21:06:40.303833 bl2_stage_init 0xc1
428 21:06:40.308907 bl2_stage_init 0x02
429 21:06:40.309491
430 21:06:40.309940 L0:00000000
431 21:06:40.310372 L1:00000703
432 21:06:40.310804 L2:00008067
433 21:06:40.311230 L3:15000000
434 21:06:40.314342 S1:00000000
435 21:06:40.314837 B2:20282000
436 21:06:40.315273 B1:a0f83180
437 21:06:40.315736
438 21:06:40.316234 TE: 68035
439 21:06:40.316670
440 21:06:40.319953 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 21:06:40.320660
442 21:06:40.325561 Board ID = 1
443 21:06:40.326049 Set cpu clk to 24M
444 21:06:40.326495 Set clk81 to 24M
445 21:06:40.331112 Use GP1_pll as DSU clk.
446 21:06:40.331589 DSU clk: 1200 Mhz
447 21:06:40.332105 CPU clk: 1200 MHz
448 21:06:40.336851 Set clk81 to 166.6M
449 21:06:40.342333 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 21:06:40.342885 board id: 1
451 21:06:40.349646 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 21:06:40.360305 fw parse done
453 21:06:40.366240 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 21:06:40.408885 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 21:06:40.419905 PIEI prepare done
456 21:06:40.420482 fastboot data load
457 21:06:40.420932 fastboot data verify
458 21:06:40.425433 verify result: 266
459 21:06:40.431038 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 21:06:40.431520 LPDDR4 probe
461 21:06:40.431959 ddr clk to 1584MHz
462 21:06:40.439024 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 21:06:40.476323
464 21:06:40.476907 dmc_version 0001
465 21:06:40.482940 Check phy result
466 21:06:40.488903 INFO : End of CA training
467 21:06:40.489478 INFO : End of initialization
468 21:06:40.494418 INFO : Training has run successfully!
469 21:06:40.494907 Check phy result
470 21:06:40.500045 INFO : End of initialization
471 21:06:40.500538 INFO : End of read enable training
472 21:06:40.505613 INFO : End of fine write leveling
473 21:06:40.511222 INFO : End of Write leveling coarse delay
474 21:06:40.511704 INFO : Training has run successfully!
475 21:06:40.512178 Check phy result
476 21:06:40.516849 INFO : End of initialization
477 21:06:40.517321 INFO : End of read dq deskew training
478 21:06:40.522457 INFO : End of MPR read delay center optimization
479 21:06:40.528062 INFO : End of write delay center optimization
480 21:06:40.533609 INFO : End of read delay center optimization
481 21:06:40.534093 INFO : End of max read latency training
482 21:06:40.539206 INFO : Training has run successfully!
483 21:06:40.539676 1D training succeed
484 21:06:40.548416 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 21:06:40.596062 Check phy result
486 21:06:40.596642 INFO : End of initialization
487 21:06:40.618342 INFO : End of 2D read delay Voltage center optimization
488 21:06:40.637506 INFO : End of 2D read delay Voltage center optimization
489 21:06:40.689437 INFO : End of 2D write delay Voltage center optimization
490 21:06:40.738607 INFO : End of 2D write delay Voltage center optimization
491 21:06:40.744191 INFO : Training has run successfully!
492 21:06:40.744674
493 21:06:40.745115 channel==0
494 21:06:40.749742 RxClkDly_Margin_A0==69 ps 7
495 21:06:40.750212 TxDqDly_Margin_A0==88 ps 9
496 21:06:40.755347 RxClkDly_Margin_A1==88 ps 9
497 21:06:40.755813 TxDqDly_Margin_A1==98 ps 10
498 21:06:40.756306 TrainedVREFDQ_A0==74
499 21:06:40.760947 TrainedVREFDQ_A1==75
500 21:06:40.761468 VrefDac_Margin_A0==23
501 21:06:40.761903 DeviceVref_Margin_A0==40
502 21:06:40.766546 VrefDac_Margin_A1==23
503 21:06:40.767065 DeviceVref_Margin_A1==39
504 21:06:40.767506
505 21:06:40.767941
506 21:06:40.768414 channel==1
507 21:06:40.772113 RxClkDly_Margin_A0==78 ps 8
508 21:06:40.772585 TxDqDly_Margin_A0==98 ps 10
509 21:06:40.777721 RxClkDly_Margin_A1==78 ps 8
510 21:06:40.778200 TxDqDly_Margin_A1==78 ps 8
511 21:06:40.783315 TrainedVREFDQ_A0==75
512 21:06:40.783786 TrainedVREFDQ_A1==75
513 21:06:40.784263 VrefDac_Margin_A0==22
514 21:06:40.788981 DeviceVref_Margin_A0==39
515 21:06:40.789530 VrefDac_Margin_A1==22
516 21:06:40.794536 DeviceVref_Margin_A1==38
517 21:06:40.795017
518 21:06:40.795456 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 21:06:40.795891
520 21:06:40.828106 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 21:06:40.828684 2D training succeed
522 21:06:40.833717 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 21:06:40.839306 auto size-- 65535DDR cs0 size: 2048MB
524 21:06:40.839783 DDR cs1 size: 2048MB
525 21:06:40.844895 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 21:06:40.845369 cs0 DataBus test pass
527 21:06:40.850504 cs1 DataBus test pass
528 21:06:40.850974 cs0 AddrBus test pass
529 21:06:40.851411 cs1 AddrBus test pass
530 21:06:40.851837
531 21:06:40.856138 100bdlr_step_size ps== 478
532 21:06:40.856625 result report
533 21:06:40.861716 boot times 0Enable ddr reg access
534 21:06:40.866921 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 21:06:40.880723 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 21:06:41.536009 bl2z: ptr: 05129330, size: 00001e40
537 21:06:41.542690 0.0;M3 CHK:0;cm4_sp_mode 0
538 21:06:41.543253 MVN_1=0x00000000
539 21:06:41.543724 MVN_2=0x00000000
540 21:06:41.554355 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 21:06:41.554902 OPS=0x04
542 21:06:41.555380 ring efuse init
543 21:06:41.559908 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 21:06:41.560448 [0.017310 Inits done]
545 21:06:41.560906 secure task start!
546 21:06:41.567048 high task start!
547 21:06:41.567546 low task start!
548 21:06:41.568033 run into bl31
549 21:06:41.575712 NOTICE: BL31: v1.3(release):4fc40b1
550 21:06:41.583460 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 21:06:41.584052 NOTICE: BL31: G12A normal boot!
552 21:06:41.598914 NOTICE: BL31: BL33 decompress pass
553 21:06:41.604649 ERROR: Error initializing runtime service opteed_fast
554 21:06:42.999173 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 21:06:42.999831 bl2_stage_init 0x01
556 21:06:43.000369 bl2_stage_init 0x81
557 21:06:43.005057 hw id: 0x0000 - pwm id 0x01
558 21:06:43.005665 bl2_stage_init 0xc1
559 21:06:43.009110 bl2_stage_init 0x02
560 21:06:43.009731
561 21:06:43.010227 L0:00000000
562 21:06:43.010724 L1:00000703
563 21:06:43.011186 L2:00008067
564 21:06:43.014484 L3:15000000
565 21:06:43.015017 S1:00000000
566 21:06:43.015497 B2:20282000
567 21:06:43.016101 B1:a0f83180
568 21:06:43.016619
569 21:06:43.017077 TE: 69110
570 21:06:43.020097
571 21:06:43.025830 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 21:06:43.026481
573 21:06:43.026916 Board ID = 1
574 21:06:43.027315 Set cpu clk to 24M
575 21:06:43.031493 Set clk81 to 24M
576 21:06:43.032161 Use GP1_pll as DSU clk.
577 21:06:43.032788 DSU clk: 1200 Mhz
578 21:06:43.033251 CPU clk: 1200 MHz
579 21:06:43.037397 Set clk81 to 166.6M
580 21:06:43.042970 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 21:06:43.043456 board id: 1
582 21:06:43.051172 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 21:06:43.062033 fw parse done
584 21:06:43.068084 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 21:06:43.111220 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 21:06:43.122396 PIEI prepare done
587 21:06:43.122869 fastboot data load
588 21:06:43.123278 fastboot data verify
589 21:06:43.128413 verify result: 266
590 21:06:43.133682 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 21:06:43.134166 LPDDR4 probe
592 21:06:43.134560 ddr clk to 1584MHz
593 21:06:43.141647 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 21:06:43.179446
595 21:06:43.180116 dmc_version 0001
596 21:06:43.186308 Check phy result
597 21:06:43.192182 INFO : End of CA training
598 21:06:43.192667 INFO : End of initialization
599 21:06:43.199078 INFO : Training has run successfully!
600 21:06:43.199551 Check phy result
601 21:06:43.203737 INFO : End of initialization
602 21:06:43.204224 INFO : End of read enable training
603 21:06:43.206748 INFO : End of fine write leveling
604 21:06:43.212338 INFO : End of Write leveling coarse delay
605 21:06:43.218612 INFO : Training has run successfully!
606 21:06:43.219075 Check phy result
607 21:06:43.219475 INFO : End of initialization
608 21:06:43.223827 INFO : End of read dq deskew training
609 21:06:43.226743 INFO : End of MPR read delay center optimization
610 21:06:43.232358 INFO : End of write delay center optimization
611 21:06:43.238138 INFO : End of read delay center optimization
612 21:06:43.238597 INFO : End of max read latency training
613 21:06:43.244238 INFO : Training has run successfully!
614 21:06:43.244687 1D training succeed
615 21:06:43.252150 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 21:06:43.300196 Check phy result
617 21:06:43.300808 INFO : End of initialization
618 21:06:43.327609 INFO : End of 2D read delay Voltage center optimization
619 21:06:43.351592 INFO : End of 2D read delay Voltage center optimization
620 21:06:43.408424 INFO : End of 2D write delay Voltage center optimization
621 21:06:43.462485 INFO : End of 2D write delay Voltage center optimization
622 21:06:43.467918 INFO : Training has run successfully!
623 21:06:43.468400
624 21:06:43.468801 channel==0
625 21:06:43.473522 RxClkDly_Margin_A0==78 ps 8
626 21:06:43.474012 TxDqDly_Margin_A0==88 ps 9
627 21:06:43.476896 RxClkDly_Margin_A1==88 ps 9
628 21:06:43.477337 TxDqDly_Margin_A1==98 ps 10
629 21:06:43.482468 TrainedVREFDQ_A0==74
630 21:06:43.482935 TrainedVREFDQ_A1==75
631 21:06:43.483352 VrefDac_Margin_A0==23
632 21:06:43.488068 DeviceVref_Margin_A0==40
633 21:06:43.488507 VrefDac_Margin_A1==23
634 21:06:43.493574 DeviceVref_Margin_A1==39
635 21:06:43.494005
636 21:06:43.494407
637 21:06:43.494801 channel==1
638 21:06:43.495191 RxClkDly_Margin_A0==78 ps 8
639 21:06:43.497079 TxDqDly_Margin_A0==98 ps 10
640 21:06:43.502654 RxClkDly_Margin_A1==78 ps 8
641 21:06:43.503079 TxDqDly_Margin_A1==88 ps 9
642 21:06:43.503475 TrainedVREFDQ_A0==78
643 21:06:43.508442 TrainedVREFDQ_A1==75
644 21:06:43.508912 VrefDac_Margin_A0==22
645 21:06:43.513968 DeviceVref_Margin_A0==36
646 21:06:43.514401 VrefDac_Margin_A1==22
647 21:06:43.514793 DeviceVref_Margin_A1==39
648 21:06:43.515181
649 21:06:43.522853 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 21:06:43.523291
651 21:06:43.548915 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000019 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000019 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 21:06:43.554501 2D training succeed
653 21:06:43.557985 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 21:06:43.563352 auto size-- 65535DDR cs0 size: 2048MB
655 21:06:43.563776 DDR cs1 size: 2048MB
656 21:06:43.568934 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 21:06:43.569356 cs0 DataBus test pass
658 21:06:43.574534 cs1 DataBus test pass
659 21:06:43.574952 cs0 AddrBus test pass
660 21:06:43.575342 cs1 AddrBus test pass
661 21:06:43.575727
662 21:06:43.580212 100bdlr_step_size ps== 478
663 21:06:43.580691 result report
664 21:06:43.581114 boot times 0Enable ddr reg access
665 21:06:43.590555 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 21:06:43.604439 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 21:06:44.264039 bl2z: ptr: 05129330, size: 00001e40
668 21:06:44.272667 0.0;M3 CHK:0;cm4_sp_mode 0
669 21:06:44.273186 MVN_1=0x00000000
670 21:06:44.273580 MVN_2=0x00000000
671 21:06:44.285677 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 21:06:44.286287 OPS=0x04
673 21:06:44.286694 ring efuse init
674 21:06:44.289872 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 21:06:44.290489 [0.017354 Inits done]
676 21:06:44.290895 secure task start!
677 21:06:44.297041 high task start!
678 21:06:44.297342 low task start!
679 21:06:44.297546 run into bl31
680 21:06:44.305680 NOTICE: BL31: v1.3(release):4fc40b1
681 21:06:44.313414 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 21:06:44.313712 NOTICE: BL31: G12A normal boot!
683 21:06:44.329049 NOTICE: BL31: BL33 decompress pass
684 21:06:44.334721 ERROR: Error initializing runtime service opteed_fast
685 21:06:45.130150
686 21:06:45.130751
687 21:06:45.135546 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 21:06:45.136035
689 21:06:45.139019 Model: Libre Computer AML-S905D3-CC Solitude
690 21:06:45.285969 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 21:06:45.301386 DRAM: 2 GiB (effective 3.8 GiB)
692 21:06:45.402313 Core: 406 devices, 33 uclasses, devicetree: separate
693 21:06:45.408225 WDT: Not starting watchdog@f0d0
694 21:06:45.433243 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 21:06:45.445555 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 21:06:45.450596 ** Bad device specification mmc 0 **
697 21:06:45.460565 Card did not respond to voltage select! : -110
698 21:06:45.468225 ** Bad device specification mmc 0 **
699 21:06:45.468657 Couldn't find partition mmc 0
700 21:06:45.476574 Card did not respond to voltage select! : -110
701 21:06:45.482050 ** Bad device specification mmc 0 **
702 21:06:45.482477 Couldn't find partition mmc 0
703 21:06:45.487111 Error: could not access storage.
704 21:06:45.784664 Net: eth0: ethernet@ff3f0000
705 21:06:45.785174 starting USB...
706 21:06:46.029224 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 21:06:46.029755 Starting the controller
708 21:06:46.036203 USB XHCI 1.10
709 21:06:47.590433 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 21:06:47.598786 scanning usb for storage devices... 0 Storage Device(s) found
712 21:06:47.650268 Hit any key to stop autoboot: 1
713 21:06:47.651046 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 21:06:47.651688 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 21:06:47.652218 Setting prompt string to ['=>']
716 21:06:47.652715 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 21:06:47.664801 0
718 21:06:47.665652 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 21:06:47.766826 => setenv autoload no
721 21:06:47.767652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 21:06:47.772469 setenv autoload no
724 21:06:47.873892 => setenv initrd_high 0xffffffff
725 21:06:47.874692 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 21:06:47.878829 setenv initrd_high 0xffffffff
728 21:06:47.980202 => setenv fdt_high 0xffffffff
729 21:06:47.981028 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 21:06:47.985157 setenv fdt_high 0xffffffff
732 21:06:48.086582 => dhcp
733 21:06:48.087400 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 21:06:48.090501 dhcp
735 21:06:48.647120 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 21:06:48.647739 Speed: 1000, full duplex
737 21:06:48.648224 BOOTP broadcast 1
738 21:06:48.895158 BOOTP broadcast 2
739 21:06:49.396227 BOOTP broadcast 3
740 21:06:50.397215 BOOTP broadcast 4
741 21:06:52.398191 BOOTP broadcast 5
742 21:06:52.411811 DHCP client bound to address 192.168.6.12 (3764 ms)
744 21:06:52.513285 => setenv serverip 192.168.6.2
745 21:06:52.514159 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 21:06:52.518539 setenv serverip 192.168.6.2
748 21:06:52.619959 => tftpboot 0x01080000 794744/tftp-deploy-4g8wfq9l/kernel/uImage
749 21:06:52.620887 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 21:06:52.627450 tftpboot 0x01080000 794744/tftp-deploy-4g8wfq9l/kernel/uImage
751 21:06:52.627938 Speed: 1000, full duplex
752 21:06:52.628401 Using ethernet@ff3f0000 device
753 21:06:52.632934 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 21:06:52.638504 Filename '794744/tftp-deploy-4g8wfq9l/kernel/uImage'.
755 21:06:52.642377 Load address: 0x1080000
756 21:06:55.883156 Loading: *################################################## 42.1 MiB
757 21:06:55.883797 13 MiB/s
758 21:06:55.884293 done
759 21:06:55.887456 Bytes transferred = 44136520 (2a17848 hex)
761 21:06:55.988977 => tftpboot 0x08000000 794744/tftp-deploy-4g8wfq9l/ramdisk/ramdisk.cpio.gz.uboot
762 21:06:55.989660 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
763 21:06:55.996463 tftpboot 0x08000000 794744/tftp-deploy-4g8wfq9l/ramdisk/ramdisk.cpio.gz.uboot
764 21:06:55.996898 Speed: 1000, full duplex
765 21:06:55.997294 Using ethernet@ff3f0000 device
766 21:06:56.001998 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 21:06:56.011816 Filename '794744/tftp-deploy-4g8wfq9l/ramdisk/ramdisk.cpio.gz.uboot'.
768 21:06:56.012240 Load address: 0x8000000
769 21:07:02.947744 Loading: *################################################T # UDP wrong checksum 00000005 0000f4bd
770 21:07:07.948179 T UDP wrong checksum 00000005 0000f4bd
771 21:07:09.269474 UDP wrong checksum 00000005 0000fdf9
772 21:07:17.950281 T T UDP wrong checksum 00000005 0000f4bd
773 21:07:37.952434 T T T UDP wrong checksum 00000005 0000f4bd
774 21:07:38.170920 T UDP wrong checksum 000000ff 0000122b
775 21:07:38.343236 UDP wrong checksum 000000ff 0000a11d
776 21:07:46.263872 T UDP wrong checksum 000000ff 00008b38
777 21:07:46.294445 UDP wrong checksum 000000ff 0000142b
778 21:07:52.957202 T
779 21:07:52.957884 Retry count exceeded; starting again
781 21:07:52.959395 end: 2.4.3 bootloader-commands (duration 00:01:05) [common]
784 21:07:52.961466 end: 2.4 uboot-commands (duration 00:01:24) [common]
786 21:07:52.962945 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
788 21:07:52.964123 end: 2 uboot-action (duration 00:01:24) [common]
790 21:07:52.965849 Cleaning after the job
791 21:07:52.966474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/ramdisk
792 21:07:52.967916 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/kernel
793 21:07:53.017482 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/dtb
794 21:07:53.018402 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794744/tftp-deploy-4g8wfq9l/modules
795 21:07:53.039898 start: 4.1 power-off (timeout 00:00:30) [common]
796 21:07:53.040776 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
797 21:07:53.075178 >> OK - accepted request
798 21:07:53.077390 Returned 0 in 0 seconds
799 21:07:53.178161 end: 4.1 power-off (duration 00:00:00) [common]
801 21:07:53.179119 start: 4.2 read-feedback (timeout 00:10:00) [common]
802 21:07:53.179769 Listened to connection for namespace 'common' for up to 1s
803 21:07:54.180210 Finalising connection for namespace 'common'
804 21:07:54.181078 Disconnecting from shell: Finalise
805 21:07:54.181458 =>
806 21:07:54.283083 end: 4.2 read-feedback (duration 00:00:01) [common]
807 21:07:54.283776 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/794744
808 21:07:55.274449 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/794744
809 21:07:55.275063 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.