Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:19:44.708437 lava-dispatcher, installed at version: 2024.01
2 21:19:44.709249 start: 0 validate
3 21:19:44.709743 Start time: 2024-10-02 21:19:44.709713+00:00 (UTC)
4 21:19:44.710282 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:19:44.710837 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:19:44.752018 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:19:44.752591 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 21:19:44.782310 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:19:44.782927 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:19:45.830418 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:19:45.830939 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 21:19:45.872434 validate duration: 1.16
14 21:19:45.873297 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:19:45.873636 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:19:45.873939 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:19:45.874515 Not decompressing ramdisk as can be used compressed.
18 21:19:45.874954 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:19:45.875195 saving as /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/ramdisk/rootfs.cpio.gz
20 21:19:45.875455 total size: 8181887 (7 MB)
21 21:19:45.912416 progress 0 % (0 MB)
22 21:19:45.926685 progress 5 % (0 MB)
23 21:19:45.940268 progress 10 % (0 MB)
24 21:19:45.947693 progress 15 % (1 MB)
25 21:19:45.954423 progress 20 % (1 MB)
26 21:19:45.961893 progress 25 % (1 MB)
27 21:19:45.968676 progress 30 % (2 MB)
28 21:19:45.975700 progress 35 % (2 MB)
29 21:19:45.982172 progress 40 % (3 MB)
30 21:19:45.989416 progress 45 % (3 MB)
31 21:19:45.996377 progress 50 % (3 MB)
32 21:19:46.003642 progress 55 % (4 MB)
33 21:19:46.010355 progress 60 % (4 MB)
34 21:19:46.017642 progress 65 % (5 MB)
35 21:19:46.024304 progress 70 % (5 MB)
36 21:19:46.031603 progress 75 % (5 MB)
37 21:19:46.038491 progress 80 % (6 MB)
38 21:19:46.047142 progress 85 % (6 MB)
39 21:19:46.052922 progress 90 % (7 MB)
40 21:19:46.058849 progress 95 % (7 MB)
41 21:19:46.063877 progress 100 % (7 MB)
42 21:19:46.064617 7 MB downloaded in 0.19 s (41.25 MB/s)
43 21:19:46.065214 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:19:46.066167 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:19:46.066497 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:19:46.066794 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:19:46.067280 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 21:19:46.067555 saving as /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/kernel/Image
50 21:19:46.067790 total size: 66023936 (62 MB)
51 21:19:46.068043 No compression specified
52 21:19:46.108418 progress 0 % (0 MB)
53 21:19:46.150756 progress 5 % (3 MB)
54 21:19:46.192744 progress 10 % (6 MB)
55 21:19:46.235523 progress 15 % (9 MB)
56 21:19:46.277388 progress 20 % (12 MB)
57 21:19:46.319717 progress 25 % (15 MB)
58 21:19:46.363724 progress 30 % (18 MB)
59 21:19:46.404805 progress 35 % (22 MB)
60 21:19:46.446520 progress 40 % (25 MB)
61 21:19:46.488135 progress 45 % (28 MB)
62 21:19:46.529737 progress 50 % (31 MB)
63 21:19:46.571736 progress 55 % (34 MB)
64 21:19:46.612638 progress 60 % (37 MB)
65 21:19:46.654481 progress 65 % (40 MB)
66 21:19:46.695131 progress 70 % (44 MB)
67 21:19:46.736352 progress 75 % (47 MB)
68 21:19:46.777712 progress 80 % (50 MB)
69 21:19:46.818651 progress 85 % (53 MB)
70 21:19:46.860629 progress 90 % (56 MB)
71 21:19:46.901748 progress 95 % (59 MB)
72 21:19:46.942844 progress 100 % (62 MB)
73 21:19:46.943630 62 MB downloaded in 0.88 s (71.89 MB/s)
74 21:19:46.944148 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:19:46.944983 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:19:46.945264 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:19:46.945545 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:19:46.946005 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:19:46.946294 saving as /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:19:46.946503 total size: 54703 (0 MB)
82 21:19:46.946713 No compression specified
83 21:19:46.985935 progress 59 % (0 MB)
84 21:19:46.986912 progress 100 % (0 MB)
85 21:19:46.987604 0 MB downloaded in 0.04 s (1.27 MB/s)
86 21:19:46.988429 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:19:46.989488 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:19:46.989858 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:19:46.990252 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:19:46.990837 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 21:19:46.991165 saving as /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/modules/modules.tar
93 21:19:46.991437 total size: 16280760 (15 MB)
94 21:19:46.991710 Using unxz to decompress xz
95 21:19:47.031867 progress 0 % (0 MB)
96 21:19:47.134534 progress 5 % (0 MB)
97 21:19:47.254498 progress 10 % (1 MB)
98 21:19:47.370245 progress 15 % (2 MB)
99 21:19:47.488772 progress 20 % (3 MB)
100 21:19:47.602739 progress 25 % (3 MB)
101 21:19:47.717370 progress 30 % (4 MB)
102 21:19:47.825637 progress 35 % (5 MB)
103 21:19:47.937808 progress 40 % (6 MB)
104 21:19:48.053519 progress 45 % (7 MB)
105 21:19:48.165377 progress 50 % (7 MB)
106 21:19:48.279544 progress 55 % (8 MB)
107 21:19:48.396109 progress 60 % (9 MB)
108 21:19:48.508011 progress 65 % (10 MB)
109 21:19:48.627651 progress 70 % (10 MB)
110 21:19:48.767198 progress 75 % (11 MB)
111 21:19:48.903106 progress 80 % (12 MB)
112 21:19:49.015043 progress 85 % (13 MB)
113 21:19:49.132158 progress 90 % (14 MB)
114 21:19:49.238521 progress 95 % (14 MB)
115 21:19:49.353870 progress 100 % (15 MB)
116 21:19:49.367928 15 MB downloaded in 2.38 s (6.53 MB/s)
117 21:19:49.368833 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:19:49.370420 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:19:49.370936 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:19:49.371446 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:19:49.371926 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:19:49.372464 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:19:49.373562 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw
125 21:19:49.374419 makedir: /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin
126 21:19:49.375049 makedir: /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/tests
127 21:19:49.375652 makedir: /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/results
128 21:19:49.376292 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-add-keys
129 21:19:49.377243 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-add-sources
130 21:19:49.378159 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-background-process-start
131 21:19:49.379122 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-background-process-stop
132 21:19:49.380129 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-common-functions
133 21:19:49.381048 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-echo-ipv4
134 21:19:49.381944 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-install-packages
135 21:19:49.382866 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-installed-packages
136 21:19:49.383772 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-os-build
137 21:19:49.384713 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-probe-channel
138 21:19:49.385632 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-probe-ip
139 21:19:49.386536 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-target-ip
140 21:19:49.387428 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-target-mac
141 21:19:49.388367 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-target-storage
142 21:19:49.389297 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-test-case
143 21:19:49.390268 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-test-event
144 21:19:49.391160 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-test-feedback
145 21:19:49.392114 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-test-raise
146 21:19:49.393025 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-test-reference
147 21:19:49.393963 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-test-runner
148 21:19:49.394874 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-test-set
149 21:19:49.395760 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-test-shell
150 21:19:49.396719 Updating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-install-packages (oe)
151 21:19:49.397680 Updating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/bin/lava-installed-packages (oe)
152 21:19:49.398495 Creating /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/environment
153 21:19:49.399213 LAVA metadata
154 21:19:49.399691 - LAVA_JOB_ID=794921
155 21:19:49.400176 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:19:49.400843 start: 1.5.2.1 ssh-authorize (timeout 00:09:56) [common]
157 21:19:49.402762 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:19:49.403355 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:56) [common]
159 21:19:49.403762 skipped lava-vland-overlay
160 21:19:49.404294 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:19:49.404808 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:56) [common]
162 21:19:49.405233 skipped lava-multinode-overlay
163 21:19:49.405713 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:19:49.406207 start: 1.5.2.4 test-definition (timeout 00:09:56) [common]
165 21:19:49.406682 Loading test definitions
166 21:19:49.407218 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:56) [common]
167 21:19:49.407649 Using /lava-794921 at stage 0
168 21:19:49.409980 uuid=794921_1.5.2.4.1 testdef=None
169 21:19:49.410555 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:19:49.411069 start: 1.5.2.4.2 test-overlay (timeout 00:09:56) [common]
171 21:19:49.414480 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:19:49.416054 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:56) [common]
174 21:19:49.418404 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:19:49.419267 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:56) [common]
177 21:19:49.421544 runner path: /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/0/tests/0_dmesg test_uuid 794921_1.5.2.4.1
178 21:19:49.422151 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:19:49.422928 Creating lava-test-runner.conf files
181 21:19:49.423132 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/794921/lava-overlay-p71nf5yw/lava-794921/0 for stage 0
182 21:19:49.423481 - 0_dmesg
183 21:19:49.423845 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:19:49.424165 start: 1.5.2.5 compress-overlay (timeout 00:09:56) [common]
185 21:19:49.448240 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:19:49.448649 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 21:19:49.448914 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:19:49.449180 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:19:49.449443 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 21:19:50.382803 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:19:50.383284 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
192 21:19:50.383528 extracting modules file /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/794921/extract-overlay-ramdisk-pxqabqk5/ramdisk
193 21:19:52.388447 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 21:19:52.389096 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
195 21:19:52.389500 [common] Applying overlay /var/lib/lava/dispatcher/tmp/794921/compress-overlay-9dqf0lt6/overlay-1.5.2.5.tar.gz to ramdisk
196 21:19:52.389805 [common] Applying overlay /var/lib/lava/dispatcher/tmp/794921/compress-overlay-9dqf0lt6/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/794921/extract-overlay-ramdisk-pxqabqk5/ramdisk
197 21:19:52.432255 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:19:52.432799 start: 1.5.6 prepare-kernel (timeout 00:09:53) [common]
199 21:19:52.433194 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:53) [common]
200 21:19:52.433493 Converting downloaded kernel to a uImage
201 21:19:52.433897 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/kernel/Image /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/kernel/uImage
202 21:19:53.112897 output: Image Name:
203 21:19:53.113288 output: Created: Wed Oct 2 21:19:52 2024
204 21:19:53.113497 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:19:53.113700 output: Data Size: 66023936 Bytes = 64476.50 KiB = 62.97 MiB
206 21:19:53.113901 output: Load Address: 01080000
207 21:19:53.114104 output: Entry Point: 01080000
208 21:19:53.114302 output:
209 21:19:53.114632 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 21:19:53.114894 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 21:19:53.115161 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 21:19:53.115411 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:19:53.115664 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 21:19:53.115911 Building ramdisk /var/lib/lava/dispatcher/tmp/794921/extract-overlay-ramdisk-pxqabqk5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/794921/extract-overlay-ramdisk-pxqabqk5/ramdisk
215 21:19:56.474558 >> 256019 blocks
216 21:20:07.588931 Adding RAMdisk u-boot header.
217 21:20:07.589368 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/794921/extract-overlay-ramdisk-pxqabqk5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/794921/extract-overlay-ramdisk-pxqabqk5/ramdisk.cpio.gz.uboot
218 21:20:07.941420 output: Image Name:
219 21:20:07.941839 output: Created: Wed Oct 2 21:20:07 2024
220 21:20:07.942048 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:20:07.942252 output: Data Size: 33807247 Bytes = 33014.89 KiB = 32.24 MiB
222 21:20:07.942453 output: Load Address: 00000000
223 21:20:07.942651 output: Entry Point: 00000000
224 21:20:07.942846 output:
225 21:20:07.943469 rename /var/lib/lava/dispatcher/tmp/794921/extract-overlay-ramdisk-pxqabqk5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/ramdisk/ramdisk.cpio.gz.uboot
226 21:20:07.943877 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 21:20:07.944453 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
228 21:20:07.945046 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
229 21:20:07.945538 No LXC device requested
230 21:20:07.946074 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:20:07.946620 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
232 21:20:07.947149 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:20:07.947592 Checking files for TFTP limit of 4294967296 bytes.
234 21:20:07.950511 end: 1 tftp-deploy (duration 00:00:22) [common]
235 21:20:07.951134 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:20:07.951701 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:20:07.952277 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:20:07.952830 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:20:07.953407 Using kernel file from prepare-kernel: 794921/tftp-deploy-mzmoq3zp/kernel/uImage
240 21:20:07.954086 substitutions:
241 21:20:07.954533 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:20:07.954972 - {DTB_ADDR}: 0x01070000
243 21:20:07.955407 - {DTB}: 794921/tftp-deploy-mzmoq3zp/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:20:07.955843 - {INITRD}: 794921/tftp-deploy-mzmoq3zp/ramdisk/ramdisk.cpio.gz.uboot
245 21:20:07.956309 - {KERNEL_ADDR}: 0x01080000
246 21:20:07.956744 - {KERNEL}: 794921/tftp-deploy-mzmoq3zp/kernel/uImage
247 21:20:07.957177 - {LAVA_MAC}: None
248 21:20:07.957646 - {PRESEED_CONFIG}: None
249 21:20:07.958078 - {PRESEED_LOCAL}: None
250 21:20:07.958506 - {RAMDISK_ADDR}: 0x08000000
251 21:20:07.958929 - {RAMDISK}: 794921/tftp-deploy-mzmoq3zp/ramdisk/ramdisk.cpio.gz.uboot
252 21:20:07.959357 - {ROOT_PART}: None
253 21:20:07.959784 - {ROOT}: None
254 21:20:07.960246 - {SERVER_IP}: 192.168.6.2
255 21:20:07.960682 - {TEE_ADDR}: 0x83000000
256 21:20:07.961111 - {TEE}: None
257 21:20:07.961537 Parsed boot commands:
258 21:20:07.961947 - setenv autoload no
259 21:20:07.962369 - setenv initrd_high 0xffffffff
260 21:20:07.962792 - setenv fdt_high 0xffffffff
261 21:20:07.963212 - dhcp
262 21:20:07.963634 - setenv serverip 192.168.6.2
263 21:20:07.964081 - tftpboot 0x01080000 794921/tftp-deploy-mzmoq3zp/kernel/uImage
264 21:20:07.964510 - tftpboot 0x08000000 794921/tftp-deploy-mzmoq3zp/ramdisk/ramdisk.cpio.gz.uboot
265 21:20:07.964933 - tftpboot 0x01070000 794921/tftp-deploy-mzmoq3zp/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:20:07.965358 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:20:07.965788 - bootm 0x01080000 0x08000000 0x01070000
268 21:20:07.966325 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:20:07.967939 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:20:07.968449 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:20:07.983831 Setting prompt string to ['lava-test: # ']
273 21:20:07.985448 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:20:07.986093 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:20:07.986675 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:20:07.987238 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:20:07.988521 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:20:08.027803 >> OK - accepted request
279 21:20:08.030038 Returned 0 in 0 seconds
280 21:20:08.131194 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:20:08.132944 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:20:08.133562 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:20:08.134102 Setting prompt string to ['Hit any key to stop autoboot']
285 21:20:08.134594 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:20:08.136356 Trying 192.168.56.21...
287 21:20:08.136872 Connected to conserv1.
288 21:20:08.137316 Escape character is '^]'.
289 21:20:08.137766
290 21:20:08.138226 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 21:20:08.138685
292 21:20:19.579619 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 21:20:19.580338 bl2_stage_init 0x01
294 21:20:19.580822 bl2_stage_init 0x81
295 21:20:19.585511 hw id: 0x0000 - pwm id 0x01
296 21:20:19.586038 bl2_stage_init 0xc1
297 21:20:19.586482 bl2_stage_init 0x02
298 21:20:19.586926
299 21:20:19.590659 L0:00000000
300 21:20:19.591149 L1:20000703
301 21:20:19.591583 L2:00008067
302 21:20:19.592044 L3:14000000
303 21:20:19.593431 B2:00402000
304 21:20:19.593893 B1:e0f83180
305 21:20:19.594321
306 21:20:19.594748 TE: 58124
307 21:20:19.595172
308 21:20:19.604632 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 21:20:19.605121
310 21:20:19.605553 Board ID = 1
311 21:20:19.605979 Set A53 clk to 24M
312 21:20:19.606404 Set A73 clk to 24M
313 21:20:19.610210 Set clk81 to 24M
314 21:20:19.610669 A53 clk: 1200 MHz
315 21:20:19.611097 A73 clk: 1200 MHz
316 21:20:19.613816 CLK81: 166.6M
317 21:20:19.614271 smccc: 00012a92
318 21:20:19.619111 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 21:20:19.624708 board id: 1
320 21:20:19.630014 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:20:19.640699 fw parse done
322 21:20:19.645596 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:20:19.689247 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:20:19.700296 PIEI prepare done
325 21:20:19.700595 fastboot data load
326 21:20:19.700818 fastboot data verify
327 21:20:19.705683 verify result: 266
328 21:20:19.711329 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 21:20:19.711573 LPDDR4 probe
330 21:20:19.711768 ddr clk to 1584MHz
331 21:20:19.719325 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:20:19.756761
333 21:20:19.757250 dmc_version 0001
334 21:20:19.763241 Check phy result
335 21:20:19.769096 INFO : End of CA training
336 21:20:19.769566 INFO : End of initialization
337 21:20:19.774808 INFO : Training has run successfully!
338 21:20:19.775275 Check phy result
339 21:20:19.780327 INFO : End of initialization
340 21:20:19.780794 INFO : End of read enable training
341 21:20:19.783715 INFO : End of fine write leveling
342 21:20:19.789260 INFO : End of Write leveling coarse delay
343 21:20:19.794826 INFO : Training has run successfully!
344 21:20:19.795285 Check phy result
345 21:20:19.795715 INFO : End of initialization
346 21:20:19.800452 INFO : End of read dq deskew training
347 21:20:19.806035 INFO : End of MPR read delay center optimization
348 21:20:19.806520 INFO : End of write delay center optimization
349 21:20:19.811717 INFO : End of read delay center optimization
350 21:20:19.817242 INFO : End of max read latency training
351 21:20:19.817705 INFO : Training has run successfully!
352 21:20:19.822846 1D training succeed
353 21:20:19.828783 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:20:19.876371 Check phy result
355 21:20:19.876846 INFO : End of initialization
356 21:20:19.898076 INFO : End of 2D read delay Voltage center optimization
357 21:20:19.918337 INFO : End of 2D read delay Voltage center optimization
358 21:20:19.970447 INFO : End of 2D write delay Voltage center optimization
359 21:20:20.019878 INFO : End of 2D write delay Voltage center optimization
360 21:20:20.025260 INFO : Training has run successfully!
361 21:20:20.025724
362 21:20:20.026159 channel==0
363 21:20:20.030907 RxClkDly_Margin_A0==88 ps 9
364 21:20:20.031360 TxDqDly_Margin_A0==98 ps 10
365 21:20:20.034250 RxClkDly_Margin_A1==88 ps 9
366 21:20:20.034707 TxDqDly_Margin_A1==98 ps 10
367 21:20:20.039774 TrainedVREFDQ_A0==74
368 21:20:20.040277 TrainedVREFDQ_A1==74
369 21:20:20.040712 VrefDac_Margin_A0==25
370 21:20:20.045436 DeviceVref_Margin_A0==40
371 21:20:20.045887 VrefDac_Margin_A1==25
372 21:20:20.051066 DeviceVref_Margin_A1==40
373 21:20:20.051518
374 21:20:20.051950
375 21:20:20.052413 channel==1
376 21:20:20.052839 RxClkDly_Margin_A0==98 ps 10
377 21:20:20.056623 TxDqDly_Margin_A0==98 ps 10
378 21:20:20.057085 RxClkDly_Margin_A1==88 ps 9
379 21:20:20.062141 TxDqDly_Margin_A1==88 ps 9
380 21:20:20.062598 TrainedVREFDQ_A0==77
381 21:20:20.063028 TrainedVREFDQ_A1==77
382 21:20:20.067813 VrefDac_Margin_A0==22
383 21:20:20.068298 DeviceVref_Margin_A0==37
384 21:20:20.073340 VrefDac_Margin_A1==24
385 21:20:20.073792 DeviceVref_Margin_A1==37
386 21:20:20.074218
387 21:20:20.079013 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:20:20.079471
389 21:20:20.107072 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 21:20:20.112749 2D training succeed
391 21:20:20.118181 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:20:20.118637 auto size-- 65535DDR cs0 size: 2048MB
393 21:20:20.123726 DDR cs1 size: 2048MB
394 21:20:20.124226 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:20:20.129302 cs0 DataBus test pass
396 21:20:20.129757 cs1 DataBus test pass
397 21:20:20.130182 cs0 AddrBus test pass
398 21:20:20.134857 cs1 AddrBus test pass
399 21:20:20.135309
400 21:20:20.135738 100bdlr_step_size ps== 420
401 21:20:20.136215 result report
402 21:20:20.140536 boot times 0Enable ddr reg access
403 21:20:20.148219 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:20:20.161620 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 21:20:20.735387 0.0;M3 CHK:0;cm4_sp_mode 0
406 21:20:20.736087 MVN_1=0x00000000
407 21:20:20.740781 MVN_2=0x00000000
408 21:20:20.746580 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 21:20:20.747047 OPS=0x10
410 21:20:20.747485 ring efuse init
411 21:20:20.747912 chipver efuse init
412 21:20:20.752189 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 21:20:20.757725 [0.018961 Inits done]
414 21:20:20.758189 secure task start!
415 21:20:20.758626 high task start!
416 21:20:20.762275 low task start!
417 21:20:20.762736 run into bl31
418 21:20:20.768947 NOTICE: BL31: v1.3(release):4fc40b1
419 21:20:20.776809 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 21:20:20.777291 NOTICE: BL31: G12A normal boot!
421 21:20:20.802137 NOTICE: BL31: BL33 decompress pass
422 21:20:20.807816 ERROR: Error initializing runtime service opteed_fast
423 21:20:22.040718
424 21:20:22.041310
425 21:20:22.049073 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 21:20:22.049558
427 21:20:22.050006 Model: Libre Computer AML-A311D-CC Alta
428 21:20:22.257532 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 21:20:22.280908 DRAM: 2 GiB (effective 3.8 GiB)
430 21:20:22.423880 Core: 408 devices, 31 uclasses, devicetree: separate
431 21:20:22.429744 WDT: Not starting watchdog@f0d0
432 21:20:22.462101 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 21:20:22.474456 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 21:20:22.479454 ** Bad device specification mmc 0 **
435 21:20:22.489815 Card did not respond to voltage select! : -110
436 21:20:22.497427 ** Bad device specification mmc 0 **
437 21:20:22.497945 Couldn't find partition mmc 0
438 21:20:22.505790 Card did not respond to voltage select! : -110
439 21:20:22.511264 ** Bad device specification mmc 0 **
440 21:20:22.511741 Couldn't find partition mmc 0
441 21:20:22.516305 Error: could not access storage.
442 21:20:23.779815 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 21:20:23.780526 bl2_stage_init 0x81
444 21:20:23.785373 hw id: 0x0000 - pwm id 0x01
445 21:20:23.785874 bl2_stage_init 0xc1
446 21:20:23.786326 bl2_stage_init 0x02
447 21:20:23.786767
448 21:20:23.790983 L0:00000000
449 21:20:23.791476 L1:20000703
450 21:20:23.791922 L2:00008067
451 21:20:23.792411 L3:14000000
452 21:20:23.792853 B2:00402000
453 21:20:23.793786 B1:e0f83180
454 21:20:23.794269
455 21:20:23.794714 TE: 58150
456 21:20:23.795156
457 21:20:23.804984 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 21:20:23.805472
459 21:20:23.805920 Board ID = 1
460 21:20:23.806361 Set A53 clk to 24M
461 21:20:23.806796 Set A73 clk to 24M
462 21:20:23.810561 Set clk81 to 24M
463 21:20:23.811033 A53 clk: 1200 MHz
464 21:20:23.811475 A73 clk: 1200 MHz
465 21:20:23.816168 CLK81: 166.6M
466 21:20:23.816652 smccc: 00012aac
467 21:20:23.821765 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 21:20:23.822234 board id: 1
469 21:20:23.830360 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 21:20:23.841101 fw parse done
471 21:20:23.846963 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 21:20:23.889593 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 21:20:23.900507 PIEI prepare done
474 21:20:23.900970 fastboot data load
475 21:20:23.901415 fastboot data verify
476 21:20:23.906206 verify result: 266
477 21:20:23.911751 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 21:20:23.912269 LPDDR4 probe
479 21:20:23.912714 ddr clk to 1584MHz
480 21:20:23.919761 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 21:20:23.957026
482 21:20:23.957497 dmc_version 0001
483 21:20:23.963674 Check phy result
484 21:20:23.969552 INFO : End of CA training
485 21:20:23.970021 INFO : End of initialization
486 21:20:23.975186 INFO : Training has run successfully!
487 21:20:23.975653 Check phy result
488 21:20:23.980754 INFO : End of initialization
489 21:20:23.981217 INFO : End of read enable training
490 21:20:23.986354 INFO : End of fine write leveling
491 21:20:23.991946 INFO : End of Write leveling coarse delay
492 21:20:23.992440 INFO : Training has run successfully!
493 21:20:23.992878 Check phy result
494 21:20:23.997569 INFO : End of initialization
495 21:20:23.998032 INFO : End of read dq deskew training
496 21:20:24.003167 INFO : End of MPR read delay center optimization
497 21:20:24.008724 INFO : End of write delay center optimization
498 21:20:24.014361 INFO : End of read delay center optimization
499 21:20:24.014847 INFO : End of max read latency training
500 21:20:24.019932 INFO : Training has run successfully!
501 21:20:24.020436 1D training succeed
502 21:20:24.029268 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 21:20:24.076711 Check phy result
504 21:20:24.077186 INFO : End of initialization
505 21:20:24.098448 INFO : End of 2D read delay Voltage center optimization
506 21:20:24.117870 INFO : End of 2D read delay Voltage center optimization
507 21:20:24.169871 INFO : End of 2D write delay Voltage center optimization
508 21:20:24.219258 INFO : End of 2D write delay Voltage center optimization
509 21:20:24.224820 INFO : Training has run successfully!
510 21:20:24.225302
511 21:20:24.225755 channel==0
512 21:20:24.230399 RxClkDly_Margin_A0==88 ps 9
513 21:20:24.230866 TxDqDly_Margin_A0==98 ps 10
514 21:20:24.236031 RxClkDly_Margin_A1==88 ps 9
515 21:20:24.236503 TxDqDly_Margin_A1==98 ps 10
516 21:20:24.236952 TrainedVREFDQ_A0==74
517 21:20:24.241643 TrainedVREFDQ_A1==76
518 21:20:24.242119 VrefDac_Margin_A0==25
519 21:20:24.242561 DeviceVref_Margin_A0==40
520 21:20:24.247252 VrefDac_Margin_A1==25
521 21:20:24.247737 DeviceVref_Margin_A1==38
522 21:20:24.248268
523 21:20:24.248750
524 21:20:24.253177 channel==1
525 21:20:24.253804 RxClkDly_Margin_A0==88 ps 9
526 21:20:24.254295 TxDqDly_Margin_A0==88 ps 9
527 21:20:24.258572 RxClkDly_Margin_A1==88 ps 9
528 21:20:24.259144 TxDqDly_Margin_A1==88 ps 9
529 21:20:24.264050 TrainedVREFDQ_A0==77
530 21:20:24.264556 TrainedVREFDQ_A1==77
531 21:20:24.265008 VrefDac_Margin_A0==23
532 21:20:24.269633 DeviceVref_Margin_A0==37
533 21:20:24.270116 VrefDac_Margin_A1==24
534 21:20:24.275233 DeviceVref_Margin_A1==37
535 21:20:24.275744
536 21:20:24.276232 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 21:20:24.276683
538 21:20:24.308790 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000018 dram_vref_reg_value 0x 00000060
539 21:20:24.309316 2D training succeed
540 21:20:24.314437 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 21:20:24.320020 auto size-- 65535DDR cs0 size: 2048MB
542 21:20:24.320503 DDR cs1 size: 2048MB
543 21:20:24.325617 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 21:20:24.326090 cs0 DataBus test pass
545 21:20:24.331252 cs1 DataBus test pass
546 21:20:24.331721 cs0 AddrBus test pass
547 21:20:24.332207 cs1 AddrBus test pass
548 21:20:24.332644
549 21:20:24.336781 100bdlr_step_size ps== 420
550 21:20:24.337267 result report
551 21:20:24.342362 boot times 0Enable ddr reg access
552 21:20:24.347574 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 21:20:24.361051 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 21:20:24.934760 0.0;M3 CHK:0;cm4_sp_mode 0
555 21:20:24.935357 MVN_1=0x00000000
556 21:20:24.940301 MVN_2=0x00000000
557 21:20:24.946023 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 21:20:24.946529 OPS=0x10
559 21:20:24.946996 ring efuse init
560 21:20:24.947454 chipver efuse init
561 21:20:24.951608 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 21:20:24.957246 [0.018961 Inits done]
563 21:20:24.957708 secure task start!
564 21:20:24.958133 high task start!
565 21:20:24.961734 low task start!
566 21:20:24.962186 run into bl31
567 21:20:24.968414 NOTICE: BL31: v1.3(release):4fc40b1
568 21:20:24.976333 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 21:20:24.976798 NOTICE: BL31: G12A normal boot!
570 21:20:25.001624 NOTICE: BL31: BL33 decompress pass
571 21:20:25.007337 ERROR: Error initializing runtime service opteed_fast
572 21:20:26.240352
573 21:20:26.240965
574 21:20:26.248780 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 21:20:26.249263
576 21:20:26.249709 Model: Libre Computer AML-A311D-CC Alta
577 21:20:26.457093 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 21:20:26.480435 DRAM: 2 GiB (effective 3.8 GiB)
579 21:20:26.623503 Core: 408 devices, 31 uclasses, devicetree: separate
580 21:20:26.629388 WDT: Not starting watchdog@f0d0
581 21:20:26.661740 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 21:20:26.673995 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 21:20:26.679086 ** Bad device specification mmc 0 **
584 21:20:26.689394 Card did not respond to voltage select! : -110
585 21:20:26.697049 ** Bad device specification mmc 0 **
586 21:20:26.697525 Couldn't find partition mmc 0
587 21:20:26.705363 Card did not respond to voltage select! : -110
588 21:20:26.710806 ** Bad device specification mmc 0 **
589 21:20:26.711277 Couldn't find partition mmc 0
590 21:20:26.715977 Error: could not access storage.
591 21:20:27.059585 Net: eth0: ethernet@ff3f0000
592 21:20:27.060181 starting USB...
593 21:20:27.311252 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 21:20:27.311813 Starting the controller
595 21:20:27.318339 USB XHCI 1.10
596 21:20:29.029809 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 21:20:29.030469 bl2_stage_init 0x01
598 21:20:29.030940 bl2_stage_init 0x81
599 21:20:29.035429 hw id: 0x0000 - pwm id 0x01
600 21:20:29.035917 bl2_stage_init 0xc1
601 21:20:29.036413 bl2_stage_init 0x02
602 21:20:29.036862
603 21:20:29.041002 L0:00000000
604 21:20:29.041482 L1:20000703
605 21:20:29.041931 L2:00008067
606 21:20:29.042370 L3:14000000
607 21:20:29.046584 B2:00402000
608 21:20:29.047060 B1:e0f83180
609 21:20:29.047504
610 21:20:29.047948 TE: 58124
611 21:20:29.048440
612 21:20:29.052093 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 21:20:29.052596
614 21:20:29.053047 Board ID = 1
615 21:20:29.057829 Set A53 clk to 24M
616 21:20:29.058305 Set A73 clk to 24M
617 21:20:29.058748 Set clk81 to 24M
618 21:20:29.063364 A53 clk: 1200 MHz
619 21:20:29.063839 A73 clk: 1200 MHz
620 21:20:29.064319 CLK81: 166.6M
621 21:20:29.064758 smccc: 00012a92
622 21:20:29.069013 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 21:20:29.074611 board id: 1
624 21:20:29.080563 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 21:20:29.090958 fw parse done
626 21:20:29.096970 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 21:20:29.139658 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 21:20:29.151522 PIEI prepare done
629 21:20:29.152045 fastboot data load
630 21:20:29.152501 fastboot data verify
631 21:20:29.157406 verify result: 266
632 21:20:29.161867 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 21:20:29.162353 LPDDR4 probe
634 21:20:29.162795 ddr clk to 1584MHz
635 21:20:29.169786 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 21:20:29.207072
637 21:20:29.207580 dmc_version 0001
638 21:20:29.213687 Check phy result
639 21:20:29.219577 INFO : End of CA training
640 21:20:29.220083 INFO : End of initialization
641 21:20:29.225128 INFO : Training has run successfully!
642 21:20:29.225612 Check phy result
643 21:20:29.230800 INFO : End of initialization
644 21:20:29.231276 INFO : End of read enable training
645 21:20:29.236343 INFO : End of fine write leveling
646 21:20:29.241987 INFO : End of Write leveling coarse delay
647 21:20:29.242466 INFO : Training has run successfully!
648 21:20:29.242911 Check phy result
649 21:20:29.247554 INFO : End of initialization
650 21:20:29.248063 INFO : End of read dq deskew training
651 21:20:29.253205 INFO : End of MPR read delay center optimization
652 21:20:29.258760 INFO : End of write delay center optimization
653 21:20:29.264356 INFO : End of read delay center optimization
654 21:20:29.264841 INFO : End of max read latency training
655 21:20:29.269926 INFO : Training has run successfully!
656 21:20:29.270398 1D training succeed
657 21:20:29.279145 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 21:20:29.326765 Check phy result
659 21:20:29.327299 INFO : End of initialization
660 21:20:29.348490 INFO : End of 2D read delay Voltage center optimization
661 21:20:29.367872 INFO : End of 2D read delay Voltage center optimization
662 21:20:29.419819 INFO : End of 2D write delay Voltage center optimization
663 21:20:29.469196 INFO : End of 2D write delay Voltage center optimization
664 21:20:29.474726 INFO : Training has run successfully!
665 21:20:29.475216
666 21:20:29.475663 channel==0
667 21:20:29.480362 RxClkDly_Margin_A0==88 ps 9
668 21:20:29.480847 TxDqDly_Margin_A0==98 ps 10
669 21:20:29.485946 RxClkDly_Margin_A1==88 ps 9
670 21:20:29.486420 TxDqDly_Margin_A1==88 ps 9
671 21:20:29.486863 TrainedVREFDQ_A0==74
672 21:20:29.491570 TrainedVREFDQ_A1==74
673 21:20:29.492089 VrefDac_Margin_A0==25
674 21:20:29.492538 DeviceVref_Margin_A0==40
675 21:20:29.497122 VrefDac_Margin_A1==25
676 21:20:29.497606 DeviceVref_Margin_A1==40
677 21:20:29.498043
678 21:20:29.498482
679 21:20:29.498923 channel==1
680 21:20:29.502739 RxClkDly_Margin_A0==78 ps 8
681 21:20:29.503222 TxDqDly_Margin_A0==98 ps 10
682 21:20:29.508355 RxClkDly_Margin_A1==88 ps 9
683 21:20:29.508862 TxDqDly_Margin_A1==88 ps 9
684 21:20:29.513961 TrainedVREFDQ_A0==77
685 21:20:29.514444 TrainedVREFDQ_A1==77
686 21:20:29.514895 VrefDac_Margin_A0==23
687 21:20:29.519544 DeviceVref_Margin_A0==37
688 21:20:29.520057 VrefDac_Margin_A1==24
689 21:20:29.525125 DeviceVref_Margin_A1==37
690 21:20:29.525596
691 21:20:29.526044 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 21:20:29.526484
693 21:20:29.558723 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 21:20:29.559259 2D training succeed
695 21:20:29.564353 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 21:20:29.569964 auto size-- 65535DDR cs0 size: 2048MB
697 21:20:29.570444 DDR cs1 size: 2048MB
698 21:20:29.575506 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 21:20:29.576021 cs0 DataBus test pass
700 21:20:29.581116 cs1 DataBus test pass
701 21:20:29.581585 cs0 AddrBus test pass
702 21:20:29.582029 cs1 AddrBus test pass
703 21:20:29.582467
704 21:20:29.586730 100bdlr_step_size ps== 420
705 21:20:29.587211 result report
706 21:20:29.592328 boot times 0Enable ddr reg access
707 21:20:29.597503 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 21:20:29.611081 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 21:20:30.184685 0.0;M3 CHK:0;cm4_sp_mode 0
710 21:20:30.185299 MVN_1=0x00000000
711 21:20:30.190150 MVN_2=0x00000000
712 21:20:30.196102 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 21:20:30.196690 OPS=0x10
714 21:20:30.197125 ring efuse init
715 21:20:30.197555 chipver efuse init
716 21:20:30.201511 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 21:20:30.207171 [0.018961 Inits done]
718 21:20:30.207643 secure task start!
719 21:20:30.208102 high task start!
720 21:20:30.211682 low task start!
721 21:20:30.212182 run into bl31
722 21:20:30.218348 NOTICE: BL31: v1.3(release):4fc40b1
723 21:20:30.226137 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 21:20:30.226617 NOTICE: BL31: G12A normal boot!
725 21:20:30.251501 NOTICE: BL31: BL33 decompress pass
726 21:20:30.257206 ERROR: Error initializing runtime service opteed_fast
727 21:20:31.490126
728 21:20:31.490778
729 21:20:31.498478 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 21:20:31.498975
731 21:20:31.499424 Model: Libre Computer AML-A311D-CC Alta
732 21:20:31.706910 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 21:20:31.730303 DRAM: 2 GiB (effective 3.8 GiB)
734 21:20:31.873378 Core: 408 devices, 31 uclasses, devicetree: separate
735 21:20:31.879197 WDT: Not starting watchdog@f0d0
736 21:20:31.911403 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 21:20:31.923888 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 21:20:31.928834 ** Bad device specification mmc 0 **
739 21:20:31.939241 Card did not respond to voltage select! : -110
740 21:20:31.946846 ** Bad device specification mmc 0 **
741 21:20:31.947360 Couldn't find partition mmc 0
742 21:20:31.955244 Card did not respond to voltage select! : -110
743 21:20:31.960683 ** Bad device specification mmc 0 **
744 21:20:31.961188 Couldn't find partition mmc 0
745 21:20:31.965743 Error: could not access storage.
746 21:20:32.309297 Net: eth0: ethernet@ff3f0000
747 21:20:32.309858 starting USB...
748 21:20:32.561119 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 21:20:32.561758 Starting the controller
750 21:20:32.568080 USB XHCI 1.10
751 21:20:34.730111 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 21:20:34.730749 bl2_stage_init 0x01
753 21:20:34.731208 bl2_stage_init 0x81
754 21:20:34.735675 hw id: 0x0000 - pwm id 0x01
755 21:20:34.736187 bl2_stage_init 0xc1
756 21:20:34.736645 bl2_stage_init 0x02
757 21:20:34.737085
758 21:20:34.741178 L0:00000000
759 21:20:34.741650 L1:20000703
760 21:20:34.742096 L2:00008067
761 21:20:34.742532 L3:14000000
762 21:20:34.746863 B2:00402000
763 21:20:34.747333 B1:e0f83180
764 21:20:34.747773
765 21:20:34.748260 TE: 58159
766 21:20:34.748703
767 21:20:34.752267 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 21:20:34.752746
769 21:20:34.753193 Board ID = 1
770 21:20:34.757951 Set A53 clk to 24M
771 21:20:34.758441 Set A73 clk to 24M
772 21:20:34.758885 Set clk81 to 24M
773 21:20:34.763574 A53 clk: 1200 MHz
774 21:20:34.764072 A73 clk: 1200 MHz
775 21:20:34.764516 CLK81: 166.6M
776 21:20:34.764950 smccc: 00012ab5
777 21:20:34.769165 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 21:20:34.774716 board id: 1
779 21:20:34.780601 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 21:20:34.791208 fw parse done
781 21:20:34.797325 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 21:20:34.839696 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 21:20:34.850645 PIEI prepare done
784 21:20:34.851110 fastboot data load
785 21:20:34.851559 fastboot data verify
786 21:20:34.856267 verify result: 266
787 21:20:34.861838 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 21:20:34.862306 LPDDR4 probe
789 21:20:34.862748 ddr clk to 1584MHz
790 21:20:34.869862 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 21:20:34.907091
792 21:20:34.907557 dmc_version 0001
793 21:20:34.913779 Check phy result
794 21:20:34.919645 INFO : End of CA training
795 21:20:34.920139 INFO : End of initialization
796 21:20:34.925261 INFO : Training has run successfully!
797 21:20:34.925728 Check phy result
798 21:20:34.930825 INFO : End of initialization
799 21:20:34.931291 INFO : End of read enable training
800 21:20:34.936521 INFO : End of fine write leveling
801 21:20:34.942043 INFO : End of Write leveling coarse delay
802 21:20:34.942508 INFO : Training has run successfully!
803 21:20:34.942951 Check phy result
804 21:20:34.947637 INFO : End of initialization
805 21:20:34.948127 INFO : End of read dq deskew training
806 21:20:34.953312 INFO : End of MPR read delay center optimization
807 21:20:34.958825 INFO : End of write delay center optimization
808 21:20:34.964427 INFO : End of read delay center optimization
809 21:20:34.964889 INFO : End of max read latency training
810 21:20:34.970071 INFO : Training has run successfully!
811 21:20:34.970537 1D training succeed
812 21:20:34.979231 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 21:20:35.025911 Check phy result
814 21:20:35.026430 INFO : End of initialization
815 21:20:35.047594 INFO : End of 2D read delay Voltage center optimization
816 21:20:35.068215 INFO : End of 2D read delay Voltage center optimization
817 21:20:35.120469 INFO : End of 2D write delay Voltage center optimization
818 21:20:35.169728 INFO : End of 2D write delay Voltage center optimization
819 21:20:35.175224 INFO : Training has run successfully!
820 21:20:35.175692
821 21:20:35.176196 channel==0
822 21:20:35.180821 RxClkDly_Margin_A0==88 ps 9
823 21:20:35.181288 TxDqDly_Margin_A0==98 ps 10
824 21:20:35.186442 RxClkDly_Margin_A1==88 ps 9
825 21:20:35.186905 TxDqDly_Margin_A1==88 ps 9
826 21:20:35.187365 TrainedVREFDQ_A0==74
827 21:20:35.192048 TrainedVREFDQ_A1==74
828 21:20:35.192553 VrefDac_Margin_A0==25
829 21:20:35.193000 DeviceVref_Margin_A0==40
830 21:20:35.197876 VrefDac_Margin_A1==25
831 21:20:35.198373 DeviceVref_Margin_A1==40
832 21:20:35.198798
833 21:20:35.199220
834 21:20:35.199640 channel==1
835 21:20:35.203304 RxClkDly_Margin_A0==98 ps 10
836 21:20:35.203782 TxDqDly_Margin_A0==88 ps 9
837 21:20:35.209781 RxClkDly_Margin_A1==88 ps 9
838 21:20:35.210284 TxDqDly_Margin_A1==98 ps 10
839 21:20:35.214497 TrainedVREFDQ_A0==77
840 21:20:35.214962 TrainedVREFDQ_A1==77
841 21:20:35.215392 VrefDac_Margin_A0==22
842 21:20:35.220066 DeviceVref_Margin_A0==37
843 21:20:35.220521 VrefDac_Margin_A1==24
844 21:20:35.225706 DeviceVref_Margin_A1==37
845 21:20:35.226205
846 21:20:35.226648 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 21:20:35.227102
848 21:20:35.259229 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
849 21:20:35.259759 2D training succeed
850 21:20:35.264854 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 21:20:35.270452 auto size-- 65535DDR cs0 size: 2048MB
852 21:20:35.270912 DDR cs1 size: 2048MB
853 21:20:35.276039 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 21:20:35.276503 cs0 DataBus test pass
855 21:20:35.281696 cs1 DataBus test pass
856 21:20:35.282147 cs0 AddrBus test pass
857 21:20:35.282571 cs1 AddrBus test pass
858 21:20:35.282992
859 21:20:35.287191 100bdlr_step_size ps== 420
860 21:20:35.287651 result report
861 21:20:35.292851 boot times 0Enable ddr reg access
862 21:20:35.298063 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 21:20:35.311541 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 21:20:35.883633 0.0;M3 CHK:0;cm4_sp_mode 0
865 21:20:35.884342 MVN_1=0x00000000
866 21:20:35.889065 MVN_2=0x00000000
867 21:20:35.894839 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 21:20:35.895327 OPS=0x10
869 21:20:35.895787 ring efuse init
870 21:20:35.896281 chipver efuse init
871 21:20:35.900430 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 21:20:35.906064 [0.018961 Inits done]
873 21:20:35.906629 secure task start!
874 21:20:35.907105 high task start!
875 21:20:35.910610 low task start!
876 21:20:35.911100 run into bl31
877 21:20:35.917295 NOTICE: BL31: v1.3(release):4fc40b1
878 21:20:35.925072 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 21:20:35.925565 NOTICE: BL31: G12A normal boot!
880 21:20:35.950469 NOTICE: BL31: BL33 decompress pass
881 21:20:35.956195 ERROR: Error initializing runtime service opteed_fast
882 21:20:37.189147
883 21:20:37.189795
884 21:20:37.197458 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 21:20:37.197963
886 21:20:37.198421 Model: Libre Computer AML-A311D-CC Alta
887 21:20:37.405968 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 21:20:37.429340 DRAM: 2 GiB (effective 3.8 GiB)
889 21:20:37.572338 Core: 408 devices, 31 uclasses, devicetree: separate
890 21:20:37.578139 WDT: Not starting watchdog@f0d0
891 21:20:37.610474 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 21:20:37.622992 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 21:20:37.627887 ** Bad device specification mmc 0 **
894 21:20:37.638246 Card did not respond to voltage select! : -110
895 21:20:37.645968 ** Bad device specification mmc 0 **
896 21:20:37.646452 Couldn't find partition mmc 0
897 21:20:37.654271 Card did not respond to voltage select! : -110
898 21:20:37.659723 ** Bad device specification mmc 0 **
899 21:20:37.660234 Couldn't find partition mmc 0
900 21:20:37.664788 Error: could not access storage.
901 21:20:38.007216 Net: eth0: ethernet@ff3f0000
902 21:20:38.007746 starting USB...
903 21:20:38.259135 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 21:20:38.259655 Starting the controller
905 21:20:38.265987 USB XHCI 1.10
906 21:20:39.820368 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 21:20:39.828530 scanning usb for storage devices... 0 Storage Device(s) found
909 21:20:39.880151 Hit any key to stop autoboot: 1
910 21:20:39.881052 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 21:20:39.881751 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 21:20:39.882298 Setting prompt string to ['=>']
913 21:20:39.882840 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 21:20:39.896249 0
915 21:20:39.897268 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 21:20:39.897833 Sending with 10 millisecond of delay
918 21:20:41.032676 => setenv autoload no
919 21:20:41.043533 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 21:20:41.048885 setenv autoload no
921 21:20:41.049643 Sending with 10 millisecond of delay
923 21:20:42.846758 => setenv initrd_high 0xffffffff
924 21:20:42.857602 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 21:20:42.858467 setenv initrd_high 0xffffffff
926 21:20:42.859219 Sending with 10 millisecond of delay
928 21:20:44.475782 => setenv fdt_high 0xffffffff
929 21:20:44.486658 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 21:20:44.487570 setenv fdt_high 0xffffffff
931 21:20:44.488364 Sending with 10 millisecond of delay
933 21:20:44.780384 => dhcp
934 21:20:44.791072 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 21:20:44.791806 dhcp
936 21:20:44.792191 Speed: 1000, full duplex
937 21:20:44.792482 BOOTP broadcast 1
938 21:20:45.038784 BOOTP broadcast 2
939 21:20:45.539880 BOOTP broadcast 3
940 21:20:45.552716 DHCP client bound to address 192.168.6.33 (761 ms)
941 21:20:45.553549 Sending with 10 millisecond of delay
943 21:20:47.230093 => setenv serverip 192.168.6.2
944 21:20:47.240885 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
945 21:20:47.241788 setenv serverip 192.168.6.2
946 21:20:47.242475 Sending with 10 millisecond of delay
948 21:20:50.965963 => tftpboot 0x01080000 794921/tftp-deploy-mzmoq3zp/kernel/uImage
949 21:20:50.976757 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
950 21:20:50.977565 tftpboot 0x01080000 794921/tftp-deploy-mzmoq3zp/kernel/uImage
951 21:20:50.978013 Speed: 1000, full duplex
952 21:20:50.978424 Using ethernet@ff3f0000 device
953 21:20:50.979327 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 21:20:50.985034 Filename '794921/tftp-deploy-mzmoq3zp/kernel/uImage'.
955 21:20:50.988712 Load address: 0x1080000
956 21:20:51.178283 Loading: *# UDP wrong checksum 000000ff 0000b269
957 21:20:51.218216 # UDP wrong checksum 000000ff 0000395c
958 21:21:02.937307 #################################T ############### 63 MiB
959 21:21:02.938107 5.3 MiB/s
960 21:21:02.938700 done
961 21:21:02.941176 Bytes transferred = 66024000 (3ef7240 hex)
962 21:21:02.942258 Sending with 10 millisecond of delay
964 21:21:07.631430 => tftpboot 0x08000000 794921/tftp-deploy-mzmoq3zp/ramdisk/ramdisk.cpio.gz.uboot
965 21:21:07.642200 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
966 21:21:07.642720 tftpboot 0x08000000 794921/tftp-deploy-mzmoq3zp/ramdisk/ramdisk.cpio.gz.uboot
967 21:21:07.642958 Speed: 1000, full duplex
968 21:21:07.643181 Using ethernet@ff3f0000 device
969 21:21:07.644482 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
970 21:21:07.655317 Filename '794921/tftp-deploy-mzmoq3zp/ramdisk/ramdisk.cpio.gz.uboot'.
971 21:21:07.655754 Load address: 0x8000000
972 21:21:10.196617 Loading: *################################################# UDP wrong checksum 00000007 0000c415
973 21:21:15.196317 T UDP wrong checksum 00000007 0000c415
974 21:21:25.198046 T T UDP wrong checksum 00000007 0000c415
975 21:21:45.201193 T T T UDP wrong checksum 00000007 0000c415
976 21:22:02.247321 T T T T UDP wrong checksum 000000ff 0000754c
977 21:22:02.285774 UDP wrong checksum 000000ff 0000fa3e
978 21:22:02.813960 UDP wrong checksum 000000ff 00003b8e
979 21:22:02.820620 UDP wrong checksum 000000ff 0000d280
980 21:22:05.207564
981 21:22:05.208302 Retry count exceeded; starting again
983 21:22:05.210181 end: 2.4.3 bootloader-commands (duration 00:01:25) [common]
986 21:22:05.212320 end: 2.4 uboot-commands (duration 00:01:57) [common]
988 21:22:05.213861 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
990 21:22:05.215057 end: 2 uboot-action (duration 00:01:57) [common]
992 21:22:05.216870 Cleaning after the job
993 21:22:05.217536 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/ramdisk
994 21:22:05.219142 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/kernel
995 21:22:05.279188 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/dtb
996 21:22:05.280285 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794921/tftp-deploy-mzmoq3zp/modules
997 21:22:05.311741 start: 4.1 power-off (timeout 00:00:30) [common]
998 21:22:05.312577 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
999 21:22:05.348304 >> OK - accepted request
1000 21:22:05.350419 Returned 0 in 0 seconds
1001 21:22:05.451253 end: 4.1 power-off (duration 00:00:00) [common]
1003 21:22:05.452373 start: 4.2 read-feedback (timeout 00:10:00) [common]
1004 21:22:05.453022 Listened to connection for namespace 'common' for up to 1s
1005 21:22:06.453934 Finalising connection for namespace 'common'
1006 21:22:06.454426 Disconnecting from shell: Finalise
1007 21:22:06.454721 =>
1008 21:22:06.555402 end: 4.2 read-feedback (duration 00:00:01) [common]
1009 21:22:06.555873 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/794921
1010 21:22:06.858276 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/794921
1011 21:22:06.858869 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.