Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:17:24.782131 lava-dispatcher, installed at version: 2024.01
2 21:17:24.782941 start: 0 validate
3 21:17:24.783431 Start time: 2024-10-02 21:17:24.783401+00:00 (UTC)
4 21:17:24.784004 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:17:24.784548 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:17:24.825235 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:17:24.825841 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fkernel%2FImage exists
8 21:17:24.860719 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:17:24.861346 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 21:17:25.908884 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:17:25.909373 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-42-gf23aa4c0761a7%2Farm64%2Fdefconfig%2Bkselftest%2Fgcc-12%2Fmodules.tar.xz exists
12 21:17:25.955471 validate duration: 1.17
14 21:17:25.956364 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:17:25.956702 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:17:25.957008 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:17:25.957597 Not decompressing ramdisk as can be used compressed.
18 21:17:25.958035 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:17:25.958309 saving as /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/ramdisk/rootfs.cpio.gz
20 21:17:25.958588 total size: 8181887 (7 MB)
21 21:17:26.012799 progress 0 % (0 MB)
22 21:17:26.022509 progress 5 % (0 MB)
23 21:17:26.033528 progress 10 % (0 MB)
24 21:17:26.045119 progress 15 % (1 MB)
25 21:17:26.052084 progress 20 % (1 MB)
26 21:17:26.057964 progress 25 % (1 MB)
27 21:17:26.063212 progress 30 % (2 MB)
28 21:17:26.069071 progress 35 % (2 MB)
29 21:17:26.074406 progress 40 % (3 MB)
30 21:17:26.080195 progress 45 % (3 MB)
31 21:17:26.085688 progress 50 % (3 MB)
32 21:17:26.091463 progress 55 % (4 MB)
33 21:17:26.096771 progress 60 % (4 MB)
34 21:17:26.102539 progress 65 % (5 MB)
35 21:17:26.107880 progress 70 % (5 MB)
36 21:17:26.113597 progress 75 % (5 MB)
37 21:17:26.118870 progress 80 % (6 MB)
38 21:17:26.124518 progress 85 % (6 MB)
39 21:17:26.129915 progress 90 % (7 MB)
40 21:17:26.135506 progress 95 % (7 MB)
41 21:17:26.140676 progress 100 % (7 MB)
42 21:17:26.141345 7 MB downloaded in 0.18 s (42.70 MB/s)
43 21:17:26.141892 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:17:26.142773 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:17:26.143060 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:17:26.143326 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:17:26.143805 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+kselftest/gcc-12/kernel/Image
49 21:17:26.144121 saving as /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/kernel/Image
50 21:17:26.144362 total size: 66023936 (62 MB)
51 21:17:26.144597 No compression specified
52 21:17:26.181385 progress 0 % (0 MB)
53 21:17:26.225155 progress 5 % (3 MB)
54 21:17:26.269584 progress 10 % (6 MB)
55 21:17:26.311421 progress 15 % (9 MB)
56 21:17:26.352770 progress 20 % (12 MB)
57 21:17:26.394190 progress 25 % (15 MB)
58 21:17:26.436252 progress 30 % (18 MB)
59 21:17:26.477572 progress 35 % (22 MB)
60 21:17:26.519506 progress 40 % (25 MB)
61 21:17:26.561089 progress 45 % (28 MB)
62 21:17:26.602922 progress 50 % (31 MB)
63 21:17:26.644393 progress 55 % (34 MB)
64 21:17:26.685461 progress 60 % (37 MB)
65 21:17:26.726959 progress 65 % (40 MB)
66 21:17:26.767792 progress 70 % (44 MB)
67 21:17:26.809205 progress 75 % (47 MB)
68 21:17:26.851786 progress 80 % (50 MB)
69 21:17:26.892679 progress 85 % (53 MB)
70 21:17:26.933987 progress 90 % (56 MB)
71 21:17:26.974685 progress 95 % (59 MB)
72 21:17:27.014789 progress 100 % (62 MB)
73 21:17:27.015558 62 MB downloaded in 0.87 s (72.28 MB/s)
74 21:17:27.016061 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:17:27.016875 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:17:27.017146 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:17:27.017407 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:17:27.017866 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+kselftest/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 21:17:27.018133 saving as /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 21:17:27.018340 total size: 53209 (0 MB)
82 21:17:27.018548 No compression specified
83 21:17:27.054728 progress 61 % (0 MB)
84 21:17:27.055560 progress 100 % (0 MB)
85 21:17:27.056123 0 MB downloaded in 0.04 s (1.34 MB/s)
86 21:17:27.056587 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:17:27.057390 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:17:27.057646 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:17:27.057906 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:17:27.058365 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-42-gf23aa4c0761a7/arm64/defconfig+kselftest/gcc-12/modules.tar.xz
92 21:17:27.058606 saving as /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/modules/modules.tar
93 21:17:27.058808 total size: 16280760 (15 MB)
94 21:17:27.059018 Using unxz to decompress xz
95 21:17:27.094431 progress 0 % (0 MB)
96 21:17:27.195097 progress 5 % (0 MB)
97 21:17:27.310430 progress 10 % (1 MB)
98 21:17:27.423736 progress 15 % (2 MB)
99 21:17:27.539452 progress 20 % (3 MB)
100 21:17:27.652392 progress 25 % (3 MB)
101 21:17:27.765507 progress 30 % (4 MB)
102 21:17:27.873588 progress 35 % (5 MB)
103 21:17:27.983117 progress 40 % (6 MB)
104 21:17:28.097611 progress 45 % (7 MB)
105 21:17:28.207082 progress 50 % (7 MB)
106 21:17:28.321348 progress 55 % (8 MB)
107 21:17:28.437514 progress 60 % (9 MB)
108 21:17:28.548014 progress 65 % (10 MB)
109 21:17:28.663548 progress 70 % (10 MB)
110 21:17:28.802270 progress 75 % (11 MB)
111 21:17:28.936928 progress 80 % (12 MB)
112 21:17:29.046891 progress 85 % (13 MB)
113 21:17:29.162666 progress 90 % (14 MB)
114 21:17:29.268088 progress 95 % (14 MB)
115 21:17:29.381039 progress 100 % (15 MB)
116 21:17:29.394528 15 MB downloaded in 2.34 s (6.65 MB/s)
117 21:17:29.395139 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:17:29.396024 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:17:29.396627 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:17:29.397201 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:17:29.397741 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:17:29.398296 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:17:29.399374 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5
125 21:17:29.400424 makedir: /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin
126 21:17:29.401206 makedir: /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/tests
127 21:17:29.401897 makedir: /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/results
128 21:17:29.402566 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-add-keys
129 21:17:29.403616 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-add-sources
130 21:17:29.404713 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-background-process-start
131 21:17:29.405770 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-background-process-stop
132 21:17:29.406849 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-common-functions
133 21:17:29.407839 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-echo-ipv4
134 21:17:29.408957 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-install-packages
135 21:17:29.409985 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-installed-packages
136 21:17:29.410950 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-os-build
137 21:17:29.411916 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-probe-channel
138 21:17:29.412976 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-probe-ip
139 21:17:29.413949 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-target-ip
140 21:17:29.414906 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-target-mac
141 21:17:29.415891 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-target-storage
142 21:17:29.416992 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-test-case
143 21:17:29.417977 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-test-event
144 21:17:29.418938 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-test-feedback
145 21:17:29.419896 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-test-raise
146 21:17:29.420911 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-test-reference
147 21:17:29.421873 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-test-runner
148 21:17:29.422854 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-test-set
149 21:17:29.423855 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-test-shell
150 21:17:29.424962 Updating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-install-packages (oe)
151 21:17:29.426036 Updating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/bin/lava-installed-packages (oe)
152 21:17:29.426933 Creating /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/environment
153 21:17:29.427807 LAVA metadata
154 21:17:29.428383 - LAVA_JOB_ID=794917
155 21:17:29.428858 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:17:29.429589 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:17:29.431566 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:17:29.432262 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:17:29.432683 skipped lava-vland-overlay
160 21:17:29.433169 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:17:29.433672 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:17:29.434092 skipped lava-multinode-overlay
163 21:17:29.434573 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:17:29.435069 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:17:29.435540 Loading test definitions
166 21:17:29.436103 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:17:29.436544 Using /lava-794917 at stage 0
168 21:17:29.438706 uuid=794917_1.5.2.4.1 testdef=None
169 21:17:29.439267 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:17:29.439777 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:17:29.441820 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:17:29.442630 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:17:29.444907 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:17:29.445740 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:17:29.447914 runner path: /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/0/tests/0_dmesg test_uuid 794917_1.5.2.4.1
178 21:17:29.448506 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:17:29.449270 Creating lava-test-runner.conf files
181 21:17:29.449472 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/794917/lava-overlay-oafx98j5/lava-794917/0 for stage 0
182 21:17:29.449805 - 0_dmesg
183 21:17:29.450148 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:17:29.450424 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:17:29.474666 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:17:29.475088 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:56) [common]
187 21:17:29.475352 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:17:29.475620 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:17:29.475884 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
190 21:17:30.399106 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:17:30.399567 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:17:30.399812 extracting modules file /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/794917/extract-overlay-ramdisk-r_6a4tab/ramdisk
193 21:17:31.920858 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 21:17:31.921332 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 21:17:31.921607 [common] Applying overlay /var/lib/lava/dispatcher/tmp/794917/compress-overlay-ovu0o0xg/overlay-1.5.2.5.tar.gz to ramdisk
196 21:17:31.921819 [common] Applying overlay /var/lib/lava/dispatcher/tmp/794917/compress-overlay-ovu0o0xg/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/794917/extract-overlay-ramdisk-r_6a4tab/ramdisk
197 21:17:31.951655 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:17:31.952085 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 21:17:31.952362 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 21:17:31.952588 Converting downloaded kernel to a uImage
201 21:17:31.952890 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/kernel/Image /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/kernel/uImage
202 21:17:32.625948 output: Image Name:
203 21:17:32.626346 output: Created: Wed Oct 2 21:17:31 2024
204 21:17:32.626555 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:17:32.626760 output: Data Size: 66023936 Bytes = 64476.50 KiB = 62.97 MiB
206 21:17:32.626962 output: Load Address: 01080000
207 21:17:32.627159 output: Entry Point: 01080000
208 21:17:32.627354 output:
209 21:17:32.627676 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 21:17:32.627940 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 21:17:32.628247 start: 1.5.7 configure-preseed-file (timeout 00:09:53) [common]
212 21:17:32.628501 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:17:32.628754 start: 1.5.8 compress-ramdisk (timeout 00:09:53) [common]
214 21:17:32.629005 Building ramdisk /var/lib/lava/dispatcher/tmp/794917/extract-overlay-ramdisk-r_6a4tab/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/794917/extract-overlay-ramdisk-r_6a4tab/ramdisk
215 21:17:35.988158 >> 256019 blocks
216 21:17:47.026865 Adding RAMdisk u-boot header.
217 21:17:47.027331 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/794917/extract-overlay-ramdisk-r_6a4tab/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/794917/extract-overlay-ramdisk-r_6a4tab/ramdisk.cpio.gz.uboot
218 21:17:47.370076 output: Image Name:
219 21:17:47.370726 output: Created: Wed Oct 2 21:17:47 2024
220 21:17:47.371200 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:17:47.371660 output: Data Size: 33807809 Bytes = 33015.44 KiB = 32.24 MiB
222 21:17:47.372215 output: Load Address: 00000000
223 21:17:47.372676 output: Entry Point: 00000000
224 21:17:47.373117 output:
225 21:17:47.374305 rename /var/lib/lava/dispatcher/tmp/794917/extract-overlay-ramdisk-r_6a4tab/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/ramdisk/ramdisk.cpio.gz.uboot
226 21:17:47.375098 end: 1.5.8 compress-ramdisk (duration 00:00:15) [common]
227 21:17:47.375715 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
228 21:17:47.376357 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
229 21:17:47.376881 No LXC device requested
230 21:17:47.377451 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:17:47.378021 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
232 21:17:47.378573 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:17:47.379048 Checking files for TFTP limit of 4294967296 bytes.
234 21:17:47.382030 end: 1 tftp-deploy (duration 00:00:21) [common]
235 21:17:47.382679 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:17:47.383277 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:17:47.383843 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:17:47.384467 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:17:47.385069 Using kernel file from prepare-kernel: 794917/tftp-deploy-vljatviy/kernel/uImage
240 21:17:47.385748 substitutions:
241 21:17:47.386203 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:17:47.386653 - {DTB_ADDR}: 0x01070000
243 21:17:47.387133 - {DTB}: 794917/tftp-deploy-vljatviy/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 21:17:47.387593 - {INITRD}: 794917/tftp-deploy-vljatviy/ramdisk/ramdisk.cpio.gz.uboot
245 21:17:47.388066 - {KERNEL_ADDR}: 0x01080000
246 21:17:47.388516 - {KERNEL}: 794917/tftp-deploy-vljatviy/kernel/uImage
247 21:17:47.388960 - {LAVA_MAC}: None
248 21:17:47.389448 - {PRESEED_CONFIG}: None
249 21:17:47.389891 - {PRESEED_LOCAL}: None
250 21:17:47.390326 - {RAMDISK_ADDR}: 0x08000000
251 21:17:47.390758 - {RAMDISK}: 794917/tftp-deploy-vljatviy/ramdisk/ramdisk.cpio.gz.uboot
252 21:17:47.391194 - {ROOT_PART}: None
253 21:17:47.391625 - {ROOT}: None
254 21:17:47.392127 - {SERVER_IP}: 192.168.6.2
255 21:17:47.392602 - {TEE_ADDR}: 0x83000000
256 21:17:47.393058 - {TEE}: None
257 21:17:47.393519 Parsed boot commands:
258 21:17:47.393964 - setenv autoload no
259 21:17:47.394410 - setenv initrd_high 0xffffffff
260 21:17:47.394845 - setenv fdt_high 0xffffffff
261 21:17:47.395280 - dhcp
262 21:17:47.395715 - setenv serverip 192.168.6.2
263 21:17:47.396193 - tftpboot 0x01080000 794917/tftp-deploy-vljatviy/kernel/uImage
264 21:17:47.396638 - tftpboot 0x08000000 794917/tftp-deploy-vljatviy/ramdisk/ramdisk.cpio.gz.uboot
265 21:17:47.397078 - tftpboot 0x01070000 794917/tftp-deploy-vljatviy/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 21:17:47.397513 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:17:47.397955 - bootm 0x01080000 0x08000000 0x01070000
268 21:17:47.398529 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:17:47.400228 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:17:47.400743 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 21:17:47.417226 Setting prompt string to ['lava-test: # ']
273 21:17:47.418834 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:17:47.419513 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:17:47.420180 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:17:47.420811 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:17:47.422064 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 21:17:47.456212 >> OK - accepted request
279 21:17:47.458090 Returned 0 in 0 seconds
280 21:17:47.559333 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:17:47.561248 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:17:47.561895 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:17:47.562438 Setting prompt string to ['Hit any key to stop autoboot']
285 21:17:47.562928 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:17:47.564673 Trying 192.168.56.21...
287 21:17:47.565193 Connected to conserv1.
288 21:17:47.565651 Escape character is '^]'.
289 21:17:47.566116
290 21:17:47.566578 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 21:17:47.567066
292 21:17:54.844767 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 21:17:54.845215 bl2_stage_init 0x01
294 21:17:54.845492 bl2_stage_init 0x81
295 21:17:54.850165 hw id: 0x0000 - pwm id 0x01
296 21:17:54.850510 bl2_stage_init 0xc1
297 21:17:54.855656 bl2_stage_init 0x02
298 21:17:54.856070
299 21:17:54.856553 L0:00000000
300 21:17:54.857028 L1:00000703
301 21:17:54.857477 L2:00008067
302 21:17:54.857919 L3:15000000
303 21:17:54.861302 S1:00000000
304 21:17:54.861815 B2:20282000
305 21:17:54.862269 B1:a0f83180
306 21:17:54.862711
307 21:17:54.863152 TE: 70751
308 21:17:54.863593
309 21:17:54.866871 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 21:17:54.867357
311 21:17:54.872521 Board ID = 1
312 21:17:54.873031 Set cpu clk to 24M
313 21:17:54.873484 Set clk81 to 24M
314 21:17:54.878085 Use GP1_pll as DSU clk.
315 21:17:54.878608 DSU clk: 1200 Mhz
316 21:17:54.879056 CPU clk: 1200 MHz
317 21:17:54.883655 Set clk81 to 166.6M
318 21:17:54.889276 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 21:17:54.889772 board id: 1
320 21:17:54.896525 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:17:54.907126 fw parse done
322 21:17:54.913078 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:17:54.955826 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:17:54.966764 PIEI prepare done
325 21:17:54.967292 fastboot data load
326 21:17:54.967758 fastboot data verify
327 21:17:54.972343 verify result: 266
328 21:17:54.977885 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 21:17:54.978188 LPDDR4 probe
330 21:17:54.978408 ddr clk to 1584MHz
331 21:17:54.986020 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:17:55.023378
333 21:17:55.023795 dmc_version 0001
334 21:17:55.029960 Check phy result
335 21:17:55.035857 INFO : End of CA training
336 21:17:55.036243 INFO : End of initialization
337 21:17:55.041480 INFO : Training has run successfully!
338 21:17:55.042292 Check phy result
339 21:17:55.047129 INFO : End of initialization
340 21:17:55.047683 INFO : End of read enable training
341 21:17:55.052681 INFO : End of fine write leveling
342 21:17:55.058266 INFO : End of Write leveling coarse delay
343 21:17:55.058791 INFO : Training has run successfully!
344 21:17:55.059219 Check phy result
345 21:17:55.063878 INFO : End of initialization
346 21:17:55.064444 INFO : End of read dq deskew training
347 21:17:55.069433 INFO : End of MPR read delay center optimization
348 21:17:55.075067 INFO : End of write delay center optimization
349 21:17:55.080679 INFO : End of read delay center optimization
350 21:17:55.081187 INFO : End of max read latency training
351 21:17:55.086248 INFO : Training has run successfully!
352 21:17:55.086766 1D training succeed
353 21:17:55.095274 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:17:55.143005 Check phy result
355 21:17:55.143624 INFO : End of initialization
356 21:17:55.165476 INFO : End of 2D read delay Voltage center optimization
357 21:17:55.184693 INFO : End of 2D read delay Voltage center optimization
358 21:17:55.236517 INFO : End of 2D write delay Voltage center optimization
359 21:17:55.285608 INFO : End of 2D write delay Voltage center optimization
360 21:17:55.291219 INFO : Training has run successfully!
361 21:17:55.291736
362 21:17:55.292248 channel==0
363 21:17:55.296806 RxClkDly_Margin_A0==78 ps 8
364 21:17:55.297341 TxDqDly_Margin_A0==88 ps 9
365 21:17:55.300151 RxClkDly_Margin_A1==78 ps 8
366 21:17:55.300678 TxDqDly_Margin_A1==98 ps 10
367 21:17:55.305771 TrainedVREFDQ_A0==74
368 21:17:55.306294 TrainedVREFDQ_A1==74
369 21:17:55.306718 VrefDac_Margin_A0==24
370 21:17:55.312301 DeviceVref_Margin_A0==40
371 21:17:55.312805 VrefDac_Margin_A1==22
372 21:17:55.316864 DeviceVref_Margin_A1==40
373 21:17:55.317367
374 21:17:55.317791
375 21:17:55.318200 channel==1
376 21:17:55.318601 RxClkDly_Margin_A0==78 ps 8
377 21:17:55.320238 TxDqDly_Margin_A0==98 ps 10
378 21:17:55.325837 RxClkDly_Margin_A1==78 ps 8
379 21:17:55.326365 TxDqDly_Margin_A1==88 ps 9
380 21:17:55.326786 TrainedVREFDQ_A0==78
381 21:17:55.331403 TrainedVREFDQ_A1==75
382 21:17:55.331910 VrefDac_Margin_A0==22
383 21:17:55.337132 DeviceVref_Margin_A0==36
384 21:17:55.337635 VrefDac_Margin_A1==22
385 21:17:55.338052 DeviceVref_Margin_A1==39
386 21:17:55.338453
387 21:17:55.342617 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:17:55.343124
389 21:17:55.376141 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 21:17:55.376807 2D training succeed
391 21:17:55.381796 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:17:55.387419 auto size-- 65535DDR cs0 size: 2048MB
393 21:17:55.387949 DDR cs1 size: 2048MB
394 21:17:55.393146 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:17:55.393665 cs0 DataBus test pass
396 21:17:55.394088 cs1 DataBus test pass
397 21:17:55.398591 cs0 AddrBus test pass
398 21:17:55.399110 cs1 AddrBus test pass
399 21:17:55.399545
400 21:17:55.404238 100bdlr_step_size ps== 478
401 21:17:55.404758 result report
402 21:17:55.405172 boot times 0Enable ddr reg access
403 21:17:55.413950 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:17:55.427747 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 21:17:56.083038 bl2z: ptr: 05129330, size: 00001e40
406 21:17:56.091927 0.0;M3 CHK:0;cm4_sp_mode 0
407 21:17:56.092539 MVN_1=0x00000000
408 21:17:56.092956 MVN_2=0x00000000
409 21:17:56.103378 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 21:17:56.103945 OPS=0x04
411 21:17:56.104399 ring efuse init
412 21:17:56.109171 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 21:17:56.109674 [0.017319 Inits done]
414 21:17:56.110084 secure task start!
415 21:17:56.116929 high task start!
416 21:17:56.117423 low task start!
417 21:17:56.117831 run into bl31
418 21:17:56.125580 NOTICE: BL31: v1.3(release):4fc40b1
419 21:17:56.133360 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 21:17:56.133862 NOTICE: BL31: G12A normal boot!
421 21:17:56.148944 NOTICE: BL31: BL33 decompress pass
422 21:17:56.154663 ERROR: Error initializing runtime service opteed_fast
423 21:17:58.893655 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 21:17:58.894055 bl2_stage_init 0x01
425 21:17:58.894274 bl2_stage_init 0x81
426 21:17:58.899097 hw id: 0x0000 - pwm id 0x01
427 21:17:58.899750 bl2_stage_init 0xc1
428 21:17:58.904745 bl2_stage_init 0x02
429 21:17:58.905225
430 21:17:58.905634 L0:00000000
431 21:17:58.906028 L1:00000703
432 21:17:58.906419 L2:00008067
433 21:17:58.906848 L3:15000000
434 21:17:58.910845 S1:00000000
435 21:17:58.911335 B2:20282000
436 21:17:58.911746 B1:a0f83180
437 21:17:58.912177
438 21:17:58.912572 TE: 68235
439 21:17:58.912960
440 21:17:58.916452 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 21:17:58.916975
442 21:17:58.921954 Board ID = 1
443 21:17:58.922471 Set cpu clk to 24M
444 21:17:58.922874 Set clk81 to 24M
445 21:17:58.925494 Use GP1_pll as DSU clk.
446 21:17:58.926017 DSU clk: 1200 Mhz
447 21:17:58.930885 CPU clk: 1200 MHz
448 21:17:58.931427 Set clk81 to 166.6M
449 21:17:58.936456 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 21:17:58.936981 board id: 1
451 21:17:58.945280 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 21:17:58.956374 fw parse done
453 21:17:58.962217 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 21:17:59.006014 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 21:17:59.016781 PIEI prepare done
456 21:17:59.017317 fastboot data load
457 21:17:59.017728 fastboot data verify
458 21:17:59.022268 verify result: 266
459 21:17:59.027823 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 21:17:59.028398 LPDDR4 probe
461 21:17:59.028801 ddr clk to 1584MHz
462 21:17:59.035702 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 21:17:59.073579
464 21:17:59.074190 dmc_version 0001
465 21:17:59.080536 Check phy result
466 21:17:59.086705 INFO : End of CA training
467 21:17:59.087221 INFO : End of initialization
468 21:17:59.092212 INFO : Training has run successfully!
469 21:17:59.092754 Check phy result
470 21:17:59.098898 INFO : End of initialization
471 21:17:59.099504 INFO : End of read enable training
472 21:17:59.101403 INFO : End of fine write leveling
473 21:17:59.108390 INFO : End of Write leveling coarse delay
474 21:17:59.112986 INFO : Training has run successfully!
475 21:17:59.113518 Check phy result
476 21:17:59.113948 INFO : End of initialization
477 21:17:59.117771 INFO : End of read dq deskew training
478 21:17:59.123315 INFO : End of MPR read delay center optimization
479 21:17:59.123866 INFO : End of write delay center optimization
480 21:17:59.128928 INFO : End of read delay center optimization
481 21:17:59.134551 INFO : End of max read latency training
482 21:17:59.135078 INFO : Training has run successfully!
483 21:17:59.140169 1D training succeed
484 21:17:59.146049 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 21:17:59.194337 Check phy result
486 21:17:59.194965 INFO : End of initialization
487 21:17:59.221782 INFO : End of 2D read delay Voltage center optimization
488 21:17:59.245883 INFO : End of 2D read delay Voltage center optimization
489 21:17:59.302568 INFO : End of 2D write delay Voltage center optimization
490 21:17:59.356486 INFO : End of 2D write delay Voltage center optimization
491 21:17:59.362073 INFO : Training has run successfully!
492 21:17:59.362409
493 21:17:59.362646 channel==0
494 21:17:59.367842 RxClkDly_Margin_A0==88 ps 9
495 21:17:59.368207 TxDqDly_Margin_A0==88 ps 9
496 21:17:59.371038 RxClkDly_Margin_A1==88 ps 9
497 21:17:59.371389 TxDqDly_Margin_A1==88 ps 9
498 21:17:59.376602 TrainedVREFDQ_A0==75
499 21:17:59.376917 TrainedVREFDQ_A1==74
500 21:17:59.377150 VrefDac_Margin_A0==23
501 21:17:59.382140 DeviceVref_Margin_A0==39
502 21:17:59.382480 VrefDac_Margin_A1==23
503 21:17:59.387852 DeviceVref_Margin_A1==40
504 21:17:59.388219
505 21:17:59.388449
506 21:17:59.388670 channel==1
507 21:17:59.388884 RxClkDly_Margin_A0==88 ps 9
508 21:17:59.391505 TxDqDly_Margin_A0==98 ps 10
509 21:17:59.397550 RxClkDly_Margin_A1==78 ps 8
510 21:17:59.397896 TxDqDly_Margin_A1==88 ps 9
511 21:17:59.398148 TrainedVREFDQ_A0==78
512 21:17:59.402805 TrainedVREFDQ_A1==75
513 21:17:59.403168 VrefDac_Margin_A0==22
514 21:17:59.408431 DeviceVref_Margin_A0==36
515 21:17:59.408761 VrefDac_Margin_A1==20
516 21:17:59.408983 DeviceVref_Margin_A1==39
517 21:17:59.409189
518 21:17:59.413713 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 21:17:59.414038
520 21:17:59.447104 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 21:17:59.447463 2D training succeed
522 21:17:59.452736 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 21:17:59.458317 auto size-- 65535DDR cs0 size: 2048MB
524 21:17:59.458619 DDR cs1 size: 2048MB
525 21:17:59.463906 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 21:17:59.464195 cs0 DataBus test pass
527 21:17:59.464408 cs1 DataBus test pass
528 21:17:59.469531 cs0 AddrBus test pass
529 21:17:59.469827 cs1 AddrBus test pass
530 21:17:59.470044
531 21:17:59.475156 100bdlr_step_size ps== 471
532 21:17:59.475508 result report
533 21:17:59.475723 boot times 0Enable ddr reg access
534 21:17:59.483533 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 21:17:59.497604 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 21:18:00.158569 bl2z: ptr: 05129330, size: 00001e40
537 21:18:00.166899 0.0;M3 CHK:0;cm4_sp_mode 0
538 21:18:00.167215 MVN_1=0x00000000
539 21:18:00.167429 MVN_2=0x00000000
540 21:18:00.178264 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 21:18:00.178604 OPS=0x04
542 21:18:00.178822 ring efuse init
543 21:18:00.181557 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 21:18:00.186798 [0.017354 Inits done]
545 21:18:00.187075 secure task start!
546 21:18:00.187283 high task start!
547 21:18:00.187486 low task start!
548 21:18:00.190191 run into bl31
549 21:18:00.199651 NOTICE: BL31: v1.3(release):4fc40b1
550 21:18:00.207466 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 21:18:00.207817 NOTICE: BL31: G12A normal boot!
552 21:18:00.223001 NOTICE: BL31: BL33 decompress pass
553 21:18:00.228696 ERROR: Error initializing runtime service opteed_fast
554 21:18:01.592995 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 21:18:01.593418 bl2_stage_init 0x01
556 21:18:01.593632 bl2_stage_init 0x81
557 21:18:01.598530 hw id: 0x0000 - pwm id 0x01
558 21:18:01.598900 bl2_stage_init 0xc1
559 21:18:01.604143 bl2_stage_init 0x02
560 21:18:01.604535
561 21:18:01.604853 L0:00000000
562 21:18:01.605156 L1:00000703
563 21:18:01.605382 L2:00008067
564 21:18:01.605587 L3:15000000
565 21:18:01.609732 S1:00000000
566 21:18:01.610103 B2:20282000
567 21:18:01.610415 B1:a0f83180
568 21:18:01.610717
569 21:18:01.611019 TE: 69184
570 21:18:01.611313
571 21:18:01.615345 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 21:18:01.615620
573 21:18:01.620916 Board ID = 1
574 21:18:01.621182 Set cpu clk to 24M
575 21:18:01.621392 Set clk81 to 24M
576 21:18:01.626557 Use GP1_pll as DSU clk.
577 21:18:01.626938 DSU clk: 1200 Mhz
578 21:18:01.627258 CPU clk: 1200 MHz
579 21:18:01.632150 Set clk81 to 166.6M
580 21:18:01.637728 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 21:18:01.638102 board id: 1
582 21:18:01.644942 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 21:18:01.655790 fw parse done
584 21:18:01.661567 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 21:18:01.704201 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 21:18:01.715238 PIEI prepare done
587 21:18:01.715538 fastboot data load
588 21:18:01.715749 fastboot data verify
589 21:18:01.720781 verify result: 266
590 21:18:01.726392 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 21:18:01.726729 LPDDR4 probe
592 21:18:01.727023 ddr clk to 1584MHz
593 21:18:01.734344 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 21:18:01.771621
595 21:18:01.771954 dmc_version 0001
596 21:18:01.778245 Check phy result
597 21:18:01.784166 INFO : End of CA training
598 21:18:01.784457 INFO : End of initialization
599 21:18:01.789812 INFO : Training has run successfully!
600 21:18:01.790098 Check phy result
601 21:18:01.795332 INFO : End of initialization
602 21:18:01.795697 INFO : End of read enable training
603 21:18:01.800946 INFO : End of fine write leveling
604 21:18:01.806543 INFO : End of Write leveling coarse delay
605 21:18:01.806806 INFO : Training has run successfully!
606 21:18:01.807014 Check phy result
607 21:18:01.812150 INFO : End of initialization
608 21:18:01.812519 INFO : End of read dq deskew training
609 21:18:01.817771 INFO : End of MPR read delay center optimization
610 21:18:01.823393 INFO : End of write delay center optimization
611 21:18:01.828948 INFO : End of read delay center optimization
612 21:18:01.829242 INFO : End of max read latency training
613 21:18:01.834556 INFO : Training has run successfully!
614 21:18:01.834809 1D training succeed
615 21:18:01.843845 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 21:18:01.891378 Check phy result
617 21:18:01.891896 INFO : End of initialization
618 21:18:01.913749 INFO : End of 2D read delay Voltage center optimization
619 21:18:01.932979 INFO : End of 2D read delay Voltage center optimization
620 21:18:01.984808 INFO : End of 2D write delay Voltage center optimization
621 21:18:02.033962 INFO : End of 2D write delay Voltage center optimization
622 21:18:02.039514 INFO : Training has run successfully!
623 21:18:02.039777
624 21:18:02.040010 channel==0
625 21:18:02.045198 RxClkDly_Margin_A0==78 ps 8
626 21:18:02.045701 TxDqDly_Margin_A0==98 ps 10
627 21:18:02.050713 RxClkDly_Margin_A1==88 ps 9
628 21:18:02.051194 TxDqDly_Margin_A1==88 ps 9
629 21:18:02.051644 TrainedVREFDQ_A0==74
630 21:18:02.056292 TrainedVREFDQ_A1==74
631 21:18:02.056772 VrefDac_Margin_A0==23
632 21:18:02.057217 DeviceVref_Margin_A0==40
633 21:18:02.061921 VrefDac_Margin_A1==23
634 21:18:02.062403 DeviceVref_Margin_A1==40
635 21:18:02.062845
636 21:18:02.063287
637 21:18:02.063728 channel==1
638 21:18:02.067511 RxClkDly_Margin_A0==88 ps 9
639 21:18:02.068011 TxDqDly_Margin_A0==98 ps 10
640 21:18:02.073116 RxClkDly_Margin_A1==78 ps 8
641 21:18:02.073597 TxDqDly_Margin_A1==78 ps 8
642 21:18:02.079069 TrainedVREFDQ_A0==78
643 21:18:02.079548 TrainedVREFDQ_A1==75
644 21:18:02.080025 VrefDac_Margin_A0==23
645 21:18:02.084368 DeviceVref_Margin_A0==36
646 21:18:02.084896 VrefDac_Margin_A1==20
647 21:18:02.089900 DeviceVref_Margin_A1==39
648 21:18:02.090385
649 21:18:02.090833 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 21:18:02.091274
651 21:18:02.123498 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000019 00000017 00000018 00000015 00000018 00000014 00000016 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 21:18:02.124073 2D training succeed
653 21:18:02.129190 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 21:18:02.134713 auto size-- 65535DDR cs0 size: 2048MB
655 21:18:02.135218 DDR cs1 size: 2048MB
656 21:18:02.140291 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 21:18:02.140770 cs0 DataBus test pass
658 21:18:02.145924 cs1 DataBus test pass
659 21:18:02.146398 cs0 AddrBus test pass
660 21:18:02.146848 cs1 AddrBus test pass
661 21:18:02.147291
662 21:18:02.151526 100bdlr_step_size ps== 478
663 21:18:02.152086 result report
664 21:18:02.157142 boot times 0Enable ddr reg access
665 21:18:02.162266 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 21:18:02.176214 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 21:18:02.831161 bl2z: ptr: 05129330, size: 00001e40
668 21:18:02.836982 0.0;M3 CHK:0;cm4_sp_mode 0
669 21:18:02.837492 MVN_1=0x00000000
670 21:18:02.837947 MVN_2=0x00000000
671 21:18:02.848689 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 21:18:02.849207 OPS=0x04
673 21:18:02.849666 ring efuse init
674 21:18:02.854090 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 21:18:02.854576 [0.017320 Inits done]
676 21:18:02.855025 secure task start!
677 21:18:02.861295 high task start!
678 21:18:02.861788 low task start!
679 21:18:02.862235 run into bl31
680 21:18:02.869954 NOTICE: BL31: v1.3(release):4fc40b1
681 21:18:02.877783 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 21:18:02.878271 NOTICE: BL31: G12A normal boot!
683 21:18:02.893295 NOTICE: BL31: BL33 decompress pass
684 21:18:02.899048 ERROR: Error initializing runtime service opteed_fast
685 21:18:03.694445
686 21:18:03.695115
687 21:18:03.699749 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 21:18:03.700298
689 21:18:03.703211 Model: Libre Computer AML-S905D3-CC Solitude
690 21:18:03.850328 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 21:18:03.865685 DRAM: 2 GiB (effective 3.8 GiB)
692 21:18:03.966675 Core: 406 devices, 33 uclasses, devicetree: separate
693 21:18:03.972571 WDT: Not starting watchdog@f0d0
694 21:18:03.997586 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 21:18:04.009779 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 21:18:04.014740 ** Bad device specification mmc 0 **
697 21:18:04.024809 Card did not respond to voltage select! : -110
698 21:18:04.032472 ** Bad device specification mmc 0 **
699 21:18:04.032943 Couldn't find partition mmc 0
700 21:18:04.040770 Card did not respond to voltage select! : -110
701 21:18:04.046298 ** Bad device specification mmc 0 **
702 21:18:04.046764 Couldn't find partition mmc 0
703 21:18:04.051337 Error: could not access storage.
704 21:18:04.347917 Net: eth0: ethernet@ff3f0000
705 21:18:04.348623 starting USB...
706 21:18:04.592708 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 21:18:04.593370 Starting the controller
708 21:18:04.599697 USB XHCI 1.10
709 21:18:06.153200 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 21:18:06.161478 scanning usb for storage devices... 0 Storage Device(s) found
712 21:18:06.213181 Hit any key to stop autoboot: 1
713 21:18:06.214154 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 21:18:06.214806 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 21:18:06.215337 Setting prompt string to ['=>']
716 21:18:06.215877 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 21:18:06.227485 0
718 21:18:06.228498 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 21:18:06.329903 => setenv autoload no
721 21:18:06.330754 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 21:18:06.336074 setenv autoload no
724 21:18:06.437749 => setenv initrd_high 0xffffffff
725 21:18:06.438520 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 21:18:06.443146 setenv initrd_high 0xffffffff
728 21:18:06.544735 => setenv fdt_high 0xffffffff
729 21:18:06.545512 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 21:18:06.550032 setenv fdt_high 0xffffffff
732 21:18:06.651596 => dhcp
733 21:18:06.652426 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 21:18:06.656842 dhcp
735 21:18:07.812601 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete... done
736 21:18:07.813026 Speed: 1000, full duplex
737 21:18:07.813242 BOOTP broadcast 1
738 21:18:08.061809 BOOTP broadcast 2
739 21:18:08.562438 BOOTP broadcast 3
740 21:18:09.563391 BOOTP broadcast 4
741 21:18:11.564249 BOOTP broadcast 5
742 21:18:11.575122 DHCP client bound to address 192.168.6.12 (3763 ms)
744 21:18:11.677471 => setenv serverip 192.168.6.2
745 21:18:11.678168 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 21:18:11.681393 setenv serverip 192.168.6.2
748 21:18:11.782532 => tftpboot 0x01080000 794917/tftp-deploy-vljatviy/kernel/uImage
749 21:18:11.783266 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 21:18:11.789659 tftpboot 0x01080000 794917/tftp-deploy-vljatviy/kernel/uImage
751 21:18:11.789983 Speed: 1000, full duplex
752 21:18:11.790200 Using ethernet@ff3f0000 device
753 21:18:11.795197 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 21:18:11.800707 Filename '794917/tftp-deploy-vljatviy/kernel/uImage'.
755 21:18:11.804551 Load address: 0x1080000
756 21:18:12.178901 Loading: *## UDP wrong checksum 000000ff 0000a8e1
757 21:18:12.189455 UDP wrong checksum 000000ff 00002ad4
758 21:18:13.757306 ############# UDP wrong checksum 000000ff 0000e5e5
759 21:18:13.810787 UDP wrong checksum 000000ff 000077d8
760 21:18:23.627057 #######################T ############ 63 MiB
761 21:18:23.627679 5.3 MiB/s
762 21:18:23.628149 done
763 21:18:23.631176 Bytes transferred = 66024000 (3ef7240 hex)
765 21:18:23.738311 => tftpboot 0x08000000 794917/tftp-deploy-vljatviy/ramdisk/ramdisk.cpio.gz.uboot
766 21:18:23.739362 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
767 21:18:23.747580 tftpboot 0x08000000 794917/tftp-deploy-vljatviy/ramdisk/ramdisk.cpio.gz.uboot
768 21:18:23.748148 Speed: 1000, full duplex
769 21:18:23.748582 Using ethernet@ff3f0000 device
770 21:18:23.752787 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
771 21:18:23.761064 Filename '794917/tftp-deploy-vljatviy/ramdisk/ramdisk.cpio.gz.uboot'.
772 21:18:23.761571 Load address: 0x8000000
773 21:18:27.770752 Loading: *################################################# UDP wrong checksum 00000007 00004980
774 21:18:32.771457 T UDP wrong checksum 00000007 00004980
775 21:18:41.708558 T UDP wrong checksum 00000005 000000e7
776 21:18:42.772399 T UDP wrong checksum 00000007 00004980
777 21:19:02.776450 T T T UDP wrong checksum 00000007 00004980
778 21:19:14.843042 T T T UDP wrong checksum 000000ff 00006cff
779 21:19:14.853660 UDP wrong checksum 000000ff 0000eff1
780 21:19:22.782372 T
781 21:19:22.782800 Retry count exceeded; starting again
783 21:19:22.783716 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
786 21:19:22.784741 end: 2.4 uboot-commands (duration 00:01:35) [common]
788 21:19:22.785461 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
790 21:19:22.786020 end: 2 uboot-action (duration 00:01:35) [common]
792 21:19:22.786849 Cleaning after the job
793 21:19:22.787184 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/ramdisk
794 21:19:22.788562 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/kernel
795 21:19:22.827548 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/dtb
796 21:19:22.828852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/794917/tftp-deploy-vljatviy/modules
797 21:19:22.862142 start: 4.1 power-off (timeout 00:00:30) [common]
798 21:19:22.862954 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
799 21:19:22.896862 >> OK - accepted request
800 21:19:22.898915 Returned 0 in 0 seconds
801 21:19:22.999784 end: 4.1 power-off (duration 00:00:00) [common]
803 21:19:23.000950 start: 4.2 read-feedback (timeout 00:10:00) [common]
804 21:19:23.001712 Listened to connection for namespace 'common' for up to 1s
805 21:19:24.002644 Finalising connection for namespace 'common'
806 21:19:24.003220 Disconnecting from shell: Finalise
807 21:19:24.003566 =>
808 21:19:24.104414 end: 4.2 read-feedback (duration 00:00:01) [common]
809 21:19:24.105236 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/794917
810 21:19:24.467950 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/794917
811 21:19:24.468571 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.