Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:23:13.979650 lava-dispatcher, installed at version: 2024.01
2 01:23:13.980463 start: 0 validate
3 01:23:13.980951 Start time: 2024-10-03 01:23:13.980921+00:00 (UTC)
4 01:23:13.981491 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:23:13.982037 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:23:14.024878 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:23:14.025442 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fkernel%2FImage exists
8 01:23:14.060155 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:23:14.060769 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:23:14.096173 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:23:14.096661 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:23:14.127747 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:23:14.128274 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fmodules.tar.xz exists
14 01:23:14.172106 validate duration: 0.19
16 01:23:14.173585 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:23:14.174190 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:23:14.175016 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:23:14.176014 Not decompressing ramdisk as can be used compressed.
20 01:23:14.176780 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 01:23:14.177294 saving as /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/ramdisk/initrd.cpio.gz
22 01:23:14.177804 total size: 5628182 (5 MB)
23 01:23:14.220245 progress 0 % (0 MB)
24 01:23:14.229699 progress 5 % (0 MB)
25 01:23:14.238180 progress 10 % (0 MB)
26 01:23:14.245814 progress 15 % (0 MB)
27 01:23:14.254002 progress 20 % (1 MB)
28 01:23:14.258526 progress 25 % (1 MB)
29 01:23:14.262390 progress 30 % (1 MB)
30 01:23:14.266372 progress 35 % (1 MB)
31 01:23:14.269883 progress 40 % (2 MB)
32 01:23:14.273769 progress 45 % (2 MB)
33 01:23:14.277187 progress 50 % (2 MB)
34 01:23:14.281141 progress 55 % (2 MB)
35 01:23:14.285005 progress 60 % (3 MB)
36 01:23:14.288474 progress 65 % (3 MB)
37 01:23:14.292423 progress 70 % (3 MB)
38 01:23:14.295830 progress 75 % (4 MB)
39 01:23:14.299629 progress 80 % (4 MB)
40 01:23:14.302902 progress 85 % (4 MB)
41 01:23:14.306511 progress 90 % (4 MB)
42 01:23:14.310102 progress 95 % (5 MB)
43 01:23:14.313352 progress 100 % (5 MB)
44 01:23:14.313984 5 MB downloaded in 0.14 s (39.41 MB/s)
45 01:23:14.314533 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:23:14.315418 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:23:14.315707 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:23:14.315973 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:23:14.316491 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/kernel/Image
51 01:23:14.316759 saving as /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/kernel/Image
52 01:23:14.316969 total size: 39424512 (37 MB)
53 01:23:14.317178 No compression specified
54 01:23:14.354575 progress 0 % (0 MB)
55 01:23:14.378492 progress 5 % (1 MB)
56 01:23:14.401675 progress 10 % (3 MB)
57 01:23:14.424542 progress 15 % (5 MB)
58 01:23:14.447691 progress 20 % (7 MB)
59 01:23:14.471290 progress 25 % (9 MB)
60 01:23:14.495120 progress 30 % (11 MB)
61 01:23:14.518407 progress 35 % (13 MB)
62 01:23:14.541604 progress 40 % (15 MB)
63 01:23:14.565024 progress 45 % (16 MB)
64 01:23:14.588068 progress 50 % (18 MB)
65 01:23:14.610921 progress 55 % (20 MB)
66 01:23:14.633668 progress 60 % (22 MB)
67 01:23:14.657425 progress 65 % (24 MB)
68 01:23:14.680678 progress 70 % (26 MB)
69 01:23:14.703512 progress 75 % (28 MB)
70 01:23:14.726239 progress 80 % (30 MB)
71 01:23:14.749296 progress 85 % (31 MB)
72 01:23:14.772082 progress 90 % (33 MB)
73 01:23:14.795233 progress 95 % (35 MB)
74 01:23:14.817818 progress 100 % (37 MB)
75 01:23:14.818344 37 MB downloaded in 0.50 s (74.99 MB/s)
76 01:23:14.818838 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:23:14.819726 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:23:14.820042 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:23:14.820336 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:23:14.820814 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:23:14.821074 saving as /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:23:14.821292 total size: 54703 (0 MB)
84 01:23:14.821512 No compression specified
85 01:23:14.862337 progress 59 % (0 MB)
86 01:23:14.863183 progress 100 % (0 MB)
87 01:23:14.863742 0 MB downloaded in 0.04 s (1.23 MB/s)
88 01:23:14.864250 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:23:14.865095 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:23:14.865369 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:23:14.865641 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:23:14.866094 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 01:23:14.866345 saving as /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/nfsrootfs/full.rootfs.tar
95 01:23:14.866561 total size: 107552908 (102 MB)
96 01:23:14.866779 Using unxz to decompress xz
97 01:23:14.900828 progress 0 % (0 MB)
98 01:23:15.538380 progress 5 % (5 MB)
99 01:23:16.261756 progress 10 % (10 MB)
100 01:23:16.978832 progress 15 % (15 MB)
101 01:23:17.726137 progress 20 % (20 MB)
102 01:23:18.291703 progress 25 % (25 MB)
103 01:23:18.909392 progress 30 % (30 MB)
104 01:23:19.640715 progress 35 % (35 MB)
105 01:23:20.002293 progress 40 % (41 MB)
106 01:23:20.436128 progress 45 % (46 MB)
107 01:23:21.130399 progress 50 % (51 MB)
108 01:23:21.814783 progress 55 % (56 MB)
109 01:23:22.570045 progress 60 % (61 MB)
110 01:23:23.328198 progress 65 % (66 MB)
111 01:23:24.056334 progress 70 % (71 MB)
112 01:23:24.815458 progress 75 % (76 MB)
113 01:23:25.490643 progress 80 % (82 MB)
114 01:23:26.196955 progress 85 % (87 MB)
115 01:23:26.917048 progress 90 % (92 MB)
116 01:23:27.620617 progress 95 % (97 MB)
117 01:23:28.353104 progress 100 % (102 MB)
118 01:23:28.364848 102 MB downloaded in 13.50 s (7.60 MB/s)
119 01:23:28.365395 end: 1.4.1 http-download (duration 00:00:13) [common]
121 01:23:28.366224 end: 1.4 download-retry (duration 00:00:14) [common]
122 01:23:28.366489 start: 1.5 download-retry (timeout 00:09:46) [common]
123 01:23:28.366749 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 01:23:28.367223 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/modules.tar.xz
125 01:23:28.367468 saving as /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/modules/modules.tar
126 01:23:28.367672 total size: 11756024 (11 MB)
127 01:23:28.367882 Using unxz to decompress xz
128 01:23:28.414899 progress 0 % (0 MB)
129 01:23:28.484374 progress 5 % (0 MB)
130 01:23:28.562480 progress 10 % (1 MB)
131 01:23:28.649564 progress 15 % (1 MB)
132 01:23:28.731234 progress 20 % (2 MB)
133 01:23:28.813615 progress 25 % (2 MB)
134 01:23:28.894233 progress 30 % (3 MB)
135 01:23:28.973845 progress 35 % (3 MB)
136 01:23:29.051657 progress 40 % (4 MB)
137 01:23:29.128232 progress 45 % (5 MB)
138 01:23:29.206518 progress 50 % (5 MB)
139 01:23:29.282864 progress 55 % (6 MB)
140 01:23:29.367535 progress 60 % (6 MB)
141 01:23:29.453556 progress 65 % (7 MB)
142 01:23:29.535708 progress 70 % (7 MB)
143 01:23:29.629490 progress 75 % (8 MB)
144 01:23:29.724007 progress 80 % (9 MB)
145 01:23:29.800845 progress 85 % (9 MB)
146 01:23:29.876798 progress 90 % (10 MB)
147 01:23:29.955324 progress 95 % (10 MB)
148 01:23:30.032028 progress 100 % (11 MB)
149 01:23:30.045106 11 MB downloaded in 1.68 s (6.68 MB/s)
150 01:23:30.045792 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:23:30.046797 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:23:30.047125 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 01:23:30.047442 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 01:23:40.389854 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/795771/extract-nfsrootfs-sfrmxbj0
156 01:23:40.390464 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 01:23:40.390753 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 01:23:40.391377 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_
159 01:23:40.391808 makedir: /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin
160 01:23:40.392172 makedir: /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/tests
161 01:23:40.392491 makedir: /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/results
162 01:23:40.392817 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-add-keys
163 01:23:40.393351 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-add-sources
164 01:23:40.393871 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-background-process-start
165 01:23:40.394376 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-background-process-stop
166 01:23:40.394905 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-common-functions
167 01:23:40.395436 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-echo-ipv4
168 01:23:40.395967 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-install-packages
169 01:23:40.396531 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-installed-packages
170 01:23:40.397024 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-os-build
171 01:23:40.397504 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-probe-channel
172 01:23:40.397983 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-probe-ip
173 01:23:40.398481 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-target-ip
174 01:23:40.398994 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-target-mac
175 01:23:40.399476 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-target-storage
176 01:23:40.399962 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-test-case
177 01:23:40.400485 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-test-event
178 01:23:40.400961 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-test-feedback
179 01:23:40.401433 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-test-raise
180 01:23:40.401907 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-test-reference
181 01:23:40.402377 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-test-runner
182 01:23:40.402857 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-test-set
183 01:23:40.403332 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-test-shell
184 01:23:40.403824 Updating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-install-packages (oe)
185 01:23:40.404398 Updating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/bin/lava-installed-packages (oe)
186 01:23:40.404844 Creating /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/environment
187 01:23:40.405219 LAVA metadata
188 01:23:40.405478 - LAVA_JOB_ID=795771
189 01:23:40.405692 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:23:40.406058 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 01:23:40.407101 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:23:40.407422 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 01:23:40.407628 skipped lava-vland-overlay
194 01:23:40.407868 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:23:40.408156 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 01:23:40.408378 skipped lava-multinode-overlay
197 01:23:40.408619 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:23:40.408867 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 01:23:40.409119 Loading test definitions
200 01:23:40.409396 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 01:23:40.409613 Using /lava-795771 at stage 0
202 01:23:40.410830 uuid=795771_1.6.2.4.1 testdef=None
203 01:23:40.411145 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:23:40.411404 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 01:23:40.413277 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:23:40.414094 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 01:23:40.416407 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:23:40.417234 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 01:23:40.419425 runner path: /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/0/tests/0_dmesg test_uuid 795771_1.6.2.4.1
212 01:23:40.420035 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:23:40.420796 Creating lava-test-runner.conf files
215 01:23:40.420994 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795771/lava-overlay-ni8dj2d_/lava-795771/0 for stage 0
216 01:23:40.421340 - 0_dmesg
217 01:23:40.421689 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:23:40.421964 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 01:23:40.443659 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:23:40.444096 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 01:23:40.444359 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:23:40.444623 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:23:40.444881 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 01:23:41.083669 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:23:41.084179 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 01:23:41.084437 extracting modules file /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795771/extract-nfsrootfs-sfrmxbj0
227 01:23:42.466771 extracting modules file /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795771/extract-overlay-ramdisk-gpjemhz8/ramdisk
228 01:23:43.874482 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:23:43.874940 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 01:23:43.875221 [common] Applying overlay to NFS
231 01:23:43.875435 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795771/compress-overlay-ievx3jwq/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795771/extract-nfsrootfs-sfrmxbj0
232 01:23:43.904895 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:23:43.905304 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 01:23:43.905574 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 01:23:43.905804 Converting downloaded kernel to a uImage
236 01:23:43.906123 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/kernel/Image /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/kernel/uImage
237 01:23:44.315914 output: Image Name:
238 01:23:44.316356 output: Created: Thu Oct 3 01:23:43 2024
239 01:23:44.316569 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:23:44.316775 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
241 01:23:44.316977 output: Load Address: 01080000
242 01:23:44.317177 output: Entry Point: 01080000
243 01:23:44.317376 output:
244 01:23:44.317710 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 01:23:44.317975 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 01:23:44.318238 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 01:23:44.318490 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:23:44.318746 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 01:23:44.319002 Building ramdisk /var/lib/lava/dispatcher/tmp/795771/extract-overlay-ramdisk-gpjemhz8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795771/extract-overlay-ramdisk-gpjemhz8/ramdisk
250 01:23:46.561829 >> 173426 blocks
251 01:23:54.298773 Adding RAMdisk u-boot header.
252 01:23:54.299405 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795771/extract-overlay-ramdisk-gpjemhz8/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795771/extract-overlay-ramdisk-gpjemhz8/ramdisk.cpio.gz.uboot
253 01:23:54.556431 output: Image Name:
254 01:23:54.556843 output: Created: Thu Oct 3 01:23:54 2024
255 01:23:54.557056 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:23:54.557262 output: Data Size: 24126859 Bytes = 23561.39 KiB = 23.01 MiB
257 01:23:54.557465 output: Load Address: 00000000
258 01:23:54.557665 output: Entry Point: 00000000
259 01:23:54.557862 output:
260 01:23:54.558540 rename /var/lib/lava/dispatcher/tmp/795771/extract-overlay-ramdisk-gpjemhz8/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/ramdisk/ramdisk.cpio.gz.uboot
261 01:23:54.558959 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:23:54.559245 end: 1.6 prepare-tftp-overlay (duration 00:00:25) [common]
263 01:23:54.559518 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 01:23:54.559761 No LXC device requested
265 01:23:54.560095 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:23:54.560683 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 01:23:54.561244 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:23:54.561701 Checking files for TFTP limit of 4294967296 bytes.
269 01:23:54.564688 end: 1 tftp-deploy (duration 00:00:40) [common]
270 01:23:54.565332 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:23:54.565913 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:23:54.566467 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:23:54.567027 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:23:54.567609 Using kernel file from prepare-kernel: 795771/tftp-deploy-k1_g_ile/kernel/uImage
275 01:23:54.568343 substitutions:
276 01:23:54.568799 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:23:54.569246 - {DTB_ADDR}: 0x01070000
278 01:23:54.569691 - {DTB}: 795771/tftp-deploy-k1_g_ile/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:23:54.570133 - {INITRD}: 795771/tftp-deploy-k1_g_ile/ramdisk/ramdisk.cpio.gz.uboot
280 01:23:54.570572 - {KERNEL_ADDR}: 0x01080000
281 01:23:54.571007 - {KERNEL}: 795771/tftp-deploy-k1_g_ile/kernel/uImage
282 01:23:54.571439 - {LAVA_MAC}: None
283 01:23:54.571918 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/795771/extract-nfsrootfs-sfrmxbj0
284 01:23:54.572415 - {NFS_SERVER_IP}: 192.168.6.2
285 01:23:54.572857 - {PRESEED_CONFIG}: None
286 01:23:54.573290 - {PRESEED_LOCAL}: None
287 01:23:54.573724 - {RAMDISK_ADDR}: 0x08000000
288 01:23:54.574157 - {RAMDISK}: 795771/tftp-deploy-k1_g_ile/ramdisk/ramdisk.cpio.gz.uboot
289 01:23:54.574593 - {ROOT_PART}: None
290 01:23:54.575028 - {ROOT}: None
291 01:23:54.575463 - {SERVER_IP}: 192.168.6.2
292 01:23:54.575893 - {TEE_ADDR}: 0x83000000
293 01:23:54.576363 - {TEE}: None
294 01:23:54.576840 Parsed boot commands:
295 01:23:54.577298 - setenv autoload no
296 01:23:54.577769 - setenv initrd_high 0xffffffff
297 01:23:54.578208 - setenv fdt_high 0xffffffff
298 01:23:54.578635 - dhcp
299 01:23:54.579063 - setenv serverip 192.168.6.2
300 01:23:54.579490 - tftpboot 0x01080000 795771/tftp-deploy-k1_g_ile/kernel/uImage
301 01:23:54.579918 - tftpboot 0x08000000 795771/tftp-deploy-k1_g_ile/ramdisk/ramdisk.cpio.gz.uboot
302 01:23:54.580393 - tftpboot 0x01070000 795771/tftp-deploy-k1_g_ile/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:23:54.580825 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/795771/extract-nfsrootfs-sfrmxbj0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:23:54.581267 - bootm 0x01080000 0x08000000 0x01070000
305 01:23:54.581837 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:23:54.583478 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:23:54.583938 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:23:54.599681 Setting prompt string to ['lava-test: # ']
310 01:23:54.601371 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:23:54.602054 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:23:54.602702 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:23:54.603402 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:23:54.604698 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:23:54.642544 >> OK - accepted request
316 01:23:54.645046 Returned 0 in 0 seconds
317 01:23:54.746329 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:23:54.748238 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:23:54.748896 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:23:54.749465 Setting prompt string to ['Hit any key to stop autoboot']
322 01:23:54.749969 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:23:54.751658 Trying 192.168.56.21...
324 01:23:54.752225 Connected to conserv1.
325 01:23:54.752686 Escape character is '^]'.
326 01:23:54.753142
327 01:23:54.753589 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:23:54.754044
329 01:24:06.453684 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:24:06.454127 bl2_stage_init 0x01
331 01:24:06.454378 bl2_stage_init 0x81
332 01:24:06.459191 hw id: 0x0000 - pwm id 0x01
333 01:24:06.459526 bl2_stage_init 0xc1
334 01:24:06.459760 bl2_stage_init 0x02
335 01:24:06.460028
336 01:24:06.464663 L0:00000000
337 01:24:06.464961 L1:20000703
338 01:24:06.465168 L2:00008067
339 01:24:06.465367 L3:14000000
340 01:24:06.470310 B2:00402000
341 01:24:06.470627 B1:e0f83180
342 01:24:06.470871
343 01:24:06.471107 TE: 58124
344 01:24:06.471333
345 01:24:06.475959 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:24:06.476606
347 01:24:06.477028 Board ID = 1
348 01:24:06.481411 Set A53 clk to 24M
349 01:24:06.481895 Set A73 clk to 24M
350 01:24:06.482296 Set clk81 to 24M
351 01:24:06.487164 A53 clk: 1200 MHz
352 01:24:06.487636 A73 clk: 1200 MHz
353 01:24:06.488069 CLK81: 166.6M
354 01:24:06.488461 smccc: 00012a91
355 01:24:06.492693 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:24:06.498421 board id: 1
357 01:24:06.504478 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:24:06.514961 fw parse done
359 01:24:06.520735 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:24:06.564452 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:24:06.574189 PIEI prepare done
362 01:24:06.574680 fastboot data load
363 01:24:06.575085 fastboot data verify
364 01:24:06.579932 verify result: 266
365 01:24:06.585691 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:24:06.586241 LPDDR4 probe
367 01:24:06.586692 ddr clk to 1584MHz
368 01:24:06.593406 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:24:06.630713
370 01:24:06.631245 dmc_version 0001
371 01:24:06.637476 Check phy result
372 01:24:06.643339 INFO : End of CA training
373 01:24:06.644022 INFO : End of initialization
374 01:24:06.649044 INFO : Training has run successfully!
375 01:24:06.649631 Check phy result
376 01:24:06.654505 INFO : End of initialization
377 01:24:06.655084 INFO : End of read enable training
378 01:24:06.657730 INFO : End of fine write leveling
379 01:24:06.663268 INFO : End of Write leveling coarse delay
380 01:24:06.668921 INFO : Training has run successfully!
381 01:24:06.669421 Check phy result
382 01:24:06.669866 INFO : End of initialization
383 01:24:06.674552 INFO : End of read dq deskew training
384 01:24:06.680086 INFO : End of MPR read delay center optimization
385 01:24:06.680582 INFO : End of write delay center optimization
386 01:24:06.685630 INFO : End of read delay center optimization
387 01:24:06.691221 INFO : End of max read latency training
388 01:24:06.691769 INFO : Training has run successfully!
389 01:24:06.696895 1D training succeed
390 01:24:06.703031 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:24:06.750346 Check phy result
392 01:24:06.750945 INFO : End of initialization
393 01:24:06.773390 INFO : End of 2D read delay Voltage center optimization
394 01:24:06.792386 INFO : End of 2D read delay Voltage center optimization
395 01:24:06.843776 INFO : End of 2D write delay Voltage center optimization
396 01:24:06.893761 INFO : End of 2D write delay Voltage center optimization
397 01:24:06.899361 INFO : Training has run successfully!
398 01:24:06.899900
399 01:24:06.900394 channel==0
400 01:24:06.904928 RxClkDly_Margin_A0==88 ps 9
401 01:24:06.905477 TxDqDly_Margin_A0==98 ps 10
402 01:24:06.908224 RxClkDly_Margin_A1==88 ps 9
403 01:24:06.908724 TxDqDly_Margin_A1==98 ps 10
404 01:24:06.913797 TrainedVREFDQ_A0==74
405 01:24:06.914315 TrainedVREFDQ_A1==75
406 01:24:06.919414 VrefDac_Margin_A0==25
407 01:24:06.919937 DeviceVref_Margin_A0==40
408 01:24:06.920459 VrefDac_Margin_A1==25
409 01:24:06.924896 DeviceVref_Margin_A1==39
410 01:24:06.925391
411 01:24:06.925852
412 01:24:06.926293 channel==1
413 01:24:06.926722 RxClkDly_Margin_A0==88 ps 9
414 01:24:06.928408 TxDqDly_Margin_A0==98 ps 10
415 01:24:06.934542 RxClkDly_Margin_A1==98 ps 10
416 01:24:06.935159 TxDqDly_Margin_A1==88 ps 9
417 01:24:06.935616 TrainedVREFDQ_A0==77
418 01:24:06.939805 TrainedVREFDQ_A1==77
419 01:24:06.940444 VrefDac_Margin_A0==22
420 01:24:06.945372 DeviceVref_Margin_A0==37
421 01:24:06.945971 VrefDac_Margin_A1==22
422 01:24:06.946442 DeviceVref_Margin_A1==37
423 01:24:06.946896
424 01:24:06.950939 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:24:06.951524
426 01:24:06.984435 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:24:06.985170 2D training succeed
428 01:24:06.990146 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:24:06.995591 auto size-- 65535DDR cs0 size: 2048MB
430 01:24:06.996156 DDR cs1 size: 2048MB
431 01:24:07.001153 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:24:07.001659 cs0 DataBus test pass
433 01:24:07.002115 cs1 DataBus test pass
434 01:24:07.006941 cs0 AddrBus test pass
435 01:24:07.007541 cs1 AddrBus test pass
436 01:24:07.008047
437 01:24:07.012389 100bdlr_step_size ps== 420
438 01:24:07.012925 result report
439 01:24:07.013384 boot times 0Enable ddr reg access
440 01:24:07.022154 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:24:07.035774 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:24:07.609358 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:24:07.610008 MVN_1=0x00000000
444 01:24:07.615042 MVN_2=0x00000000
445 01:24:07.620561 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:24:07.621059 OPS=0x10
447 01:24:07.621525 ring efuse init
448 01:24:07.621969 chipver efuse init
449 01:24:07.626195 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:24:07.631856 [0.018961 Inits done]
451 01:24:07.632407 secure task start!
452 01:24:07.632863 high task start!
453 01:24:07.635415 low task start!
454 01:24:07.635892 run into bl31
455 01:24:07.643101 NOTICE: BL31: v1.3(release):4fc40b1
456 01:24:07.650021 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:24:07.650515 NOTICE: BL31: G12A normal boot!
458 01:24:07.676335 NOTICE: BL31: BL33 decompress pass
459 01:24:07.681175 ERROR: Error initializing runtime service opteed_fast
460 01:24:08.914840
461 01:24:08.915507
462 01:24:08.923093 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:24:08.923619
464 01:24:08.924117 Model: Libre Computer AML-A311D-CC Alta
465 01:24:09.131523 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:24:09.154144 DRAM: 2 GiB (effective 3.8 GiB)
467 01:24:09.298004 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:24:09.303796 WDT: Not starting watchdog@f0d0
469 01:24:09.337029 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:24:09.348744 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:24:09.352751 ** Bad device specification mmc 0 **
472 01:24:09.363862 Card did not respond to voltage select! : -110
473 01:24:09.370952 ** Bad device specification mmc 0 **
474 01:24:09.371511 Couldn't find partition mmc 0
475 01:24:09.379842 Card did not respond to voltage select! : -110
476 01:24:09.385373 ** Bad device specification mmc 0 **
477 01:24:09.385942 Couldn't find partition mmc 0
478 01:24:09.389542 Error: could not access storage.
479 01:24:10.653788 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:24:10.654235 bl2_stage_init 0x01
481 01:24:10.654463 bl2_stage_init 0x81
482 01:24:10.659353 hw id: 0x0000 - pwm id 0x01
483 01:24:10.659740 bl2_stage_init 0xc1
484 01:24:10.659975 bl2_stage_init 0x02
485 01:24:10.660231
486 01:24:10.664939 L0:00000000
487 01:24:10.665341 L1:20000703
488 01:24:10.665586 L2:00008067
489 01:24:10.665811 L3:14000000
490 01:24:10.670655 B2:00402000
491 01:24:10.671288 B1:e0f83180
492 01:24:10.671616
493 01:24:10.672021 TE: 58124
494 01:24:10.672382
495 01:24:10.676209 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:24:10.676807
497 01:24:10.677208 Board ID = 1
498 01:24:10.681773 Set A53 clk to 24M
499 01:24:10.682197 Set A73 clk to 24M
500 01:24:10.682419 Set clk81 to 24M
501 01:24:10.687389 A53 clk: 1200 MHz
502 01:24:10.687779 A73 clk: 1200 MHz
503 01:24:10.688027 CLK81: 166.6M
504 01:24:10.688261 smccc: 00012a92
505 01:24:10.692994 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:24:10.698575 board id: 1
507 01:24:10.704417 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:24:10.715144 fw parse done
509 01:24:10.720396 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:24:10.763001 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:24:10.774602 PIEI prepare done
512 01:24:10.775041 fastboot data load
513 01:24:10.775267 fastboot data verify
514 01:24:10.780255 verify result: 266
515 01:24:10.785886 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:24:10.786302 LPDDR4 probe
517 01:24:10.786533 ddr clk to 1584MHz
518 01:24:10.793366 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:24:10.830279
520 01:24:10.830716 dmc_version 0001
521 01:24:10.837014 Check phy result
522 01:24:10.843696 INFO : End of CA training
523 01:24:10.844144 INFO : End of initialization
524 01:24:10.849250 INFO : Training has run successfully!
525 01:24:10.849675 Check phy result
526 01:24:10.854938 INFO : End of initialization
527 01:24:10.855390 INFO : End of read enable training
528 01:24:10.858217 INFO : End of fine write leveling
529 01:24:10.863733 INFO : End of Write leveling coarse delay
530 01:24:10.869404 INFO : Training has run successfully!
531 01:24:10.870065 Check phy result
532 01:24:10.870441 INFO : End of initialization
533 01:24:10.874955 INFO : End of read dq deskew training
534 01:24:10.880680 INFO : End of MPR read delay center optimization
535 01:24:10.881090 INFO : End of write delay center optimization
536 01:24:10.886082 INFO : End of read delay center optimization
537 01:24:10.891754 INFO : End of max read latency training
538 01:24:10.892364 INFO : Training has run successfully!
539 01:24:10.897401 1D training succeed
540 01:24:10.902486 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:24:10.950589 Check phy result
542 01:24:10.951042 INFO : End of initialization
543 01:24:10.973035 INFO : End of 2D read delay Voltage center optimization
544 01:24:10.992542 INFO : End of 2D read delay Voltage center optimization
545 01:24:11.043424 INFO : End of 2D write delay Voltage center optimization
546 01:24:11.095023 INFO : End of 2D write delay Voltage center optimization
547 01:24:11.099152 INFO : Training has run successfully!
548 01:24:11.099523
549 01:24:11.099747 channel==0
550 01:24:11.104714 RxClkDly_Margin_A0==88 ps 9
551 01:24:11.105091 TxDqDly_Margin_A0==98 ps 10
552 01:24:11.110607 RxClkDly_Margin_A1==88 ps 9
553 01:24:11.111014 TxDqDly_Margin_A1==98 ps 10
554 01:24:11.111256 TrainedVREFDQ_A0==74
555 01:24:11.116041 TrainedVREFDQ_A1==75
556 01:24:11.116472 VrefDac_Margin_A0==25
557 01:24:11.116738 DeviceVref_Margin_A0==40
558 01:24:11.121677 VrefDac_Margin_A1==25
559 01:24:11.122030 DeviceVref_Margin_A1==39
560 01:24:11.122240
561 01:24:11.122464
562 01:24:11.127099 channel==1
563 01:24:11.127453 RxClkDly_Margin_A0==88 ps 9
564 01:24:11.127700 TxDqDly_Margin_A0==98 ps 10
565 01:24:11.132654 RxClkDly_Margin_A1==88 ps 9
566 01:24:11.133000 TxDqDly_Margin_A1==88 ps 9
567 01:24:11.138335 TrainedVREFDQ_A0==77
568 01:24:11.138690 TrainedVREFDQ_A1==77
569 01:24:11.138940 VrefDac_Margin_A0==23
570 01:24:11.143865 DeviceVref_Margin_A0==37
571 01:24:11.144252 VrefDac_Margin_A1==24
572 01:24:11.149606 DeviceVref_Margin_A1==37
573 01:24:11.150011
574 01:24:11.150263 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:24:11.150493
576 01:24:11.183142 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
577 01:24:11.183575 2D training succeed
578 01:24:11.188692 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:24:11.194380 auto size-- 65535DDR cs0 size: 2048MB
580 01:24:11.194729 DDR cs1 size: 2048MB
581 01:24:11.199879 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:24:11.200242 cs0 DataBus test pass
583 01:24:11.205605 cs1 DataBus test pass
584 01:24:11.205940 cs0 AddrBus test pass
585 01:24:11.206186 cs1 AddrBus test pass
586 01:24:11.206410
587 01:24:11.211082 100bdlr_step_size ps== 420
588 01:24:11.211435 result report
589 01:24:11.216699 boot times 0Enable ddr reg access
590 01:24:11.221408 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:24:11.234697 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:24:11.807735 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:24:11.808487 MVN_1=0x00000000
594 01:24:11.813118 MVN_2=0x00000000
595 01:24:11.818739 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:24:11.819129 OPS=0x10
597 01:24:11.819359 ring efuse init
598 01:24:11.819583 chipver efuse init
599 01:24:11.824566 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:24:11.829926 [0.018960 Inits done]
601 01:24:11.830336 secure task start!
602 01:24:11.830570 high task start!
603 01:24:11.834779 low task start!
604 01:24:11.835188 run into bl31
605 01:24:11.843178 NOTICE: BL31: v1.3(release):4fc40b1
606 01:24:11.849704 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:24:11.850154 NOTICE: BL31: G12A normal boot!
608 01:24:11.874509 NOTICE: BL31: BL33 decompress pass
609 01:24:11.879212 ERROR: Error initializing runtime service opteed_fast
610 01:24:13.113370
611 01:24:13.113801
612 01:24:13.120986 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:24:13.121648
614 01:24:13.122193 Model: Libre Computer AML-A311D-CC Alta
615 01:24:13.328990 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:24:13.352647 DRAM: 2 GiB (effective 3.8 GiB)
617 01:24:13.496446 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:24:13.501941 WDT: Not starting watchdog@f0d0
619 01:24:13.534591 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:24:13.546827 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:24:13.550966 ** Bad device specification mmc 0 **
622 01:24:13.562326 Card did not respond to voltage select! : -110
623 01:24:13.569759 ** Bad device specification mmc 0 **
624 01:24:13.570285 Couldn't find partition mmc 0
625 01:24:13.578005 Card did not respond to voltage select! : -110
626 01:24:13.583548 ** Bad device specification mmc 0 **
627 01:24:13.584096 Couldn't find partition mmc 0
628 01:24:13.588634 Error: could not access storage.
629 01:24:13.931194 Net: eth0: ethernet@ff3f0000
630 01:24:13.931622 starting USB...
631 01:24:14.183004 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:24:14.183666 Starting the controller
633 01:24:14.190092 USB XHCI 1.10
634 01:24:15.902801 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:24:15.903498 bl2_stage_init 0x01
636 01:24:15.903976 bl2_stage_init 0x81
637 01:24:15.908453 hw id: 0x0000 - pwm id 0x01
638 01:24:15.909024 bl2_stage_init 0xc1
639 01:24:15.909493 bl2_stage_init 0x02
640 01:24:15.909945
641 01:24:15.913796 L0:00000000
642 01:24:15.914286 L1:20000703
643 01:24:15.914736 L2:00008067
644 01:24:15.915180 L3:14000000
645 01:24:15.919373 B2:00402000
646 01:24:15.919856 B1:e0f83180
647 01:24:15.920343
648 01:24:15.920791 TE: 58167
649 01:24:15.921235
650 01:24:15.925020 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:24:15.925510
652 01:24:15.925961 Board ID = 1
653 01:24:15.930914 Set A53 clk to 24M
654 01:24:15.931394 Set A73 clk to 24M
655 01:24:15.931833 Set clk81 to 24M
656 01:24:15.936268 A53 clk: 1200 MHz
657 01:24:15.936789 A73 clk: 1200 MHz
658 01:24:15.937239 CLK81: 166.6M
659 01:24:15.937677 smccc: 00012abe
660 01:24:15.941770 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:24:15.947370 board id: 1
662 01:24:15.953285 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:24:15.963942 fw parse done
664 01:24:15.969940 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:24:16.012424 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:24:16.023358 PIEI prepare done
667 01:24:16.023853 fastboot data load
668 01:24:16.024361 fastboot data verify
669 01:24:16.029061 verify result: 266
670 01:24:16.034570 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:24:16.035059 LPDDR4 probe
672 01:24:16.035516 ddr clk to 1584MHz
673 01:24:16.042546 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:24:16.079802
675 01:24:16.080340 dmc_version 0001
676 01:24:16.086494 Check phy result
677 01:24:16.092468 INFO : End of CA training
678 01:24:16.092953 INFO : End of initialization
679 01:24:16.097951 INFO : Training has run successfully!
680 01:24:16.098439 Check phy result
681 01:24:16.103552 INFO : End of initialization
682 01:24:16.104058 INFO : End of read enable training
683 01:24:16.109148 INFO : End of fine write leveling
684 01:24:16.114726 INFO : End of Write leveling coarse delay
685 01:24:16.115204 INFO : Training has run successfully!
686 01:24:16.115656 Check phy result
687 01:24:16.120314 INFO : End of initialization
688 01:24:16.120794 INFO : End of read dq deskew training
689 01:24:16.125944 INFO : End of MPR read delay center optimization
690 01:24:16.131554 INFO : End of write delay center optimization
691 01:24:16.137143 INFO : End of read delay center optimization
692 01:24:16.137628 INFO : End of max read latency training
693 01:24:16.142742 INFO : Training has run successfully!
694 01:24:16.143223 1D training succeed
695 01:24:16.151912 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:24:16.199600 Check phy result
697 01:24:16.200213 INFO : End of initialization
698 01:24:16.220527 INFO : End of 2D read delay Voltage center optimization
699 01:24:16.240678 INFO : End of 2D read delay Voltage center optimization
700 01:24:16.292930 INFO : End of 2D write delay Voltage center optimization
701 01:24:16.342171 INFO : End of 2D write delay Voltage center optimization
702 01:24:16.347650 INFO : Training has run successfully!
703 01:24:16.348213
704 01:24:16.348714 channel==0
705 01:24:16.353359 RxClkDly_Margin_A0==88 ps 9
706 01:24:16.353942 TxDqDly_Margin_A0==98 ps 10
707 01:24:16.358876 RxClkDly_Margin_A1==88 ps 9
708 01:24:16.359721 TxDqDly_Margin_A1==88 ps 9
709 01:24:16.361670 TrainedVREFDQ_A0==74
710 01:24:16.364509 TrainedVREFDQ_A1==74
711 01:24:16.365091 VrefDac_Margin_A0==25
712 01:24:16.367462 DeviceVref_Margin_A0==40
713 01:24:16.370099 VrefDac_Margin_A1==25
714 01:24:16.370856 DeviceVref_Margin_A1==40
715 01:24:16.371354
716 01:24:16.371827
717 01:24:16.372313 channel==1
718 01:24:16.375689 RxClkDly_Margin_A0==88 ps 9
719 01:24:16.376285 TxDqDly_Margin_A0==98 ps 10
720 01:24:16.381364 RxClkDly_Margin_A1==88 ps 9
721 01:24:16.382136 TxDqDly_Margin_A1==88 ps 9
722 01:24:16.386891 TrainedVREFDQ_A0==77
723 01:24:16.387446 TrainedVREFDQ_A1==77
724 01:24:16.387920 VrefDac_Margin_A0==23
725 01:24:16.392473 DeviceVref_Margin_A0==37
726 01:24:16.393022 VrefDac_Margin_A1==24
727 01:24:16.398106 DeviceVref_Margin_A1==37
728 01:24:16.398872
729 01:24:16.399585 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:24:16.400147
731 01:24:16.431615 soc_vref_reg_value 0x 00000019 00000019 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
732 01:24:16.432025 2D training succeed
733 01:24:16.437285 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:24:16.442815 auto size-- 65535DDR cs0 size: 2048MB
735 01:24:16.443119 DDR cs1 size: 2048MB
736 01:24:16.448486 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:24:16.448925 cs0 DataBus test pass
738 01:24:16.454108 cs1 DataBus test pass
739 01:24:16.454406 cs0 AddrBus test pass
740 01:24:16.454635 cs1 AddrBus test pass
741 01:24:16.454856
742 01:24:16.459741 100bdlr_step_size ps== 420
743 01:24:16.460083 result report
744 01:24:16.465315 boot times 0Enable ddr reg access
745 01:24:16.470367 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:24:16.483085 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:24:17.057679 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:24:17.058367 MVN_1=0x00000000
749 01:24:17.063039 MVN_2=0x00000000
750 01:24:17.068797 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:24:17.069361 OPS=0x10
752 01:24:17.069807 ring efuse init
753 01:24:17.070238 chipver efuse init
754 01:24:17.074364 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:24:17.079972 [0.018960 Inits done]
756 01:24:17.080491 secure task start!
757 01:24:17.080925 high task start!
758 01:24:17.084522 low task start!
759 01:24:17.084981 run into bl31
760 01:24:17.091215 NOTICE: BL31: v1.3(release):4fc40b1
761 01:24:17.099027 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:24:17.099512 NOTICE: BL31: G12A normal boot!
763 01:24:17.124412 NOTICE: BL31: BL33 decompress pass
764 01:24:17.130090 ERROR: Error initializing runtime service opteed_fast
765 01:24:18.363081
766 01:24:18.363728
767 01:24:18.371412 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:24:18.371954
769 01:24:18.372465 Model: Libre Computer AML-A311D-CC Alta
770 01:24:18.579942 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:24:18.603193 DRAM: 2 GiB (effective 3.8 GiB)
772 01:24:18.746314 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:24:18.752083 WDT: Not starting watchdog@f0d0
774 01:24:18.784284 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:24:18.796746 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:24:18.800844 ** Bad device specification mmc 0 **
777 01:24:18.812106 Card did not respond to voltage select! : -110
778 01:24:18.819740 ** Bad device specification mmc 0 **
779 01:24:18.820360 Couldn't find partition mmc 0
780 01:24:18.828061 Card did not respond to voltage select! : -110
781 01:24:18.833608 ** Bad device specification mmc 0 **
782 01:24:18.834126 Couldn't find partition mmc 0
783 01:24:18.838702 Error: could not access storage.
784 01:24:19.182170 Net: eth0: ethernet@ff3f0000
785 01:24:19.182847 starting USB...
786 01:24:19.434074 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:24:19.434726 Starting the controller
788 01:24:19.441144 USB XHCI 1.10
789 01:24:21.602737 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:24:21.603382 bl2_stage_init 0x01
791 01:24:21.603854 bl2_stage_init 0x81
792 01:24:21.608275 hw id: 0x0000 - pwm id 0x01
793 01:24:21.608772 bl2_stage_init 0xc1
794 01:24:21.609228 bl2_stage_init 0x02
795 01:24:21.609681
796 01:24:21.613877 L0:00000000
797 01:24:21.614359 L1:20000703
798 01:24:21.614813 L2:00008067
799 01:24:21.615257 L3:14000000
800 01:24:21.616855 B2:00402000
801 01:24:21.617333 B1:e0f83180
802 01:24:21.617780
803 01:24:21.618227 TE: 58124
804 01:24:21.618672
805 01:24:21.628008 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:24:21.628504
807 01:24:21.628958 Board ID = 1
808 01:24:21.629400 Set A53 clk to 24M
809 01:24:21.629837 Set A73 clk to 24M
810 01:24:21.633569 Set clk81 to 24M
811 01:24:21.634047 A53 clk: 1200 MHz
812 01:24:21.634494 A73 clk: 1200 MHz
813 01:24:21.639094 CLK81: 166.6M
814 01:24:21.639568 smccc: 00012a91
815 01:24:21.644796 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:24:21.645285 board id: 1
817 01:24:21.653412 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:24:21.664128 fw parse done
819 01:24:21.670669 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:24:21.711702 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:24:21.723514 PIEI prepare done
822 01:24:21.724026 fastboot data load
823 01:24:21.724489 fastboot data verify
824 01:24:21.729172 verify result: 266
825 01:24:21.734762 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:24:21.735241 LPDDR4 probe
827 01:24:21.735685 ddr clk to 1584MHz
828 01:24:21.742799 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:24:21.780071
830 01:24:21.780568 dmc_version 0001
831 01:24:21.786651 Check phy result
832 01:24:21.792484 INFO : End of CA training
833 01:24:21.792960 INFO : End of initialization
834 01:24:21.798173 INFO : Training has run successfully!
835 01:24:21.798651 Check phy result
836 01:24:21.803696 INFO : End of initialization
837 01:24:21.804196 INFO : End of read enable training
838 01:24:21.809332 INFO : End of fine write leveling
839 01:24:21.814927 INFO : End of Write leveling coarse delay
840 01:24:21.815403 INFO : Training has run successfully!
841 01:24:21.815843 Check phy result
842 01:24:21.820554 INFO : End of initialization
843 01:24:21.821027 INFO : End of read dq deskew training
844 01:24:21.826223 INFO : End of MPR read delay center optimization
845 01:24:21.831757 INFO : End of write delay center optimization
846 01:24:21.837345 INFO : End of read delay center optimization
847 01:24:21.837816 INFO : End of max read latency training
848 01:24:21.842934 INFO : Training has run successfully!
849 01:24:21.843405 1D training succeed
850 01:24:21.852219 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:24:21.899792 Check phy result
852 01:24:21.900349 INFO : End of initialization
853 01:24:21.921374 INFO : End of 2D read delay Voltage center optimization
854 01:24:21.941479 INFO : End of 2D read delay Voltage center optimization
855 01:24:21.993379 INFO : End of 2D write delay Voltage center optimization
856 01:24:22.042669 INFO : End of 2D write delay Voltage center optimization
857 01:24:22.048323 INFO : Training has run successfully!
858 01:24:22.048819
859 01:24:22.049285 channel==0
860 01:24:22.053726 RxClkDly_Margin_A0==88 ps 9
861 01:24:22.054215 TxDqDly_Margin_A0==98 ps 10
862 01:24:22.057157 RxClkDly_Margin_A1==88 ps 9
863 01:24:22.057645 TxDqDly_Margin_A1==88 ps 9
864 01:24:22.062732 TrainedVREFDQ_A0==74
865 01:24:22.063228 TrainedVREFDQ_A1==74
866 01:24:22.063694 VrefDac_Margin_A0==25
867 01:24:22.068389 DeviceVref_Margin_A0==40
868 01:24:22.068878 VrefDac_Margin_A1==25
869 01:24:22.073922 DeviceVref_Margin_A1==40
870 01:24:22.074393
871 01:24:22.074824
872 01:24:22.075255 channel==1
873 01:24:22.075679 RxClkDly_Margin_A0==98 ps 10
874 01:24:22.077397 TxDqDly_Margin_A0==88 ps 9
875 01:24:22.082834 RxClkDly_Margin_A1==98 ps 10
876 01:24:22.083293 TxDqDly_Margin_A1==88 ps 9
877 01:24:22.083735 TrainedVREFDQ_A0==77
878 01:24:22.088433 TrainedVREFDQ_A1==77
879 01:24:22.088898 VrefDac_Margin_A0==22
880 01:24:22.094113 DeviceVref_Margin_A0==37
881 01:24:22.094591 VrefDac_Margin_A1==22
882 01:24:22.095031 DeviceVref_Margin_A1==37
883 01:24:22.095465
884 01:24:22.103571 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:24:22.104131
886 01:24:22.131227 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 01:24:22.131761 2D training succeed
888 01:24:22.136747 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:24:22.142285 auto size-- 65535DDR cs0 size: 2048MB
890 01:24:22.142748 DDR cs1 size: 2048MB
891 01:24:22.147969 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:24:22.148474 cs0 DataBus test pass
893 01:24:22.153509 cs1 DataBus test pass
894 01:24:22.153975 cs0 AddrBus test pass
895 01:24:22.154403 cs1 AddrBus test pass
896 01:24:22.159146
897 01:24:22.159610 100bdlr_step_size ps== 420
898 01:24:22.160094 result report
899 01:24:22.164711 boot times 0Enable ddr reg access
900 01:24:22.170871 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:24:22.184345 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:24:22.756508 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:24:22.757165 MVN_1=0x00000000
904 01:24:22.761865 MVN_2=0x00000000
905 01:24:22.767608 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:24:22.768139 OPS=0x10
907 01:24:22.768598 ring efuse init
908 01:24:22.769045 chipver efuse init
909 01:24:22.773218 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:24:22.778788 [0.018961 Inits done]
911 01:24:22.779265 secure task start!
912 01:24:22.779709 high task start!
913 01:24:22.783371 low task start!
914 01:24:22.783846 run into bl31
915 01:24:22.790008 NOTICE: BL31: v1.3(release):4fc40b1
916 01:24:22.797836 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:24:22.798320 NOTICE: BL31: G12A normal boot!
918 01:24:22.823213 NOTICE: BL31: BL33 decompress pass
919 01:24:22.828903 ERROR: Error initializing runtime service opteed_fast
920 01:24:24.061878
921 01:24:24.062550
922 01:24:24.070167 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:24:24.070667
924 01:24:24.071132 Model: Libre Computer AML-A311D-CC Alta
925 01:24:24.278850 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:24:24.301982 DRAM: 2 GiB (effective 3.8 GiB)
927 01:24:24.445316 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:24:24.450843 WDT: Not starting watchdog@f0d0
929 01:24:24.483217 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:24:24.495615 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:24:24.500583 ** Bad device specification mmc 0 **
932 01:24:24.510979 Card did not respond to voltage select! : -110
933 01:24:24.518589 ** Bad device specification mmc 0 **
934 01:24:24.519068 Couldn't find partition mmc 0
935 01:24:24.526875 Card did not respond to voltage select! : -110
936 01:24:24.532442 ** Bad device specification mmc 0 **
937 01:24:24.532923 Couldn't find partition mmc 0
938 01:24:24.537513 Error: could not access storage.
939 01:24:24.879857 Net: eth0: ethernet@ff3f0000
940 01:24:24.880526 starting USB...
941 01:24:25.131831 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:24:25.132467 Starting the controller
943 01:24:25.138612 USB XHCI 1.10
944 01:24:27.003442 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 01:24:27.003859 bl2_stage_init 0x01
946 01:24:27.004141 bl2_stage_init 0x81
947 01:24:27.008951 hw id: 0x0000 - pwm id 0x01
948 01:24:27.009253 bl2_stage_init 0xc1
949 01:24:27.009471 bl2_stage_init 0x02
950 01:24:27.009681
951 01:24:27.014708 L0:00000000
952 01:24:27.015116 L1:20000703
953 01:24:27.015447 L2:00008067
954 01:24:27.015778 L3:14000000
955 01:24:27.020160 B2:00402000
956 01:24:27.020557 B1:e0f83180
957 01:24:27.020885
958 01:24:27.021207 TE: 58159
959 01:24:27.021438
960 01:24:27.025760 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 01:24:27.026042
962 01:24:27.026245 Board ID = 1
963 01:24:27.031324 Set A53 clk to 24M
964 01:24:27.031721 Set A73 clk to 24M
965 01:24:27.032117 Set clk81 to 24M
966 01:24:27.036921 A53 clk: 1200 MHz
967 01:24:27.037315 A73 clk: 1200 MHz
968 01:24:27.037552 CLK81: 166.6M
969 01:24:27.037755 smccc: 00012ab5
970 01:24:27.042530 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 01:24:27.048151 board id: 1
972 01:24:27.054037 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 01:24:27.064751 fw parse done
974 01:24:27.070781 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 01:24:27.113354 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 01:24:27.124380 PIEI prepare done
977 01:24:27.124834 fastboot data load
978 01:24:27.125231 fastboot data verify
979 01:24:27.130211 verify result: 266
980 01:24:27.135703 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 01:24:27.136197 LPDDR4 probe
982 01:24:27.136590 ddr clk to 1584MHz
983 01:24:27.143748 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 01:24:27.181073
985 01:24:27.181550 dmc_version 0001
986 01:24:27.187648 Check phy result
987 01:24:27.193522 INFO : End of CA training
988 01:24:27.193973 INFO : End of initialization
989 01:24:27.199130 INFO : Training has run successfully!
990 01:24:27.199618 Check phy result
991 01:24:27.204807 INFO : End of initialization
992 01:24:27.205272 INFO : End of read enable training
993 01:24:27.208257 INFO : End of fine write leveling
994 01:24:27.213888 INFO : End of Write leveling coarse delay
995 01:24:27.219603 INFO : Training has run successfully!
996 01:24:27.220089 Check phy result
997 01:24:27.220501 INFO : End of initialization
998 01:24:27.225001 INFO : End of read dq deskew training
999 01:24:27.230496 INFO : End of MPR read delay center optimization
1000 01:24:27.230961 INFO : End of write delay center optimization
1001 01:24:27.236178 INFO : End of read delay center optimization
1002 01:24:27.241719 INFO : End of max read latency training
1003 01:24:27.242178 INFO : Training has run successfully!
1004 01:24:27.247298 1D training succeed
1005 01:24:27.253085 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 01:24:27.300652 Check phy result
1007 01:24:27.301158 INFO : End of initialization
1008 01:24:27.322469 INFO : End of 2D read delay Voltage center optimization
1009 01:24:27.342606 INFO : End of 2D read delay Voltage center optimization
1010 01:24:27.394549 INFO : End of 2D write delay Voltage center optimization
1011 01:24:27.444202 INFO : End of 2D write delay Voltage center optimization
1012 01:24:27.449353 INFO : Training has run successfully!
1013 01:24:27.449859
1014 01:24:27.450328 channel==0
1015 01:24:27.454931 RxClkDly_Margin_A0==88 ps 9
1016 01:24:27.455420 TxDqDly_Margin_A0==98 ps 10
1017 01:24:27.460617 RxClkDly_Margin_A1==88 ps 9
1018 01:24:27.461098 TxDqDly_Margin_A1==98 ps 10
1019 01:24:27.461554 TrainedVREFDQ_A0==74
1020 01:24:27.466207 TrainedVREFDQ_A1==74
1021 01:24:27.466714 VrefDac_Margin_A0==25
1022 01:24:27.467173 DeviceVref_Margin_A0==40
1023 01:24:27.471811 VrefDac_Margin_A1==25
1024 01:24:27.472332 DeviceVref_Margin_A1==40
1025 01:24:27.472780
1026 01:24:27.473223
1027 01:24:27.477498 channel==1
1028 01:24:27.477979 RxClkDly_Margin_A0==98 ps 10
1029 01:24:27.478429 TxDqDly_Margin_A0==98 ps 10
1030 01:24:27.483009 RxClkDly_Margin_A1==98 ps 10
1031 01:24:27.483492 TxDqDly_Margin_A1==88 ps 9
1032 01:24:27.488607 TrainedVREFDQ_A0==77
1033 01:24:27.489094 TrainedVREFDQ_A1==77
1034 01:24:27.489547 VrefDac_Margin_A0==22
1035 01:24:27.494217 DeviceVref_Margin_A0==37
1036 01:24:27.494702 VrefDac_Margin_A1==22
1037 01:24:27.499886 DeviceVref_Margin_A1==37
1038 01:24:27.500405
1039 01:24:27.500857 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 01:24:27.505424
1041 01:24:27.533304 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 01:24:27.533849 2D training succeed
1043 01:24:27.538939 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 01:24:27.544493 auto size-- 65535DDR cs0 size: 2048MB
1045 01:24:27.544978 DDR cs1 size: 2048MB
1046 01:24:27.550097 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 01:24:27.550588 cs0 DataBus test pass
1048 01:24:27.555710 cs1 DataBus test pass
1049 01:24:27.556225 cs0 AddrBus test pass
1050 01:24:27.556678 cs1 AddrBus test pass
1051 01:24:27.557117
1052 01:24:27.561273 100bdlr_step_size ps== 420
1053 01:24:27.561791 result report
1054 01:24:27.566880 boot times 0Enable ddr reg access
1055 01:24:27.572334 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 01:24:27.585902 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 01:24:28.159618 0.0;M3 CHK:0;cm4_sp_mode 0
1058 01:24:28.160278 MVN_1=0x00000000
1059 01:24:28.165013 MVN_2=0x00000000
1060 01:24:28.170877 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 01:24:28.171359 OPS=0x10
1062 01:24:28.171811 ring efuse init
1063 01:24:28.172287 chipver efuse init
1064 01:24:28.176337 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 01:24:28.181977 [0.018960 Inits done]
1066 01:24:28.182449 secure task start!
1067 01:24:28.182895 high task start!
1068 01:24:28.186526 low task start!
1069 01:24:28.187005 run into bl31
1070 01:24:28.193183 NOTICE: BL31: v1.3(release):4fc40b1
1071 01:24:28.201023 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 01:24:28.201516 NOTICE: BL31: G12A normal boot!
1073 01:24:28.226355 NOTICE: BL31: BL33 decompress pass
1074 01:24:28.232077 ERROR: Error initializing runtime service opteed_fast
1075 01:24:29.465011
1076 01:24:29.465677
1077 01:24:29.472836 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 01:24:29.473341
1079 01:24:29.473797 Model: Libre Computer AML-A311D-CC Alta
1080 01:24:29.681737 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 01:24:29.705210 DRAM: 2 GiB (effective 3.8 GiB)
1082 01:24:29.848188 Core: 408 devices, 31 uclasses, devicetree: separate
1083 01:24:29.854020 WDT: Not starting watchdog@f0d0
1084 01:24:29.886260 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 01:24:29.898712 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 01:24:29.903727 ** Bad device specification mmc 0 **
1087 01:24:29.914155 Card did not respond to voltage select! : -110
1088 01:24:29.921702 ** Bad device specification mmc 0 **
1089 01:24:29.922178 Couldn't find partition mmc 0
1090 01:24:29.930150 Card did not respond to voltage select! : -110
1091 01:24:29.935559 ** Bad device specification mmc 0 **
1092 01:24:29.936082 Couldn't find partition mmc 0
1093 01:24:29.940608 Error: could not access storage.
1094 01:24:30.283192 Net: eth0: ethernet@ff3f0000
1095 01:24:30.283759 starting USB...
1096 01:24:30.534882 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 01:24:30.535411 Starting the controller
1098 01:24:30.541867 USB XHCI 1.10
1099 01:24:32.099104 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 01:24:32.107327 scanning usb for storage devices... 0 Storage Device(s) found
1102 01:24:32.158983 Hit any key to stop autoboot: 1
1103 01:24:32.159777 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 01:24:32.160419 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1105 01:24:32.160918 Setting prompt string to ['=>']
1106 01:24:32.161425 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1107 01:24:32.174759 0
1108 01:24:32.175657 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 01:24:32.176207 Sending with 10 millisecond of delay
1111 01:24:33.310972 => setenv autoload no
1112 01:24:33.321795 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 01:24:33.327145 setenv autoload no
1114 01:24:33.327934 Sending with 10 millisecond of delay
1116 01:24:35.124776 => setenv initrd_high 0xffffffff
1117 01:24:35.135599 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1118 01:24:35.136588 setenv initrd_high 0xffffffff
1119 01:24:35.137366 Sending with 10 millisecond of delay
1121 01:24:36.753701 => setenv fdt_high 0xffffffff
1122 01:24:36.764456 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 01:24:36.765032 setenv fdt_high 0xffffffff
1124 01:24:36.765564 Sending with 10 millisecond of delay
1126 01:24:37.057297 => dhcp
1127 01:24:37.068142 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1128 01:24:37.069038 dhcp
1129 01:24:37.069521 Speed: 1000, full duplex
1130 01:24:37.069974 BOOTP broadcast 1
1131 01:24:37.316577 BOOTP broadcast 2
1132 01:24:37.817615 BOOTP broadcast 3
1133 01:24:37.830499 DHCP client bound to address 192.168.6.33 (762 ms)
1134 01:24:37.831270 Sending with 10 millisecond of delay
1136 01:24:39.508129 => setenv serverip 192.168.6.2
1137 01:24:39.519006 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1138 01:24:39.519957 setenv serverip 192.168.6.2
1139 01:24:39.520782 Sending with 10 millisecond of delay
1141 01:24:43.245351 => tftpboot 0x01080000 795771/tftp-deploy-k1_g_ile/kernel/uImage
1142 01:24:43.256251 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1143 01:24:43.257257 tftpboot 0x01080000 795771/tftp-deploy-k1_g_ile/kernel/uImage
1144 01:24:43.257738 Speed: 1000, full duplex
1145 01:24:43.258178 Using ethernet@ff3f0000 device
1146 01:24:43.259295 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1147 01:24:43.264744 Filename '795771/tftp-deploy-k1_g_ile/kernel/uImage'.
1148 01:24:43.268680 Load address: 0x1080000
1149 01:24:47.148110 Loading: *################################################## 37.6 MiB
1150 01:24:47.148790 9.7 MiB/s
1151 01:24:47.149268 done
1152 01:24:47.152471 Bytes transferred = 39424576 (2599240 hex)
1153 01:24:47.153258 Sending with 10 millisecond of delay
1155 01:24:51.840517 => tftpboot 0x08000000 795771/tftp-deploy-k1_g_ile/ramdisk/ramdisk.cpio.gz.uboot
1156 01:24:51.851333 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1157 01:24:51.852301 tftpboot 0x08000000 795771/tftp-deploy-k1_g_ile/ramdisk/ramdisk.cpio.gz.uboot
1158 01:24:51.852780 Speed: 1000, full duplex
1159 01:24:51.853222 Using ethernet@ff3f0000 device
1160 01:24:51.854136 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1161 01:24:51.865986 Filename '795771/tftp-deploy-k1_g_ile/ramdisk/ramdisk.cpio.gz.uboot'.
1162 01:24:51.866484 Load address: 0x8000000
1163 01:24:53.679472 Loading: *################################################# UDP wrong checksum 00000005 000042dc
1164 01:24:58.680017 T UDP wrong checksum 00000005 000042dc
1165 01:25:08.681922 T T UDP wrong checksum 00000005 000042dc
1166 01:25:28.684368 T T T UDP wrong checksum 00000005 000042dc
1167 01:25:48.691001 T T T T
1168 01:25:48.691450 Retry count exceeded; starting again
1170 01:25:48.694752 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1173 01:25:48.695832 end: 2.4 uboot-commands (duration 00:01:54) [common]
1175 01:25:48.696658 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1177 01:25:48.697281 end: 2 uboot-action (duration 00:01:54) [common]
1179 01:25:48.698162 Cleaning after the job
1180 01:25:48.698500 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/ramdisk
1181 01:25:48.703196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/kernel
1182 01:25:48.707612 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/dtb
1183 01:25:48.708630 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/nfsrootfs
1184 01:25:48.741163 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795771/tftp-deploy-k1_g_ile/modules
1185 01:25:48.748226 start: 4.1 power-off (timeout 00:00:30) [common]
1186 01:25:48.748886 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1187 01:25:48.785525 >> OK - accepted request
1188 01:25:48.787545 Returned 0 in 0 seconds
1189 01:25:48.888331 end: 4.1 power-off (duration 00:00:00) [common]
1191 01:25:48.889671 start: 4.2 read-feedback (timeout 00:10:00) [common]
1192 01:25:48.890433 Listened to connection for namespace 'common' for up to 1s
1193 01:25:49.890409 Finalising connection for namespace 'common'
1194 01:25:49.891220 Disconnecting from shell: Finalise
1195 01:25:49.891782 =>
1196 01:25:49.992828 end: 4.2 read-feedback (duration 00:00:01) [common]
1197 01:25:49.993300 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795771
1198 01:25:51.937246 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795771
1199 01:25:51.937923 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.