Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:51:25.288534 lava-dispatcher, installed at version: 2024.01
2 01:51:25.289285 start: 0 validate
3 01:51:25.289727 Start time: 2024-10-03 01:51:25.289697+00:00 (UTC)
4 01:51:25.290270 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:51:25.290796 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:51:25.328791 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:51:25.329406 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 01:51:25.357572 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:51:25.358201 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:51:26.402048 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:51:26.402749 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 01:51:26.446550 validate duration: 1.16
14 01:51:26.447857 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:51:26.448382 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:51:26.448945 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:51:26.449818 Not decompressing ramdisk as can be used compressed.
18 01:51:26.450490 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:51:26.450920 saving as /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/ramdisk/rootfs.cpio.gz
20 01:51:26.451361 total size: 8181887 (7 MB)
21 01:51:26.487020 progress 0 % (0 MB)
22 01:51:26.497363 progress 5 % (0 MB)
23 01:51:26.507569 progress 10 % (0 MB)
24 01:51:26.513776 progress 15 % (1 MB)
25 01:51:26.519179 progress 20 % (1 MB)
26 01:51:26.524960 progress 25 % (1 MB)
27 01:51:26.530307 progress 30 % (2 MB)
28 01:51:26.536099 progress 35 % (2 MB)
29 01:51:26.541421 progress 40 % (3 MB)
30 01:51:26.547111 progress 45 % (3 MB)
31 01:51:26.552376 progress 50 % (3 MB)
32 01:51:26.557975 progress 55 % (4 MB)
33 01:51:26.563211 progress 60 % (4 MB)
34 01:51:26.568988 progress 65 % (5 MB)
35 01:51:26.574231 progress 70 % (5 MB)
36 01:51:26.579744 progress 75 % (5 MB)
37 01:51:26.584949 progress 80 % (6 MB)
38 01:51:26.590541 progress 85 % (6 MB)
39 01:51:26.595707 progress 90 % (7 MB)
40 01:51:26.601269 progress 95 % (7 MB)
41 01:51:26.606048 progress 100 % (7 MB)
42 01:51:26.606695 7 MB downloaded in 0.16 s (50.24 MB/s)
43 01:51:26.607254 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:51:26.608206 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:51:26.608513 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:51:26.608792 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:51:26.609287 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/kernel/Image
49 01:51:26.609539 saving as /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/kernel/Image
50 01:51:26.609752 total size: 169937408 (162 MB)
51 01:51:26.609965 No compression specified
52 01:51:26.641845 progress 0 % (0 MB)
53 01:51:26.746408 progress 5 % (8 MB)
54 01:51:26.851022 progress 10 % (16 MB)
55 01:51:26.956321 progress 15 % (24 MB)
56 01:51:27.062006 progress 20 % (32 MB)
57 01:51:27.165890 progress 25 % (40 MB)
58 01:51:27.269640 progress 30 % (48 MB)
59 01:51:27.374158 progress 35 % (56 MB)
60 01:51:27.480436 progress 40 % (64 MB)
61 01:51:27.587065 progress 45 % (72 MB)
62 01:51:27.694334 progress 50 % (81 MB)
63 01:51:27.801189 progress 55 % (89 MB)
64 01:51:27.909195 progress 60 % (97 MB)
65 01:51:28.017986 progress 65 % (105 MB)
66 01:51:28.126536 progress 70 % (113 MB)
67 01:51:28.236201 progress 75 % (121 MB)
68 01:51:28.344324 progress 80 % (129 MB)
69 01:51:28.451075 progress 85 % (137 MB)
70 01:51:28.556502 progress 90 % (145 MB)
71 01:51:28.661925 progress 95 % (153 MB)
72 01:51:28.767216 progress 100 % (162 MB)
73 01:51:28.767752 162 MB downloaded in 2.16 s (75.10 MB/s)
74 01:51:28.768257 end: 1.2.1 http-download (duration 00:00:02) [common]
76 01:51:28.769076 end: 1.2 download-retry (duration 00:00:02) [common]
77 01:51:28.769398 start: 1.3 download-retry (timeout 00:09:58) [common]
78 01:51:28.769687 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 01:51:28.770194 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:51:28.770477 saving as /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:51:28.770686 total size: 53209 (0 MB)
82 01:51:28.770896 No compression specified
83 01:51:28.810166 progress 61 % (0 MB)
84 01:51:28.811184 progress 100 % (0 MB)
85 01:51:28.811824 0 MB downloaded in 0.04 s (1.23 MB/s)
86 01:51:28.812446 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:51:28.813434 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:51:28.813755 start: 1.4 download-retry (timeout 00:09:58) [common]
90 01:51:28.814072 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 01:51:28.814721 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 01:51:28.815033 saving as /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/modules/modules.tar
93 01:51:28.815292 total size: 27663052 (26 MB)
94 01:51:28.815549 Using unxz to decompress xz
95 01:51:28.848385 progress 0 % (0 MB)
96 01:51:29.035694 progress 5 % (1 MB)
97 01:51:29.245237 progress 10 % (2 MB)
98 01:51:29.444018 progress 15 % (3 MB)
99 01:51:29.684116 progress 20 % (5 MB)
100 01:51:29.889131 progress 25 % (6 MB)
101 01:51:30.091204 progress 30 % (7 MB)
102 01:51:30.293107 progress 35 % (9 MB)
103 01:51:30.493091 progress 40 % (10 MB)
104 01:51:30.684681 progress 45 % (11 MB)
105 01:51:30.895908 progress 50 % (13 MB)
106 01:51:31.106614 progress 55 % (14 MB)
107 01:51:31.310197 progress 60 % (15 MB)
108 01:51:31.498402 progress 65 % (17 MB)
109 01:51:31.706214 progress 70 % (18 MB)
110 01:51:31.906560 progress 75 % (19 MB)
111 01:51:32.106254 progress 80 % (21 MB)
112 01:51:32.312970 progress 85 % (22 MB)
113 01:51:32.532525 progress 90 % (23 MB)
114 01:51:32.734632 progress 95 % (25 MB)
115 01:51:32.937941 progress 100 % (26 MB)
116 01:51:32.949597 26 MB downloaded in 4.13 s (6.38 MB/s)
117 01:51:32.950390 end: 1.4.1 http-download (duration 00:00:04) [common]
119 01:51:32.951425 end: 1.4 download-retry (duration 00:00:04) [common]
120 01:51:32.951770 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 01:51:32.952329 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 01:51:32.952989 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:51:32.953684 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 01:51:32.954963 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x
125 01:51:32.956233 makedir: /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin
126 01:51:32.957140 makedir: /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/tests
127 01:51:32.957961 makedir: /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/results
128 01:51:32.958765 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-add-keys
129 01:51:32.960055 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-add-sources
130 01:51:32.961337 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-background-process-start
131 01:51:32.962580 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-background-process-stop
132 01:51:32.963889 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-common-functions
133 01:51:32.965160 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-echo-ipv4
134 01:51:32.966384 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-install-packages
135 01:51:32.967538 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-installed-packages
136 01:51:32.968774 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-os-build
137 01:51:32.969945 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-probe-channel
138 01:51:32.971114 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-probe-ip
139 01:51:32.972323 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-target-ip
140 01:51:32.973548 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-target-mac
141 01:51:32.974729 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-target-storage
142 01:51:32.975928 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-test-case
143 01:51:32.977225 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-test-event
144 01:51:32.978430 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-test-feedback
145 01:51:32.979618 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-test-raise
146 01:51:32.980882 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-test-reference
147 01:51:32.982060 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-test-runner
148 01:51:32.983370 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-test-set
149 01:51:32.984617 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-test-shell
150 01:51:32.985804 Updating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-install-packages (oe)
151 01:51:32.987067 Updating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/bin/lava-installed-packages (oe)
152 01:51:32.988190 Creating /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/environment
153 01:51:32.988755 LAVA metadata
154 01:51:32.989103 - LAVA_JOB_ID=795988
155 01:51:32.989377 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:51:32.989853 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 01:51:32.991177 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:51:32.991602 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 01:51:32.991860 skipped lava-vland-overlay
160 01:51:32.992225 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:51:32.992550 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 01:51:32.992819 skipped lava-multinode-overlay
163 01:51:32.993120 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:51:32.993435 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 01:51:32.993756 Loading test definitions
166 01:51:32.994109 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 01:51:32.994394 Using /lava-795988 at stage 0
168 01:51:32.995942 uuid=795988_1.5.2.4.1 testdef=None
169 01:51:32.996394 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:51:32.996725 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 01:51:32.999074 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:51:33.000155 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 01:51:33.003143 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:51:33.004234 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 01:51:33.007173 runner path: /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/0/tests/0_dmesg test_uuid 795988_1.5.2.4.1
178 01:51:33.007969 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:51:33.008974 Creating lava-test-runner.conf files
181 01:51:33.009224 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795988/lava-overlay-7pey7d7x/lava-795988/0 for stage 0
182 01:51:33.009766 - 0_dmesg
183 01:51:33.010234 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:51:33.010590 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 01:51:33.040440 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:51:33.040987 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 01:51:33.041315 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:51:33.041647 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:51:33.041967 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 01:51:33.992566 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:51:33.993057 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 01:51:33.993349 extracting modules file /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795988/extract-overlay-ramdisk-qs7too3d/ramdisk
193 01:51:35.943899 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 01:51:35.944449 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
195 01:51:35.944728 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795988/compress-overlay-fz62dht1/overlay-1.5.2.5.tar.gz to ramdisk
196 01:51:35.944942 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795988/compress-overlay-fz62dht1/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795988/extract-overlay-ramdisk-qs7too3d/ramdisk
197 01:51:35.976952 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:51:35.977426 start: 1.5.6 prepare-kernel (timeout 00:09:50) [common]
199 01:51:35.977706 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:50) [common]
200 01:51:35.977939 Converting downloaded kernel to a uImage
201 01:51:35.978257 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/kernel/Image /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/kernel/uImage
202 01:51:37.689652 output: Image Name:
203 01:51:37.690088 output: Created: Thu Oct 3 01:51:35 2024
204 01:51:37.690304 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:51:37.690526 output: Data Size: 169937408 Bytes = 165954.50 KiB = 162.06 MiB
206 01:51:37.690739 output: Load Address: 01080000
207 01:51:37.690943 output: Entry Point: 01080000
208 01:51:37.691141 output:
209 01:51:37.691482 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 01:51:37.691775 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 01:51:37.692093 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 01:51:37.692373 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:51:37.692646 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 01:51:37.692921 Building ramdisk /var/lib/lava/dispatcher/tmp/795988/extract-overlay-ramdisk-qs7too3d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795988/extract-overlay-ramdisk-qs7too3d/ramdisk
215 01:51:43.855607 >> 441386 blocks
216 01:52:02.231585 Adding RAMdisk u-boot header.
217 01:52:02.232265 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795988/extract-overlay-ramdisk-qs7too3d/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795988/extract-overlay-ramdisk-qs7too3d/ramdisk.cpio.gz.uboot
218 01:52:02.799787 output: Image Name:
219 01:52:02.800443 output: Created: Thu Oct 3 01:52:02 2024
220 01:52:02.800851 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:52:02.801244 output: Data Size: 53553013 Bytes = 52297.86 KiB = 51.07 MiB
222 01:52:02.801634 output: Load Address: 00000000
223 01:52:02.802022 output: Entry Point: 00000000
224 01:52:02.802406 output:
225 01:52:02.803355 rename /var/lib/lava/dispatcher/tmp/795988/extract-overlay-ramdisk-qs7too3d/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/ramdisk/ramdisk.cpio.gz.uboot
226 01:52:02.804083 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 01:52:02.804624 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
228 01:52:02.805137 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 01:52:02.805582 No LXC device requested
230 01:52:02.806066 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:52:02.806563 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 01:52:02.807042 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:52:02.807456 Checking files for TFTP limit of 4294967296 bytes.
234 01:52:02.810095 end: 1 tftp-deploy (duration 00:00:36) [common]
235 01:52:02.810661 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:52:02.811177 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:52:02.811666 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:52:02.812195 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:52:02.812718 Using kernel file from prepare-kernel: 795988/tftp-deploy-ydjf1fqv/kernel/uImage
240 01:52:02.813311 substitutions:
241 01:52:02.813711 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:52:02.814107 - {DTB_ADDR}: 0x01070000
243 01:52:02.814499 - {DTB}: 795988/tftp-deploy-ydjf1fqv/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:52:02.814890 - {INITRD}: 795988/tftp-deploy-ydjf1fqv/ramdisk/ramdisk.cpio.gz.uboot
245 01:52:02.815280 - {KERNEL_ADDR}: 0x01080000
246 01:52:02.815668 - {KERNEL}: 795988/tftp-deploy-ydjf1fqv/kernel/uImage
247 01:52:02.816086 - {LAVA_MAC}: None
248 01:52:02.816513 - {PRESEED_CONFIG}: None
249 01:52:02.816906 - {PRESEED_LOCAL}: None
250 01:52:02.817292 - {RAMDISK_ADDR}: 0x08000000
251 01:52:02.817674 - {RAMDISK}: 795988/tftp-deploy-ydjf1fqv/ramdisk/ramdisk.cpio.gz.uboot
252 01:52:02.818064 - {ROOT_PART}: None
253 01:52:02.818449 - {ROOT}: None
254 01:52:02.818834 - {SERVER_IP}: 192.168.6.2
255 01:52:02.819223 - {TEE_ADDR}: 0x83000000
256 01:52:02.819607 - {TEE}: None
257 01:52:02.820010 Parsed boot commands:
258 01:52:02.820390 - setenv autoload no
259 01:52:02.820774 - setenv initrd_high 0xffffffff
260 01:52:02.821158 - setenv fdt_high 0xffffffff
261 01:52:02.821538 - dhcp
262 01:52:02.821918 - setenv serverip 192.168.6.2
263 01:52:02.822299 - tftpboot 0x01080000 795988/tftp-deploy-ydjf1fqv/kernel/uImage
264 01:52:02.822682 - tftpboot 0x08000000 795988/tftp-deploy-ydjf1fqv/ramdisk/ramdisk.cpio.gz.uboot
265 01:52:02.823063 - tftpboot 0x01070000 795988/tftp-deploy-ydjf1fqv/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:52:02.823445 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:52:02.823833 - bootm 0x01080000 0x08000000 0x01070000
268 01:52:02.824336 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:52:02.825794 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:52:02.826229 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:52:02.840161 Setting prompt string to ['lava-test: # ']
273 01:52:02.841640 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:52:02.842216 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:52:02.842746 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:52:02.843251 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:52:02.844407 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:52:02.880878 >> OK - accepted request
279 01:52:02.883024 Returned 0 in 0 seconds
280 01:52:02.984158 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:52:02.985780 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:52:02.986330 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:52:02.986823 Setting prompt string to ['Hit any key to stop autoboot']
285 01:52:02.987267 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:52:02.988867 Trying 192.168.56.21...
287 01:52:02.989348 Connected to conserv1.
288 01:52:02.989763 Escape character is '^]'.
289 01:52:02.990181
290 01:52:02.990604 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:52:02.991024
292 01:52:10.128010 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:52:10.128436 bl2_stage_init 0x01
294 01:52:10.128670 bl2_stage_init 0x81
295 01:52:10.133462 hw id: 0x0000 - pwm id 0x01
296 01:52:10.133762 bl2_stage_init 0xc1
297 01:52:10.133973 bl2_stage_init 0x02
298 01:52:10.134185
299 01:52:10.139099 L0:00000000
300 01:52:10.139390 L1:00000703
301 01:52:10.139601 L2:00008067
302 01:52:10.139806 L3:15000000
303 01:52:10.140036 S1:00000000
304 01:52:10.144750 B2:20282000
305 01:52:10.145035 B1:a0f83180
306 01:52:10.145247
307 01:52:10.145452 TE: 68501
308 01:52:10.145653
309 01:52:10.150318 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:52:10.150590
311 01:52:10.150797 Board ID = 1
312 01:52:10.155819 Set cpu clk to 24M
313 01:52:10.156132 Set clk81 to 24M
314 01:52:10.156529 Use GP1_pll as DSU clk.
315 01:52:10.161486 DSU clk: 1200 Mhz
316 01:52:10.161913 CPU clk: 1200 MHz
317 01:52:10.162306 Set clk81 to 166.6M
318 01:52:10.167125 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:52:10.173388 board id: 1
320 01:52:10.177403 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:52:10.188870 fw parse done
322 01:52:10.194324 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:52:10.236820 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:52:10.248514 PIEI prepare done
325 01:52:10.249155 fastboot data load
326 01:52:10.249561 fastboot data verify
327 01:52:10.254604 verify result: 266
328 01:52:10.259808 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:52:10.260448 LPDDR4 probe
330 01:52:10.260833 ddr clk to 1584MHz
331 01:52:10.268324 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:52:10.304691
333 01:52:10.305124 dmc_version 0001
334 01:52:10.310851 Check phy result
335 01:52:10.317568 INFO : End of CA training
336 01:52:10.318118 INFO : End of initialization
337 01:52:10.323185 INFO : Training has run successfully!
338 01:52:10.323624 Check phy result
339 01:52:10.328699 INFO : End of initialization
340 01:52:10.329135 INFO : End of read enable training
341 01:52:10.334381 INFO : End of fine write leveling
342 01:52:10.340192 INFO : End of Write leveling coarse delay
343 01:52:10.340764 INFO : Training has run successfully!
344 01:52:10.341462 Check phy result
345 01:52:10.345492 INFO : End of initialization
346 01:52:10.345965 INFO : End of read dq deskew training
347 01:52:10.351353 INFO : End of MPR read delay center optimization
348 01:52:10.356799 INFO : End of write delay center optimization
349 01:52:10.362452 INFO : End of read delay center optimization
350 01:52:10.362996 INFO : End of max read latency training
351 01:52:10.368028 INFO : Training has run successfully!
352 01:52:10.368609 1D training succeed
353 01:52:10.377154 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:52:10.424701 Check phy result
355 01:52:10.425193 INFO : End of initialization
356 01:52:10.447024 INFO : End of 2D read delay Voltage center optimization
357 01:52:10.465341 INFO : End of 2D read delay Voltage center optimization
358 01:52:10.517248 INFO : End of 2D write delay Voltage center optimization
359 01:52:10.567438 INFO : End of 2D write delay Voltage center optimization
360 01:52:10.572878 INFO : Training has run successfully!
361 01:52:10.573477
362 01:52:10.573941 channel==0
363 01:52:10.578725 RxClkDly_Margin_A0==88 ps 9
364 01:52:10.579335 TxDqDly_Margin_A0==98 ps 10
365 01:52:10.581815 RxClkDly_Margin_A1==78 ps 8
366 01:52:10.582400 TxDqDly_Margin_A1==98 ps 10
367 01:52:10.587347 TrainedVREFDQ_A0==74
368 01:52:10.587932 TrainedVREFDQ_A1==75
369 01:52:10.592976 VrefDac_Margin_A0==24
370 01:52:10.593548 DeviceVref_Margin_A0==40
371 01:52:10.593991 VrefDac_Margin_A1==23
372 01:52:10.598501 DeviceVref_Margin_A1==39
373 01:52:10.598894
374 01:52:10.599299
375 01:52:10.599754 channel==1
376 01:52:10.600245 RxClkDly_Margin_A0==78 ps 8
377 01:52:10.604173 TxDqDly_Margin_A0==98 ps 10
378 01:52:10.604797 RxClkDly_Margin_A1==78 ps 8
379 01:52:10.609860 TxDqDly_Margin_A1==88 ps 9
380 01:52:10.610493 TrainedVREFDQ_A0==78
381 01:52:10.610950 TrainedVREFDQ_A1==75
382 01:52:10.615887 VrefDac_Margin_A0==22
383 01:52:10.616561 DeviceVref_Margin_A0==36
384 01:52:10.621155 VrefDac_Margin_A1==22
385 01:52:10.621746 DeviceVref_Margin_A1==39
386 01:52:10.622211
387 01:52:10.627901 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:52:10.628516
389 01:52:10.654354 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
390 01:52:10.660273 2D training succeed
391 01:52:10.665868 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:52:10.666274 auto size-- 65535DDR cs0 size: 2048MB
393 01:52:10.671243 DDR cs1 size: 2048MB
394 01:52:10.671608 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:52:10.676781 cs0 DataBus test pass
396 01:52:10.677166 cs1 DataBus test pass
397 01:52:10.677394 cs0 AddrBus test pass
398 01:52:10.682407 cs1 AddrBus test pass
399 01:52:10.682762
400 01:52:10.682973 100bdlr_step_size ps== 464
401 01:52:10.683181 result report
402 01:52:10.687993 boot times 0Enable ddr reg access
403 01:52:10.694671 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:52:10.708568 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:52:11.364176 bl2z: ptr: 05129330, size: 00001e40
406 01:52:11.372256 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:52:11.372797 MVN_1=0x00000000
408 01:52:11.373246 MVN_2=0x00000000
409 01:52:11.383722 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:52:11.384277 OPS=0x04
411 01:52:11.384726 ring efuse init
412 01:52:11.389389 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:52:11.389905 [0.017319 Inits done]
414 01:52:11.390342 secure task start!
415 01:52:11.396212 high task start!
416 01:52:11.396715 low task start!
417 01:52:11.397153 run into bl31
418 01:52:11.405230 NOTICE: BL31: v1.3(release):4fc40b1
419 01:52:11.412114 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:52:11.412632 NOTICE: BL31: G12A normal boot!
421 01:52:11.428572 NOTICE: BL31: BL33 decompress pass
422 01:52:11.433789 ERROR: Error initializing runtime service opteed_fast
423 01:52:14.127292 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:52:14.127948 bl2_stage_init 0x01
425 01:52:14.128451 bl2_stage_init 0x81
426 01:52:14.132832 hw id: 0x0000 - pwm id 0x01
427 01:52:14.133346 bl2_stage_init 0xc1
428 01:52:14.133783 bl2_stage_init 0x02
429 01:52:14.134215
430 01:52:14.138418 L0:00000000
431 01:52:14.138926 L1:00000703
432 01:52:14.139357 L2:00008067
433 01:52:14.139783 L3:15000000
434 01:52:14.140252 S1:00000000
435 01:52:14.144048 B2:20282000
436 01:52:14.144552 B1:a0f83180
437 01:52:14.144983
438 01:52:14.145414 TE: 68899
439 01:52:14.145847
440 01:52:14.149628 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:52:14.150131
442 01:52:14.155258 Board ID = 1
443 01:52:14.155763 Set cpu clk to 24M
444 01:52:14.156234 Set clk81 to 24M
445 01:52:14.160812 Use GP1_pll as DSU clk.
446 01:52:14.161331 DSU clk: 1200 Mhz
447 01:52:14.161760 CPU clk: 1200 MHz
448 01:52:14.162185 Set clk81 to 166.6M
449 01:52:14.172030 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:52:14.172555 board id: 1
451 01:52:14.177495 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:52:14.189380 fw parse done
453 01:52:14.195341 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:52:14.237896 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:52:14.249757 PIEI prepare done
456 01:52:14.250304 fastboot data load
457 01:52:14.250741 fastboot data verify
458 01:52:14.255232 verify result: 266
459 01:52:14.260828 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:52:14.261366 LPDDR4 probe
461 01:52:14.261810 ddr clk to 1584MHz
462 01:52:14.267941 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 01:52:14.305891
464 01:52:14.306437 dmc_version 0001
465 01:52:14.313221 Check phy result
466 01:52:14.319480 INFO : End of CA training
467 01:52:14.320022 INFO : End of initialization
468 01:52:14.325153 INFO : Training has run successfully!
469 01:52:14.325660 Check phy result
470 01:52:14.330797 INFO : End of initialization
471 01:52:14.331400 INFO : End of read enable training
472 01:52:14.336339 INFO : End of fine write leveling
473 01:52:14.341980 INFO : End of Write leveling coarse delay
474 01:52:14.342515 INFO : Training has run successfully!
475 01:52:14.342954 Check phy result
476 01:52:14.347565 INFO : End of initialization
477 01:52:14.348130 INFO : End of read dq deskew training
478 01:52:14.353191 INFO : End of MPR read delay center optimization
479 01:52:14.358746 INFO : End of write delay center optimization
480 01:52:14.364384 INFO : End of read delay center optimization
481 01:52:14.364939 INFO : End of max read latency training
482 01:52:14.369975 INFO : Training has run successfully!
483 01:52:14.370520 1D training succeed
484 01:52:14.378455 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 01:52:14.426618 Check phy result
486 01:52:14.427196 INFO : End of initialization
487 01:52:14.454051 INFO : End of 2D read delay Voltage center optimization
488 01:52:14.478091 INFO : End of 2D read delay Voltage center optimization
489 01:52:14.535490 INFO : End of 2D write delay Voltage center optimization
490 01:52:14.589612 INFO : End of 2D write delay Voltage center optimization
491 01:52:14.595108 INFO : Training has run successfully!
492 01:52:14.595654
493 01:52:14.596138 channel==0
494 01:52:14.600794 RxClkDly_Margin_A0==78 ps 8
495 01:52:14.601336 TxDqDly_Margin_A0==98 ps 10
496 01:52:14.606304 RxClkDly_Margin_A1==78 ps 8
497 01:52:14.606834 TxDqDly_Margin_A1==88 ps 9
498 01:52:14.607273 TrainedVREFDQ_A0==74
499 01:52:14.611900 TrainedVREFDQ_A1==75
500 01:52:14.612477 VrefDac_Margin_A0==23
501 01:52:14.612914 DeviceVref_Margin_A0==40
502 01:52:14.617524 VrefDac_Margin_A1==23
503 01:52:14.618062 DeviceVref_Margin_A1==39
504 01:52:14.618502
505 01:52:14.618933
506 01:52:14.619367 channel==1
507 01:52:14.623117 RxClkDly_Margin_A0==88 ps 9
508 01:52:14.623658 TxDqDly_Margin_A0==98 ps 10
509 01:52:14.628855 RxClkDly_Margin_A1==88 ps 9
510 01:52:14.629448 TxDqDly_Margin_A1==88 ps 9
511 01:52:14.634323 TrainedVREFDQ_A0==78
512 01:52:14.634870 TrainedVREFDQ_A1==75
513 01:52:14.635315 VrefDac_Margin_A0==23
514 01:52:14.639934 DeviceVref_Margin_A0==36
515 01:52:14.640513 VrefDac_Margin_A1==22
516 01:52:14.645566 DeviceVref_Margin_A1==39
517 01:52:14.646099
518 01:52:14.646544 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 01:52:14.646975
520 01:52:14.679121 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000018 00000019 00000015 00000017 00000015 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 01:52:14.679745 2D training succeed
522 01:52:14.684807 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 01:52:14.690319 auto size-- 65535DDR cs0 size: 2048MB
524 01:52:14.690866 DDR cs1 size: 2048MB
525 01:52:14.695939 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 01:52:14.696513 cs0 DataBus test pass
527 01:52:14.701554 cs1 DataBus test pass
528 01:52:14.702089 cs0 AddrBus test pass
529 01:52:14.702526 cs1 AddrBus test pass
530 01:52:14.702954
531 01:52:14.707089 100bdlr_step_size ps== 471
532 01:52:14.707634 result report
533 01:52:14.712700 boot times 0Enable ddr reg access
534 01:52:14.716892 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 01:52:14.730854 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 01:52:15.389530 bl2z: ptr: 05129330, size: 00001e40
537 01:52:15.398086 0.0;M3 CHK:0;cm4_sp_mode 0
538 01:52:15.398464 MVN_1=0x00000000
539 01:52:15.398712 MVN_2=0x00000000
540 01:52:15.409518 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 01:52:15.409896 OPS=0x04
542 01:52:15.410145 ring efuse init
543 01:52:15.412512 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 01:52:15.418540 [0.017354 Inits done]
545 01:52:15.418887 secure task start!
546 01:52:15.419131 high task start!
547 01:52:15.419362 low task start!
548 01:52:15.422000 run into bl31
549 01:52:15.431367 NOTICE: BL31: v1.3(release):4fc40b1
550 01:52:15.439083 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 01:52:15.439440 NOTICE: BL31: G12A normal boot!
552 01:52:15.454824 NOTICE: BL31: BL33 decompress pass
553 01:52:15.459558 ERROR: Error initializing runtime service opteed_fast
554 01:52:16.833163 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 01:52:16.833808 bl2_stage_init 0x01
556 01:52:16.834274 bl2_stage_init 0x81
557 01:52:16.838747 hw id: 0x0000 - pwm id 0x01
558 01:52:16.839273 bl2_stage_init 0xc1
559 01:52:16.839728 bl2_stage_init 0x02
560 01:52:16.840221
561 01:52:16.844368 L0:00000000
562 01:52:16.844890 L1:00000703
563 01:52:16.845340 L2:00008067
564 01:52:16.845783 L3:15000000
565 01:52:16.846219 S1:00000000
566 01:52:16.849908 B2:20282000
567 01:52:16.850423 B1:a0f83180
568 01:52:16.850869
569 01:52:16.851316 TE: 73326
570 01:52:16.851760
571 01:52:16.855526 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 01:52:16.856085
573 01:52:16.856549 Board ID = 1
574 01:52:16.861184 Set cpu clk to 24M
575 01:52:16.861706 Set clk81 to 24M
576 01:52:16.862158 Use GP1_pll as DSU clk.
577 01:52:16.866730 DSU clk: 1200 Mhz
578 01:52:16.867251 CPU clk: 1200 MHz
579 01:52:16.867699 Set clk81 to 166.6M
580 01:52:16.872344 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 01:52:16.877894 board id: 1
582 01:52:16.882428 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 01:52:16.894187 fw parse done
584 01:52:16.899096 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 01:52:16.942335 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 01:52:16.953630 PIEI prepare done
587 01:52:16.954172 fastboot data load
588 01:52:16.954635 fastboot data verify
589 01:52:16.959219 verify result: 266
590 01:52:16.964737 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 01:52:16.965260 LPDDR4 probe
592 01:52:16.965712 ddr clk to 1584MHz
593 01:52:16.972686 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 01:52:17.010056
595 01:52:17.010612 dmc_version 0001
596 01:52:17.015786 Check phy result
597 01:52:17.022605 INFO : End of CA training
598 01:52:17.023125 INFO : End of initialization
599 01:52:17.028204 INFO : Training has run successfully!
600 01:52:17.028731 Check phy result
601 01:52:17.033816 INFO : End of initialization
602 01:52:17.034339 INFO : End of read enable training
603 01:52:17.037316 INFO : End of fine write leveling
604 01:52:17.042811 INFO : End of Write leveling coarse delay
605 01:52:17.048386 INFO : Training has run successfully!
606 01:52:17.048902 Check phy result
607 01:52:17.049356 INFO : End of initialization
608 01:52:17.054000 INFO : End of read dq deskew training
609 01:52:17.057461 INFO : End of MPR read delay center optimization
610 01:52:17.062986 INFO : End of write delay center optimization
611 01:52:17.068582 INFO : End of read delay center optimization
612 01:52:17.069099 INFO : End of max read latency training
613 01:52:17.074185 INFO : Training has run successfully!
614 01:52:17.074710 1D training succeed
615 01:52:17.082286 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 01:52:17.129847 Check phy result
617 01:52:17.130397 INFO : End of initialization
618 01:52:17.151199 INFO : End of 2D read delay Voltage center optimization
619 01:52:17.170467 INFO : End of 2D read delay Voltage center optimization
620 01:52:17.222487 INFO : End of 2D write delay Voltage center optimization
621 01:52:17.272449 INFO : End of 2D write delay Voltage center optimization
622 01:52:17.278029 INFO : Training has run successfully!
623 01:52:17.278553
624 01:52:17.279008 channel==0
625 01:52:17.283642 RxClkDly_Margin_A0==88 ps 9
626 01:52:17.284222 TxDqDly_Margin_A0==98 ps 10
627 01:52:17.286861 RxClkDly_Margin_A1==88 ps 9
628 01:52:17.287374 TxDqDly_Margin_A1==98 ps 10
629 01:52:17.292448 TrainedVREFDQ_A0==74
630 01:52:17.292965 TrainedVREFDQ_A1==74
631 01:52:17.298055 VrefDac_Margin_A0==23
632 01:52:17.298568 DeviceVref_Margin_A0==40
633 01:52:17.299019 VrefDac_Margin_A1==23
634 01:52:17.303644 DeviceVref_Margin_A1==40
635 01:52:17.304191
636 01:52:17.304649
637 01:52:17.305096 channel==1
638 01:52:17.305533 RxClkDly_Margin_A0==78 ps 8
639 01:52:17.307143 TxDqDly_Margin_A0==98 ps 10
640 01:52:17.312714 RxClkDly_Margin_A1==78 ps 8
641 01:52:17.313238 TxDqDly_Margin_A1==88 ps 9
642 01:52:17.313691 TrainedVREFDQ_A0==78
643 01:52:17.318316 TrainedVREFDQ_A1==77
644 01:52:17.318833 VrefDac_Margin_A0==22
645 01:52:17.323858 DeviceVref_Margin_A0==36
646 01:52:17.324409 VrefDac_Margin_A1==22
647 01:52:17.324857 DeviceVref_Margin_A1==37
648 01:52:17.325296
649 01:52:17.329522 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 01:52:17.330056
651 01:52:17.362981 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 01:52:17.363616 2D training succeed
653 01:52:17.368610 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 01:52:17.374188 auto size-- 65535DDR cs0 size: 2048MB
655 01:52:17.374722 DDR cs1 size: 2048MB
656 01:52:17.379852 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 01:52:17.380411 cs0 DataBus test pass
658 01:52:17.380872 cs1 DataBus test pass
659 01:52:17.385398 cs0 AddrBus test pass
660 01:52:17.385919 cs1 AddrBus test pass
661 01:52:17.386373
662 01:52:17.390985 100bdlr_step_size ps== 478
663 01:52:17.391518 result report
664 01:52:17.391968 boot times 0Enable ddr reg access
665 01:52:17.400092 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 01:52:17.413626 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 01:52:18.068159 bl2z: ptr: 05129330, size: 00001e40
668 01:52:18.076777 0.0;M3 CHK:0;cm4_sp_mode 0
669 01:52:18.077379 MVN_1=0x00000000
670 01:52:18.077840 MVN_2=0x00000000
671 01:52:18.088253 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 01:52:18.088847 OPS=0x04
673 01:52:18.089321 ring efuse init
674 01:52:18.091301 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 01:52:18.097113 [0.017319 Inits done]
676 01:52:18.097640 secure task start!
677 01:52:18.098091 high task start!
678 01:52:18.098533 low task start!
679 01:52:18.100630 run into bl31
680 01:52:18.110028 NOTICE: BL31: v1.3(release):4fc40b1
681 01:52:18.116824 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 01:52:18.117363 NOTICE: BL31: G12A normal boot!
683 01:52:18.133378 NOTICE: BL31: BL33 decompress pass
684 01:52:18.139069 ERROR: Error initializing runtime service opteed_fast
685 01:52:18.934327
686 01:52:18.934734
687 01:52:18.939921 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 01:52:18.940792
689 01:52:18.942635 Model: Libre Computer AML-S905D3-CC Solitude
690 01:52:19.089240 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 01:52:19.105749 DRAM: 2 GiB (effective 3.8 GiB)
692 01:52:19.206684 Core: 406 devices, 33 uclasses, devicetree: separate
693 01:52:19.212015 WDT: Not starting watchdog@f0d0
694 01:52:19.237503 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 01:52:19.249695 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 01:52:19.254731 ** Bad device specification mmc 0 **
697 01:52:19.264709 Card did not respond to voltage select! : -110
698 01:52:19.271506 ** Bad device specification mmc 0 **
699 01:52:19.271840 Couldn't find partition mmc 0
700 01:52:19.280699 Card did not respond to voltage select! : -110
701 01:52:19.286295 ** Bad device specification mmc 0 **
702 01:52:19.286619 Couldn't find partition mmc 0
703 01:52:19.291276 Error: could not access storage.
704 01:52:19.588735 Net: eth0: ethernet@ff3f0000
705 01:52:19.589169 starting USB...
706 01:52:19.833561 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 01:52:19.833987 Starting the controller
708 01:52:19.839492 USB XHCI 1.10
709 01:52:21.394459 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 01:52:21.401926 scanning usb for storage devices... 0 Storage Device(s) found
712 01:52:21.453550 Hit any key to stop autoboot: 1
713 01:52:21.454411 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
714 01:52:21.454871 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 01:52:21.455135 Setting prompt string to ['=>']
716 01:52:21.455399 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 01:52:21.467933 0
718 01:52:21.468968 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 01:52:21.570287 => setenv autoload no
721 01:52:21.571038 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 01:52:21.576726 setenv autoload no
724 01:52:21.678338 => setenv initrd_high 0xffffffff
725 01:52:21.679345 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 01:52:21.683520 setenv initrd_high 0xffffffff
728 01:52:21.785127 => setenv fdt_high 0xffffffff
729 01:52:21.786094 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 01:52:21.789513 setenv fdt_high 0xffffffff
732 01:52:21.891111 => dhcp
733 01:52:21.891851 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 01:52:21.895112 dhcp
735 01:52:22.901285 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 01:52:22.901931 Speed: 1000, full duplex
737 01:52:22.902393 BOOTP broadcast 1
738 01:52:23.149634 BOOTP broadcast 2
739 01:52:23.651188 BOOTP broadcast 3
740 01:52:24.652297 BOOTP broadcast 4
741 01:52:26.652756 BOOTP broadcast 5
742 01:52:26.667109 DHCP client bound to address 192.168.6.12 (3765 ms)
744 01:52:26.769013 => setenv serverip 192.168.6.2
745 01:52:26.769917 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 01:52:26.773848 setenv serverip 192.168.6.2
748 01:52:26.875789 => tftpboot 0x01080000 795988/tftp-deploy-ydjf1fqv/kernel/uImage
749 01:52:26.877445 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 01:52:26.884127 tftpboot 0x01080000 795988/tftp-deploy-ydjf1fqv/kernel/uImage
751 01:52:26.884986 Speed: 1000, full duplex
752 01:52:26.885644 Using ethernet@ff3f0000 device
753 01:52:26.889506 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 01:52:26.895013 Filename '795988/tftp-deploy-ydjf1fqv/kernel/uImage'.
755 01:52:26.899037 Load address: 0x1080000
756 01:52:37.824427 Loading: *################T ###
757 01:52:37.825068 TFTP error: trying to overwrite reserved memory...
759 01:52:37.826402 end: 2.4.3 bootloader-commands (duration 00:00:16) [common]
762 01:52:37.828194 end: 2.4 uboot-commands (duration 00:00:35) [common]
764 01:52:37.829530 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
766 01:52:37.830520 end: 2 uboot-action (duration 00:00:35) [common]
768 01:52:37.832028 Cleaning after the job
769 01:52:37.832582 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/ramdisk
770 01:52:37.862297 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/kernel
771 01:52:37.873424 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/dtb
772 01:52:37.874167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795988/tftp-deploy-ydjf1fqv/modules
773 01:52:37.881858 start: 4.1 power-off (timeout 00:00:30) [common]
774 01:52:37.882468 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
775 01:52:37.914708 >> OK - accepted request
776 01:52:37.917436 Returned 0 in 0 seconds
777 01:52:38.018382 end: 4.1 power-off (duration 00:00:00) [common]
779 01:52:38.020124 start: 4.2 read-feedback (timeout 00:10:00) [common]
780 01:52:38.021226 Listened to connection for namespace 'common' for up to 1s
781 01:52:39.021018 Finalising connection for namespace 'common'
782 01:52:39.021741 Disconnecting from shell: Finalise
783 01:52:39.022229 =>
784 01:52:39.123223 end: 4.2 read-feedback (duration 00:00:01) [common]
785 01:52:39.123911 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795988
786 01:52:39.436292 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795988
787 01:52:39.436922 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.