Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:20:33.905173 lava-dispatcher, installed at version: 2024.01
2 01:20:33.905991 start: 0 validate
3 01:20:33.906514 Start time: 2024-10-03 01:20:33.906484+00:00 (UTC)
4 01:20:33.907088 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:20:33.907647 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:20:33.946185 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:20:33.946801 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fkernel%2FImage exists
8 01:20:33.976176 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:20:33.976825 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:20:35.025301 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:20:35.025846 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fmodules.tar.xz exists
12 01:20:35.069127 validate duration: 1.16
14 01:20:35.069936 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:20:35.070258 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:20:35.070543 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:20:35.071112 Not decompressing ramdisk as can be used compressed.
18 01:20:35.071523 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:20:35.071757 saving as /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/ramdisk/rootfs.cpio.gz
20 01:20:35.072023 total size: 8181887 (7 MB)
21 01:20:35.113444 progress 0 % (0 MB)
22 01:20:35.123211 progress 5 % (0 MB)
23 01:20:35.133445 progress 10 % (0 MB)
24 01:20:35.144170 progress 15 % (1 MB)
25 01:20:35.149405 progress 20 % (1 MB)
26 01:20:35.154961 progress 25 % (1 MB)
27 01:20:35.160170 progress 30 % (2 MB)
28 01:20:35.165681 progress 35 % (2 MB)
29 01:20:35.170860 progress 40 % (3 MB)
30 01:20:35.176397 progress 45 % (3 MB)
31 01:20:35.181532 progress 50 % (3 MB)
32 01:20:35.186999 progress 55 % (4 MB)
33 01:20:35.192119 progress 60 % (4 MB)
34 01:20:35.197612 progress 65 % (5 MB)
35 01:20:35.202615 progress 70 % (5 MB)
36 01:20:35.208097 progress 75 % (5 MB)
37 01:20:35.213206 progress 80 % (6 MB)
38 01:20:35.218558 progress 85 % (6 MB)
39 01:20:35.223363 progress 90 % (7 MB)
40 01:20:35.228471 progress 95 % (7 MB)
41 01:20:35.233239 progress 100 % (7 MB)
42 01:20:35.233876 7 MB downloaded in 0.16 s (48.22 MB/s)
43 01:20:35.234416 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:20:35.235304 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:20:35.235595 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:20:35.235869 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:20:35.236364 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/kernel/Image
49 01:20:35.236634 saving as /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/kernel/Image
50 01:20:35.236844 total size: 39424512 (37 MB)
51 01:20:35.237055 No compression specified
52 01:20:35.268726 progress 0 % (0 MB)
53 01:20:35.295447 progress 5 % (1 MB)
54 01:20:35.321852 progress 10 % (3 MB)
55 01:20:35.346810 progress 15 % (5 MB)
56 01:20:35.370603 progress 20 % (7 MB)
57 01:20:35.394749 progress 25 % (9 MB)
58 01:20:35.418586 progress 30 % (11 MB)
59 01:20:35.442749 progress 35 % (13 MB)
60 01:20:35.466792 progress 40 % (15 MB)
61 01:20:35.490834 progress 45 % (16 MB)
62 01:20:35.514785 progress 50 % (18 MB)
63 01:20:35.538745 progress 55 % (20 MB)
64 01:20:35.562810 progress 60 % (22 MB)
65 01:20:35.586654 progress 65 % (24 MB)
66 01:20:35.610599 progress 70 % (26 MB)
67 01:20:35.634358 progress 75 % (28 MB)
68 01:20:35.657949 progress 80 % (30 MB)
69 01:20:35.681504 progress 85 % (31 MB)
70 01:20:35.705181 progress 90 % (33 MB)
71 01:20:35.729493 progress 95 % (35 MB)
72 01:20:35.753375 progress 100 % (37 MB)
73 01:20:35.753989 37 MB downloaded in 0.52 s (72.71 MB/s)
74 01:20:35.754532 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:20:35.755420 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:20:35.755736 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:20:35.756057 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:20:35.756595 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:20:35.756913 saving as /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:20:35.757144 total size: 54703 (0 MB)
82 01:20:35.757378 No compression specified
83 01:20:35.801215 progress 59 % (0 MB)
84 01:20:35.802150 progress 100 % (0 MB)
85 01:20:35.802805 0 MB downloaded in 0.05 s (1.14 MB/s)
86 01:20:35.803340 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:20:35.804211 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:20:35.804484 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:20:35.804753 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:20:35.805229 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/modules.tar.xz
92 01:20:35.805483 saving as /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/modules/modules.tar
93 01:20:35.805690 total size: 11756024 (11 MB)
94 01:20:35.805907 Using unxz to decompress xz
95 01:20:35.837981 progress 0 % (0 MB)
96 01:20:35.910277 progress 5 % (0 MB)
97 01:20:35.991774 progress 10 % (1 MB)
98 01:20:36.083623 progress 15 % (1 MB)
99 01:20:36.166760 progress 20 % (2 MB)
100 01:20:36.250912 progress 25 % (2 MB)
101 01:20:36.333196 progress 30 % (3 MB)
102 01:20:36.414749 progress 35 % (3 MB)
103 01:20:36.494922 progress 40 % (4 MB)
104 01:20:36.573192 progress 45 % (5 MB)
105 01:20:36.653245 progress 50 % (5 MB)
106 01:20:36.731880 progress 55 % (6 MB)
107 01:20:36.818518 progress 60 % (6 MB)
108 01:20:36.907309 progress 65 % (7 MB)
109 01:20:36.991520 progress 70 % (7 MB)
110 01:20:37.087263 progress 75 % (8 MB)
111 01:20:37.183305 progress 80 % (9 MB)
112 01:20:37.261586 progress 85 % (9 MB)
113 01:20:37.339233 progress 90 % (10 MB)
114 01:20:37.419329 progress 95 % (10 MB)
115 01:20:37.499597 progress 100 % (11 MB)
116 01:20:37.514195 11 MB downloaded in 1.71 s (6.56 MB/s)
117 01:20:37.514966 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:20:37.516914 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:20:37.517547 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 01:20:37.518150 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 01:20:37.518721 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:20:37.519295 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 01:20:37.520529 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7
125 01:20:37.521526 makedir: /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin
126 01:20:37.522272 makedir: /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/tests
127 01:20:37.522993 makedir: /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/results
128 01:20:37.523680 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-add-keys
129 01:20:37.524787 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-add-sources
130 01:20:37.525858 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-background-process-start
131 01:20:37.526950 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-background-process-stop
132 01:20:37.528092 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-common-functions
133 01:20:37.529198 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-echo-ipv4
134 01:20:37.530264 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-install-packages
135 01:20:37.531380 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-installed-packages
136 01:20:37.532454 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-os-build
137 01:20:37.533541 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-probe-channel
138 01:20:37.534605 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-probe-ip
139 01:20:37.535699 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-target-ip
140 01:20:37.536811 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-target-mac
141 01:20:37.537896 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-target-storage
142 01:20:37.539027 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-test-case
143 01:20:37.540296 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-test-event
144 01:20:37.541372 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-test-feedback
145 01:20:37.542471 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-test-raise
146 01:20:37.543524 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-test-reference
147 01:20:37.544621 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-test-runner
148 01:20:37.545676 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-test-set
149 01:20:37.546729 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-test-shell
150 01:20:37.547782 Updating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-install-packages (oe)
151 01:20:37.549054 Updating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/bin/lava-installed-packages (oe)
152 01:20:37.550086 Creating /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/environment
153 01:20:37.550923 LAVA metadata
154 01:20:37.551479 - LAVA_JOB_ID=795751
155 01:20:37.552034 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:20:37.552822 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 01:20:37.554916 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:20:37.555616 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 01:20:37.556141 skipped lava-vland-overlay
160 01:20:37.556708 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:20:37.557273 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 01:20:37.557744 skipped lava-multinode-overlay
163 01:20:37.558290 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:20:37.558826 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 01:20:37.559331 Loading test definitions
166 01:20:37.559900 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 01:20:37.560296 Using /lava-795751 at stage 0
168 01:20:37.561611 uuid=795751_1.5.2.4.1 testdef=None
169 01:20:37.561946 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:20:37.562237 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 01:20:37.564135 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:20:37.564994 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 01:20:37.567350 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:20:37.568270 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 01:20:37.570607 runner path: /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/0/tests/0_dmesg test_uuid 795751_1.5.2.4.1
178 01:20:37.571267 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:20:37.572196 Creating lava-test-runner.conf files
181 01:20:37.572425 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795751/lava-overlay-w28yujk7/lava-795751/0 for stage 0
182 01:20:37.572813 - 0_dmesg
183 01:20:37.573231 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:20:37.573555 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:20:37.599675 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:20:37.600150 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:20:37.600426 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:20:37.600700 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:20:37.600967 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:20:38.583607 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:20:38.584106 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 01:20:38.584366 extracting modules file /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795751/extract-overlay-ramdisk-mkjtrn2f/ramdisk
193 01:20:39.956135 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:20:39.956627 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 01:20:39.956904 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795751/compress-overlay-inzwguua/overlay-1.5.2.5.tar.gz to ramdisk
196 01:20:39.957119 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795751/compress-overlay-inzwguua/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795751/extract-overlay-ramdisk-mkjtrn2f/ramdisk
197 01:20:39.987914 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:20:39.988393 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 01:20:39.988669 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 01:20:39.988905 Converting downloaded kernel to a uImage
201 01:20:39.989222 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/kernel/Image /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/kernel/uImage
202 01:20:40.395098 output: Image Name:
203 01:20:40.395497 output: Created: Thu Oct 3 01:20:39 2024
204 01:20:40.395727 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:20:40.395947 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
206 01:20:40.396189 output: Load Address: 01080000
207 01:20:40.396398 output: Entry Point: 01080000
208 01:20:40.396606 output:
209 01:20:40.396946 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:20:40.397226 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:20:40.397517 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 01:20:40.397791 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:20:40.398068 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 01:20:40.398337 Building ramdisk /var/lib/lava/dispatcher/tmp/795751/extract-overlay-ramdisk-mkjtrn2f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795751/extract-overlay-ramdisk-mkjtrn2f/ramdisk
215 01:20:43.292636 >> 188209 blocks
216 01:20:51.721067 Adding RAMdisk u-boot header.
217 01:20:51.721522 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795751/extract-overlay-ramdisk-mkjtrn2f/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795751/extract-overlay-ramdisk-mkjtrn2f/ramdisk.cpio.gz.uboot
218 01:20:52.002350 output: Image Name:
219 01:20:52.002778 output: Created: Thu Oct 3 01:20:51 2024
220 01:20:52.003199 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:20:52.003621 output: Data Size: 26755941 Bytes = 26128.85 KiB = 25.52 MiB
222 01:20:52.004072 output: Load Address: 00000000
223 01:20:52.004489 output: Entry Point: 00000000
224 01:20:52.004892 output:
225 01:20:52.005980 rename /var/lib/lava/dispatcher/tmp/795751/extract-overlay-ramdisk-mkjtrn2f/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/ramdisk/ramdisk.cpio.gz.uboot
226 01:20:52.006700 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 01:20:52.007250 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 01:20:52.007784 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 01:20:52.008285 No LXC device requested
230 01:20:52.008799 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:20:52.009319 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 01:20:52.009827 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:20:52.010247 Checking files for TFTP limit of 4294967296 bytes.
234 01:20:52.011959 end: 1 tftp-deploy (duration 00:00:17) [common]
235 01:20:52.012555 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:20:52.013097 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:20:52.013609 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:20:52.014141 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:20:52.014682 Using kernel file from prepare-kernel: 795751/tftp-deploy-m6w088ov/kernel/uImage
240 01:20:52.015295 substitutions:
241 01:20:52.015711 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:20:52.016152 - {DTB_ADDR}: 0x01070000
243 01:20:52.016441 - {DTB}: 795751/tftp-deploy-m6w088ov/dtb/meson-g12b-a311d-libretech-cc.dtb
244 01:20:52.016664 - {INITRD}: 795751/tftp-deploy-m6w088ov/ramdisk/ramdisk.cpio.gz.uboot
245 01:20:52.016880 - {KERNEL_ADDR}: 0x01080000
246 01:20:52.017087 - {KERNEL}: 795751/tftp-deploy-m6w088ov/kernel/uImage
247 01:20:52.017300 - {LAVA_MAC}: None
248 01:20:52.017685 - {PRESEED_CONFIG}: None
249 01:20:52.018092 - {PRESEED_LOCAL}: None
250 01:20:52.018487 - {RAMDISK_ADDR}: 0x08000000
251 01:20:52.018882 - {RAMDISK}: 795751/tftp-deploy-m6w088ov/ramdisk/ramdisk.cpio.gz.uboot
252 01:20:52.019280 - {ROOT_PART}: None
253 01:20:52.019680 - {ROOT}: None
254 01:20:52.020103 - {SERVER_IP}: 192.168.6.2
255 01:20:52.020509 - {TEE_ADDR}: 0x83000000
256 01:20:52.020906 - {TEE}: None
257 01:20:52.021300 Parsed boot commands:
258 01:20:52.021683 - setenv autoload no
259 01:20:52.022076 - setenv initrd_high 0xffffffff
260 01:20:52.022466 - setenv fdt_high 0xffffffff
261 01:20:52.022854 - dhcp
262 01:20:52.023243 - setenv serverip 192.168.6.2
263 01:20:52.023631 - tftpboot 0x01080000 795751/tftp-deploy-m6w088ov/kernel/uImage
264 01:20:52.024049 - tftpboot 0x08000000 795751/tftp-deploy-m6w088ov/ramdisk/ramdisk.cpio.gz.uboot
265 01:20:52.024452 - tftpboot 0x01070000 795751/tftp-deploy-m6w088ov/dtb/meson-g12b-a311d-libretech-cc.dtb
266 01:20:52.024846 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:20:52.025249 - bootm 0x01080000 0x08000000 0x01070000
268 01:20:52.025760 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:20:52.027274 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:20:52.027733 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 01:20:52.042715 Setting prompt string to ['lava-test: # ']
273 01:20:52.044241 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:20:52.044867 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:20:52.045449 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:20:52.045987 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:20:52.047147 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 01:20:52.083476 >> OK - accepted request
279 01:20:52.085439 Returned 0 in 0 seconds
280 01:20:52.186594 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:20:52.187629 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:20:52.188009 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:20:52.188332 Setting prompt string to ['Hit any key to stop autoboot']
285 01:20:52.188605 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:20:52.189567 Trying 192.168.56.21...
287 01:20:52.189856 Connected to conserv1.
288 01:20:52.190089 Escape character is '^]'.
289 01:20:52.190323
290 01:20:52.190561 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:20:52.190791
292 01:21:04.200856 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 01:21:04.201280 bl2_stage_init 0x01
294 01:21:04.201520 bl2_stage_init 0x81
295 01:21:04.206370 hw id: 0x0000 - pwm id 0x01
296 01:21:04.206715 bl2_stage_init 0xc1
297 01:21:04.206949 bl2_stage_init 0x02
298 01:21:04.207167
299 01:21:04.212033 L0:00000000
300 01:21:04.212327 L1:20000703
301 01:21:04.212547 L2:00008067
302 01:21:04.212762 L3:14000000
303 01:21:04.217567 B2:00402000
304 01:21:04.217848 B1:e0f83180
305 01:21:04.218060
306 01:21:04.218265 TE: 58124
307 01:21:04.218462
308 01:21:04.223105 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 01:21:04.223375
310 01:21:04.223580 Board ID = 1
311 01:21:04.228684 Set A53 clk to 24M
312 01:21:04.228944 Set A73 clk to 24M
313 01:21:04.229145 Set clk81 to 24M
314 01:21:04.234317 A53 clk: 1200 MHz
315 01:21:04.234566 A73 clk: 1200 MHz
316 01:21:04.234765 CLK81: 166.6M
317 01:21:04.234962 smccc: 00012a92
318 01:21:04.240006 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 01:21:04.245481 board id: 1
320 01:21:04.250502 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:21:04.262058 fw parse done
322 01:21:04.267946 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:21:04.309747 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:21:04.321677 PIEI prepare done
325 01:21:04.321953 fastboot data load
326 01:21:04.322164 fastboot data verify
327 01:21:04.327212 verify result: 266
328 01:21:04.332829 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 01:21:04.333082 LPDDR4 probe
330 01:21:04.333291 ddr clk to 1584MHz
331 01:21:04.340209 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:21:04.378051
333 01:21:04.378404 dmc_version 0001
334 01:21:04.383845 Check phy result
335 01:21:04.390589 INFO : End of CA training
336 01:21:04.390876 INFO : End of initialization
337 01:21:04.396225 INFO : Training has run successfully!
338 01:21:04.396534 Check phy result
339 01:21:04.401882 INFO : End of initialization
340 01:21:04.402179 INFO : End of read enable training
341 01:21:04.405153 INFO : End of fine write leveling
342 01:21:04.410904 INFO : End of Write leveling coarse delay
343 01:21:04.416297 INFO : Training has run successfully!
344 01:21:04.416839 Check phy result
345 01:21:04.417273 INFO : End of initialization
346 01:21:04.421942 INFO : End of read dq deskew training
347 01:21:04.427554 INFO : End of MPR read delay center optimization
348 01:21:04.428122 INFO : End of write delay center optimization
349 01:21:04.433190 INFO : End of read delay center optimization
350 01:21:04.438769 INFO : End of max read latency training
351 01:21:04.439274 INFO : Training has run successfully!
352 01:21:04.444320 1D training succeed
353 01:21:04.449464 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:21:04.496948 Check phy result
355 01:21:04.497443 INFO : End of initialization
356 01:21:04.519127 INFO : End of 2D read delay Voltage center optimization
357 01:21:04.538910 INFO : End of 2D read delay Voltage center optimization
358 01:21:04.591040 INFO : End of 2D write delay Voltage center optimization
359 01:21:04.641370 INFO : End of 2D write delay Voltage center optimization
360 01:21:04.646852 INFO : Training has run successfully!
361 01:21:04.647280
362 01:21:04.647549 channel==0
363 01:21:04.652475 RxClkDly_Margin_A0==88 ps 9
364 01:21:04.653071 TxDqDly_Margin_A0==98 ps 10
365 01:21:04.658150 RxClkDly_Margin_A1==88 ps 9
366 01:21:04.658583 TxDqDly_Margin_A1==98 ps 10
367 01:21:04.658900 TrainedVREFDQ_A0==74
368 01:21:04.663696 TrainedVREFDQ_A1==74
369 01:21:04.664350 VrefDac_Margin_A0==25
370 01:21:04.664814 DeviceVref_Margin_A0==40
371 01:21:04.669314 VrefDac_Margin_A1==25
372 01:21:04.670203 DeviceVref_Margin_A1==40
373 01:21:04.670843
374 01:21:04.671428
375 01:21:04.674912 channel==1
376 01:21:04.675598 RxClkDly_Margin_A0==98 ps 10
377 01:21:04.676202 TxDqDly_Margin_A0==88 ps 9
378 01:21:04.680435 RxClkDly_Margin_A1==98 ps 10
379 01:21:04.681023 TxDqDly_Margin_A1==98 ps 10
380 01:21:04.686037 TrainedVREFDQ_A0==76
381 01:21:04.686623 TrainedVREFDQ_A1==77
382 01:21:04.687117 VrefDac_Margin_A0==22
383 01:21:04.691617 DeviceVref_Margin_A0==38
384 01:21:04.692174 VrefDac_Margin_A1==22
385 01:21:04.697194 DeviceVref_Margin_A1==37
386 01:21:04.697704
387 01:21:04.698120 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:21:04.702767
389 01:21:04.730666 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000014 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 01:21:04.731267 2D training succeed
391 01:21:04.736234 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:21:04.741879 auto size-- 65535DDR cs0 size: 2048MB
393 01:21:04.742377 DDR cs1 size: 2048MB
394 01:21:04.747565 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:21:04.748102 cs0 DataBus test pass
396 01:21:04.753200 cs1 DataBus test pass
397 01:21:04.753848 cs0 AddrBus test pass
398 01:21:04.754417 cs1 AddrBus test pass
399 01:21:04.754987
400 01:21:04.758842 100bdlr_step_size ps== 420
401 01:21:04.759485 result report
402 01:21:04.764440 boot times 0Enable ddr reg access
403 01:21:04.768943 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:21:04.783218 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 01:21:05.356914 0.0;M3 CHK:0;cm4_sp_mode 0
406 01:21:05.357601 MVN_1=0x00000000
407 01:21:05.362357 MVN_2=0x00000000
408 01:21:05.368219 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 01:21:05.368731 OPS=0x10
410 01:21:05.369205 ring efuse init
411 01:21:05.369662 chipver efuse init
412 01:21:05.373768 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 01:21:05.379335 [0.018961 Inits done]
414 01:21:05.379862 secure task start!
415 01:21:05.380389 high task start!
416 01:21:05.383546 low task start!
417 01:21:05.384084 run into bl31
418 01:21:05.390620 NOTICE: BL31: v1.3(release):4fc40b1
419 01:21:05.397500 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 01:21:05.398059 NOTICE: BL31: G12A normal boot!
421 01:21:05.423762 NOTICE: BL31: BL33 decompress pass
422 01:21:05.428822 ERROR: Error initializing runtime service opteed_fast
423 01:21:06.662371
424 01:21:06.662798
425 01:21:06.670711 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 01:21:06.671004
427 01:21:06.671222 Model: Libre Computer AML-A311D-CC Alta
428 01:21:06.878768 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 01:21:06.901718 DRAM: 2 GiB (effective 3.8 GiB)
430 01:21:07.045692 Core: 408 devices, 31 uclasses, devicetree: separate
431 01:21:07.051626 WDT: Not starting watchdog@f0d0
432 01:21:07.083792 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 01:21:07.096177 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 01:21:07.101179 ** Bad device specification mmc 0 **
435 01:21:07.111407 Card did not respond to voltage select! : -110
436 01:21:07.118244 ** Bad device specification mmc 0 **
437 01:21:07.118516 Couldn't find partition mmc 0
438 01:21:07.127469 Card did not respond to voltage select! : -110
439 01:21:07.132967 ** Bad device specification mmc 0 **
440 01:21:07.133248 Couldn't find partition mmc 0
441 01:21:07.137942 Error: could not access storage.
442 01:21:08.401185 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 01:21:08.401639 bl2_stage_init 0x01
444 01:21:08.401883 bl2_stage_init 0x81
445 01:21:08.406696 hw id: 0x0000 - pwm id 0x01
446 01:21:08.407155 bl2_stage_init 0xc1
447 01:21:08.407520 bl2_stage_init 0x02
448 01:21:08.407871
449 01:21:08.412293 L0:00000000
450 01:21:08.412758 L1:20000703
451 01:21:08.413036 L2:00008067
452 01:21:08.413282 L3:14000000
453 01:21:08.415523 B2:00402000
454 01:21:08.415859 B1:e0f83180
455 01:21:08.416140
456 01:21:08.416368 TE: 58124
457 01:21:08.416588
458 01:21:08.426329 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 01:21:08.426858
460 01:21:08.427313 Board ID = 1
461 01:21:08.427763 Set A53 clk to 24M
462 01:21:08.428248 Set A73 clk to 24M
463 01:21:08.431944 Set clk81 to 24M
464 01:21:08.432486 A53 clk: 1200 MHz
465 01:21:08.432970 A73 clk: 1200 MHz
466 01:21:08.436075 CLK81: 166.6M
467 01:21:08.436575 smccc: 00012a92
468 01:21:08.441633 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 01:21:08.442122 board id: 1
470 01:21:08.451864 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 01:21:08.462295 fw parse done
472 01:21:08.468266 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 01:21:08.510881 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 01:21:08.521914 PIEI prepare done
475 01:21:08.522449 fastboot data load
476 01:21:08.522925 fastboot data verify
477 01:21:08.527500 verify result: 266
478 01:21:08.533043 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 01:21:08.533578 LPDDR4 probe
480 01:21:08.534041 ddr clk to 1584MHz
481 01:21:08.541009 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 01:21:08.578232
483 01:21:08.578846 dmc_version 0001
484 01:21:08.585092 Check phy result
485 01:21:08.590790 INFO : End of CA training
486 01:21:08.591277 INFO : End of initialization
487 01:21:08.596474 INFO : Training has run successfully!
488 01:21:08.596965 Check phy result
489 01:21:08.601970 INFO : End of initialization
490 01:21:08.602454 INFO : End of read enable training
491 01:21:08.607608 INFO : End of fine write leveling
492 01:21:08.613282 INFO : End of Write leveling coarse delay
493 01:21:08.613770 INFO : Training has run successfully!
494 01:21:08.614221 Check phy result
495 01:21:08.618817 INFO : End of initialization
496 01:21:08.619301 INFO : End of read dq deskew training
497 01:21:08.624514 INFO : End of MPR read delay center optimization
498 01:21:08.629964 INFO : End of write delay center optimization
499 01:21:08.635566 INFO : End of read delay center optimization
500 01:21:08.636093 INFO : End of max read latency training
501 01:21:08.641224 INFO : Training has run successfully!
502 01:21:08.641705 1D training succeed
503 01:21:08.650365 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 01:21:08.698021 Check phy result
505 01:21:08.698562 INFO : End of initialization
506 01:21:08.719762 INFO : End of 2D read delay Voltage center optimization
507 01:21:08.740097 INFO : End of 2D read delay Voltage center optimization
508 01:21:08.792093 INFO : End of 2D write delay Voltage center optimization
509 01:21:08.841448 INFO : End of 2D write delay Voltage center optimization
510 01:21:08.846959 INFO : Training has run successfully!
511 01:21:08.847449
512 01:21:08.847906 channel==0
513 01:21:08.852576 RxClkDly_Margin_A0==88 ps 9
514 01:21:08.853065 TxDqDly_Margin_A0==98 ps 10
515 01:21:08.858162 RxClkDly_Margin_A1==88 ps 9
516 01:21:08.858644 TxDqDly_Margin_A1==98 ps 10
517 01:21:08.859100 TrainedVREFDQ_A0==74
518 01:21:08.863798 TrainedVREFDQ_A1==75
519 01:21:08.864313 VrefDac_Margin_A0==25
520 01:21:08.864766 DeviceVref_Margin_A0==40
521 01:21:08.869370 VrefDac_Margin_A1==25
522 01:21:08.869849 DeviceVref_Margin_A1==39
523 01:21:08.870297
524 01:21:08.870741
525 01:21:08.875026 channel==1
526 01:21:08.875571 RxClkDly_Margin_A0==98 ps 10
527 01:21:08.876075 TxDqDly_Margin_A0==88 ps 9
528 01:21:08.880622 RxClkDly_Margin_A1==98 ps 10
529 01:21:08.881170 TxDqDly_Margin_A1==88 ps 9
530 01:21:08.886351 TrainedVREFDQ_A0==77
531 01:21:08.886846 TrainedVREFDQ_A1==77
532 01:21:08.887308 VrefDac_Margin_A0==22
533 01:21:08.891788 DeviceVref_Margin_A0==37
534 01:21:08.892321 VrefDac_Margin_A1==22
535 01:21:08.897343 DeviceVref_Margin_A1==37
536 01:21:08.897827
537 01:21:08.898280 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 01:21:08.898727
539 01:21:08.931016 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 01:21:08.931596 2D training succeed
541 01:21:08.936557 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 01:21:08.942169 auto size-- 65535DDR cs0 size: 2048MB
543 01:21:08.942676 DDR cs1 size: 2048MB
544 01:21:08.947764 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 01:21:08.948301 cs0 DataBus test pass
546 01:21:08.953346 cs1 DataBus test pass
547 01:21:08.953834 cs0 AddrBus test pass
548 01:21:08.954287 cs1 AddrBus test pass
549 01:21:08.954742
550 01:21:08.958949 100bdlr_step_size ps== 420
551 01:21:08.959448 result report
552 01:21:08.964539 boot times 0Enable ddr reg access
553 01:21:08.969943 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 01:21:08.983403 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 01:21:09.556535 0.0;M3 CHK:0;cm4_sp_mode 0
556 01:21:09.556946 MVN_1=0x00000000
557 01:21:09.561897 MVN_2=0x00000000
558 01:21:09.567744 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 01:21:09.568109 OPS=0x10
560 01:21:09.568339 ring efuse init
561 01:21:09.568548 chipver efuse init
562 01:21:09.575974 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 01:21:09.576353 [0.018960 Inits done]
564 01:21:09.576573 secure task start!
565 01:21:09.582490 high task start!
566 01:21:09.582806 low task start!
567 01:21:09.583026 run into bl31
568 01:21:09.590173 NOTICE: BL31: v1.3(release):4fc40b1
569 01:21:09.597005 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 01:21:09.597347 NOTICE: BL31: G12A normal boot!
571 01:21:09.623488 NOTICE: BL31: BL33 decompress pass
572 01:21:09.628127 ERROR: Error initializing runtime service opteed_fast
573 01:21:10.862009
574 01:21:10.862627
575 01:21:10.869349 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 01:21:10.869858
577 01:21:10.870286 Model: Libre Computer AML-A311D-CC Alta
578 01:21:11.077828 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 01:21:11.102171 DRAM: 2 GiB (effective 3.8 GiB)
580 01:21:11.245203 Core: 408 devices, 31 uclasses, devicetree: separate
581 01:21:11.250026 WDT: Not starting watchdog@f0d0
582 01:21:11.283298 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 01:21:11.295654 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 01:21:11.299827 ** Bad device specification mmc 0 **
585 01:21:11.310972 Card did not respond to voltage select! : -110
586 01:21:11.317698 ** Bad device specification mmc 0 **
587 01:21:11.318189 Couldn't find partition mmc 0
588 01:21:11.327047 Card did not respond to voltage select! : -110
589 01:21:11.332514 ** Bad device specification mmc 0 **
590 01:21:11.332987 Couldn't find partition mmc 0
591 01:21:11.336667 Error: could not access storage.
592 01:21:11.680106 Net: eth0: ethernet@ff3f0000
593 01:21:11.680670 starting USB...
594 01:21:11.931818 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 01:21:11.932447 Starting the controller
596 01:21:11.938897 USB XHCI 1.10
597 01:21:13.652758 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 01:21:13.653348 bl2_stage_init 0x01
599 01:21:13.653774 bl2_stage_init 0x81
600 01:21:13.658332 hw id: 0x0000 - pwm id 0x01
601 01:21:13.658803 bl2_stage_init 0xc1
602 01:21:13.659221 bl2_stage_init 0x02
603 01:21:13.659628
604 01:21:13.663948 L0:00000000
605 01:21:13.664440 L1:20000703
606 01:21:13.664855 L2:00008067
607 01:21:13.665259 L3:14000000
608 01:21:13.666770 B2:00402000
609 01:21:13.667218 B1:e0f83180
610 01:21:13.667627
611 01:21:13.668060 TE: 58124
612 01:21:13.668475
613 01:21:13.677903 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 01:21:13.678374
615 01:21:13.678790 Board ID = 1
616 01:21:13.679191 Set A53 clk to 24M
617 01:21:13.679590 Set A73 clk to 24M
618 01:21:13.683543 Set clk81 to 24M
619 01:21:13.684029 A53 clk: 1200 MHz
620 01:21:13.684446 A73 clk: 1200 MHz
621 01:21:13.689072 CLK81: 166.6M
622 01:21:13.689530 smccc: 00012a92
623 01:21:13.694724 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 01:21:13.695182 board id: 1
625 01:21:13.700313 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 01:21:13.714075 fw parse done
627 01:21:13.720084 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 01:21:13.762659 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 01:21:13.773516 PIEI prepare done
630 01:21:13.773975 fastboot data load
631 01:21:13.774388 fastboot data verify
632 01:21:13.779193 verify result: 266
633 01:21:13.784783 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 01:21:13.785240 LPDDR4 probe
635 01:21:13.785649 ddr clk to 1584MHz
636 01:21:13.792738 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 01:21:13.830067
638 01:21:13.830571 dmc_version 0001
639 01:21:13.836732 Check phy result
640 01:21:13.842582 INFO : End of CA training
641 01:21:13.843034 INFO : End of initialization
642 01:21:13.848237 INFO : Training has run successfully!
643 01:21:13.848710 Check phy result
644 01:21:13.853797 INFO : End of initialization
645 01:21:13.854256 INFO : End of read enable training
646 01:21:13.857177 INFO : End of fine write leveling
647 01:21:13.862745 INFO : End of Write leveling coarse delay
648 01:21:13.868399 INFO : Training has run successfully!
649 01:21:13.868853 Check phy result
650 01:21:13.869259 INFO : End of initialization
651 01:21:13.873987 INFO : End of read dq deskew training
652 01:21:13.877335 INFO : End of MPR read delay center optimization
653 01:21:13.882865 INFO : End of write delay center optimization
654 01:21:13.888456 INFO : End of read delay center optimization
655 01:21:13.888925 INFO : End of max read latency training
656 01:21:13.894071 INFO : Training has run successfully!
657 01:21:13.894532 1D training succeed
658 01:21:13.902217 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 01:21:13.949781 Check phy result
660 01:21:13.950270 INFO : End of initialization
661 01:21:13.972539 INFO : End of 2D read delay Voltage center optimization
662 01:21:13.992634 INFO : End of 2D read delay Voltage center optimization
663 01:21:14.044659 INFO : End of 2D write delay Voltage center optimization
664 01:21:14.094083 INFO : End of 2D write delay Voltage center optimization
665 01:21:14.099570 INFO : Training has run successfully!
666 01:21:14.100064
667 01:21:14.100490 channel==0
668 01:21:14.105227 RxClkDly_Margin_A0==88 ps 9
669 01:21:14.105687 TxDqDly_Margin_A0==98 ps 10
670 01:21:14.108544 RxClkDly_Margin_A1==88 ps 9
671 01:21:14.109006 TxDqDly_Margin_A1==88 ps 9
672 01:21:14.114092 TrainedVREFDQ_A0==74
673 01:21:14.114553 TrainedVREFDQ_A1==74
674 01:21:14.114968 VrefDac_Margin_A0==24
675 01:21:14.119689 DeviceVref_Margin_A0==40
676 01:21:14.120172 VrefDac_Margin_A1==24
677 01:21:14.125221 DeviceVref_Margin_A1==40
678 01:21:14.125677
679 01:21:14.126094
680 01:21:14.126505 channel==1
681 01:21:14.126909 RxClkDly_Margin_A0==98 ps 10
682 01:21:14.130930 TxDqDly_Margin_A0==88 ps 9
683 01:21:14.131389 RxClkDly_Margin_A1==88 ps 9
684 01:21:14.136460 TxDqDly_Margin_A1==88 ps 9
685 01:21:14.136932 TrainedVREFDQ_A0==76
686 01:21:14.137348 TrainedVREFDQ_A1==77
687 01:21:14.142058 VrefDac_Margin_A0==22
688 01:21:14.142514 DeviceVref_Margin_A0==38
689 01:21:14.147698 VrefDac_Margin_A1==24
690 01:21:14.148213 DeviceVref_Margin_A1==37
691 01:21:14.148629
692 01:21:14.153239 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 01:21:14.153699
694 01:21:14.181124 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 01:21:14.186774 2D training succeed
696 01:21:14.192396 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 01:21:14.192857 auto size-- 65535DDR cs0 size: 2048MB
698 01:21:14.198009 DDR cs1 size: 2048MB
699 01:21:14.198503 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 01:21:14.203598 cs0 DataBus test pass
701 01:21:14.204118 cs1 DataBus test pass
702 01:21:14.204540 cs0 AddrBus test pass
703 01:21:14.209215 cs1 AddrBus test pass
704 01:21:14.209673
705 01:21:14.210083 100bdlr_step_size ps== 420
706 01:21:14.210495 result report
707 01:21:14.214774 boot times 0Enable ddr reg access
708 01:21:14.222308 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 01:21:14.235170 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 01:21:14.809301 0.0;M3 CHK:0;cm4_sp_mode 0
711 01:21:14.809715 MVN_1=0x00000000
712 01:21:14.814800 MVN_2=0x00000000
713 01:21:14.820520 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 01:21:14.820821 OPS=0x10
715 01:21:14.821048 ring efuse init
716 01:21:14.821272 chipver efuse init
717 01:21:14.826110 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 01:21:14.831680 [0.018961 Inits done]
719 01:21:14.831971 secure task start!
720 01:21:14.832256 high task start!
721 01:21:14.836351 low task start!
722 01:21:14.836612 run into bl31
723 01:21:14.842900 NOTICE: BL31: v1.3(release):4fc40b1
724 01:21:14.850783 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 01:21:14.851084 NOTICE: BL31: G12A normal boot!
726 01:21:14.876408 NOTICE: BL31: BL33 decompress pass
727 01:21:14.881900 ERROR: Error initializing runtime service opteed_fast
728 01:21:16.114842
729 01:21:16.115279
730 01:21:16.123247 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 01:21:16.123718
732 01:21:16.124088 Model: Libre Computer AML-A311D-CC Alta
733 01:21:16.331793 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 01:21:16.355182 DRAM: 2 GiB (effective 3.8 GiB)
735 01:21:16.498152 Core: 408 devices, 31 uclasses, devicetree: separate
736 01:21:16.503926 WDT: Not starting watchdog@f0d0
737 01:21:16.536174 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 01:21:16.548655 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 01:21:16.553664 ** Bad device specification mmc 0 **
740 01:21:16.564035 Card did not respond to voltage select! : -110
741 01:21:16.571818 ** Bad device specification mmc 0 **
742 01:21:16.572261 Couldn't find partition mmc 0
743 01:21:16.579997 Card did not respond to voltage select! : -110
744 01:21:16.585522 ** Bad device specification mmc 0 **
745 01:21:16.586136 Couldn't find partition mmc 0
746 01:21:16.590615 Error: could not access storage.
747 01:21:16.934038 Net: eth0: ethernet@ff3f0000
748 01:21:16.934607 starting USB...
749 01:21:17.185854 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 01:21:17.186260 Starting the controller
751 01:21:17.192805 USB XHCI 1.10
752 01:21:19.351698 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
753 01:21:19.352383 bl2_stage_init 0x81
754 01:21:19.357196 hw id: 0x0000 - pwm id 0x01
755 01:21:19.357655 bl2_stage_init 0xc1
756 01:21:19.358074 bl2_stage_init 0x02
757 01:21:19.358484
758 01:21:19.362811 L0:00000000
759 01:21:19.363274 L1:20000703
760 01:21:19.363679 L2:00008067
761 01:21:19.364115 L3:14000000
762 01:21:19.364523 B2:00402000
763 01:21:19.365588 B1:e0f83180
764 01:21:19.366041
765 01:21:19.366460 TE: 58150
766 01:21:19.366866
767 01:21:19.376828 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 01:21:19.377367
769 01:21:19.377787 Board ID = 1
770 01:21:19.378188 Set A53 clk to 24M
771 01:21:19.378587 Set A73 clk to 24M
772 01:21:19.382435 Set clk81 to 24M
773 01:21:19.382898 A53 clk: 1200 MHz
774 01:21:19.383303 A73 clk: 1200 MHz
775 01:21:19.387854 CLK81: 166.6M
776 01:21:19.388342 smccc: 00012aac
777 01:21:19.393544 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 01:21:19.394001 board id: 1
779 01:21:19.402386 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 01:21:19.412703 fw parse done
781 01:21:19.418639 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 01:21:19.461346 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 01:21:19.472210 PIEI prepare done
784 01:21:19.472688 fastboot data load
785 01:21:19.473101 fastboot data verify
786 01:21:19.477936 verify result: 266
787 01:21:19.483460 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 01:21:19.483931 LPDDR4 probe
789 01:21:19.484384 ddr clk to 1584MHz
790 01:21:19.491441 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 01:21:19.528743
792 01:21:19.529256 dmc_version 0001
793 01:21:19.535397 Check phy result
794 01:21:19.541299 INFO : End of CA training
795 01:21:19.541759 INFO : End of initialization
796 01:21:19.546933 INFO : Training has run successfully!
797 01:21:19.547373 Check phy result
798 01:21:19.552489 INFO : End of initialization
799 01:21:19.552943 INFO : End of read enable training
800 01:21:19.558147 INFO : End of fine write leveling
801 01:21:19.563627 INFO : End of Write leveling coarse delay
802 01:21:19.564100 INFO : Training has run successfully!
803 01:21:19.564514 Check phy result
804 01:21:19.569296 INFO : End of initialization
805 01:21:19.569736 INFO : End of read dq deskew training
806 01:21:19.574947 INFO : End of MPR read delay center optimization
807 01:21:19.580514 INFO : End of write delay center optimization
808 01:21:19.586134 INFO : End of read delay center optimization
809 01:21:19.586584 INFO : End of max read latency training
810 01:21:19.591669 INFO : Training has run successfully!
811 01:21:19.592150 1D training succeed
812 01:21:19.600851 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 01:21:19.648561 Check phy result
814 01:21:19.649067 INFO : End of initialization
815 01:21:19.670297 INFO : End of 2D read delay Voltage center optimization
816 01:21:19.690462 INFO : End of 2D read delay Voltage center optimization
817 01:21:19.742636 INFO : End of 2D write delay Voltage center optimization
818 01:21:19.792017 INFO : End of 2D write delay Voltage center optimization
819 01:21:19.797502 INFO : Training has run successfully!
820 01:21:19.797978
821 01:21:19.798398 channel==0
822 01:21:19.802975 RxClkDly_Margin_A0==88 ps 9
823 01:21:19.803450 TxDqDly_Margin_A0==98 ps 10
824 01:21:19.806408 RxClkDly_Margin_A1==88 ps 9
825 01:21:19.806863 TxDqDly_Margin_A1==98 ps 10
826 01:21:19.812058 TrainedVREFDQ_A0==74
827 01:21:19.812531 TrainedVREFDQ_A1==74
828 01:21:19.812961 VrefDac_Margin_A0==25
829 01:21:19.817636 DeviceVref_Margin_A0==40
830 01:21:19.818170 VrefDac_Margin_A1==25
831 01:21:19.823244 DeviceVref_Margin_A1==40
832 01:21:19.823785
833 01:21:19.824238
834 01:21:19.824631 channel==1
835 01:21:19.825017 RxClkDly_Margin_A0==98 ps 10
836 01:21:19.828799 TxDqDly_Margin_A0==98 ps 10
837 01:21:19.829256 RxClkDly_Margin_A1==98 ps 10
838 01:21:19.834446 TxDqDly_Margin_A1==88 ps 9
839 01:21:19.834905 TrainedVREFDQ_A0==77
840 01:21:19.835303 TrainedVREFDQ_A1==77
841 01:21:19.839872 VrefDac_Margin_A0==22
842 01:21:19.840335 DeviceVref_Margin_A0==37
843 01:21:19.845482 VrefDac_Margin_A1==24
844 01:21:19.845918 DeviceVref_Margin_A1==37
845 01:21:19.846306
846 01:21:19.851178 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 01:21:19.851624
848 01:21:19.879131 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
849 01:21:19.884632 2D training succeed
850 01:21:19.890283 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 01:21:19.890740 auto size-- 65535DDR cs0 size: 2048MB
852 01:21:19.895902 DDR cs1 size: 2048MB
853 01:21:19.896385 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 01:21:19.901447 cs0 DataBus test pass
855 01:21:19.901888 cs1 DataBus test pass
856 01:21:19.902285 cs0 AddrBus test pass
857 01:21:19.907120 cs1 AddrBus test pass
858 01:21:19.907551
859 01:21:19.907951 100bdlr_step_size ps== 420
860 01:21:19.908399 result report
861 01:21:19.912626 boot times 0Enable ddr reg access
862 01:21:19.920374 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 01:21:19.933841 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 01:21:20.506950 0.0;M3 CHK:0;cm4_sp_mode 0
865 01:21:20.507550 MVN_1=0x00000000
866 01:21:20.512348 MVN_2=0x00000000
867 01:21:20.518164 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 01:21:20.518624 OPS=0x10
869 01:21:20.519048 ring efuse init
870 01:21:20.519461 chipver efuse init
871 01:21:20.523701 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 01:21:20.529305 [0.018961 Inits done]
873 01:21:20.529750 secure task start!
874 01:21:20.530157 high task start!
875 01:21:20.533899 low task start!
876 01:21:20.534341 run into bl31
877 01:21:20.540565 NOTICE: BL31: v1.3(release):4fc40b1
878 01:21:20.548379 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 01:21:20.548827 NOTICE: BL31: G12A normal boot!
880 01:21:20.573795 NOTICE: BL31: BL33 decompress pass
881 01:21:20.579503 ERROR: Error initializing runtime service opteed_fast
882 01:21:21.812498
883 01:21:21.813110
884 01:21:21.820738 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 01:21:21.821218
886 01:21:21.821639 Model: Libre Computer AML-A311D-CC Alta
887 01:21:22.029172 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 01:21:22.052617 DRAM: 2 GiB (effective 3.8 GiB)
889 01:21:22.195574 Core: 408 devices, 31 uclasses, devicetree: separate
890 01:21:22.201397 WDT: Not starting watchdog@f0d0
891 01:21:22.233654 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 01:21:22.246121 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 01:21:22.251049 ** Bad device specification mmc 0 **
894 01:21:22.261382 Card did not respond to voltage select! : -110
895 01:21:22.269038 ** Bad device specification mmc 0 **
896 01:21:22.269491 Couldn't find partition mmc 0
897 01:21:22.277413 Card did not respond to voltage select! : -110
898 01:21:22.282896 ** Bad device specification mmc 0 **
899 01:21:22.283337 Couldn't find partition mmc 0
900 01:21:22.287965 Error: could not access storage.
901 01:21:22.631528 Net: eth0: ethernet@ff3f0000
902 01:21:22.632138 starting USB...
903 01:21:22.883425 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 01:21:22.884067 Starting the controller
905 01:21:22.890297 USB XHCI 1.10
906 01:21:24.444253 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 01:21:24.452481 scanning usb for storage devices... 0 Storage Device(s) found
909 01:21:24.503693 Hit any key to stop autoboot: 1
910 01:21:24.504511 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 01:21:24.504872 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 01:21:24.505140 Setting prompt string to ['=>']
913 01:21:24.505405 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 01:21:24.509914 0
915 01:21:24.510523 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 01:21:24.510823 Sending with 10 millisecond of delay
918 01:21:25.645266 => setenv autoload no
919 01:21:25.658213 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
920 01:21:25.664587 setenv autoload no
921 01:21:25.665495 Sending with 10 millisecond of delay
923 01:21:27.462380 => setenv initrd_high 0xffffffff
924 01:21:27.473154 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 01:21:27.473977 setenv initrd_high 0xffffffff
926 01:21:27.474690 Sending with 10 millisecond of delay
928 01:21:29.090598 => setenv fdt_high 0xffffffff
929 01:21:29.101376 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 01:21:29.102187 setenv fdt_high 0xffffffff
931 01:21:29.102901 Sending with 10 millisecond of delay
933 01:21:29.394658 => dhcp
934 01:21:29.405415 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 01:21:29.406242 dhcp
936 01:21:29.406679 Speed: 1000, full duplex
937 01:21:29.407092 BOOTP broadcast 1
938 01:21:29.853741 BOOTP broadcast 2
939 01:21:29.856770 DHCP client bound to address 192.168.6.33 (260 ms)
940 01:21:29.857477 Sending with 10 millisecond of delay
942 01:21:31.533666 => setenv serverip 192.168.6.2
943 01:21:31.544401 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
944 01:21:31.545242 setenv serverip 192.168.6.2
945 01:21:31.545927 Sending with 10 millisecond of delay
947 01:21:35.269794 => tftpboot 0x01080000 795751/tftp-deploy-m6w088ov/kernel/uImage
948 01:21:35.280507 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
949 01:21:35.281012 tftpboot 0x01080000 795751/tftp-deploy-m6w088ov/kernel/uImage
950 01:21:35.281253 Speed: 1000, full duplex
951 01:21:35.281464 Using ethernet@ff3f0000 device
952 01:21:35.283270 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
953 01:21:35.288693 Filename '795751/tftp-deploy-m6w088ov/kernel/uImage'.
954 01:21:35.292704 Load address: 0x1080000
955 01:21:39.451618 Loading: *################################################## 37.6 MiB
956 01:21:39.452264 9 MiB/s
957 01:21:39.452695 done
958 01:21:39.454619 Bytes transferred = 39424576 (2599240 hex)
959 01:21:39.455367 Sending with 10 millisecond of delay
961 01:21:44.144539 => tftpboot 0x08000000 795751/tftp-deploy-m6w088ov/ramdisk/ramdisk.cpio.gz.uboot
962 01:21:44.155308 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:08)
963 01:21:44.156116 tftpboot 0x08000000 795751/tftp-deploy-m6w088ov/ramdisk/ramdisk.cpio.gz.uboot
964 01:21:44.156605 Speed: 1000, full duplex
965 01:21:44.157042 Using ethernet@ff3f0000 device
966 01:21:44.157771 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
967 01:21:44.169575 Filename '795751/tftp-deploy-m6w088ov/ramdisk/ramdisk.cpio.gz.uboot'.
968 01:21:44.170037 Load address: 0x8000000
969 01:21:46.235845 Loading: *############################################ UDP wrong checksum 00000005 0000195f
970 01:21:46.614135 ##### UDP wrong checksum 00000005 000021a7
971 01:21:48.589793 UDP wrong checksum 000000ff 00009e66
972 01:21:48.649936 UDP wrong checksum 000000ff 00002759
973 01:21:49.269795 UDP wrong checksum 000000ff 00005c0e
974 01:21:49.289916 UDP wrong checksum 000000ff 0000f900
975 01:21:51.615267 T UDP wrong checksum 00000005 000021a7
976 01:22:01.618297 T T UDP wrong checksum 00000005 000021a7
977 01:22:21.622484 T T T T UDP wrong checksum 00000005 000021a7
978 01:22:30.381337 T UDP wrong checksum 000000ff 0000a378
979 01:22:30.429210 UDP wrong checksum 000000ff 0000386b
980 01:22:31.361169 UDP wrong checksum 000000ff 0000612b
981 01:22:31.401314 UDP wrong checksum 000000ff 0000f11d
982 01:22:41.626970 T T
983 01:22:41.627644 Retry count exceeded; starting again
985 01:22:41.629298 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
988 01:22:41.631366 end: 2.4 uboot-commands (duration 00:01:50) [common]
990 01:22:41.632993 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
992 01:22:41.634141 end: 2 uboot-action (duration 00:01:50) [common]
994 01:22:41.635822 Cleaning after the job
995 01:22:41.636470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/ramdisk
996 01:22:41.637955 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/kernel
997 01:22:41.646925 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/dtb
998 01:22:41.648205 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795751/tftp-deploy-m6w088ov/modules
999 01:22:41.655330 start: 4.1 power-off (timeout 00:00:30) [common]
1000 01:22:41.656440 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1001 01:22:41.694045 >> OK - accepted request
1002 01:22:41.696967 Returned 0 in 0 seconds
1003 01:22:41.798242 end: 4.1 power-off (duration 00:00:00) [common]
1005 01:22:41.800139 start: 4.2 read-feedback (timeout 00:10:00) [common]
1006 01:22:41.801367 Listened to connection for namespace 'common' for up to 1s
1007 01:22:42.801402 Finalising connection for namespace 'common'
1008 01:22:42.802238 Disconnecting from shell: Finalise
1009 01:22:42.802834 =>
1010 01:22:42.903913 end: 4.2 read-feedback (duration 00:00:01) [common]
1011 01:22:42.904715 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795751
1012 01:22:43.188947 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795751
1013 01:22:43.189555 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.