Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:18:34.065608 lava-dispatcher, installed at version: 2024.01
2 01:18:34.066394 start: 0 validate
3 01:18:34.066865 Start time: 2024-10-03 01:18:34.066836+00:00 (UTC)
4 01:18:34.067409 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:18:34.067953 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:18:34.102495 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:18:34.103070 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fkernel%2FImage exists
8 01:18:34.132364 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:18:34.132972 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:18:35.182070 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:18:35.182597 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2BCONFIG_ARM64_64K_PAGES%3Dy%2Fclang-16%2Fmodules.tar.xz exists
12 01:18:35.222624 validate duration: 1.16
14 01:18:35.224207 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:18:35.224554 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:18:35.224855 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:18:35.225454 Not decompressing ramdisk as can be used compressed.
18 01:18:35.225898 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:18:35.226168 saving as /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/ramdisk/rootfs.cpio.gz
20 01:18:35.226433 total size: 8181887 (7 MB)
21 01:18:35.261220 progress 0 % (0 MB)
22 01:18:35.272657 progress 5 % (0 MB)
23 01:18:35.283550 progress 10 % (0 MB)
24 01:18:35.289871 progress 15 % (1 MB)
25 01:18:35.295502 progress 20 % (1 MB)
26 01:18:35.301564 progress 25 % (1 MB)
27 01:18:35.307138 progress 30 % (2 MB)
28 01:18:35.313093 progress 35 % (2 MB)
29 01:18:35.318535 progress 40 % (3 MB)
30 01:18:35.324471 progress 45 % (3 MB)
31 01:18:35.329878 progress 50 % (3 MB)
32 01:18:35.335734 progress 55 % (4 MB)
33 01:18:35.341361 progress 60 % (4 MB)
34 01:18:35.347128 progress 65 % (5 MB)
35 01:18:35.352736 progress 70 % (5 MB)
36 01:18:35.358503 progress 75 % (5 MB)
37 01:18:35.364057 progress 80 % (6 MB)
38 01:18:35.369924 progress 85 % (6 MB)
39 01:18:35.375558 progress 90 % (7 MB)
40 01:18:35.381322 progress 95 % (7 MB)
41 01:18:35.386234 progress 100 % (7 MB)
42 01:18:35.386914 7 MB downloaded in 0.16 s (48.63 MB/s)
43 01:18:35.387470 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:18:35.388409 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:18:35.388708 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:18:35.388981 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:18:35.389452 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/kernel/Image
49 01:18:35.389729 saving as /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/kernel/Image
50 01:18:35.389941 total size: 39424512 (37 MB)
51 01:18:35.390152 No compression specified
52 01:18:35.425899 progress 0 % (0 MB)
53 01:18:35.452311 progress 5 % (1 MB)
54 01:18:35.476887 progress 10 % (3 MB)
55 01:18:35.502022 progress 15 % (5 MB)
56 01:18:35.527140 progress 20 % (7 MB)
57 01:18:35.552488 progress 25 % (9 MB)
58 01:18:35.577826 progress 30 % (11 MB)
59 01:18:35.603161 progress 35 % (13 MB)
60 01:18:35.628171 progress 40 % (15 MB)
61 01:18:35.653703 progress 45 % (16 MB)
62 01:18:35.678622 progress 50 % (18 MB)
63 01:18:35.703429 progress 55 % (20 MB)
64 01:18:35.728507 progress 60 % (22 MB)
65 01:18:35.753902 progress 65 % (24 MB)
66 01:18:35.779184 progress 70 % (26 MB)
67 01:18:35.804002 progress 75 % (28 MB)
68 01:18:35.828619 progress 80 % (30 MB)
69 01:18:35.853560 progress 85 % (31 MB)
70 01:18:35.878285 progress 90 % (33 MB)
71 01:18:35.902989 progress 95 % (35 MB)
72 01:18:35.927854 progress 100 % (37 MB)
73 01:18:35.928408 37 MB downloaded in 0.54 s (69.83 MB/s)
74 01:18:35.928898 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:18:35.929719 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:18:35.929994 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:18:35.930261 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:18:35.930767 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:18:35.931054 saving as /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:18:35.931264 total size: 53209 (0 MB)
82 01:18:35.931476 No compression specified
83 01:18:35.970039 progress 61 % (0 MB)
84 01:18:35.970890 progress 100 % (0 MB)
85 01:18:35.971446 0 MB downloaded in 0.04 s (1.26 MB/s)
86 01:18:35.971945 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:18:35.972804 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:18:35.973070 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:18:35.973336 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:18:35.973955 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+CONFIG_ARM64_64K_PAGES=y/clang-16/modules.tar.xz
92 01:18:35.974236 saving as /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/modules/modules.tar
93 01:18:35.974444 total size: 11756024 (11 MB)
94 01:18:35.974657 Using unxz to decompress xz
95 01:18:36.008932 progress 0 % (0 MB)
96 01:18:36.080986 progress 5 % (0 MB)
97 01:18:36.163019 progress 10 % (1 MB)
98 01:18:36.254158 progress 15 % (1 MB)
99 01:18:36.338116 progress 20 % (2 MB)
100 01:18:36.424125 progress 25 % (2 MB)
101 01:18:36.507546 progress 30 % (3 MB)
102 01:18:36.589226 progress 35 % (3 MB)
103 01:18:36.669687 progress 40 % (4 MB)
104 01:18:36.749638 progress 45 % (5 MB)
105 01:18:36.830562 progress 50 % (5 MB)
106 01:18:36.909236 progress 55 % (6 MB)
107 01:18:36.995816 progress 60 % (6 MB)
108 01:18:37.085541 progress 65 % (7 MB)
109 01:18:37.170567 progress 70 % (7 MB)
110 01:18:37.266985 progress 75 % (8 MB)
111 01:18:37.364612 progress 80 % (9 MB)
112 01:18:37.442999 progress 85 % (9 MB)
113 01:18:37.522546 progress 90 % (10 MB)
114 01:18:37.603809 progress 95 % (10 MB)
115 01:18:37.683631 progress 100 % (11 MB)
116 01:18:37.698172 11 MB downloaded in 1.72 s (6.50 MB/s)
117 01:18:37.698798 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:18:37.699635 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:18:37.699907 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 01:18:37.700406 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 01:18:37.700955 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:18:37.701513 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 01:18:37.702585 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3
125 01:18:37.703508 makedir: /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin
126 01:18:37.704332 makedir: /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/tests
127 01:18:37.705092 makedir: /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/results
128 01:18:37.705780 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-add-keys
129 01:18:37.706928 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-add-sources
130 01:18:37.707960 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-background-process-start
131 01:18:37.709044 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-background-process-stop
132 01:18:37.710090 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-common-functions
133 01:18:37.711093 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-echo-ipv4
134 01:18:37.712101 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-install-packages
135 01:18:37.713124 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-installed-packages
136 01:18:37.714139 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-os-build
137 01:18:37.715130 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-probe-channel
138 01:18:37.716147 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-probe-ip
139 01:18:37.717149 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-target-ip
140 01:18:37.718119 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-target-mac
141 01:18:37.719094 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-target-storage
142 01:18:37.720117 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-test-case
143 01:18:37.721120 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-test-event
144 01:18:37.722092 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-test-feedback
145 01:18:37.723062 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-test-raise
146 01:18:37.724073 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-test-reference
147 01:18:37.725070 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-test-runner
148 01:18:37.726047 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-test-set
149 01:18:37.727016 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-test-shell
150 01:18:37.728079 Updating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-install-packages (oe)
151 01:18:37.729181 Updating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/bin/lava-installed-packages (oe)
152 01:18:37.730089 Creating /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/environment
153 01:18:37.730871 LAVA metadata
154 01:18:37.731400 - LAVA_JOB_ID=795785
155 01:18:37.731872 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:18:37.732667 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:18:37.734665 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:18:37.735318 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:18:37.735773 skipped lava-vland-overlay
160 01:18:37.736346 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:18:37.736862 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:18:37.737293 skipped lava-multinode-overlay
163 01:18:37.737783 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:18:37.738300 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:18:37.738782 Loading test definitions
166 01:18:37.739325 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:18:37.739765 Using /lava-795785 at stage 0
168 01:18:37.741173 uuid=795785_1.5.2.4.1 testdef=None
169 01:18:37.741500 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:18:37.741773 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:18:37.743628 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:18:37.744485 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:18:37.746838 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:18:37.747715 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:18:37.750005 runner path: /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/0/tests/0_dmesg test_uuid 795785_1.5.2.4.1
178 01:18:37.750610 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:18:37.751399 Creating lava-test-runner.conf files
181 01:18:37.751608 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795785/lava-overlay-3qtoukh3/lava-795785/0 for stage 0
182 01:18:37.751964 - 0_dmesg
183 01:18:37.752368 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:18:37.752657 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:18:37.777602 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:18:37.778050 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:18:37.778323 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:18:37.778595 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:18:37.778864 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:18:38.774181 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:18:38.774690 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 01:18:38.775190 extracting modules file /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795785/extract-overlay-ramdisk-lzt9q8uq/ramdisk
193 01:18:40.170532 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:18:40.171012 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 01:18:40.171309 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795785/compress-overlay-72ipd_u2/overlay-1.5.2.5.tar.gz to ramdisk
196 01:18:40.171543 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795785/compress-overlay-72ipd_u2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795785/extract-overlay-ramdisk-lzt9q8uq/ramdisk
197 01:18:40.202761 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:18:40.203180 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 01:18:40.203451 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 01:18:40.203678 Converting downloaded kernel to a uImage
201 01:18:40.204002 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/kernel/Image /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/kernel/uImage
202 01:18:40.609955 output: Image Name:
203 01:18:40.610394 output: Created: Thu Oct 3 01:18:40 2024
204 01:18:40.610623 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:18:40.610841 output: Data Size: 39424512 Bytes = 38500.50 KiB = 37.60 MiB
206 01:18:40.611067 output: Load Address: 01080000
207 01:18:40.611304 output: Entry Point: 01080000
208 01:18:40.611537 output:
209 01:18:40.611905 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:18:40.612277 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:18:40.612599 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 01:18:40.612864 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:18:40.613126 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 01:18:40.613399 Building ramdisk /var/lib/lava/dispatcher/tmp/795785/extract-overlay-ramdisk-lzt9q8uq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795785/extract-overlay-ramdisk-lzt9q8uq/ramdisk
215 01:18:43.150563 >> 188209 blocks
216 01:18:51.548288 Adding RAMdisk u-boot header.
217 01:18:51.548996 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795785/extract-overlay-ramdisk-lzt9q8uq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795785/extract-overlay-ramdisk-lzt9q8uq/ramdisk.cpio.gz.uboot
218 01:18:51.815596 output: Image Name:
219 01:18:51.816051 output: Created: Thu Oct 3 01:18:51 2024
220 01:18:51.816476 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:18:51.816878 output: Data Size: 26756881 Bytes = 26129.77 KiB = 25.52 MiB
222 01:18:51.817277 output: Load Address: 00000000
223 01:18:51.817671 output: Entry Point: 00000000
224 01:18:51.818062 output:
225 01:18:51.819202 rename /var/lib/lava/dispatcher/tmp/795785/extract-overlay-ramdisk-lzt9q8uq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/ramdisk/ramdisk.cpio.gz.uboot
226 01:18:51.819912 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 01:18:51.820489 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 01:18:51.821014 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 01:18:51.821462 No LXC device requested
230 01:18:51.821957 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:18:51.822470 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 01:18:51.822962 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:18:51.823376 Checking files for TFTP limit of 4294967296 bytes.
234 01:18:51.826058 end: 1 tftp-deploy (duration 00:00:17) [common]
235 01:18:51.826630 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:18:51.827149 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:18:51.827644 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:18:51.828180 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:18:51.828711 Using kernel file from prepare-kernel: 795785/tftp-deploy-1_cpvzu_/kernel/uImage
240 01:18:51.829340 substitutions:
241 01:18:51.829749 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:18:51.830151 - {DTB_ADDR}: 0x01070000
243 01:18:51.830543 - {DTB}: 795785/tftp-deploy-1_cpvzu_/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:18:51.830940 - {INITRD}: 795785/tftp-deploy-1_cpvzu_/ramdisk/ramdisk.cpio.gz.uboot
245 01:18:51.831336 - {KERNEL_ADDR}: 0x01080000
246 01:18:51.831726 - {KERNEL}: 795785/tftp-deploy-1_cpvzu_/kernel/uImage
247 01:18:51.832152 - {LAVA_MAC}: None
248 01:18:51.832586 - {PRESEED_CONFIG}: None
249 01:18:51.832980 - {PRESEED_LOCAL}: None
250 01:18:51.833366 - {RAMDISK_ADDR}: 0x08000000
251 01:18:51.833751 - {RAMDISK}: 795785/tftp-deploy-1_cpvzu_/ramdisk/ramdisk.cpio.gz.uboot
252 01:18:51.834142 - {ROOT_PART}: None
253 01:18:51.834527 - {ROOT}: None
254 01:18:51.834913 - {SERVER_IP}: 192.168.6.2
255 01:18:51.835303 - {TEE_ADDR}: 0x83000000
256 01:18:51.835687 - {TEE}: None
257 01:18:51.836097 Parsed boot commands:
258 01:18:51.836474 - setenv autoload no
259 01:18:51.836859 - setenv initrd_high 0xffffffff
260 01:18:51.837245 - setenv fdt_high 0xffffffff
261 01:18:51.837629 - dhcp
262 01:18:51.838014 - setenv serverip 192.168.6.2
263 01:18:51.838398 - tftpboot 0x01080000 795785/tftp-deploy-1_cpvzu_/kernel/uImage
264 01:18:51.838788 - tftpboot 0x08000000 795785/tftp-deploy-1_cpvzu_/ramdisk/ramdisk.cpio.gz.uboot
265 01:18:51.839174 - tftpboot 0x01070000 795785/tftp-deploy-1_cpvzu_/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:18:51.839562 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:18:51.839952 - bootm 0x01080000 0x08000000 0x01070000
268 01:18:51.840474 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:18:51.841962 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:18:51.842401 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:18:51.857311 Setting prompt string to ['lava-test: # ']
273 01:18:51.858786 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:18:51.859376 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:18:51.859914 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:18:51.860476 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:18:51.861617 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:18:51.895371 >> OK - accepted request
279 01:18:51.897484 Returned 0 in 0 seconds
280 01:18:51.998580 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:18:52.000205 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:18:52.000778 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:18:52.001275 Setting prompt string to ['Hit any key to stop autoboot']
285 01:18:52.001713 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:18:52.003267 Trying 192.168.56.21...
287 01:18:52.003752 Connected to conserv1.
288 01:18:52.004227 Escape character is '^]'.
289 01:18:52.004670
290 01:18:52.005094 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:18:52.005519
292 01:18:59.548796 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:18:59.549437 bl2_stage_init 0x01
294 01:18:59.549879 bl2_stage_init 0x81
295 01:18:59.554310 hw id: 0x0000 - pwm id 0x01
296 01:18:59.554782 bl2_stage_init 0xc1
297 01:18:59.558476 bl2_stage_init 0x02
298 01:18:59.558921
299 01:18:59.559335 L0:00000000
300 01:18:59.559746 L1:00000703
301 01:18:59.560207 L2:00008067
302 01:18:59.563970 L3:15000000
303 01:18:59.564426 S1:00000000
304 01:18:59.564822 B2:20282000
305 01:18:59.565214 B1:a0f83180
306 01:18:59.565602
307 01:18:59.569614 TE: 71630
308 01:18:59.570043
309 01:18:59.575125 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:18:59.575557
311 01:18:59.575951 Board ID = 1
312 01:18:59.576375 Set cpu clk to 24M
313 01:18:59.578725 Set clk81 to 24M
314 01:18:59.579143 Use GP1_pll as DSU clk.
315 01:18:59.584297 DSU clk: 1200 Mhz
316 01:18:59.584723 CPU clk: 1200 MHz
317 01:18:59.585118 Set clk81 to 166.6M
318 01:18:59.589916 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:18:59.595439 board id: 1
320 01:18:59.599757 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:18:59.611631 fw parse done
322 01:18:59.617562 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:18:59.660728 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:18:59.671744 PIEI prepare done
325 01:18:59.672215 fastboot data load
326 01:18:59.672611 fastboot data verify
327 01:18:59.677285 verify result: 266
328 01:18:59.682962 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:18:59.683381 LPDDR4 probe
330 01:18:59.683775 ddr clk to 1584MHz
331 01:18:59.690944 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:18:59.728078
333 01:18:59.728549 dmc_version 0001
334 01:18:59.735756 Check phy result
335 01:18:59.741678 INFO : End of CA training
336 01:18:59.742111 INFO : End of initialization
337 01:18:59.747335 INFO : Training has run successfully!
338 01:18:59.747758 Check phy result
339 01:18:59.752854 INFO : End of initialization
340 01:18:59.753276 INFO : End of read enable training
341 01:18:59.758478 INFO : End of fine write leveling
342 01:18:59.764191 INFO : End of Write leveling coarse delay
343 01:18:59.764609 INFO : Training has run successfully!
344 01:18:59.765003 Check phy result
345 01:18:59.769892 INFO : End of initialization
346 01:18:59.770334 INFO : End of read dq deskew training
347 01:18:59.775310 INFO : End of MPR read delay center optimization
348 01:18:59.780846 INFO : End of write delay center optimization
349 01:18:59.786508 INFO : End of read delay center optimization
350 01:18:59.786929 INFO : End of max read latency training
351 01:18:59.792214 INFO : Training has run successfully!
352 01:18:59.792633 1D training succeed
353 01:18:59.801307 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:18:59.849565 Check phy result
355 01:18:59.850019 INFO : End of initialization
356 01:18:59.876035 INFO : End of 2D read delay Voltage center optimization
357 01:18:59.901241 INFO : End of 2D read delay Voltage center optimization
358 01:18:59.958171 INFO : End of 2D write delay Voltage center optimization
359 01:19:00.012258 INFO : End of 2D write delay Voltage center optimization
360 01:19:00.017605 INFO : Training has run successfully!
361 01:19:00.018215
362 01:19:00.018647 channel==0
363 01:19:00.030954 RxClkDly_Margin_A0==78 ps 8
364 01:19:00.031687 TxDqDly_Margin_A0==98 ps 10
365 01:19:00.032284 RxClkDly_Margin_A1==69 ps 7
366 01:19:00.032784 TxDqDly_Margin_A1==88 ps 9
367 01:19:00.033267 TrainedVREFDQ_A0==74
368 01:19:00.034400 TrainedVREFDQ_A1==74
369 01:19:00.034937 VrefDac_Margin_A0==23
370 01:19:00.035385 DeviceVref_Margin_A0==40
371 01:19:00.039976 VrefDac_Margin_A1==23
372 01:19:00.040624 DeviceVref_Margin_A1==40
373 01:19:00.041043
374 01:19:00.041450
375 01:19:00.041852 channel==1
376 01:19:00.045474 RxClkDly_Margin_A0==78 ps 8
377 01:19:00.045960 TxDqDly_Margin_A0==88 ps 9
378 01:19:00.051165 RxClkDly_Margin_A1==88 ps 9
379 01:19:00.051630 TxDqDly_Margin_A1==88 ps 9
380 01:19:00.056615 TrainedVREFDQ_A0==75
381 01:19:00.057084 TrainedVREFDQ_A1==77
382 01:19:00.057489 VrefDac_Margin_A0==22
383 01:19:00.062270 DeviceVref_Margin_A0==39
384 01:19:00.062743 VrefDac_Margin_A1==22
385 01:19:00.063146 DeviceVref_Margin_A1==37
386 01:19:00.067837
387 01:19:00.068332 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:19:00.068737
389 01:19:00.101863 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000060
390 01:19:00.102445 2D training succeed
391 01:19:00.107052 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:19:00.112709 auto size-- 65535DDR cs0 size: 2048MB
393 01:19:00.113346 DDR cs1 size: 2048MB
394 01:19:00.118283 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:19:00.118772 cs0 DataBus test pass
396 01:19:00.123828 cs1 DataBus test pass
397 01:19:00.124364 cs0 AddrBus test pass
398 01:19:00.124765 cs1 AddrBus test pass
399 01:19:00.125157
400 01:19:00.129406 100bdlr_step_size ps== 478
401 01:19:00.129950 result report
402 01:19:00.134955 boot times 0Enable ddr reg access
403 01:19:00.140152 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:19:00.153016 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:19:00.813179 bl2z: ptr: 05129330, size: 00001e40
406 01:19:00.823078 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:19:00.823716 MVN_1=0x00000000
408 01:19:00.824184 MVN_2=0x00000000
409 01:19:00.834497 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:19:00.834897 OPS=0x04
411 01:19:00.835114 ring efuse init
412 01:19:00.837396 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:19:00.843238 [0.017354 Inits done]
414 01:19:00.843628 secure task start!
415 01:19:00.843840 high task start!
416 01:19:00.844069 low task start!
417 01:19:00.846425 run into bl31
418 01:19:00.856172 NOTICE: BL31: v1.3(release):4fc40b1
419 01:19:00.862979 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:19:00.863238 NOTICE: BL31: G12A normal boot!
421 01:19:00.879461 NOTICE: BL31: BL33 decompress pass
422 01:19:00.884066 ERROR: Error initializing runtime service opteed_fast
423 01:19:03.597336 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:19:03.597728 bl2_stage_init 0x01
425 01:19:03.597964 bl2_stage_init 0x81
426 01:19:03.602905 hw id: 0x0000 - pwm id 0x01
427 01:19:03.603190 bl2_stage_init 0xc1
428 01:19:03.608479 bl2_stage_init 0x02
429 01:19:03.608762
430 01:19:03.608986 L0:00000000
431 01:19:03.609212 L1:00000703
432 01:19:03.609428 L2:00008067
433 01:19:03.609644 L3:15000000
434 01:19:03.614079 S1:00000000
435 01:19:03.614367 B2:20282000
436 01:19:03.614596 B1:a0f83180
437 01:19:03.614811
438 01:19:03.615031 TE: 71904
439 01:19:03.615245
440 01:19:03.619677 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:19:03.619956
442 01:19:03.625306 Board ID = 1
443 01:19:03.625579 Set cpu clk to 24M
444 01:19:03.625800 Set clk81 to 24M
445 01:19:03.630895 Use GP1_pll as DSU clk.
446 01:19:03.631170 DSU clk: 1200 Mhz
447 01:19:03.631395 CPU clk: 1200 MHz
448 01:19:03.636486 Set clk81 to 166.6M
449 01:19:03.642064 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:19:03.642353 board id: 1
451 01:19:03.649248 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:19:03.659922 fw parse done
453 01:19:03.665911 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:19:03.708587 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:19:03.719588 PIEI prepare done
456 01:19:03.719895 fastboot data load
457 01:19:03.720167 fastboot data verify
458 01:19:03.725031 verify result: 266
459 01:19:03.730711 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:19:03.730990 LPDDR4 probe
461 01:19:03.731214 ddr clk to 1584MHz
462 01:19:03.738665 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 01:19:03.776048
464 01:19:03.776424 dmc_version 0001
465 01:19:03.782627 Check phy result
466 01:19:03.788587 INFO : End of CA training
467 01:19:03.788899 INFO : End of initialization
468 01:19:03.794112 INFO : Training has run successfully!
469 01:19:03.794429 Check phy result
470 01:19:03.799763 INFO : End of initialization
471 01:19:03.800095 INFO : End of read enable training
472 01:19:03.803085 INFO : End of fine write leveling
473 01:19:03.808708 INFO : End of Write leveling coarse delay
474 01:19:03.814254 INFO : Training has run successfully!
475 01:19:03.814663 Check phy result
476 01:19:03.814993 INFO : End of initialization
477 01:19:03.819828 INFO : End of read dq deskew training
478 01:19:03.823193 INFO : End of MPR read delay center optimization
479 01:19:03.828791 INFO : End of write delay center optimization
480 01:19:03.834421 INFO : End of read delay center optimization
481 01:19:03.834855 INFO : End of max read latency training
482 01:19:03.839989 INFO : Training has run successfully!
483 01:19:03.840396 1D training succeed
484 01:19:03.848180 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 01:19:03.895865 Check phy result
486 01:19:03.896358 INFO : End of initialization
487 01:19:03.918199 INFO : End of 2D read delay Voltage center optimization
488 01:19:03.937245 INFO : End of 2D read delay Voltage center optimization
489 01:19:03.989217 INFO : End of 2D write delay Voltage center optimization
490 01:19:04.038471 INFO : End of 2D write delay Voltage center optimization
491 01:19:04.043862 INFO : Training has run successfully!
492 01:19:04.044330
493 01:19:04.044681 channel==0
494 01:19:04.049433 RxClkDly_Margin_A0==78 ps 8
495 01:19:04.049851 TxDqDly_Margin_A0==98 ps 10
496 01:19:04.055008 RxClkDly_Margin_A1==88 ps 9
497 01:19:04.055410 TxDqDly_Margin_A1==88 ps 9
498 01:19:04.055674 TrainedVREFDQ_A0==74
499 01:19:04.060674 TrainedVREFDQ_A1==74
500 01:19:04.061097 VrefDac_Margin_A0==23
501 01:19:04.061380 DeviceVref_Margin_A0==40
502 01:19:04.066423 VrefDac_Margin_A1==23
503 01:19:04.066784 DeviceVref_Margin_A1==40
504 01:19:04.067021
505 01:19:04.067388
506 01:19:04.067675 channel==1
507 01:19:04.071846 RxClkDly_Margin_A0==78 ps 8
508 01:19:04.072278 TxDqDly_Margin_A0==98 ps 10
509 01:19:04.077513 RxClkDly_Margin_A1==78 ps 8
510 01:19:04.077925 TxDqDly_Margin_A1==88 ps 9
511 01:19:04.083147 TrainedVREFDQ_A0==78
512 01:19:04.083543 TrainedVREFDQ_A1==75
513 01:19:04.083825 VrefDac_Margin_A0==22
514 01:19:04.088833 DeviceVref_Margin_A0==36
515 01:19:04.089262 VrefDac_Margin_A1==22
516 01:19:04.094410 DeviceVref_Margin_A1==39
517 01:19:04.094821
518 01:19:04.095099 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 01:19:04.095359
520 01:19:04.127883 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 01:19:04.128512 2D training succeed
522 01:19:04.133426 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 01:19:04.139014 auto size-- 65535DDR cs0 size: 2048MB
524 01:19:04.139467 DDR cs1 size: 2048MB
525 01:19:04.144616 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 01:19:04.145066 cs0 DataBus test pass
527 01:19:04.150273 cs1 DataBus test pass
528 01:19:04.150731 cs0 AddrBus test pass
529 01:19:04.151133 cs1 AddrBus test pass
530 01:19:04.151527
531 01:19:04.155829 100bdlr_step_size ps== 464
532 01:19:04.156341 result report
533 01:19:04.161402 boot times 0Enable ddr reg access
534 01:19:04.166709 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 01:19:04.180438 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 01:19:04.835382 bl2z: ptr: 05129330, size: 00001e40
537 01:19:04.841703 0.0;M3 CHK:0;cm4_sp_mode 0
538 01:19:04.842216 MVN_1=0x00000000
539 01:19:04.842647 MVN_2=0x00000000
540 01:19:04.853130 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 01:19:04.853696 OPS=0x04
542 01:19:04.854144 ring efuse init
543 01:19:04.856080 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 01:19:04.862310 [0.017319 Inits done]
545 01:19:04.862778 secure task start!
546 01:19:04.863205 high task start!
547 01:19:04.863622 low task start!
548 01:19:04.865923 run into bl31
549 01:19:04.875183 NOTICE: BL31: v1.3(release):4fc40b1
550 01:19:04.882037 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 01:19:04.882507 NOTICE: BL31: G12A normal boot!
552 01:19:04.898469 NOTICE: BL31: BL33 decompress pass
553 01:19:04.903245 ERROR: Error initializing runtime service opteed_fast
554 01:19:06.295200 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 01:19:06.295806 bl2_stage_init 0x01
556 01:19:06.296296 bl2_stage_init 0x81
557 01:19:06.300812 hw id: 0x0000 - pwm id 0x01
558 01:19:06.301280 bl2_stage_init 0xc1
559 01:19:06.306315 bl2_stage_init 0x02
560 01:19:06.306774
561 01:19:06.307195 L0:00000000
562 01:19:06.307603 L1:00000703
563 01:19:06.308034 L2:00008067
564 01:19:06.308442 L3:15000000
565 01:19:06.311976 S1:00000000
566 01:19:06.312501 B2:20282000
567 01:19:06.312923 B1:a0f83180
568 01:19:06.313329
569 01:19:06.313741 TE: 69283
570 01:19:06.314147
571 01:19:06.317530 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 01:19:06.318000
573 01:19:06.323091 Board ID = 1
574 01:19:06.323545 Set cpu clk to 24M
575 01:19:06.323957 Set clk81 to 24M
576 01:19:06.328778 Use GP1_pll as DSU clk.
577 01:19:06.329298 DSU clk: 1200 Mhz
578 01:19:06.329734 CPU clk: 1200 MHz
579 01:19:06.334301 Set clk81 to 166.6M
580 01:19:06.340006 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 01:19:06.340478 board id: 1
582 01:19:06.346203 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 01:19:06.358091 fw parse done
584 01:19:06.363145 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 01:19:06.406365 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 01:19:06.418341 PIEI prepare done
587 01:19:06.418894 fastboot data load
588 01:19:06.419327 fastboot data verify
589 01:19:06.423801 verify result: 266
590 01:19:06.429386 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 01:19:06.429849 LPDDR4 probe
592 01:19:06.430263 ddr clk to 1584MHz
593 01:19:06.437437 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 01:19:06.474716
595 01:19:06.475269 dmc_version 0001
596 01:19:06.481182 Check phy result
597 01:19:06.488160 INFO : End of CA training
598 01:19:06.488613 INFO : End of initialization
599 01:19:06.493768 INFO : Training has run successfully!
600 01:19:06.494227 Check phy result
601 01:19:06.499373 INFO : End of initialization
602 01:19:06.499832 INFO : End of read enable training
603 01:19:06.505040 INFO : End of fine write leveling
604 01:19:06.510642 INFO : End of Write leveling coarse delay
605 01:19:06.511191 INFO : Training has run successfully!
606 01:19:06.511605 Check phy result
607 01:19:06.516343 INFO : End of initialization
608 01:19:06.516829 INFO : End of read dq deskew training
609 01:19:06.521868 INFO : End of MPR read delay center optimization
610 01:19:06.527448 INFO : End of write delay center optimization
611 01:19:06.533091 INFO : End of read delay center optimization
612 01:19:06.533591 INFO : End of max read latency training
613 01:19:06.538634 INFO : Training has run successfully!
614 01:19:06.539138 1D training succeed
615 01:19:06.547079 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 01:19:06.595610 Check phy result
617 01:19:06.596189 INFO : End of initialization
618 01:19:06.623391 INFO : End of 2D read delay Voltage center optimization
619 01:19:06.646916 INFO : End of 2D read delay Voltage center optimization
620 01:19:06.704312 INFO : End of 2D write delay Voltage center optimization
621 01:19:06.758361 INFO : End of 2D write delay Voltage center optimization
622 01:19:06.763947 INFO : Training has run successfully!
623 01:19:06.764500
624 01:19:06.764913 channel==0
625 01:19:06.769565 RxClkDly_Margin_A0==78 ps 8
626 01:19:06.770071 TxDqDly_Margin_A0==98 ps 10
627 01:19:06.775162 RxClkDly_Margin_A1==88 ps 9
628 01:19:06.775657 TxDqDly_Margin_A1==98 ps 10
629 01:19:06.776106 TrainedVREFDQ_A0==74
630 01:19:06.780760 TrainedVREFDQ_A1==75
631 01:19:06.781437 VrefDac_Margin_A0==23
632 01:19:06.781976 DeviceVref_Margin_A0==40
633 01:19:06.786363 VrefDac_Margin_A1==23
634 01:19:06.786863 DeviceVref_Margin_A1==39
635 01:19:06.787262
636 01:19:06.787658
637 01:19:06.791959 channel==1
638 01:19:06.792486 RxClkDly_Margin_A0==78 ps 8
639 01:19:06.792894 TxDqDly_Margin_A0==88 ps 9
640 01:19:06.797564 RxClkDly_Margin_A1==88 ps 9
641 01:19:06.798062 TxDqDly_Margin_A1==88 ps 9
642 01:19:06.803165 TrainedVREFDQ_A0==75
643 01:19:06.803664 TrainedVREFDQ_A1==78
644 01:19:06.804101 VrefDac_Margin_A0==22
645 01:19:06.808741 DeviceVref_Margin_A0==39
646 01:19:06.809233 VrefDac_Margin_A1==22
647 01:19:06.814317 DeviceVref_Margin_A1==36
648 01:19:06.814817
649 01:19:06.815220 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 01:19:06.815613
651 01:19:06.847907 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
652 01:19:06.848676 2D training succeed
653 01:19:06.853591 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 01:19:06.859244 auto size-- 65535DDR cs0 size: 2048MB
655 01:19:06.859751 DDR cs1 size: 2048MB
656 01:19:06.864732 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 01:19:06.865232 cs0 DataBus test pass
658 01:19:06.870321 cs1 DataBus test pass
659 01:19:06.870817 cs0 AddrBus test pass
660 01:19:06.871221 cs1 AddrBus test pass
661 01:19:06.871611
662 01:19:06.875955 100bdlr_step_size ps== 471
663 01:19:06.876664 result report
664 01:19:06.881551 boot times 0Enable ddr reg access
665 01:19:06.886675 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 01:19:06.900265 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 01:19:07.559975 bl2z: ptr: 05129330, size: 00001e40
668 01:19:07.567343 0.0;M3 CHK:0;cm4_sp_mode 0
669 01:19:07.567867 MVN_1=0x00000000
670 01:19:07.568313 MVN_2=0x00000000
671 01:19:07.578788 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 01:19:07.579337 OPS=0x04
673 01:19:07.579759 ring efuse init
674 01:19:07.581790 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 01:19:07.587939 [0.017354 Inits done]
676 01:19:07.588478 secure task start!
677 01:19:07.588880 high task start!
678 01:19:07.589267 low task start!
679 01:19:07.592246 run into bl31
680 01:19:07.600811 NOTICE: BL31: v1.3(release):4fc40b1
681 01:19:07.608512 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 01:19:07.609033 NOTICE: BL31: G12A normal boot!
683 01:19:07.624313 NOTICE: BL31: BL33 decompress pass
684 01:19:07.629460 ERROR: Error initializing runtime service opteed_fast
685 01:19:08.425433
686 01:19:08.425860
687 01:19:08.430612 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 01:19:08.431021
689 01:19:08.433808 Model: Libre Computer AML-S905D3-CC Solitude
690 01:19:08.581083 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 01:19:08.596405 DRAM: 2 GiB (effective 3.8 GiB)
692 01:19:08.697557 Core: 406 devices, 33 uclasses, devicetree: separate
693 01:19:08.703189 WDT: Not starting watchdog@f0d0
694 01:19:08.728479 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 01:19:08.740850 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 01:19:08.744916 ** Bad device specification mmc 0 **
697 01:19:08.755860 Card did not respond to voltage select! : -110
698 01:19:08.762531 ** Bad device specification mmc 0 **
699 01:19:08.762901 Couldn't find partition mmc 0
700 01:19:08.771912 Card did not respond to voltage select! : -110
701 01:19:08.777354 ** Bad device specification mmc 0 **
702 01:19:08.777772 Couldn't find partition mmc 0
703 01:19:08.782275 Error: could not access storage.
704 01:19:09.079082 Net: eth0: ethernet@ff3f0000
705 01:19:09.079925 starting USB...
706 01:19:09.324463 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 01:19:09.325212 Starting the controller
708 01:19:09.331023 USB XHCI 1.10
709 01:19:10.887719 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 01:19:10.895122 scanning usb for storage devices... 0 Storage Device(s) found
712 01:19:10.946650 Hit any key to stop autoboot: 1
713 01:19:10.947508 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 01:19:10.948134 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 01:19:10.948620 Setting prompt string to ['=>']
716 01:19:10.949102 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 01:19:10.961938 0
718 01:19:10.962808 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 01:19:11.064059 => setenv autoload no
721 01:19:11.064801 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 01:19:11.069615 setenv autoload no
724 01:19:11.171097 => setenv initrd_high 0xffffffff
725 01:19:11.171817 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 01:19:11.176195 setenv initrd_high 0xffffffff
728 01:19:11.277652 => setenv fdt_high 0xffffffff
729 01:19:11.278580 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 01:19:11.282083 setenv fdt_high 0xffffffff
732 01:19:11.383610 => dhcp
733 01:19:11.384592 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 01:19:11.387788 dhcp
735 01:19:11.993029 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 01:19:11.993652 Speed: 1000, full duplex
737 01:19:11.994088 BOOTP broadcast 1
738 01:19:12.241786 BOOTP broadcast 2
739 01:19:12.742175 BOOTP broadcast 3
740 01:19:13.744082 BOOTP broadcast 4
741 01:19:15.745048 BOOTP broadcast 5
742 01:19:15.755888 DHCP client bound to address 192.168.6.12 (3762 ms)
744 01:19:15.857776 => setenv serverip 192.168.6.2
745 01:19:15.858510 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 01:19:15.862041 setenv serverip 192.168.6.2
748 01:19:15.963482 => tftpboot 0x01080000 795785/tftp-deploy-1_cpvzu_/kernel/uImage
749 01:19:15.964232 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 01:19:15.970821 tftpboot 0x01080000 795785/tftp-deploy-1_cpvzu_/kernel/uImage
751 01:19:15.971304 Speed: 1000, full duplex
752 01:19:15.971723 Using ethernet@ff3f0000 device
753 01:19:15.976262 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 01:19:15.981841 Filename '795785/tftp-deploy-1_cpvzu_/kernel/uImage'.
755 01:19:15.985702 Load address: 0x1080000
756 01:19:19.289882 Loading: *################################################## 37.6 MiB
757 01:19:19.290525 11.4 MiB/s
758 01:19:19.290958 done
759 01:19:19.293296 Bytes transferred = 39424576 (2599240 hex)
761 01:19:19.394894 => tftpboot 0x08000000 795785/tftp-deploy-1_cpvzu_/ramdisk/ramdisk.cpio.gz.uboot
762 01:19:19.395652 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
763 01:19:19.402258 tftpboot 0x08000000 795785/tftp-deploy-1_cpvzu_/ramdisk/ramdisk.cpio.gz.uboot
764 01:19:19.402724 Speed: 1000, full duplex
765 01:19:19.403122 Using ethernet@ff3f0000 device
766 01:19:19.407770 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
767 01:19:19.417506 Filename '795785/tftp-deploy-1_cpvzu_/ramdisk/ramdisk.cpio.gz.uboot'.
768 01:19:19.418033 Load address: 0x8000000
769 01:19:26.777196 Loading: *#####################################T ############ UDP wrong checksum 00000005 00004c22
770 01:19:31.780113 T UDP wrong checksum 00000005 00004c22
771 01:19:35.407602 UDP wrong checksum 000000ff 000006a6
772 01:19:35.418730 UDP wrong checksum 000000ff 00008998
773 01:19:41.779576 T T UDP wrong checksum 00000005 00004c22
774 01:19:48.335318 T UDP wrong checksum 00000005 0000f6b1
775 01:20:01.784845 T T T UDP wrong checksum 00000005 00004c22
776 01:20:02.675828 UDP wrong checksum 000000ff 000054df
777 01:20:02.710582 UDP wrong checksum 000000ff 0000e6d1
778 01:20:06.097749 UDP wrong checksum 000000ff 000081f5
779 01:20:06.109294 UDP wrong checksum 000000ff 000005e8
780 01:20:16.787141 T T
781 01:20:16.787744 Retry count exceeded; starting again
783 01:20:16.789220 end: 2.4.3 bootloader-commands (duration 00:01:06) [common]
786 01:20:16.791046 end: 2.4 uboot-commands (duration 00:01:25) [common]
788 01:20:16.792504 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
790 01:20:16.793538 end: 2 uboot-action (duration 00:01:25) [common]
792 01:20:16.795085 Cleaning after the job
793 01:20:16.795627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/ramdisk
794 01:20:16.796963 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/kernel
795 01:20:16.820532 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/dtb
796 01:20:16.821831 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795785/tftp-deploy-1_cpvzu_/modules
797 01:20:16.828255 start: 4.1 power-off (timeout 00:00:30) [common]
798 01:20:16.829265 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
799 01:20:16.863883 >> OK - accepted request
800 01:20:16.865925 Returned 0 in 0 seconds
801 01:20:16.967023 end: 4.1 power-off (duration 00:00:00) [common]
803 01:20:16.968757 start: 4.2 read-feedback (timeout 00:10:00) [common]
804 01:20:16.969883 Listened to connection for namespace 'common' for up to 1s
805 01:20:17.970089 Finalising connection for namespace 'common'
806 01:20:17.970820 Disconnecting from shell: Finalise
807 01:20:17.971337 =>
808 01:20:18.072428 end: 4.2 read-feedback (duration 00:00:01) [common]
809 01:20:18.073151 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795785
810 01:20:18.396048 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795785
811 01:20:18.396762 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.