Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:52:25.501519 lava-dispatcher, installed at version: 2024.01
2 01:52:25.502297 start: 0 validate
3 01:52:25.502792 Start time: 2024-10-03 01:52:25.502762+00:00 (UTC)
4 01:52:25.503335 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:52:25.503875 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 01:52:25.541312 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:52:25.541920 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 01:52:25.576571 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:52:25.577218 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:52:26.623423 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:52:26.623960 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
12 01:52:26.664761 validate duration: 1.16
14 01:52:26.665718 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:52:26.666076 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:52:26.666388 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:52:26.667012 Not decompressing ramdisk as can be used compressed.
18 01:52:26.667532 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 01:52:26.667829 saving as /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/ramdisk/rootfs.cpio.gz
20 01:52:26.668157 total size: 8181887 (7 MB)
21 01:52:26.705753 progress 0 % (0 MB)
22 01:52:26.717013 progress 5 % (0 MB)
23 01:52:26.726001 progress 10 % (0 MB)
24 01:52:26.732018 progress 15 % (1 MB)
25 01:52:26.737576 progress 20 % (1 MB)
26 01:52:26.743456 progress 25 % (1 MB)
27 01:52:26.748933 progress 30 % (2 MB)
28 01:52:26.754800 progress 35 % (2 MB)
29 01:52:26.760305 progress 40 % (3 MB)
30 01:52:26.766146 progress 45 % (3 MB)
31 01:52:26.771689 progress 50 % (3 MB)
32 01:52:26.777561 progress 55 % (4 MB)
33 01:52:26.782979 progress 60 % (4 MB)
34 01:52:26.788829 progress 65 % (5 MB)
35 01:52:26.794305 progress 70 % (5 MB)
36 01:52:26.800164 progress 75 % (5 MB)
37 01:52:26.805526 progress 80 % (6 MB)
38 01:52:26.811302 progress 85 % (6 MB)
39 01:52:26.816665 progress 90 % (7 MB)
40 01:52:26.822489 progress 95 % (7 MB)
41 01:52:26.827496 progress 100 % (7 MB)
42 01:52:26.828207 7 MB downloaded in 0.16 s (48.76 MB/s)
43 01:52:26.828773 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:52:26.829673 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:52:26.829968 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:52:26.830244 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:52:26.830721 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/kernel/Image
49 01:52:26.830971 saving as /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/kernel/Image
50 01:52:26.831178 total size: 169937408 (162 MB)
51 01:52:26.831392 No compression specified
52 01:52:26.864295 progress 0 % (0 MB)
53 01:52:26.973576 progress 5 % (8 MB)
54 01:52:27.083753 progress 10 % (16 MB)
55 01:52:27.194515 progress 15 % (24 MB)
56 01:52:27.305562 progress 20 % (32 MB)
57 01:52:27.414094 progress 25 % (40 MB)
58 01:52:27.523135 progress 30 % (48 MB)
59 01:52:27.632752 progress 35 % (56 MB)
60 01:52:27.744294 progress 40 % (64 MB)
61 01:52:27.855520 progress 45 % (72 MB)
62 01:52:27.967177 progress 50 % (81 MB)
63 01:52:28.078554 progress 55 % (89 MB)
64 01:52:28.189706 progress 60 % (97 MB)
65 01:52:28.300508 progress 65 % (105 MB)
66 01:52:28.411941 progress 70 % (113 MB)
67 01:52:28.522567 progress 75 % (121 MB)
68 01:52:28.633922 progress 80 % (129 MB)
69 01:52:28.744897 progress 85 % (137 MB)
70 01:52:28.854952 progress 90 % (145 MB)
71 01:52:28.964733 progress 95 % (153 MB)
72 01:52:29.075238 progress 100 % (162 MB)
73 01:52:29.075797 162 MB downloaded in 2.24 s (72.20 MB/s)
74 01:52:29.076310 end: 1.2.1 http-download (duration 00:00:02) [common]
76 01:52:29.077137 end: 1.2 download-retry (duration 00:00:02) [common]
77 01:52:29.077412 start: 1.3 download-retry (timeout 00:09:58) [common]
78 01:52:29.077691 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 01:52:29.078287 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 01:52:29.078573 saving as /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/dtb/meson-g12b-a311d-libretech-cc.dtb
81 01:52:29.078793 total size: 54703 (0 MB)
82 01:52:29.079011 No compression specified
83 01:52:29.121526 progress 59 % (0 MB)
84 01:52:29.122613 progress 100 % (0 MB)
85 01:52:29.123346 0 MB downloaded in 0.04 s (1.17 MB/s)
86 01:52:29.124036 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:52:29.125115 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:52:29.125490 start: 1.4 download-retry (timeout 00:09:58) [common]
90 01:52:29.125834 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 01:52:29.126448 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/modules.tar.xz
92 01:52:29.126767 saving as /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/modules/modules.tar
93 01:52:29.127043 total size: 27663052 (26 MB)
94 01:52:29.127320 Using unxz to decompress xz
95 01:52:29.169726 progress 0 % (0 MB)
96 01:52:29.378170 progress 5 % (1 MB)
97 01:52:29.610779 progress 10 % (2 MB)
98 01:52:29.814024 progress 15 % (3 MB)
99 01:52:30.058902 progress 20 % (5 MB)
100 01:52:30.267413 progress 25 % (6 MB)
101 01:52:30.473094 progress 30 % (7 MB)
102 01:52:30.681870 progress 35 % (9 MB)
103 01:52:30.885084 progress 40 % (10 MB)
104 01:52:31.084049 progress 45 % (11 MB)
105 01:52:31.302801 progress 50 % (13 MB)
106 01:52:31.518234 progress 55 % (14 MB)
107 01:52:31.730055 progress 60 % (15 MB)
108 01:52:31.926677 progress 65 % (17 MB)
109 01:52:32.142727 progress 70 % (18 MB)
110 01:52:32.374661 progress 75 % (19 MB)
111 01:52:32.604540 progress 80 % (21 MB)
112 01:52:32.835901 progress 85 % (22 MB)
113 01:52:33.078401 progress 90 % (23 MB)
114 01:52:33.303106 progress 95 % (25 MB)
115 01:52:33.532109 progress 100 % (26 MB)
116 01:52:33.544351 26 MB downloaded in 4.42 s (5.97 MB/s)
117 01:52:33.545025 end: 1.4.1 http-download (duration 00:00:04) [common]
119 01:52:33.545946 end: 1.4 download-retry (duration 00:00:04) [common]
120 01:52:33.546268 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 01:52:33.546561 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 01:52:33.546834 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:52:33.547108 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 01:52:33.547854 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2
125 01:52:33.548419 makedir: /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin
126 01:52:33.548835 makedir: /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/tests
127 01:52:33.549212 makedir: /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/results
128 01:52:33.549602 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-add-keys
129 01:52:33.550228 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-add-sources
130 01:52:33.550811 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-background-process-start
131 01:52:33.551387 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-background-process-stop
132 01:52:33.552024 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-common-functions
133 01:52:33.552604 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-echo-ipv4
134 01:52:33.553179 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-install-packages
135 01:52:33.553759 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-installed-packages
136 01:52:33.554312 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-os-build
137 01:52:33.554814 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-probe-channel
138 01:52:33.555323 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-probe-ip
139 01:52:33.555807 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-target-ip
140 01:52:33.556624 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-target-mac
141 01:52:33.557609 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-target-storage
142 01:52:33.558599 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-test-case
143 01:52:33.559566 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-test-event
144 01:52:33.560589 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-test-feedback
145 01:52:33.561599 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-test-raise
146 01:52:33.562611 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-test-reference
147 01:52:33.563591 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-test-runner
148 01:52:33.564616 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-test-set
149 01:52:33.565585 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-test-shell
150 01:52:33.566687 Updating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-install-packages (oe)
151 01:52:33.567738 Updating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/bin/lava-installed-packages (oe)
152 01:52:33.568699 Creating /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/environment
153 01:52:33.569472 LAVA metadata
154 01:52:33.569998 - LAVA_JOB_ID=795993
155 01:52:33.570469 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:52:33.571188 start: 1.5.2.1 ssh-authorize (timeout 00:09:53) [common]
157 01:52:33.573121 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:52:33.573717 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:53) [common]
159 01:52:33.574130 skipped lava-vland-overlay
160 01:52:33.574622 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:52:33.575135 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:53) [common]
162 01:52:33.575591 skipped lava-multinode-overlay
163 01:52:33.576145 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:52:33.576665 start: 1.5.2.4 test-definition (timeout 00:09:53) [common]
165 01:52:33.577147 Loading test definitions
166 01:52:33.577690 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:53) [common]
167 01:52:33.578131 Using /lava-795993 at stage 0
168 01:52:33.580246 uuid=795993_1.5.2.4.1 testdef=None
169 01:52:33.580572 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:52:33.580847 start: 1.5.2.4.2 test-overlay (timeout 00:09:53) [common]
171 01:52:33.582672 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:52:33.583480 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:53) [common]
174 01:52:33.585780 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:52:33.586630 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:53) [common]
177 01:52:33.588884 runner path: /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/0/tests/0_dmesg test_uuid 795993_1.5.2.4.1
178 01:52:33.589482 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:52:33.590264 Creating lava-test-runner.conf files
181 01:52:33.590468 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795993/lava-overlay-gl623th2/lava-795993/0 for stage 0
182 01:52:33.590812 - 0_dmesg
183 01:52:33.591163 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:52:33.591444 start: 1.5.2.5 compress-overlay (timeout 00:09:53) [common]
185 01:52:33.615233 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:52:33.615631 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:53) [common]
187 01:52:33.615900 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:52:33.616207 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:52:33.616483 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
190 01:52:34.605252 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 01:52:34.605712 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
192 01:52:34.605959 extracting modules file /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795993/extract-overlay-ramdisk-k8uc32fw/ramdisk
193 01:52:36.345196 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 01:52:36.345694 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
195 01:52:36.345968 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795993/compress-overlay-80pfcuht/overlay-1.5.2.5.tar.gz to ramdisk
196 01:52:36.346180 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795993/compress-overlay-80pfcuht/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795993/extract-overlay-ramdisk-k8uc32fw/ramdisk
197 01:52:36.376365 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:52:36.376794 start: 1.5.6 prepare-kernel (timeout 00:09:50) [common]
199 01:52:36.377065 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:50) [common]
200 01:52:36.377292 Converting downloaded kernel to a uImage
201 01:52:36.377608 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/kernel/Image /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/kernel/uImage
202 01:52:38.070577 output: Image Name:
203 01:52:38.071014 output: Created: Thu Oct 3 01:52:36 2024
204 01:52:38.071262 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:52:38.071486 output: Data Size: 169937408 Bytes = 165954.50 KiB = 162.06 MiB
206 01:52:38.071701 output: Load Address: 01080000
207 01:52:38.071909 output: Entry Point: 01080000
208 01:52:38.072171 output:
209 01:52:38.072528 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
210 01:52:38.072842 end: 1.5.6 prepare-kernel (duration 00:00:02) [common]
211 01:52:38.073135 start: 1.5.7 configure-preseed-file (timeout 00:09:49) [common]
212 01:52:38.073405 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:52:38.073700 start: 1.5.8 compress-ramdisk (timeout 00:09:49) [common]
214 01:52:38.073984 Building ramdisk /var/lib/lava/dispatcher/tmp/795993/extract-overlay-ramdisk-k8uc32fw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795993/extract-overlay-ramdisk-k8uc32fw/ramdisk
215 01:52:43.660845 >> 441386 blocks
216 01:53:02.141403 Adding RAMdisk u-boot header.
217 01:53:02.142059 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795993/extract-overlay-ramdisk-k8uc32fw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795993/extract-overlay-ramdisk-k8uc32fw/ramdisk.cpio.gz.uboot
218 01:53:02.694691 output: Image Name:
219 01:53:02.695109 output: Created: Thu Oct 3 01:53:02 2024
220 01:53:02.695315 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:53:02.695519 output: Data Size: 53552202 Bytes = 52297.07 KiB = 51.07 MiB
222 01:53:02.695720 output: Load Address: 00000000
223 01:53:02.695919 output: Entry Point: 00000000
224 01:53:02.696310 output:
225 01:53:02.697461 rename /var/lib/lava/dispatcher/tmp/795993/extract-overlay-ramdisk-k8uc32fw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/ramdisk/ramdisk.cpio.gz.uboot
226 01:53:02.698230 end: 1.5.8 compress-ramdisk (duration 00:00:25) [common]
227 01:53:02.698819 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
228 01:53:02.699393 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
229 01:53:02.699888 No LXC device requested
230 01:53:02.700475 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:53:02.701033 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
232 01:53:02.701571 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:53:02.702023 Checking files for TFTP limit of 4294967296 bytes.
234 01:53:02.704973 end: 1 tftp-deploy (duration 00:00:36) [common]
235 01:53:02.705603 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:53:02.706177 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:53:02.706724 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:53:02.707272 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:53:02.707852 Using kernel file from prepare-kernel: 795993/tftp-deploy-so3j_v9c/kernel/uImage
240 01:53:02.708576 substitutions:
241 01:53:02.709027 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:53:02.709468 - {DTB_ADDR}: 0x01070000
243 01:53:02.709905 - {DTB}: 795993/tftp-deploy-so3j_v9c/dtb/meson-g12b-a311d-libretech-cc.dtb
244 01:53:02.710346 - {INITRD}: 795993/tftp-deploy-so3j_v9c/ramdisk/ramdisk.cpio.gz.uboot
245 01:53:02.710780 - {KERNEL_ADDR}: 0x01080000
246 01:53:02.711330 - {KERNEL}: 795993/tftp-deploy-so3j_v9c/kernel/uImage
247 01:53:02.711779 - {LAVA_MAC}: None
248 01:53:02.712290 - {PRESEED_CONFIG}: None
249 01:53:02.712731 - {PRESEED_LOCAL}: None
250 01:53:02.713165 - {RAMDISK_ADDR}: 0x08000000
251 01:53:02.713592 - {RAMDISK}: 795993/tftp-deploy-so3j_v9c/ramdisk/ramdisk.cpio.gz.uboot
252 01:53:02.714024 - {ROOT_PART}: None
253 01:53:02.714456 - {ROOT}: None
254 01:53:02.714886 - {SERVER_IP}: 192.168.6.2
255 01:53:02.715317 - {TEE_ADDR}: 0x83000000
256 01:53:02.715745 - {TEE}: None
257 01:53:02.716207 Parsed boot commands:
258 01:53:02.716628 - setenv autoload no
259 01:53:02.717058 - setenv initrd_high 0xffffffff
260 01:53:02.717487 - setenv fdt_high 0xffffffff
261 01:53:02.717917 - dhcp
262 01:53:02.718347 - setenv serverip 192.168.6.2
263 01:53:02.718772 - tftpboot 0x01080000 795993/tftp-deploy-so3j_v9c/kernel/uImage
264 01:53:02.719201 - tftpboot 0x08000000 795993/tftp-deploy-so3j_v9c/ramdisk/ramdisk.cpio.gz.uboot
265 01:53:02.719628 - tftpboot 0x01070000 795993/tftp-deploy-so3j_v9c/dtb/meson-g12b-a311d-libretech-cc.dtb
266 01:53:02.720082 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:53:02.720520 - bootm 0x01080000 0x08000000 0x01070000
268 01:53:02.721064 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:53:02.722688 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:53:02.723174 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 01:53:02.738561 Setting prompt string to ['lava-test: # ']
273 01:53:02.740181 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:53:02.740846 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:53:02.741448 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:53:02.742025 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:53:02.743260 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 01:53:02.780102 >> OK - accepted request
279 01:53:02.782311 Returned 0 in 0 seconds
280 01:53:02.883483 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:53:02.885293 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:53:02.885916 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:53:02.886466 Setting prompt string to ['Hit any key to stop autoboot']
285 01:53:02.886963 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:53:02.888709 Trying 192.168.56.21...
287 01:53:02.889234 Connected to conserv1.
288 01:53:02.889692 Escape character is '^]'.
289 01:53:02.890155
290 01:53:02.890616 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 01:53:02.891102
292 01:53:14.442520 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 01:53:14.443216 bl2_stage_init 0x01
294 01:53:14.443708 bl2_stage_init 0x81
295 01:53:14.447871 hw id: 0x0000 - pwm id 0x01
296 01:53:14.448482 bl2_stage_init 0xc1
297 01:53:14.448962 bl2_stage_init 0x02
298 01:53:14.449410
299 01:53:14.453441 L0:00000000
300 01:53:14.453972 L1:20000703
301 01:53:14.454448 L2:00008067
302 01:53:14.454889 L3:14000000
303 01:53:14.456376 B2:00402000
304 01:53:14.456849 B1:e0f83180
305 01:53:14.457288
306 01:53:14.457756 TE: 58159
307 01:53:14.458200
308 01:53:14.467451 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 01:53:14.467970
310 01:53:14.468442 Board ID = 1
311 01:53:14.468886 Set A53 clk to 24M
312 01:53:14.469345 Set A73 clk to 24M
313 01:53:14.473136 Set clk81 to 24M
314 01:53:14.473629 A53 clk: 1200 MHz
315 01:53:14.474064 A73 clk: 1200 MHz
316 01:53:14.478839 CLK81: 166.6M
317 01:53:14.479338 smccc: 00012ab5
318 01:53:14.484418 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 01:53:14.484921 board id: 1
320 01:53:14.492057 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:53:14.503603 fw parse done
322 01:53:14.508869 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:53:14.551084 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:53:14.562991 PIEI prepare done
325 01:53:14.563508 fastboot data load
326 01:53:14.563949 fastboot data verify
327 01:53:14.568551 verify result: 266
328 01:53:14.574145 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 01:53:14.574657 LPDDR4 probe
330 01:53:14.575098 ddr clk to 1584MHz
331 01:53:14.581464 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:53:14.618437
333 01:53:14.619016 dmc_version 0001
334 01:53:14.625981 Check phy result
335 01:53:14.632043 INFO : End of CA training
336 01:53:14.632562 INFO : End of initialization
337 01:53:14.637516 INFO : Training has run successfully!
338 01:53:14.638032 Check phy result
339 01:53:14.643139 INFO : End of initialization
340 01:53:14.643648 INFO : End of read enable training
341 01:53:14.648705 INFO : End of fine write leveling
342 01:53:14.654298 INFO : End of Write leveling coarse delay
343 01:53:14.654808 INFO : Training has run successfully!
344 01:53:14.655249 Check phy result
345 01:53:14.660041 INFO : End of initialization
346 01:53:14.660563 INFO : End of read dq deskew training
347 01:53:14.665498 INFO : End of MPR read delay center optimization
348 01:53:14.671141 INFO : End of write delay center optimization
349 01:53:14.676692 INFO : End of read delay center optimization
350 01:53:14.677197 INFO : End of max read latency training
351 01:53:14.682331 INFO : Training has run successfully!
352 01:53:14.682833 1D training succeed
353 01:53:14.690525 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:53:14.738202 Check phy result
355 01:53:14.738739 INFO : End of initialization
356 01:53:14.760054 INFO : End of 2D read delay Voltage center optimization
357 01:53:14.779841 INFO : End of 2D read delay Voltage center optimization
358 01:53:14.831759 INFO : End of 2D write delay Voltage center optimization
359 01:53:14.881945 INFO : End of 2D write delay Voltage center optimization
360 01:53:14.887489 INFO : Training has run successfully!
361 01:53:14.887773
362 01:53:14.888035 channel==0
363 01:53:14.893105 RxClkDly_Margin_A0==88 ps 9
364 01:53:14.893384 TxDqDly_Margin_A0==98 ps 10
365 01:53:14.898777 RxClkDly_Margin_A1==88 ps 9
366 01:53:14.899056 TxDqDly_Margin_A1==98 ps 10
367 01:53:14.899280 TrainedVREFDQ_A0==74
368 01:53:14.904295 TrainedVREFDQ_A1==74
369 01:53:14.904583 VrefDac_Margin_A0==25
370 01:53:14.904805 DeviceVref_Margin_A0==40
371 01:53:14.909912 VrefDac_Margin_A1==25
372 01:53:14.910206 DeviceVref_Margin_A1==40
373 01:53:14.910431
374 01:53:14.910646
375 01:53:14.915578 channel==1
376 01:53:14.915864 RxClkDly_Margin_A0==98 ps 10
377 01:53:14.916119 TxDqDly_Margin_A0==88 ps 9
378 01:53:14.921252 RxClkDly_Margin_A1==98 ps 10
379 01:53:14.921915 TxDqDly_Margin_A1==88 ps 9
380 01:53:14.926739 TrainedVREFDQ_A0==76
381 01:53:14.927427 TrainedVREFDQ_A1==77
382 01:53:14.928050 VrefDac_Margin_A0==22
383 01:53:14.932336 DeviceVref_Margin_A0==38
384 01:53:14.932945 VrefDac_Margin_A1==24
385 01:53:14.938086 DeviceVref_Margin_A1==37
386 01:53:14.938690
387 01:53:14.939266 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:53:14.939817
389 01:53:14.971475 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 0000001a 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 01:53:14.972267 2D training succeed
391 01:53:14.977085 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:53:14.982712 auto size-- 65535DDR cs0 size: 2048MB
393 01:53:14.983341 DDR cs1 size: 2048MB
394 01:53:14.988291 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:53:14.988903 cs0 DataBus test pass
396 01:53:14.993874 cs1 DataBus test pass
397 01:53:14.994494 cs0 AddrBus test pass
398 01:53:14.995060 cs1 AddrBus test pass
399 01:53:14.995570
400 01:53:14.999508 100bdlr_step_size ps== 420
401 01:53:15.000174 result report
402 01:53:15.005093 boot times 0Enable ddr reg access
403 01:53:15.009497 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:53:15.023671 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 01:53:15.596029 0.0;M3 CHK:0;cm4_sp_mode 0
406 01:53:15.596797 MVN_1=0x00000000
407 01:53:15.601518 MVN_2=0x00000000
408 01:53:15.607219 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 01:53:15.607898 OPS=0x10
410 01:53:15.608560 ring efuse init
411 01:53:15.609124 chipver efuse init
412 01:53:15.612860 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 01:53:15.618466 [0.018961 Inits done]
414 01:53:15.619129 secure task start!
415 01:53:15.619711 high task start!
416 01:53:15.622088 low task start!
417 01:53:15.622720 run into bl31
418 01:53:15.629756 NOTICE: BL31: v1.3(release):4fc40b1
419 01:53:15.637541 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 01:53:15.638231 NOTICE: BL31: G12A normal boot!
421 01:53:15.662864 NOTICE: BL31: BL33 decompress pass
422 01:53:15.668312 ERROR: Error initializing runtime service opteed_fast
423 01:53:16.901452
424 01:53:16.902177
425 01:53:16.908763 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 01:53:16.909406
427 01:53:16.909969 Model: Libre Computer AML-A311D-CC Alta
428 01:53:17.117303 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 01:53:17.140609 DRAM: 2 GiB (effective 3.8 GiB)
430 01:53:17.284556 Core: 408 devices, 31 uclasses, devicetree: separate
431 01:53:17.289513 WDT: Not starting watchdog@f0d0
432 01:53:17.322729 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 01:53:17.335151 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 01:53:17.339343 ** Bad device specification mmc 0 **
435 01:53:17.350442 Card did not respond to voltage select! : -110
436 01:53:17.357280 ** Bad device specification mmc 0 **
437 01:53:17.357878 Couldn't find partition mmc 0
438 01:53:17.366453 Card did not respond to voltage select! : -110
439 01:53:17.371912 ** Bad device specification mmc 0 **
440 01:53:17.372540 Couldn't find partition mmc 0
441 01:53:17.376035 Error: could not access storage.
442 01:53:18.642692 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 01:53:18.643561 bl2_stage_init 0x81
444 01:53:18.648261 hw id: 0x0000 - pwm id 0x01
445 01:53:18.648863 bl2_stage_init 0xc1
446 01:53:18.649323 bl2_stage_init 0x02
447 01:53:18.649769
448 01:53:18.653832 L0:00000000
449 01:53:18.654394 L1:20000703
450 01:53:18.654852 L2:00008067
451 01:53:18.655297 L3:14000000
452 01:53:18.655734 B2:00402000
453 01:53:18.659406 B1:e0f83180
454 01:53:18.659948
455 01:53:18.660438 TE: 58150
456 01:53:18.660887
457 01:53:18.664990 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 01:53:18.665538
459 01:53:18.665992 Board ID = 1
460 01:53:18.670637 Set A53 clk to 24M
461 01:53:18.671163 Set A73 clk to 24M
462 01:53:18.671608 Set clk81 to 24M
463 01:53:18.676193 A53 clk: 1200 MHz
464 01:53:18.676723 A73 clk: 1200 MHz
465 01:53:18.677169 CLK81: 166.6M
466 01:53:18.677605 smccc: 00012aac
467 01:53:18.681762 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 01:53:18.687369 board id: 1
469 01:53:18.692571 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 01:53:18.703829 fw parse done
471 01:53:18.709571 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 01:53:18.751717 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 01:53:18.763324 PIEI prepare done
474 01:53:18.763867 fastboot data load
475 01:53:18.764357 fastboot data verify
476 01:53:18.769042 verify result: 266
477 01:53:18.774717 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 01:53:18.775263 LPDDR4 probe
479 01:53:18.775713 ddr clk to 1584MHz
480 01:53:18.781884 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 01:53:18.819844
482 01:53:18.820474 dmc_version 0001
483 01:53:18.825618 Check phy result
484 01:53:18.832417 INFO : End of CA training
485 01:53:18.832967 INFO : End of initialization
486 01:53:18.838002 INFO : Training has run successfully!
487 01:53:18.838546 Check phy result
488 01:53:18.843707 INFO : End of initialization
489 01:53:18.844286 INFO : End of read enable training
490 01:53:18.849189 INFO : End of fine write leveling
491 01:53:18.854780 INFO : End of Write leveling coarse delay
492 01:53:18.855327 INFO : Training has run successfully!
493 01:53:18.855771 Check phy result
494 01:53:18.860403 INFO : End of initialization
495 01:53:18.860954 INFO : End of read dq deskew training
496 01:53:18.866013 INFO : End of MPR read delay center optimization
497 01:53:18.871739 INFO : End of write delay center optimization
498 01:53:18.877221 INFO : End of read delay center optimization
499 01:53:18.877764 INFO : End of max read latency training
500 01:53:18.882832 INFO : Training has run successfully!
501 01:53:18.883396 1D training succeed
502 01:53:18.891008 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 01:53:18.939574 Check phy result
504 01:53:18.940201 INFO : End of initialization
505 01:53:18.962167 INFO : End of 2D read delay Voltage center optimization
506 01:53:18.982487 INFO : End of 2D read delay Voltage center optimization
507 01:53:19.034479 INFO : End of 2D write delay Voltage center optimization
508 01:53:19.083805 INFO : End of 2D write delay Voltage center optimization
509 01:53:19.089420 INFO : Training has run successfully!
510 01:53:19.089976
511 01:53:19.090432 channel==0
512 01:53:19.094972 RxClkDly_Margin_A0==88 ps 9
513 01:53:19.095510 TxDqDly_Margin_A0==98 ps 10
514 01:53:19.100539 RxClkDly_Margin_A1==88 ps 9
515 01:53:19.101077 TxDqDly_Margin_A1==98 ps 10
516 01:53:19.101533 TrainedVREFDQ_A0==74
517 01:53:19.106152 TrainedVREFDQ_A1==75
518 01:53:19.106710 VrefDac_Margin_A0==25
519 01:53:19.107154 DeviceVref_Margin_A0==40
520 01:53:19.111764 VrefDac_Margin_A1==24
521 01:53:19.112333 DeviceVref_Margin_A1==39
522 01:53:19.112783
523 01:53:19.113223
524 01:53:19.117478 channel==1
525 01:53:19.118013 RxClkDly_Margin_A0==98 ps 10
526 01:53:19.118499 TxDqDly_Margin_A0==98 ps 10
527 01:53:19.123058 RxClkDly_Margin_A1==98 ps 10
528 01:53:19.123615 TxDqDly_Margin_A1==98 ps 10
529 01:53:19.128564 TrainedVREFDQ_A0==77
530 01:53:19.129114 TrainedVREFDQ_A1==77
531 01:53:19.129566 VrefDac_Margin_A0==22
532 01:53:19.134113 DeviceVref_Margin_A0==37
533 01:53:19.134519 VrefDac_Margin_A1==22
534 01:53:19.139629 DeviceVref_Margin_A1==37
535 01:53:19.139969
536 01:53:19.140428 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 01:53:19.145383
538 01:53:19.173340 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
539 01:53:19.173947 2D training succeed
540 01:53:19.178943 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 01:53:19.184551 auto size-- 65535DDR cs0 size: 2048MB
542 01:53:19.185103 DDR cs1 size: 2048MB
543 01:53:19.190163 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 01:53:19.190708 cs0 DataBus test pass
545 01:53:19.195739 cs1 DataBus test pass
546 01:53:19.196333 cs0 AddrBus test pass
547 01:53:19.196779 cs1 AddrBus test pass
548 01:53:19.197213
549 01:53:19.201401 100bdlr_step_size ps== 420
550 01:53:19.201959 result report
551 01:53:19.207007 boot times 0Enable ddr reg access
552 01:53:19.211691 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 01:53:19.225935 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 01:53:19.799737 0.0;M3 CHK:0;cm4_sp_mode 0
555 01:53:19.800437 MVN_1=0x00000000
556 01:53:19.805320 MVN_2=0x00000000
557 01:53:19.811013 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 01:53:19.811602 OPS=0x10
559 01:53:19.812127 ring efuse init
560 01:53:19.812603 chipver efuse init
561 01:53:19.816627 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 01:53:19.822162 [0.018961 Inits done]
563 01:53:19.822720 secure task start!
564 01:53:19.823165 high task start!
565 01:53:19.826796 low task start!
566 01:53:19.827327 run into bl31
567 01:53:19.833265 NOTICE: BL31: v1.3(release):4fc40b1
568 01:53:19.841235 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 01:53:19.841790 NOTICE: BL31: G12A normal boot!
570 01:53:19.866523 NOTICE: BL31: BL33 decompress pass
571 01:53:19.872200 ERROR: Error initializing runtime service opteed_fast
572 01:53:21.105392
573 01:53:21.106012
574 01:53:21.113684 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 01:53:21.114254
576 01:53:21.114731 Model: Libre Computer AML-A311D-CC Alta
577 01:53:21.322056 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 01:53:21.345432 DRAM: 2 GiB (effective 3.8 GiB)
579 01:53:21.488428 Core: 408 devices, 31 uclasses, devicetree: separate
580 01:53:21.494328 WDT: Not starting watchdog@f0d0
581 01:53:21.526591 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 01:53:21.538911 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 01:53:21.544086 ** Bad device specification mmc 0 **
584 01:53:21.554299 Card did not respond to voltage select! : -110
585 01:53:21.561930 ** Bad device specification mmc 0 **
586 01:53:21.562482 Couldn't find partition mmc 0
587 01:53:21.570377 Card did not respond to voltage select! : -110
588 01:53:21.575883 ** Bad device specification mmc 0 **
589 01:53:21.576511 Couldn't find partition mmc 0
590 01:53:21.580968 Error: could not access storage.
591 01:53:21.923388 Net: eth0: ethernet@ff3f0000
592 01:53:21.924067 starting USB...
593 01:53:22.176171 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 01:53:22.176790 Starting the controller
595 01:53:22.183100 USB XHCI 1.10
596 01:53:23.892893 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 01:53:23.893527 bl2_stage_init 0x01
598 01:53:23.894014 bl2_stage_init 0x81
599 01:53:23.898447 hw id: 0x0000 - pwm id 0x01
600 01:53:23.899005 bl2_stage_init 0xc1
601 01:53:23.899485 bl2_stage_init 0x02
602 01:53:23.899946
603 01:53:23.904090 L0:00000000
604 01:53:23.904644 L1:20000703
605 01:53:23.905115 L2:00008067
606 01:53:23.905578 L3:14000000
607 01:53:23.906901 B2:00402000
608 01:53:23.907434 B1:e0f83180
609 01:53:23.907902
610 01:53:23.908398 TE: 58167
611 01:53:23.908855
612 01:53:23.918061 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 01:53:23.918615
614 01:53:23.919086 Board ID = 1
615 01:53:23.919543 Set A53 clk to 24M
616 01:53:23.920025 Set A73 clk to 24M
617 01:53:23.923693 Set clk81 to 24M
618 01:53:23.924268 A53 clk: 1200 MHz
619 01:53:23.924743 A73 clk: 1200 MHz
620 01:53:23.929309 CLK81: 166.6M
621 01:53:23.929858 smccc: 00012abd
622 01:53:23.934905 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 01:53:23.935447 board id: 1
624 01:53:23.943516 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 01:53:23.954181 fw parse done
626 01:53:23.960124 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 01:53:24.002724 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 01:53:24.013650 PIEI prepare done
629 01:53:24.014188 fastboot data load
630 01:53:24.014660 fastboot data verify
631 01:53:24.019256 verify result: 266
632 01:53:24.024868 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 01:53:24.025421 LPDDR4 probe
634 01:53:24.025885 ddr clk to 1584MHz
635 01:53:24.032802 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 01:53:24.070115
637 01:53:24.070674 dmc_version 0001
638 01:53:24.076804 Check phy result
639 01:53:24.082671 INFO : End of CA training
640 01:53:24.083216 INFO : End of initialization
641 01:53:24.088272 INFO : Training has run successfully!
642 01:53:24.088811 Check phy result
643 01:53:24.093860 INFO : End of initialization
644 01:53:24.094398 INFO : End of read enable training
645 01:53:24.099462 INFO : End of fine write leveling
646 01:53:24.105109 INFO : End of Write leveling coarse delay
647 01:53:24.105645 INFO : Training has run successfully!
648 01:53:24.106117 Check phy result
649 01:53:24.110645 INFO : End of initialization
650 01:53:24.111178 INFO : End of read dq deskew training
651 01:53:24.116266 INFO : End of MPR read delay center optimization
652 01:53:24.121841 INFO : End of write delay center optimization
653 01:53:24.127477 INFO : End of read delay center optimization
654 01:53:24.128050 INFO : End of max read latency training
655 01:53:24.133042 INFO : Training has run successfully!
656 01:53:24.133585 1D training succeed
657 01:53:24.142177 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 01:53:24.189818 Check phy result
659 01:53:24.190364 INFO : End of initialization
660 01:53:24.211580 INFO : End of 2D read delay Voltage center optimization
661 01:53:24.231810 INFO : End of 2D read delay Voltage center optimization
662 01:53:24.283794 INFO : End of 2D write delay Voltage center optimization
663 01:53:24.333197 INFO : End of 2D write delay Voltage center optimization
664 01:53:24.338805 INFO : Training has run successfully!
665 01:53:24.339343
666 01:53:24.339815 channel==0
667 01:53:24.344509 RxClkDly_Margin_A0==88 ps 9
668 01:53:24.345048 TxDqDly_Margin_A0==98 ps 10
669 01:53:24.349986 RxClkDly_Margin_A1==88 ps 9
670 01:53:24.350520 TxDqDly_Margin_A1==88 ps 9
671 01:53:24.350988 TrainedVREFDQ_A0==74
672 01:53:24.355581 TrainedVREFDQ_A1==74
673 01:53:24.356160 VrefDac_Margin_A0==25
674 01:53:24.356636 DeviceVref_Margin_A0==40
675 01:53:24.361178 VrefDac_Margin_A1==25
676 01:53:24.361718 DeviceVref_Margin_A1==40
677 01:53:24.362182
678 01:53:24.362641
679 01:53:24.363097 channel==1
680 01:53:24.366794 RxClkDly_Margin_A0==98 ps 10
681 01:53:24.367363 TxDqDly_Margin_A0==98 ps 10
682 01:53:24.372394 RxClkDly_Margin_A1==98 ps 10
683 01:53:24.372947 TxDqDly_Margin_A1==88 ps 9
684 01:53:24.377955 TrainedVREFDQ_A0==77
685 01:53:24.378508 TrainedVREFDQ_A1==77
686 01:53:24.378980 VrefDac_Margin_A0==22
687 01:53:24.383589 DeviceVref_Margin_A0==37
688 01:53:24.384168 VrefDac_Margin_A1==22
689 01:53:24.389179 DeviceVref_Margin_A1==37
690 01:53:24.389720
691 01:53:24.390191 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 01:53:24.390643
693 01:53:24.422776 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
694 01:53:24.423362 2D training succeed
695 01:53:24.428418 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 01:53:24.434001 auto size-- 65535DDR cs0 size: 2048MB
697 01:53:24.434543 DDR cs1 size: 2048MB
698 01:53:24.439577 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 01:53:24.440160 cs0 DataBus test pass
700 01:53:24.445197 cs1 DataBus test pass
701 01:53:24.445738 cs0 AddrBus test pass
702 01:53:24.446206 cs1 AddrBus test pass
703 01:53:24.446661
704 01:53:24.450776 100bdlr_step_size ps== 420
705 01:53:24.451330 result report
706 01:53:24.456532 boot times 0Enable ddr reg access
707 01:53:24.461753 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 01:53:24.475153 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 01:53:25.048208 0.0;M3 CHK:0;cm4_sp_mode 0
710 01:53:25.048634 MVN_1=0x00000000
711 01:53:25.053641 MVN_2=0x00000000
712 01:53:25.059567 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 01:53:25.059928 OPS=0x10
714 01:53:25.060244 ring efuse init
715 01:53:25.060484 chipver efuse init
716 01:53:25.067580 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 01:53:25.067922 [0.018961 Inits done]
718 01:53:25.068203 secure task start!
719 01:53:25.075115 high task start!
720 01:53:25.075456 low task start!
721 01:53:25.075701 run into bl31
722 01:53:25.081755 NOTICE: BL31: v1.3(release):4fc40b1
723 01:53:25.089579 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 01:53:25.089934 NOTICE: BL31: G12A normal boot!
725 01:53:25.114970 NOTICE: BL31: BL33 decompress pass
726 01:53:25.120604 ERROR: Error initializing runtime service opteed_fast
727 01:53:26.353540
728 01:53:26.353956
729 01:53:26.360947 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 01:53:26.361281
731 01:53:26.361509 Model: Libre Computer AML-A311D-CC Alta
732 01:53:26.570153 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 01:53:26.592838 DRAM: 2 GiB (effective 3.8 GiB)
734 01:53:26.736697 Core: 408 devices, 31 uclasses, devicetree: separate
735 01:53:26.742543 WDT: Not starting watchdog@f0d0
736 01:53:26.774836 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 01:53:26.787328 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 01:53:26.792223 ** Bad device specification mmc 0 **
739 01:53:26.802715 Card did not respond to voltage select! : -110
740 01:53:26.810216 ** Bad device specification mmc 0 **
741 01:53:26.810571 Couldn't find partition mmc 0
742 01:53:26.818577 Card did not respond to voltage select! : -110
743 01:53:26.824122 ** Bad device specification mmc 0 **
744 01:53:26.824447 Couldn't find partition mmc 0
745 01:53:26.829153 Error: could not access storage.
746 01:53:27.170737 Net: eth0: ethernet@ff3f0000
747 01:53:27.171133 starting USB...
748 01:53:27.423886 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 01:53:27.424353 Starting the controller
750 01:53:27.430671 USB XHCI 1.10
751 01:53:29.592945 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 01:53:29.593604 bl2_stage_init 0x01
753 01:53:29.594085 bl2_stage_init 0x81
754 01:53:29.598609 hw id: 0x0000 - pwm id 0x01
755 01:53:29.599139 bl2_stage_init 0xc1
756 01:53:29.599608 bl2_stage_init 0x02
757 01:53:29.600156
758 01:53:29.604278 L0:00000000
759 01:53:29.604833 L1:20000703
760 01:53:29.605296 L2:00008067
761 01:53:29.605746 L3:14000000
762 01:53:29.609866 B2:00402000
763 01:53:29.610387 B1:e0f83180
764 01:53:29.610838
765 01:53:29.611292 TE: 58124
766 01:53:29.611741
767 01:53:29.615417 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 01:53:29.615950
769 01:53:29.616462 Board ID = 1
770 01:53:29.621013 Set A53 clk to 24M
771 01:53:29.621539 Set A73 clk to 24M
772 01:53:29.621994 Set clk81 to 24M
773 01:53:29.626606 A53 clk: 1200 MHz
774 01:53:29.627129 A73 clk: 1200 MHz
775 01:53:29.627587 CLK81: 166.6M
776 01:53:29.628062 smccc: 00012a92
777 01:53:29.632245 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 01:53:29.637763 board id: 1
779 01:53:29.643616 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 01:53:29.654357 fw parse done
781 01:53:29.660312 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 01:53:29.702959 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 01:53:29.713863 PIEI prepare done
784 01:53:29.714395 fastboot data load
785 01:53:29.714859 fastboot data verify
786 01:53:29.719437 verify result: 266
787 01:53:29.725016 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 01:53:29.725538 LPDDR4 probe
789 01:53:29.725996 ddr clk to 1584MHz
790 01:53:29.733031 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 01:53:29.769396
792 01:53:29.769946 dmc_version 0001
793 01:53:29.776969 Check phy result
794 01:53:29.782901 INFO : End of CA training
795 01:53:29.783424 INFO : End of initialization
796 01:53:29.788390 INFO : Training has run successfully!
797 01:53:29.788909 Check phy result
798 01:53:29.794015 INFO : End of initialization
799 01:53:29.794531 INFO : End of read enable training
800 01:53:29.799628 INFO : End of fine write leveling
801 01:53:29.805300 INFO : End of Write leveling coarse delay
802 01:53:29.805856 INFO : Training has run successfully!
803 01:53:29.806322 Check phy result
804 01:53:29.810810 INFO : End of initialization
805 01:53:29.811328 INFO : End of read dq deskew training
806 01:53:29.816406 INFO : End of MPR read delay center optimization
807 01:53:29.822023 INFO : End of write delay center optimization
808 01:53:29.827608 INFO : End of read delay center optimization
809 01:53:29.828157 INFO : End of max read latency training
810 01:53:29.833301 INFO : Training has run successfully!
811 01:53:29.833829 1D training succeed
812 01:53:29.842359 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 01:53:29.889936 Check phy result
814 01:53:29.890530 INFO : End of initialization
815 01:53:29.910721 INFO : End of 2D read delay Voltage center optimization
816 01:53:29.931196 INFO : End of 2D read delay Voltage center optimization
817 01:53:29.984041 INFO : End of 2D write delay Voltage center optimization
818 01:53:30.033360 INFO : End of 2D write delay Voltage center optimization
819 01:53:30.038875 INFO : Training has run successfully!
820 01:53:30.039428
821 01:53:30.039912 channel==0
822 01:53:30.044548 RxClkDly_Margin_A0==88 ps 9
823 01:53:30.045126 TxDqDly_Margin_A0==98 ps 10
824 01:53:30.047786 RxClkDly_Margin_A1==88 ps 9
825 01:53:30.048360 TxDqDly_Margin_A1==98 ps 10
826 01:53:30.053321 TrainedVREFDQ_A0==74
827 01:53:30.053865 TrainedVREFDQ_A1==74
828 01:53:30.058956 VrefDac_Margin_A0==25
829 01:53:30.059486 DeviceVref_Margin_A0==40
830 01:53:30.059946 VrefDac_Margin_A1==24
831 01:53:30.064541 DeviceVref_Margin_A1==40
832 01:53:30.065107
833 01:53:30.065587
834 01:53:30.066049 channel==1
835 01:53:30.066500 RxClkDly_Margin_A0==98 ps 10
836 01:53:30.070122 TxDqDly_Margin_A0==98 ps 10
837 01:53:30.070668 RxClkDly_Margin_A1==98 ps 10
838 01:53:30.075846 TxDqDly_Margin_A1==88 ps 9
839 01:53:30.076449 TrainedVREFDQ_A0==77
840 01:53:30.076902 TrainedVREFDQ_A1==77
841 01:53:30.081330 VrefDac_Margin_A0==22
842 01:53:30.081883 DeviceVref_Margin_A0==37
843 01:53:30.086985 VrefDac_Margin_A1==22
844 01:53:30.087523 DeviceVref_Margin_A1==37
845 01:53:30.088012
846 01:53:30.092537 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 01:53:30.093079
848 01:53:30.120529 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 01:53:30.126136 2D training succeed
850 01:53:30.131723 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 01:53:30.132301 auto size-- 65535DDR cs0 size: 2048MB
852 01:53:30.137295 DDR cs1 size: 2048MB
853 01:53:30.137819 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 01:53:30.142923 cs0 DataBus test pass
855 01:53:30.143456 cs1 DataBus test pass
856 01:53:30.143919 cs0 AddrBus test pass
857 01:53:30.148545 cs1 AddrBus test pass
858 01:53:30.149072
859 01:53:30.149540 100bdlr_step_size ps== 420
860 01:53:30.150000 result report
861 01:53:30.154123 boot times 0Enable ddr reg access
862 01:53:30.161046 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 01:53:30.175378 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 01:53:30.749089 0.0;M3 CHK:0;cm4_sp_mode 0
865 01:53:30.749756 MVN_1=0x00000000
866 01:53:30.754565 MVN_2=0x00000000
867 01:53:30.760339 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 01:53:30.760874 OPS=0x10
869 01:53:30.761340 ring efuse init
870 01:53:30.761795 chipver efuse init
871 01:53:30.765896 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 01:53:30.771488 [0.018961 Inits done]
873 01:53:30.772060 secure task start!
874 01:53:30.772522 high task start!
875 01:53:30.776138 low task start!
876 01:53:30.776678 run into bl31
877 01:53:30.782811 NOTICE: BL31: v1.3(release):4fc40b1
878 01:53:30.790567 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 01:53:30.791107 NOTICE: BL31: G12A normal boot!
880 01:53:30.816065 NOTICE: BL31: BL33 decompress pass
881 01:53:30.821694 ERROR: Error initializing runtime service opteed_fast
882 01:53:32.054562
883 01:53:32.055226
884 01:53:32.062939 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 01:53:32.063479
886 01:53:32.063940 Model: Libre Computer AML-A311D-CC Alta
887 01:53:32.270655 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 01:53:32.294676 DRAM: 2 GiB (effective 3.8 GiB)
889 01:53:32.437724 Core: 408 devices, 31 uclasses, devicetree: separate
890 01:53:32.443551 WDT: Not starting watchdog@f0d0
891 01:53:32.475825 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 01:53:32.488371 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 01:53:32.493330 ** Bad device specification mmc 0 **
894 01:53:32.503847 Card did not respond to voltage select! : -110
895 01:53:32.511864 ** Bad device specification mmc 0 **
896 01:53:32.512427 Couldn't find partition mmc 0
897 01:53:32.520709 Card did not respond to voltage select! : -110
898 01:53:32.526563 ** Bad device specification mmc 0 **
899 01:53:32.527084 Couldn't find partition mmc 0
900 01:53:32.530129 Error: could not access storage.
901 01:53:32.872665 Net: eth0: ethernet@ff3f0000
902 01:53:32.873287 starting USB...
903 01:53:33.124613 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 01:53:33.125281 Starting the controller
905 01:53:33.131846 USB XHCI 1.10
906 01:53:34.685436 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 01:53:34.693958 scanning usb for storage devices... 0 Storage Device(s) found
909 01:53:34.745647 Hit any key to stop autoboot: 1
910 01:53:34.746556 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 01:53:34.747250 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 01:53:34.747787 Setting prompt string to ['=>']
913 01:53:34.748384 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 01:53:34.761417 0
915 01:53:34.762408 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 01:53:34.762965 Sending with 10 millisecond of delay
918 01:53:35.898219 => setenv autoload no
919 01:53:35.909116 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 01:53:35.914981 setenv autoload no
921 01:53:35.915817 Sending with 10 millisecond of delay
923 01:53:37.713636 => setenv initrd_high 0xffffffff
924 01:53:37.724821 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 01:53:37.725973 setenv initrd_high 0xffffffff
926 01:53:37.726746 Sending with 10 millisecond of delay
928 01:53:39.344731 => setenv fdt_high 0xffffffff
929 01:53:39.355569 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 01:53:39.356693 setenv fdt_high 0xffffffff
931 01:53:39.357490 Sending with 10 millisecond of delay
933 01:53:39.649470 => dhcp
934 01:53:39.660305 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 01:53:39.661233 dhcp
936 01:53:39.661705 Speed: 1000, full duplex
937 01:53:39.662274 BOOTP broadcast 1
938 01:53:40.128272 BOOTP broadcast 2
939 01:53:40.408871 BOOTP broadcast 3
940 01:53:40.420609 DHCP client bound to address 192.168.6.33 (761 ms)
941 01:53:40.421240 Sending with 10 millisecond of delay
943 01:53:42.098423 => setenv serverip 192.168.6.2
944 01:53:42.109039 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
945 01:53:42.109954 setenv serverip 192.168.6.2
946 01:53:42.110640 Sending with 10 millisecond of delay
948 01:53:45.835463 => tftpboot 0x01080000 795993/tftp-deploy-so3j_v9c/kernel/uImage
949 01:53:45.846430 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
950 01:53:45.847396 tftpboot 0x01080000 795993/tftp-deploy-so3j_v9c/kernel/uImage
951 01:53:45.847911 Speed: 1000, full duplex
952 01:53:45.848430 Using ethernet@ff3f0000 device
953 01:53:45.850214 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
954 01:53:45.855665 Filename '795993/tftp-deploy-so3j_v9c/kernel/uImage'.
955 01:53:45.859680 Load address: 0x1080000
956 01:53:56.408947 Loading: *##################T #
957 01:53:56.409649 TFTP error: trying to overwrite reserved memory...
959 01:53:56.411197 end: 2.4.3 bootloader-commands (duration 00:00:22) [common]
962 01:53:56.413370 end: 2.4 uboot-commands (duration 00:00:54) [common]
964 01:53:56.414996 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
966 01:53:56.416193 end: 2 uboot-action (duration 00:00:54) [common]
968 01:53:56.417860 Cleaning after the job
969 01:53:56.418457 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/ramdisk
970 01:53:56.451722 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/kernel
971 01:53:56.504959 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/dtb
972 01:53:56.505895 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795993/tftp-deploy-so3j_v9c/modules
973 01:53:56.561505 start: 4.1 power-off (timeout 00:00:30) [common]
974 01:53:56.562169 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
975 01:53:56.598854 >> OK - accepted request
976 01:53:56.601104 Returned 0 in 0 seconds
977 01:53:56.702163 end: 4.1 power-off (duration 00:00:00) [common]
979 01:53:56.703172 start: 4.2 read-feedback (timeout 00:10:00) [common]
980 01:53:56.703835 Listened to connection for namespace 'common' for up to 1s
981 01:53:57.704086 Finalising connection for namespace 'common'
982 01:53:57.704624 Disconnecting from shell: Finalise
983 01:53:57.704920 =>
984 01:53:57.805582 end: 4.2 read-feedback (duration 00:00:01) [common]
985 01:53:57.806070 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795993
986 01:53:58.144847 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795993
987 01:53:58.145464 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.