Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:54:45.389709 lava-dispatcher, installed at version: 2024.01
2 01:54:45.390515 start: 0 validate
3 01:54:45.391000 Start time: 2024-10-03 01:54:45.390969+00:00 (UTC)
4 01:54:45.391543 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:54:45.392111 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:54:45.432149 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:54:45.432723 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fkernel%2FImage exists
8 01:54:45.464372 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:54:45.464988 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:54:45.496592 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:54:45.497107 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:54:45.526078 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:54:45.526721 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Bdebug%2Fgcc-12%2Fmodules.tar.xz exists
14 01:54:45.567472 validate duration: 0.18
16 01:54:45.568563 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:54:45.568894 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:54:45.569208 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:54:45.569787 Not decompressing ramdisk as can be used compressed.
20 01:54:45.570242 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 01:54:45.570526 saving as /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/ramdisk/initrd.cpio.gz
22 01:54:45.570801 total size: 5628182 (5 MB)
23 01:54:45.610423 progress 0 % (0 MB)
24 01:54:45.614793 progress 5 % (0 MB)
25 01:54:45.619036 progress 10 % (0 MB)
26 01:54:45.622661 progress 15 % (0 MB)
27 01:54:45.626848 progress 20 % (1 MB)
28 01:54:45.630583 progress 25 % (1 MB)
29 01:54:45.634551 progress 30 % (1 MB)
30 01:54:45.638745 progress 35 % (1 MB)
31 01:54:45.642271 progress 40 % (2 MB)
32 01:54:45.646247 progress 45 % (2 MB)
33 01:54:45.649795 progress 50 % (2 MB)
34 01:54:45.653764 progress 55 % (2 MB)
35 01:54:45.657697 progress 60 % (3 MB)
36 01:54:45.661217 progress 65 % (3 MB)
37 01:54:45.665252 progress 70 % (3 MB)
38 01:54:45.668813 progress 75 % (4 MB)
39 01:54:45.672802 progress 80 % (4 MB)
40 01:54:45.676332 progress 85 % (4 MB)
41 01:54:45.680256 progress 90 % (4 MB)
42 01:54:45.684048 progress 95 % (5 MB)
43 01:54:45.687301 progress 100 % (5 MB)
44 01:54:45.687966 5 MB downloaded in 0.12 s (45.82 MB/s)
45 01:54:45.688577 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:54:45.689516 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:54:45.689832 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:54:45.690121 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:54:45.690617 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/kernel/Image
51 01:54:45.690885 saving as /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/kernel/Image
52 01:54:45.691107 total size: 169937408 (162 MB)
53 01:54:45.691325 No compression specified
54 01:54:45.730561 progress 0 % (0 MB)
55 01:54:45.846301 progress 5 % (8 MB)
56 01:54:45.972579 progress 10 % (16 MB)
57 01:54:46.099823 progress 15 % (24 MB)
58 01:54:46.227868 progress 20 % (32 MB)
59 01:54:46.352368 progress 25 % (40 MB)
60 01:54:46.477815 progress 30 % (48 MB)
61 01:54:46.603334 progress 35 % (56 MB)
62 01:54:46.731670 progress 40 % (64 MB)
63 01:54:46.859523 progress 45 % (72 MB)
64 01:54:46.987138 progress 50 % (81 MB)
65 01:54:47.126597 progress 55 % (89 MB)
66 01:54:47.261735 progress 60 % (97 MB)
67 01:54:47.389700 progress 65 % (105 MB)
68 01:54:47.516743 progress 70 % (113 MB)
69 01:54:47.644770 progress 75 % (121 MB)
70 01:54:47.773920 progress 80 % (129 MB)
71 01:54:47.901217 progress 85 % (137 MB)
72 01:54:48.028567 progress 90 % (145 MB)
73 01:54:48.156063 progress 95 % (153 MB)
74 01:54:48.285170 progress 100 % (162 MB)
75 01:54:48.285845 162 MB downloaded in 2.59 s (62.46 MB/s)
76 01:54:48.286467 end: 1.2.1 http-download (duration 00:00:03) [common]
78 01:54:48.287586 end: 1.2 download-retry (duration 00:00:03) [common]
79 01:54:48.287965 start: 1.3 download-retry (timeout 00:09:57) [common]
80 01:54:48.288364 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 01:54:48.288967 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:54:48.289319 saving as /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:54:48.289595 total size: 54703 (0 MB)
84 01:54:48.289854 No compression specified
85 01:54:48.326701 progress 59 % (0 MB)
86 01:54:48.327577 progress 100 % (0 MB)
87 01:54:48.328183 0 MB downloaded in 0.04 s (1.35 MB/s)
88 01:54:48.328674 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:54:48.329513 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:54:48.329787 start: 1.4 download-retry (timeout 00:09:57) [common]
92 01:54:48.330059 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 01:54:48.330527 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 01:54:48.330774 saving as /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/nfsrootfs/full.rootfs.tar
95 01:54:48.330987 total size: 107552908 (102 MB)
96 01:54:48.331202 Using unxz to decompress xz
97 01:54:48.367581 progress 0 % (0 MB)
98 01:54:49.128891 progress 5 % (5 MB)
99 01:54:49.866931 progress 10 % (10 MB)
100 01:54:50.585281 progress 15 % (15 MB)
101 01:54:51.339274 progress 20 % (20 MB)
102 01:54:51.906098 progress 25 % (25 MB)
103 01:54:52.527523 progress 30 % (30 MB)
104 01:54:53.259856 progress 35 % (35 MB)
105 01:54:53.637018 progress 40 % (41 MB)
106 01:54:54.057990 progress 45 % (46 MB)
107 01:54:54.747532 progress 50 % (51 MB)
108 01:54:55.423533 progress 55 % (56 MB)
109 01:54:56.170279 progress 60 % (61 MB)
110 01:54:56.917570 progress 65 % (66 MB)
111 01:54:57.644315 progress 70 % (71 MB)
112 01:54:58.405944 progress 75 % (76 MB)
113 01:54:59.080085 progress 80 % (82 MB)
114 01:54:59.780280 progress 85 % (87 MB)
115 01:55:00.516276 progress 90 % (92 MB)
116 01:55:01.224362 progress 95 % (97 MB)
117 01:55:01.964573 progress 100 % (102 MB)
118 01:55:01.977662 102 MB downloaded in 13.65 s (7.52 MB/s)
119 01:55:01.978337 end: 1.4.1 http-download (duration 00:00:14) [common]
121 01:55:01.979342 end: 1.4 download-retry (duration 00:00:14) [common]
122 01:55:01.979664 start: 1.5 download-retry (timeout 00:09:44) [common]
123 01:55:01.979976 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 01:55:01.981129 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig+debug/gcc-12/modules.tar.xz
125 01:55:01.981721 saving as /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/modules/modules.tar
126 01:55:01.982250 total size: 27663052 (26 MB)
127 01:55:01.982779 Using unxz to decompress xz
128 01:55:02.028113 progress 0 % (0 MB)
129 01:55:02.211916 progress 5 % (1 MB)
130 01:55:02.422067 progress 10 % (2 MB)
131 01:55:02.622508 progress 15 % (3 MB)
132 01:55:02.864648 progress 20 % (5 MB)
133 01:55:03.069844 progress 25 % (6 MB)
134 01:55:03.271723 progress 30 % (7 MB)
135 01:55:03.473991 progress 35 % (9 MB)
136 01:55:03.673908 progress 40 % (10 MB)
137 01:55:03.866047 progress 45 % (11 MB)
138 01:55:04.078832 progress 50 % (13 MB)
139 01:55:04.290580 progress 55 % (14 MB)
140 01:55:04.497482 progress 60 % (15 MB)
141 01:55:04.686379 progress 65 % (17 MB)
142 01:55:04.892597 progress 70 % (18 MB)
143 01:55:05.093246 progress 75 % (19 MB)
144 01:55:05.292630 progress 80 % (21 MB)
145 01:55:05.501295 progress 85 % (22 MB)
146 01:55:05.726803 progress 90 % (23 MB)
147 01:55:05.935653 progress 95 % (25 MB)
148 01:55:06.148163 progress 100 % (26 MB)
149 01:55:06.159376 26 MB downloaded in 4.18 s (6.32 MB/s)
150 01:55:06.160559 end: 1.5.1 http-download (duration 00:00:04) [common]
152 01:55:06.162387 end: 1.5 download-retry (duration 00:00:04) [common]
153 01:55:06.162970 start: 1.6 prepare-tftp-overlay (timeout 00:09:39) [common]
154 01:55:06.163543 start: 1.6.1 extract-nfsrootfs (timeout 00:09:39) [common]
155 01:55:15.873313 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/796008/extract-nfsrootfs-p41_et8d
156 01:55:15.873932 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 01:55:15.874219 start: 1.6.2 lava-overlay (timeout 00:09:30) [common]
158 01:55:15.874971 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh
159 01:55:15.875436 makedir: /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin
160 01:55:15.875795 makedir: /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/tests
161 01:55:15.876148 makedir: /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/results
162 01:55:15.876500 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-add-keys
163 01:55:15.877030 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-add-sources
164 01:55:15.877537 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-background-process-start
165 01:55:15.878033 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-background-process-stop
166 01:55:15.878555 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-common-functions
167 01:55:15.879053 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-echo-ipv4
168 01:55:15.879540 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-install-packages
169 01:55:15.880065 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-installed-packages
170 01:55:15.880663 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-os-build
171 01:55:15.881161 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-probe-channel
172 01:55:15.881678 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-probe-ip
173 01:55:15.882161 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-target-ip
174 01:55:15.882633 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-target-mac
175 01:55:15.883140 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-target-storage
176 01:55:15.883637 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-test-case
177 01:55:15.884170 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-test-event
178 01:55:15.884680 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-test-feedback
179 01:55:15.885202 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-test-raise
180 01:55:15.885693 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-test-reference
181 01:55:15.886188 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-test-runner
182 01:55:15.886687 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-test-set
183 01:55:15.887182 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-test-shell
184 01:55:15.887668 Updating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-install-packages (oe)
185 01:55:15.888246 Updating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/bin/lava-installed-packages (oe)
186 01:55:15.888704 Creating /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/environment
187 01:55:15.889078 LAVA metadata
188 01:55:15.889339 - LAVA_JOB_ID=796008
189 01:55:15.889556 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:55:15.889913 start: 1.6.2.1 ssh-authorize (timeout 00:09:30) [common]
191 01:55:15.890877 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:55:15.891203 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:30) [common]
193 01:55:15.891414 skipped lava-vland-overlay
194 01:55:15.891658 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:55:15.891913 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:30) [common]
196 01:55:15.892167 skipped lava-multinode-overlay
197 01:55:15.892417 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:55:15.892672 start: 1.6.2.4 test-definition (timeout 00:09:30) [common]
199 01:55:15.892922 Loading test definitions
200 01:55:15.893206 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:30) [common]
201 01:55:15.893435 Using /lava-796008 at stage 0
202 01:55:15.894646 uuid=796008_1.6.2.4.1 testdef=None
203 01:55:15.894963 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:55:15.895229 start: 1.6.2.4.2 test-overlay (timeout 00:09:30) [common]
205 01:55:15.897571 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:55:15.898394 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:30) [common]
208 01:55:15.900706 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:55:15.901549 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:30) [common]
211 01:55:15.903691 runner path: /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/0/tests/0_dmesg test_uuid 796008_1.6.2.4.1
212 01:55:15.904256 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:55:15.905018 Creating lava-test-runner.conf files
215 01:55:15.905223 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/796008/lava-overlay-9vu2a7hh/lava-796008/0 for stage 0
216 01:55:15.905560 - 0_dmesg
217 01:55:15.905895 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:55:15.906182 start: 1.6.2.5 compress-overlay (timeout 00:09:30) [common]
219 01:55:15.927943 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:55:15.928332 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:30) [common]
221 01:55:15.928591 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:55:15.928859 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:55:15.929124 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:30) [common]
224 01:55:16.544789 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:55:16.545252 start: 1.6.4 extract-modules (timeout 00:09:29) [common]
226 01:55:16.545501 extracting modules file /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796008/extract-nfsrootfs-p41_et8d
227 01:55:18.238511 extracting modules file /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/796008/extract-overlay-ramdisk-acvpzv0q/ramdisk
228 01:55:20.005011 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:55:20.005509 start: 1.6.5 apply-overlay-tftp (timeout 00:09:26) [common]
230 01:55:20.005791 [common] Applying overlay to NFS
231 01:55:20.006006 [common] Applying overlay /var/lib/lava/dispatcher/tmp/796008/compress-overlay-tcydnh57/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/796008/extract-nfsrootfs-p41_et8d
232 01:55:20.035960 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:55:20.036433 start: 1.6.6 prepare-kernel (timeout 00:09:26) [common]
234 01:55:20.036708 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:26) [common]
235 01:55:20.036940 Converting downloaded kernel to a uImage
236 01:55:20.037267 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/kernel/Image /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/kernel/uImage
237 01:55:21.709187 output: Image Name:
238 01:55:21.709621 output: Created: Thu Oct 3 01:55:20 2024
239 01:55:21.709831 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:55:21.710036 output: Data Size: 169937408 Bytes = 165954.50 KiB = 162.06 MiB
241 01:55:21.710237 output: Load Address: 01080000
242 01:55:21.710435 output: Entry Point: 01080000
243 01:55:21.710629 output:
244 01:55:21.710964 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:02) [common]
245 01:55:21.711226 end: 1.6.6 prepare-kernel (duration 00:00:02) [common]
246 01:55:21.711490 start: 1.6.7 configure-preseed-file (timeout 00:09:24) [common]
247 01:55:21.711741 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:55:21.712066 start: 1.6.8 compress-ramdisk (timeout 00:09:24) [common]
249 01:55:21.712349 Building ramdisk /var/lib/lava/dispatcher/tmp/796008/extract-overlay-ramdisk-acvpzv0q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/796008/extract-overlay-ramdisk-acvpzv0q/ramdisk
250 01:55:27.060564 >> 426603 blocks
251 01:55:44.714675 Adding RAMdisk u-boot header.
252 01:55:44.715306 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/796008/extract-overlay-ramdisk-acvpzv0q/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/796008/extract-overlay-ramdisk-acvpzv0q/ramdisk.cpio.gz.uboot
253 01:55:45.224635 output: Image Name:
254 01:55:45.225114 output: Created: Thu Oct 3 01:55:44 2024
255 01:55:45.225376 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:55:45.225624 output: Data Size: 50925492 Bytes = 49731.93 KiB = 48.57 MiB
257 01:55:45.225870 output: Load Address: 00000000
258 01:55:45.226113 output: Entry Point: 00000000
259 01:55:45.226355 output:
260 01:55:45.227274 rename /var/lib/lava/dispatcher/tmp/796008/extract-overlay-ramdisk-acvpzv0q/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/ramdisk/ramdisk.cpio.gz.uboot
261 01:55:45.227801 end: 1.6.8 compress-ramdisk (duration 00:00:24) [common]
262 01:55:45.228507 end: 1.6 prepare-tftp-overlay (duration 00:00:39) [common]
263 01:55:45.229344 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:00) [common]
264 01:55:45.229973 No LXC device requested
265 01:55:45.230638 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:55:45.231315 start: 1.8 deploy-device-env (timeout 00:09:00) [common]
267 01:55:45.231972 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:55:45.232563 Checking files for TFTP limit of 4294967296 bytes.
269 01:55:45.236057 end: 1 tftp-deploy (duration 00:01:00) [common]
270 01:55:45.236815 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:55:45.237506 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:55:45.238161 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:55:45.238813 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:55:45.239490 Using kernel file from prepare-kernel: 796008/tftp-deploy-8_qctal2/kernel/uImage
275 01:55:45.240354 substitutions:
276 01:55:45.240919 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:55:45.241438 - {DTB_ADDR}: 0x01070000
278 01:55:45.241950 - {DTB}: 796008/tftp-deploy-8_qctal2/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:55:45.242472 - {INITRD}: 796008/tftp-deploy-8_qctal2/ramdisk/ramdisk.cpio.gz.uboot
280 01:55:45.242983 - {KERNEL_ADDR}: 0x01080000
281 01:55:45.243490 - {KERNEL}: 796008/tftp-deploy-8_qctal2/kernel/uImage
282 01:55:45.244017 - {LAVA_MAC}: None
283 01:55:45.244603 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/796008/extract-nfsrootfs-p41_et8d
284 01:55:45.245131 - {NFS_SERVER_IP}: 192.168.6.2
285 01:55:45.245671 - {PRESEED_CONFIG}: None
286 01:55:45.246190 - {PRESEED_LOCAL}: None
287 01:55:45.246697 - {RAMDISK_ADDR}: 0x08000000
288 01:55:45.247208 - {RAMDISK}: 796008/tftp-deploy-8_qctal2/ramdisk/ramdisk.cpio.gz.uboot
289 01:55:45.247728 - {ROOT_PART}: None
290 01:55:45.248274 - {ROOT}: None
291 01:55:45.248784 - {SERVER_IP}: 192.168.6.2
292 01:55:45.249277 - {TEE_ADDR}: 0x83000000
293 01:55:45.249777 - {TEE}: None
294 01:55:45.250279 Parsed boot commands:
295 01:55:45.250769 - setenv autoload no
296 01:55:45.251327 - setenv initrd_high 0xffffffff
297 01:55:45.251858 - setenv fdt_high 0xffffffff
298 01:55:45.252445 - dhcp
299 01:55:45.252952 - setenv serverip 192.168.6.2
300 01:55:45.253454 - tftpboot 0x01080000 796008/tftp-deploy-8_qctal2/kernel/uImage
301 01:55:45.253956 - tftpboot 0x08000000 796008/tftp-deploy-8_qctal2/ramdisk/ramdisk.cpio.gz.uboot
302 01:55:45.254463 - tftpboot 0x01070000 796008/tftp-deploy-8_qctal2/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:55:45.255010 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/796008/extract-nfsrootfs-p41_et8d,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:55:45.255533 - bootm 0x01080000 0x08000000 0x01070000
305 01:55:45.256236 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:55:45.258158 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:55:45.258703 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:55:45.275064 Setting prompt string to ['lava-test: # ']
310 01:55:45.276950 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:55:45.277730 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:55:45.278441 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:55:45.279426 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:55:45.280945 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:55:45.320169 >> OK - accepted request
316 01:55:45.322200 Returned 0 in 0 seconds
317 01:55:45.423315 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:55:45.425647 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:55:45.426448 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:55:45.427166 Setting prompt string to ['Hit any key to stop autoboot']
322 01:55:45.427819 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:55:45.430034 Trying 192.168.56.21...
324 01:55:45.430698 Connected to conserv1.
325 01:55:45.431276 Escape character is '^]'.
326 01:55:45.431842
327 01:55:45.432475 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:55:45.433049
329 01:55:57.432872 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:55:57.433522 bl2_stage_init 0x01
331 01:55:57.433947 bl2_stage_init 0x81
332 01:55:57.438400 hw id: 0x0000 - pwm id 0x01
333 01:55:57.438911 bl2_stage_init 0xc1
334 01:55:57.439310 bl2_stage_init 0x02
335 01:55:57.439722
336 01:55:57.443973 L0:00000000
337 01:55:57.444493 L1:20000703
338 01:55:57.444907 L2:00008067
339 01:55:57.445295 L3:14000000
340 01:55:57.449677 B2:00402000
341 01:55:57.450185 B1:e0f83180
342 01:55:57.450576
343 01:55:57.450970 TE: 58124
344 01:55:57.451363
345 01:55:57.455247 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:55:57.455720
347 01:55:57.456160 Board ID = 1
348 01:55:57.460833 Set A53 clk to 24M
349 01:55:57.461301 Set A73 clk to 24M
350 01:55:57.461693 Set clk81 to 24M
351 01:55:57.466327 A53 clk: 1200 MHz
352 01:55:57.466783 A73 clk: 1200 MHz
353 01:55:57.467171 CLK81: 166.6M
354 01:55:57.467555 smccc: 00012a92
355 01:55:57.471925 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:55:57.477536 board id: 1
357 01:55:57.483343 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:55:57.493940 fw parse done
359 01:55:57.499964 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:55:57.542570 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:55:57.553531 PIEI prepare done
362 01:55:57.554005 fastboot data load
363 01:55:57.554400 fastboot data verify
364 01:55:57.559205 verify result: 266
365 01:55:57.564798 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:55:57.565267 LPDDR4 probe
367 01:55:57.565659 ddr clk to 1584MHz
368 01:55:57.572753 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:55:57.610084
370 01:55:57.610597 dmc_version 0001
371 01:55:57.616727 Check phy result
372 01:55:57.622609 INFO : End of CA training
373 01:55:57.623084 INFO : End of initialization
374 01:55:57.628244 INFO : Training has run successfully!
375 01:55:57.628723 Check phy result
376 01:55:57.633793 INFO : End of initialization
377 01:55:57.634262 INFO : End of read enable training
378 01:55:57.639392 INFO : End of fine write leveling
379 01:55:57.644975 INFO : End of Write leveling coarse delay
380 01:55:57.645440 INFO : Training has run successfully!
381 01:55:57.645835 Check phy result
382 01:55:57.650623 INFO : End of initialization
383 01:55:57.651111 INFO : End of read dq deskew training
384 01:55:57.656198 INFO : End of MPR read delay center optimization
385 01:55:57.661816 INFO : End of write delay center optimization
386 01:55:57.667403 INFO : End of read delay center optimization
387 01:55:57.667880 INFO : End of max read latency training
388 01:55:57.672968 INFO : Training has run successfully!
389 01:55:57.673440 1D training succeed
390 01:55:57.682221 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:55:57.729735 Check phy result
392 01:55:57.730255 INFO : End of initialization
393 01:55:57.752023 INFO : End of 2D read delay Voltage center optimization
394 01:55:57.771531 INFO : End of 2D read delay Voltage center optimization
395 01:55:57.822464 INFO : End of 2D write delay Voltage center optimization
396 01:55:57.872652 INFO : End of 2D write delay Voltage center optimization
397 01:55:57.878157 INFO : Training has run successfully!
398 01:55:57.878586
399 01:55:57.878847 channel==0
400 01:55:57.883736 RxClkDly_Margin_A0==88 ps 9
401 01:55:57.884193 TxDqDly_Margin_A0==98 ps 10
402 01:55:57.889325 RxClkDly_Margin_A1==88 ps 9
403 01:55:57.889767 TxDqDly_Margin_A1==88 ps 9
404 01:55:57.890038 TrainedVREFDQ_A0==74
405 01:55:57.894976 TrainedVREFDQ_A1==74
406 01:55:57.895406 VrefDac_Margin_A0==25
407 01:55:57.895654 DeviceVref_Margin_A0==40
408 01:55:57.900625 VrefDac_Margin_A1==25
409 01:55:57.901066 DeviceVref_Margin_A1==40
410 01:55:57.901337
411 01:55:57.901604
412 01:55:57.901852 channel==1
413 01:55:57.906158 RxClkDly_Margin_A0==98 ps 10
414 01:55:57.906578 TxDqDly_Margin_A0==98 ps 10
415 01:55:57.911773 RxClkDly_Margin_A1==98 ps 10
416 01:55:57.912228 TxDqDly_Margin_A1==88 ps 9
417 01:55:57.917359 TrainedVREFDQ_A0==77
418 01:55:57.917797 TrainedVREFDQ_A1==77
419 01:55:57.918052 VrefDac_Margin_A0==22
420 01:55:57.922981 DeviceVref_Margin_A0==37
421 01:55:57.923410 VrefDac_Margin_A1==22
422 01:55:57.928630 DeviceVref_Margin_A1==37
423 01:55:57.929044
424 01:55:57.929608 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:55:57.929878
426 01:55:57.962171 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:55:57.962651 2D training succeed
428 01:55:57.967758 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:55:57.973320 auto size-- 65535DDR cs0 size: 2048MB
430 01:55:57.973716 DDR cs1 size: 2048MB
431 01:55:57.978935 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:55:57.979326 cs0 DataBus test pass
433 01:55:57.984648 cs1 DataBus test pass
434 01:55:57.985069 cs0 AddrBus test pass
435 01:55:57.985322 cs1 AddrBus test pass
436 01:55:57.985557
437 01:55:57.990156 100bdlr_step_size ps== 420
438 01:55:57.990574 result report
439 01:55:57.995742 boot times 0Enable ddr reg access
440 01:55:58.000221 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:55:58.014439 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:55:58.586396 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:55:58.586831 MVN_1=0x00000000
444 01:55:58.591925 MVN_2=0x00000000
445 01:55:58.597638 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:55:58.597946 OPS=0x10
447 01:55:58.598202 ring efuse init
448 01:55:58.598439 chipver efuse init
449 01:55:58.603240 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:55:58.609094 [0.018961 Inits done]
451 01:55:58.609413 secure task start!
452 01:55:58.609654 high task start!
453 01:55:58.613447 low task start!
454 01:55:58.613748 run into bl31
455 01:55:58.620191 NOTICE: BL31: v1.3(release):4fc40b1
456 01:55:58.627857 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:55:58.628226 NOTICE: BL31: G12A normal boot!
458 01:55:58.653219 NOTICE: BL31: BL33 decompress pass
459 01:55:58.658385 ERROR: Error initializing runtime service opteed_fast
460 01:55:59.891859
461 01:55:59.892555
462 01:55:59.900225 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:55:59.900709
464 01:55:59.901156 Model: Libre Computer AML-A311D-CC Alta
465 01:56:00.108323 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:56:00.132104 DRAM: 2 GiB (effective 3.8 GiB)
467 01:56:00.275051 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:56:00.280908 WDT: Not starting watchdog@f0d0
469 01:56:00.313189 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:56:00.325643 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:56:00.330604 ** Bad device specification mmc 0 **
472 01:56:00.340964 Card did not respond to voltage select! : -110
473 01:56:00.347732 ** Bad device specification mmc 0 **
474 01:56:00.348255 Couldn't find partition mmc 0
475 01:56:00.356947 Card did not respond to voltage select! : -110
476 01:56:00.362461 ** Bad device specification mmc 0 **
477 01:56:00.362940 Couldn't find partition mmc 0
478 01:56:00.367537 Error: could not access storage.
479 01:56:01.633169 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
480 01:56:01.633859 bl2_stage_init 0x81
481 01:56:01.638758 hw id: 0x0000 - pwm id 0x01
482 01:56:01.639263 bl2_stage_init 0xc1
483 01:56:01.639720 bl2_stage_init 0x02
484 01:56:01.640225
485 01:56:01.644309 L0:00000000
486 01:56:01.644791 L1:20000703
487 01:56:01.645236 L2:00008067
488 01:56:01.645678 L3:14000000
489 01:56:01.646112 B2:00402000
490 01:56:01.649959 B1:e0f83180
491 01:56:01.650446
492 01:56:01.650891 TE: 58150
493 01:56:01.651331
494 01:56:01.655576 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 01:56:01.656098
496 01:56:01.656551 Board ID = 1
497 01:56:01.661094 Set A53 clk to 24M
498 01:56:01.661577 Set A73 clk to 24M
499 01:56:01.662020 Set clk81 to 24M
500 01:56:01.666707 A53 clk: 1200 MHz
501 01:56:01.667189 A73 clk: 1200 MHz
502 01:56:01.667633 CLK81: 166.6M
503 01:56:01.668104 smccc: 00012aab
504 01:56:01.672309 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 01:56:01.677991 board id: 1
506 01:56:01.683737 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 01:56:01.694411 fw parse done
508 01:56:01.700331 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 01:56:01.743046 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 01:56:01.753973 PIEI prepare done
511 01:56:01.754465 fastboot data load
512 01:56:01.754919 fastboot data verify
513 01:56:01.759606 verify result: 266
514 01:56:01.765178 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 01:56:01.765685 LPDDR4 probe
516 01:56:01.766313 ddr clk to 1584MHz
517 01:56:01.773165 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 01:56:01.810357
519 01:56:01.811121 dmc_version 0001
520 01:56:01.817123 Check phy result
521 01:56:01.823059 INFO : End of CA training
522 01:56:01.823567 INFO : End of initialization
523 01:56:01.828505 INFO : Training has run successfully!
524 01:56:01.829006 Check phy result
525 01:56:01.834082 INFO : End of initialization
526 01:56:01.834580 INFO : End of read enable training
527 01:56:01.837436 INFO : End of fine write leveling
528 01:56:01.843082 INFO : End of Write leveling coarse delay
529 01:56:01.848526 INFO : Training has run successfully!
530 01:56:01.849034 Check phy result
531 01:56:01.849481 INFO : End of initialization
532 01:56:01.854120 INFO : End of read dq deskew training
533 01:56:01.859714 INFO : End of MPR read delay center optimization
534 01:56:01.860271 INFO : End of write delay center optimization
535 01:56:01.865332 INFO : End of read delay center optimization
536 01:56:01.871028 INFO : End of max read latency training
537 01:56:01.871537 INFO : Training has run successfully!
538 01:56:01.876551 1D training succeed
539 01:56:01.882477 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 01:56:01.930198 Check phy result
541 01:56:01.930829 INFO : End of initialization
542 01:56:01.952749 INFO : End of 2D read delay Voltage center optimization
543 01:56:01.972269 INFO : End of 2D read delay Voltage center optimization
544 01:56:02.025018 INFO : End of 2D write delay Voltage center optimization
545 01:56:02.074384 INFO : End of 2D write delay Voltage center optimization
546 01:56:02.079904 INFO : Training has run successfully!
547 01:56:02.080415
548 01:56:02.080866 channel==0
549 01:56:02.085514 RxClkDly_Margin_A0==88 ps 9
550 01:56:02.086003 TxDqDly_Margin_A0==98 ps 10
551 01:56:02.091119 RxClkDly_Margin_A1==88 ps 9
552 01:56:02.091585 TxDqDly_Margin_A1==98 ps 10
553 01:56:02.092064 TrainedVREFDQ_A0==74
554 01:56:02.096756 TrainedVREFDQ_A1==74
555 01:56:02.097229 VrefDac_Margin_A0==24
556 01:56:02.097668 DeviceVref_Margin_A0==40
557 01:56:02.102318 VrefDac_Margin_A1==25
558 01:56:02.102778 DeviceVref_Margin_A1==40
559 01:56:02.103208
560 01:56:02.103640
561 01:56:02.107896 channel==1
562 01:56:02.108385 RxClkDly_Margin_A0==98 ps 10
563 01:56:02.108823 TxDqDly_Margin_A0==98 ps 10
564 01:56:02.113514 RxClkDly_Margin_A1==98 ps 10
565 01:56:02.113975 TxDqDly_Margin_A1==88 ps 9
566 01:56:02.119104 TrainedVREFDQ_A0==77
567 01:56:02.119566 TrainedVREFDQ_A1==77
568 01:56:02.120028 VrefDac_Margin_A0==22
569 01:56:02.124672 DeviceVref_Margin_A0==37
570 01:56:02.125133 VrefDac_Margin_A1==23
571 01:56:02.130294 DeviceVref_Margin_A1==37
572 01:56:02.130771
573 01:56:02.131205 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 01:56:02.135889
575 01:56:02.163883 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 01:56:02.164447 2D training succeed
577 01:56:02.169594 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 01:56:02.175163 auto size-- 65535DDR cs0 size: 2048MB
579 01:56:02.175679 DDR cs1 size: 2048MB
580 01:56:02.180700 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 01:56:02.181172 cs0 DataBus test pass
582 01:56:02.186384 cs1 DataBus test pass
583 01:56:02.186858 cs0 AddrBus test pass
584 01:56:02.187294 cs1 AddrBus test pass
585 01:56:02.187721
586 01:56:02.192024 100bdlr_step_size ps== 420
587 01:56:02.192518 result report
588 01:56:02.197547 boot times 0Enable ddr reg access
589 01:56:02.202030 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 01:56:02.216336 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 01:56:02.790060 0.0;M3 CHK:0;cm4_sp_mode 0
592 01:56:02.790670 MVN_1=0x00000000
593 01:56:02.795593 MVN_2=0x00000000
594 01:56:02.803095 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 01:56:02.803510 OPS=0x10
596 01:56:02.803726 ring efuse init
597 01:56:02.803926 chipver efuse init
598 01:56:02.808133 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 01:56:02.812431 [0.018960 Inits done]
600 01:56:02.812900 secure task start!
601 01:56:02.813331 high task start!
602 01:56:02.817693 low task start!
603 01:56:02.818152 run into bl31
604 01:56:02.827877 NOTICE: BL31: v1.3(release):4fc40b1
605 01:56:02.833551 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 01:56:02.834022 NOTICE: BL31: G12A normal boot!
607 01:56:02.859675 NOTICE: BL31: BL33 decompress pass
608 01:56:02.865054 ERROR: Error initializing runtime service opteed_fast
609 01:56:04.095431
610 01:56:04.096169
611 01:56:04.104257 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 01:56:04.104770
613 01:56:04.105137 Model: Libre Computer AML-A311D-CC Alta
614 01:56:04.312448 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 01:56:04.335402 DRAM: 2 GiB (effective 3.8 GiB)
616 01:56:04.478779 Core: 408 devices, 31 uclasses, devicetree: separate
617 01:56:04.483573 WDT: Not starting watchdog@f0d0
618 01:56:04.516804 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 01:56:04.529373 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 01:56:04.533188 ** Bad device specification mmc 0 **
621 01:56:04.544521 Card did not respond to voltage select! : -110
622 01:56:04.551409 ** Bad device specification mmc 0 **
623 01:56:04.551759 Couldn't find partition mmc 0
624 01:56:04.560558 Card did not respond to voltage select! : -110
625 01:56:04.566169 ** Bad device specification mmc 0 **
626 01:56:04.566733 Couldn't find partition mmc 0
627 01:56:04.570234 Error: could not access storage.
628 01:56:04.914674 Net: eth0: ethernet@ff3f0000
629 01:56:04.915302 starting USB...
630 01:56:05.166653 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 01:56:05.167268 Starting the controller
632 01:56:05.173529 USB XHCI 1.10
633 01:56:06.883481 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 01:56:06.884140 bl2_stage_init 0x01
635 01:56:06.884590 bl2_stage_init 0x81
636 01:56:06.889086 hw id: 0x0000 - pwm id 0x01
637 01:56:06.889635 bl2_stage_init 0xc1
638 01:56:06.890088 bl2_stage_init 0x02
639 01:56:06.890518
640 01:56:06.894699 L0:00000000
641 01:56:06.895239 L1:20000703
642 01:56:06.895681 L2:00008067
643 01:56:06.896136 L3:14000000
644 01:56:06.897627 B2:00402000
645 01:56:06.897931 B1:e0f83180
646 01:56:06.898177
647 01:56:06.898420 TE: 58159
648 01:56:06.898657
649 01:56:06.908774 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 01:56:06.909117
651 01:56:06.909390 Board ID = 1
652 01:56:06.909641 Set A53 clk to 24M
653 01:56:06.909872 Set A73 clk to 24M
654 01:56:06.914303 Set clk81 to 24M
655 01:56:06.914748 A53 clk: 1200 MHz
656 01:56:06.915146 A73 clk: 1200 MHz
657 01:56:06.920029 CLK81: 166.6M
658 01:56:06.920717 smccc: 00012ab5
659 01:56:06.925534 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 01:56:06.926025 board id: 1
661 01:56:06.934077 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 01:56:06.944801 fw parse done
663 01:56:06.950754 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 01:56:06.993330 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 01:56:07.004269 PIEI prepare done
666 01:56:07.004761 fastboot data load
667 01:56:07.005257 fastboot data verify
668 01:56:07.009914 verify result: 266
669 01:56:07.015525 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 01:56:07.016039 LPDDR4 probe
671 01:56:07.016448 ddr clk to 1584MHz
672 01:56:07.023577 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 01:56:07.060912
674 01:56:07.061570 dmc_version 0001
675 01:56:07.067439 Check phy result
676 01:56:07.073245 INFO : End of CA training
677 01:56:07.073864 INFO : End of initialization
678 01:56:07.079319 INFO : Training has run successfully!
679 01:56:07.079919 Check phy result
680 01:56:07.084506 INFO : End of initialization
681 01:56:07.085126 INFO : End of read enable training
682 01:56:07.087816 INFO : End of fine write leveling
683 01:56:07.093402 INFO : End of Write leveling coarse delay
684 01:56:07.098952 INFO : Training has run successfully!
685 01:56:07.099469 Check phy result
686 01:56:07.099916 INFO : End of initialization
687 01:56:07.104565 INFO : End of read dq deskew training
688 01:56:07.110188 INFO : End of MPR read delay center optimization
689 01:56:07.110749 INFO : End of write delay center optimization
690 01:56:07.115721 INFO : End of read delay center optimization
691 01:56:07.121417 INFO : End of max read latency training
692 01:56:07.121971 INFO : Training has run successfully!
693 01:56:07.126927 1D training succeed
694 01:56:07.132880 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 01:56:07.180592 Check phy result
696 01:56:07.181213 INFO : End of initialization
697 01:56:07.201236 INFO : End of 2D read delay Voltage center optimization
698 01:56:07.221357 INFO : End of 2D read delay Voltage center optimization
699 01:56:07.274122 INFO : End of 2D write delay Voltage center optimization
700 01:56:07.323931 INFO : End of 2D write delay Voltage center optimization
701 01:56:07.329307 INFO : Training has run successfully!
702 01:56:07.329850
703 01:56:07.330300 channel==0
704 01:56:07.334868 RxClkDly_Margin_A0==88 ps 9
705 01:56:07.335423 TxDqDly_Margin_A0==98 ps 10
706 01:56:07.338141 RxClkDly_Margin_A1==88 ps 9
707 01:56:07.338631 TxDqDly_Margin_A1==98 ps 10
708 01:56:07.343773 TrainedVREFDQ_A0==74
709 01:56:07.344376 TrainedVREFDQ_A1==75
710 01:56:07.349256 VrefDac_Margin_A0==25
711 01:56:07.349777 DeviceVref_Margin_A0==40
712 01:56:07.350219 VrefDac_Margin_A1==23
713 01:56:07.354818 DeviceVref_Margin_A1==39
714 01:56:07.355301
715 01:56:07.355741
716 01:56:07.356219 channel==1
717 01:56:07.356653 RxClkDly_Margin_A0==98 ps 10
718 01:56:07.358291 TxDqDly_Margin_A0==98 ps 10
719 01:56:07.363765 RxClkDly_Margin_A1==98 ps 10
720 01:56:07.364278 TxDqDly_Margin_A1==108 ps 11
721 01:56:07.369481 TrainedVREFDQ_A0==77
722 01:56:07.370050 TrainedVREFDQ_A1==78
723 01:56:07.370492 VrefDac_Margin_A0==22
724 01:56:07.375111 DeviceVref_Margin_A0==37
725 01:56:07.375599 VrefDac_Margin_A1==24
726 01:56:07.376071 DeviceVref_Margin_A1==36
727 01:56:07.376510
728 01:56:07.380648 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 01:56:07.381142
730 01:56:07.414195 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
731 01:56:07.414740 2D training succeed
732 01:56:07.419772 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 01:56:07.425438 auto size-- 65535DDR cs0 size: 2048MB
734 01:56:07.425981 DDR cs1 size: 2048MB
735 01:56:07.431026 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 01:56:07.431546 cs0 DataBus test pass
737 01:56:07.432024 cs1 DataBus test pass
738 01:56:07.436636 cs0 AddrBus test pass
739 01:56:07.437167 cs1 AddrBus test pass
740 01:56:07.437608
741 01:56:07.442229 100bdlr_step_size ps== 420
742 01:56:07.442728 result report
743 01:56:07.443163 boot times 0Enable ddr reg access
744 01:56:07.451568 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 01:56:07.464979 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 01:56:08.039670 0.0;M3 CHK:0;cm4_sp_mode 0
747 01:56:08.040396 MVN_1=0x00000000
748 01:56:08.045156 MVN_2=0x00000000
749 01:56:08.051001 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 01:56:08.051569 OPS=0x10
751 01:56:08.052055 ring efuse init
752 01:56:08.052500 chipver efuse init
753 01:56:08.056415 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 01:56:08.062059 [0.018961 Inits done]
755 01:56:08.062540 secure task start!
756 01:56:08.062980 high task start!
757 01:56:08.066626 low task start!
758 01:56:08.067091 run into bl31
759 01:56:08.073378 NOTICE: BL31: v1.3(release):4fc40b1
760 01:56:08.080638 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 01:56:08.081135 NOTICE: BL31: G12A normal boot!
762 01:56:08.106499 NOTICE: BL31: BL33 decompress pass
763 01:56:08.112255 ERROR: Error initializing runtime service opteed_fast
764 01:56:09.345332
765 01:56:09.345977
766 01:56:09.352651 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 01:56:09.353188
768 01:56:09.353657 Model: Libre Computer AML-A311D-CC Alta
769 01:56:09.562101 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 01:56:09.584629 DRAM: 2 GiB (effective 3.8 GiB)
771 01:56:09.728499 Core: 408 devices, 31 uclasses, devicetree: separate
772 01:56:09.733202 WDT: Not starting watchdog@f0d0
773 01:56:09.766561 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 01:56:09.779021 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 01:56:09.782984 ** Bad device specification mmc 0 **
776 01:56:09.794421 Card did not respond to voltage select! : -110
777 01:56:09.801109 ** Bad device specification mmc 0 **
778 01:56:09.801779 Couldn't find partition mmc 0
779 01:56:09.810334 Card did not respond to voltage select! : -110
780 01:56:09.815832 ** Bad device specification mmc 0 **
781 01:56:09.816436 Couldn't find partition mmc 0
782 01:56:09.820042 Error: could not access storage.
783 01:56:10.164518 Net: eth0: ethernet@ff3f0000
784 01:56:10.165139 starting USB...
785 01:56:10.416082 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 01:56:10.416710 Starting the controller
787 01:56:10.423000 USB XHCI 1.10
788 01:56:12.584710 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 01:56:12.585299 bl2_stage_init 0x01
790 01:56:12.585730 bl2_stage_init 0x81
791 01:56:12.590222 hw id: 0x0000 - pwm id 0x01
792 01:56:12.590677 bl2_stage_init 0xc1
793 01:56:12.591096 bl2_stage_init 0x02
794 01:56:12.591501
795 01:56:12.595891 L0:00000000
796 01:56:12.596496 L1:20000703
797 01:56:12.596915 L2:00008067
798 01:56:12.597316 L3:14000000
799 01:56:12.601443 B2:00402000
800 01:56:12.601927 B1:e0f83180
801 01:56:12.602324
802 01:56:12.602716 TE: 58124
803 01:56:12.603110
804 01:56:12.607184 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 01:56:12.607662
806 01:56:12.608098 Board ID = 1
807 01:56:12.612658 Set A53 clk to 24M
808 01:56:12.613106 Set A73 clk to 24M
809 01:56:12.613501 Set clk81 to 24M
810 01:56:12.618253 A53 clk: 1200 MHz
811 01:56:12.618748 A73 clk: 1200 MHz
812 01:56:12.619147 CLK81: 166.6M
813 01:56:12.619535 smccc: 00012a92
814 01:56:12.623853 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 01:56:12.629400 board id: 1
816 01:56:12.635324 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 01:56:12.645973 fw parse done
818 01:56:12.651972 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 01:56:12.694697 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 01:56:12.705583 PIEI prepare done
821 01:56:12.706074 fastboot data load
822 01:56:12.706487 fastboot data verify
823 01:56:12.711132 verify result: 266
824 01:56:12.716823 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 01:56:12.717390 LPDDR4 probe
826 01:56:12.717833 ddr clk to 1584MHz
827 01:56:12.723760 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 01:56:12.762078
829 01:56:12.762629 dmc_version 0001
830 01:56:12.768642 Check phy result
831 01:56:12.774531 INFO : End of CA training
832 01:56:12.775035 INFO : End of initialization
833 01:56:12.780154 INFO : Training has run successfully!
834 01:56:12.780636 Check phy result
835 01:56:12.785733 INFO : End of initialization
836 01:56:12.786174 INFO : End of read enable training
837 01:56:12.791273 INFO : End of fine write leveling
838 01:56:12.796924 INFO : End of Write leveling coarse delay
839 01:56:12.797418 INFO : Training has run successfully!
840 01:56:12.797835 Check phy result
841 01:56:12.802566 INFO : End of initialization
842 01:56:12.803055 INFO : End of read dq deskew training
843 01:56:12.808164 INFO : End of MPR read delay center optimization
844 01:56:12.813713 INFO : End of write delay center optimization
845 01:56:12.819307 INFO : End of read delay center optimization
846 01:56:12.819787 INFO : End of max read latency training
847 01:56:12.824932 INFO : Training has run successfully!
848 01:56:12.825428 1D training succeed
849 01:56:12.834089 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 01:56:12.881803 Check phy result
851 01:56:12.882401 INFO : End of initialization
852 01:56:12.903353 INFO : End of 2D read delay Voltage center optimization
853 01:56:12.923427 INFO : End of 2D read delay Voltage center optimization
854 01:56:12.975375 INFO : End of 2D write delay Voltage center optimization
855 01:56:13.024822 INFO : End of 2D write delay Voltage center optimization
856 01:56:13.030321 INFO : Training has run successfully!
857 01:56:13.030776
858 01:56:13.031184 channel==0
859 01:56:13.035815 RxClkDly_Margin_A0==88 ps 9
860 01:56:13.036344 TxDqDly_Margin_A0==98 ps 10
861 01:56:13.041479 RxClkDly_Margin_A1==88 ps 9
862 01:56:13.041958 TxDqDly_Margin_A1==98 ps 10
863 01:56:13.042392 TrainedVREFDQ_A0==74
864 01:56:13.047078 TrainedVREFDQ_A1==74
865 01:56:13.047590 VrefDac_Margin_A0==25
866 01:56:13.048065 DeviceVref_Margin_A0==40
867 01:56:13.052710 VrefDac_Margin_A1==25
868 01:56:13.053190 DeviceVref_Margin_A1==40
869 01:56:13.053587
870 01:56:13.053975
871 01:56:13.058373 channel==1
872 01:56:13.058854 RxClkDly_Margin_A0==98 ps 10
873 01:56:13.059254 TxDqDly_Margin_A0==88 ps 9
874 01:56:13.063838 RxClkDly_Margin_A1==88 ps 9
875 01:56:13.064293 TxDqDly_Margin_A1==88 ps 9
876 01:56:13.069403 TrainedVREFDQ_A0==76
877 01:56:13.069848 TrainedVREFDQ_A1==77
878 01:56:13.070245 VrefDac_Margin_A0==22
879 01:56:13.075040 DeviceVref_Margin_A0==38
880 01:56:13.075478 VrefDac_Margin_A1==24
881 01:56:13.080666 DeviceVref_Margin_A1==37
882 01:56:13.081086
883 01:56:13.081478 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 01:56:13.081867
885 01:56:13.114202 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
886 01:56:13.114779 2D training succeed
887 01:56:13.119755 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 01:56:13.125336 auto size-- 65535DDR cs0 size: 2048MB
889 01:56:13.125786 DDR cs1 size: 2048MB
890 01:56:13.130937 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 01:56:13.131357 cs0 DataBus test pass
892 01:56:13.136567 cs1 DataBus test pass
893 01:56:13.137023 cs0 AddrBus test pass
894 01:56:13.137413 cs1 AddrBus test pass
895 01:56:13.137794
896 01:56:13.142196 100bdlr_step_size ps== 420
897 01:56:13.142680 result report
898 01:56:13.147716 boot times 0Enable ddr reg access
899 01:56:13.153030 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 01:56:13.165539 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 01:56:13.738591 0.0;M3 CHK:0;cm4_sp_mode 0
902 01:56:13.739256 MVN_1=0x00000000
903 01:56:13.743925 MVN_2=0x00000000
904 01:56:13.749697 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 01:56:13.750176 OPS=0x10
906 01:56:13.750591 ring efuse init
907 01:56:13.750991 chipver efuse init
908 01:56:13.757880 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 01:56:13.758357 [0.018961 Inits done]
910 01:56:13.765468 secure task start!
911 01:56:13.765941 high task start!
912 01:56:13.766350 low task start!
913 01:56:13.766752 run into bl31
914 01:56:13.772087 NOTICE: BL31: v1.3(release):4fc40b1
915 01:56:13.779901 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 01:56:13.780384 NOTICE: BL31: G12A normal boot!
917 01:56:13.805334 NOTICE: BL31: BL33 decompress pass
918 01:56:13.810945 ERROR: Error initializing runtime service opteed_fast
919 01:56:15.043905
920 01:56:15.044563
921 01:56:15.051286 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 01:56:15.051769
923 01:56:15.052224 Model: Libre Computer AML-A311D-CC Alta
924 01:56:15.260923 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 01:56:15.284168 DRAM: 2 GiB (effective 3.8 GiB)
926 01:56:15.427098 Core: 408 devices, 31 uclasses, devicetree: separate
927 01:56:15.432971 WDT: Not starting watchdog@f0d0
928 01:56:15.465294 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 01:56:15.477753 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 01:56:15.482771 ** Bad device specification mmc 0 **
931 01:56:15.493048 Card did not respond to voltage select! : -110
932 01:56:15.499684 ** Bad device specification mmc 0 **
933 01:56:15.500282 Couldn't find partition mmc 0
934 01:56:15.509178 Card did not respond to voltage select! : -110
935 01:56:15.514747 ** Bad device specification mmc 0 **
936 01:56:15.515350 Couldn't find partition mmc 0
937 01:56:15.518869 Error: could not access storage.
938 01:56:15.862261 Net: eth0: ethernet@ff3f0000
939 01:56:15.862944 starting USB...
940 01:56:16.113896 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 01:56:16.114559 Starting the controller
942 01:56:16.120809 USB XHCI 1.10
943 01:56:17.984852 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
944 01:56:17.985298 bl2_stage_init 0x81
945 01:56:17.990320 hw id: 0x0000 - pwm id 0x01
946 01:56:17.990638 bl2_stage_init 0xc1
947 01:56:17.990858 bl2_stage_init 0x02
948 01:56:17.991069
949 01:56:17.996075 L0:00000000
950 01:56:17.996388 L1:20000703
951 01:56:17.996607 L2:00008067
952 01:56:17.996816 L3:14000000
953 01:56:17.997036 B2:00402000
954 01:56:17.998785 B1:e0f83180
955 01:56:17.999201
956 01:56:17.999544 TE: 58150
957 01:56:17.999888
958 01:56:18.009891 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 01:56:18.010214
960 01:56:18.010422 Board ID = 1
961 01:56:18.010626 Set A53 clk to 24M
962 01:56:18.010832 Set A73 clk to 24M
963 01:56:18.015739 Set clk81 to 24M
964 01:56:18.016047 A53 clk: 1200 MHz
965 01:56:18.016272 A73 clk: 1200 MHz
966 01:56:18.018943 CLK81: 166.6M
967 01:56:18.019219 smccc: 00012aac
968 01:56:18.024474 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 01:56:18.030003 board id: 1
970 01:56:18.034775 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 01:56:18.045968 fw parse done
972 01:56:18.051103 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 01:56:18.094090 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 01:56:18.105820 PIEI prepare done
975 01:56:18.106387 fastboot data load
976 01:56:18.107002 fastboot data verify
977 01:56:18.111255 verify result: 266
978 01:56:18.116909 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 01:56:18.117451 LPDDR4 probe
980 01:56:18.117966 ddr clk to 1584MHz
981 01:56:18.124214 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 01:56:18.162383
983 01:56:18.162979 dmc_version 0001
984 01:56:18.168933 Check phy result
985 01:56:18.174841 INFO : End of CA training
986 01:56:18.175375 INFO : End of initialization
987 01:56:18.180351 INFO : Training has run successfully!
988 01:56:18.180881 Check phy result
989 01:56:18.186000 INFO : End of initialization
990 01:56:18.186597 INFO : End of read enable training
991 01:56:18.191516 INFO : End of fine write leveling
992 01:56:18.197089 INFO : End of Write leveling coarse delay
993 01:56:18.197641 INFO : Training has run successfully!
994 01:56:18.198055 Check phy result
995 01:56:18.202598 INFO : End of initialization
996 01:56:18.203137 INFO : End of read dq deskew training
997 01:56:18.208239 INFO : End of MPR read delay center optimization
998 01:56:18.213797 INFO : End of write delay center optimization
999 01:56:18.219452 INFO : End of read delay center optimization
1000 01:56:18.220028 INFO : End of max read latency training
1001 01:56:18.225071 INFO : Training has run successfully!
1002 01:56:18.225618 1D training succeed
1003 01:56:18.234164 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 01:56:18.281840 Check phy result
1005 01:56:18.282425 INFO : End of initialization
1006 01:56:18.303450 INFO : End of 2D read delay Voltage center optimization
1007 01:56:18.323774 INFO : End of 2D read delay Voltage center optimization
1008 01:56:18.374719 INFO : End of 2D write delay Voltage center optimization
1009 01:56:18.425092 INFO : End of 2D write delay Voltage center optimization
1010 01:56:18.430580 INFO : Training has run successfully!
1011 01:56:18.431101
1012 01:56:18.431506 channel==0
1013 01:56:18.436398 RxClkDly_Margin_A0==88 ps 9
1014 01:56:18.436899 TxDqDly_Margin_A0==98 ps 10
1015 01:56:18.441826 RxClkDly_Margin_A1==88 ps 9
1016 01:56:18.442353 TxDqDly_Margin_A1==88 ps 9
1017 01:56:18.442754 TrainedVREFDQ_A0==74
1018 01:56:18.447417 TrainedVREFDQ_A1==74
1019 01:56:18.447931 VrefDac_Margin_A0==25
1020 01:56:18.448383 DeviceVref_Margin_A0==40
1021 01:56:18.453027 VrefDac_Margin_A1==25
1022 01:56:18.453530 DeviceVref_Margin_A1==40
1023 01:56:18.453924
1024 01:56:18.454318
1025 01:56:18.454712 channel==1
1026 01:56:18.458646 RxClkDly_Margin_A0==98 ps 10
1027 01:56:18.459146 TxDqDly_Margin_A0==98 ps 10
1028 01:56:18.464265 RxClkDly_Margin_A1==98 ps 10
1029 01:56:18.464785 TxDqDly_Margin_A1==88 ps 9
1030 01:56:18.469825 TrainedVREFDQ_A0==77
1031 01:56:18.470354 TrainedVREFDQ_A1==77
1032 01:56:18.470757 VrefDac_Margin_A0==22
1033 01:56:18.475397 DeviceVref_Margin_A0==37
1034 01:56:18.475899 VrefDac_Margin_A1==22
1035 01:56:18.481051 DeviceVref_Margin_A1==37
1036 01:56:18.481547
1037 01:56:18.481978 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 01:56:18.482388
1039 01:56:18.514689 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1040 01:56:18.515186 2D training succeed
1041 01:56:18.520255 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 01:56:18.526596 auto size-- 65535DDR cs0 size: 2048MB
1043 01:56:18.527218 DDR cs1 size: 2048MB
1044 01:56:18.531440 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 01:56:18.531884 cs0 DataBus test pass
1046 01:56:18.537151 cs1 DataBus test pass
1047 01:56:18.537585 cs0 AddrBus test pass
1048 01:56:18.537857 cs1 AddrBus test pass
1049 01:56:18.538109
1050 01:56:18.542728 100bdlr_step_size ps== 420
1051 01:56:18.543188 result report
1052 01:56:18.548246 boot times 0Enable ddr reg access
1053 01:56:18.552601 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 01:56:18.566224 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 01:56:19.140738 0.0;M3 CHK:0;cm4_sp_mode 0
1056 01:56:19.141360 MVN_1=0x00000000
1057 01:56:19.146175 MVN_2=0x00000000
1058 01:56:19.152012 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 01:56:19.152520 OPS=0x10
1060 01:56:19.152928 ring efuse init
1061 01:56:19.153324 chipver efuse init
1062 01:56:19.160178 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 01:56:19.160669 [0.018961 Inits done]
1064 01:56:19.167718 secure task start!
1065 01:56:19.168269 high task start!
1066 01:56:19.168676 low task start!
1067 01:56:19.169066 run into bl31
1068 01:56:19.174405 NOTICE: BL31: v1.3(release):4fc40b1
1069 01:56:19.182205 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 01:56:19.182664 NOTICE: BL31: G12A normal boot!
1071 01:56:19.207608 NOTICE: BL31: BL33 decompress pass
1072 01:56:19.212267 ERROR: Error initializing runtime service opteed_fast
1073 01:56:20.446123
1074 01:56:20.446763
1075 01:56:20.454607 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 01:56:20.455074
1077 01:56:20.455491 Model: Libre Computer AML-A311D-CC Alta
1078 01:56:20.662013 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 01:56:20.685535 DRAM: 2 GiB (effective 3.8 GiB)
1080 01:56:20.829340 Core: 408 devices, 31 uclasses, devicetree: separate
1081 01:56:20.834283 WDT: Not starting watchdog@f0d0
1082 01:56:20.867452 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 01:56:20.879918 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 01:56:20.884335 ** Bad device specification mmc 0 **
1085 01:56:20.895228 Card did not respond to voltage select! : -110
1086 01:56:20.902053 ** Bad device specification mmc 0 **
1087 01:56:20.902573 Couldn't find partition mmc 0
1088 01:56:20.911212 Card did not respond to voltage select! : -110
1089 01:56:20.916779 ** Bad device specification mmc 0 **
1090 01:56:20.917302 Couldn't find partition mmc 0
1091 01:56:20.920821 Error: could not access storage.
1092 01:56:21.264295 Net: eth0: ethernet@ff3f0000
1093 01:56:21.264921 starting USB...
1094 01:56:21.516144 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 01:56:21.516770 Starting the controller
1096 01:56:21.523029 USB XHCI 1.10
1097 01:56:23.080340 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 01:56:23.087598 scanning usb for storage devices... 0 Storage Device(s) found
1100 01:56:23.139360 Hit any key to stop autoboot: 1
1101 01:56:23.140286 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1102 01:56:23.140859 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1103 01:56:23.141336 Setting prompt string to ['=>']
1104 01:56:23.141845 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1105 01:56:23.145013 0
1106 01:56:23.145850 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 01:56:23.146332 Sending with 10 millisecond of delay
1109 01:56:24.281150 => setenv autoload no
1110 01:56:24.291956 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1111 01:56:24.296901 setenv autoload no
1112 01:56:24.297649 Sending with 10 millisecond of delay
1114 01:56:26.095299 => setenv initrd_high 0xffffffff
1115 01:56:26.106057 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1116 01:56:26.106886 setenv initrd_high 0xffffffff
1117 01:56:26.107589 Sending with 10 millisecond of delay
1119 01:56:27.723707 => setenv fdt_high 0xffffffff
1120 01:56:27.734555 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1121 01:56:27.735387 setenv fdt_high 0xffffffff
1122 01:56:27.736105 Sending with 10 millisecond of delay
1124 01:56:28.027876 => dhcp
1125 01:56:28.038618 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1126 01:56:28.039394 dhcp
1127 01:56:28.039827 Speed: 1000, full duplex
1128 01:56:28.040301 BOOTP broadcast 1
1129 01:56:28.286826 BOOTP broadcast 2
1130 01:56:28.787801 BOOTP broadcast 3
1131 01:56:28.804399 DHCP client bound to address 192.168.6.33 (765 ms)
1132 01:56:28.805138 Sending with 10 millisecond of delay
1134 01:56:30.481613 => setenv serverip 192.168.6.2
1135 01:56:30.492253 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1136 01:56:30.492932 setenv serverip 192.168.6.2
1137 01:56:30.493463 Sending with 10 millisecond of delay
1139 01:56:34.215803 => tftpboot 0x01080000 796008/tftp-deploy-8_qctal2/kernel/uImage
1140 01:56:34.227229 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1141 01:56:34.228234 tftpboot 0x01080000 796008/tftp-deploy-8_qctal2/kernel/uImage
1142 01:56:34.228718 Speed: 1000, full duplex
1143 01:56:34.229166 Using ethernet@ff3f0000 device
1144 01:56:34.229684 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1145 01:56:34.234717 Filename '796008/tftp-deploy-8_qctal2/kernel/uImage'.
1146 01:56:34.238750 Load address: 0x1080000
1147 01:56:45.016707 Loading: *#################T ##
1148 01:56:45.017132 TFTP error: trying to overwrite reserved memory...
1150 01:56:45.018026 end: 2.4.3 bootloader-commands (duration 00:00:22) [common]
1153 01:56:45.019027 end: 2.4 uboot-commands (duration 00:01:00) [common]
1155 01:56:45.019813 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'TFTP error: trying to overwrite reserved memory' (12)'
1157 01:56:45.020945 end: 2 uboot-action (duration 00:01:00) [common]
1159 01:56:45.022553 Cleaning after the job
1160 01:56:45.023109 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/ramdisk
1161 01:56:45.051833 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/kernel
1162 01:56:45.066329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/dtb
1163 01:56:45.067564 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/nfsrootfs
1164 01:56:45.099126 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/796008/tftp-deploy-8_qctal2/modules
1165 01:56:45.120007 start: 4.1 power-off (timeout 00:00:30) [common]
1166 01:56:45.120688 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1167 01:56:45.152886 >> OK - accepted request
1168 01:56:45.155070 Returned 0 in 0 seconds
1169 01:56:45.255908 end: 4.1 power-off (duration 00:00:00) [common]
1171 01:56:45.256954 start: 4.2 read-feedback (timeout 00:10:00) [common]
1172 01:56:45.257700 Listened to connection for namespace 'common' for up to 1s
1173 01:56:46.258550 Finalising connection for namespace 'common'
1174 01:56:46.259029 Disconnecting from shell: Finalise
1175 01:56:46.259294 =>
1176 01:56:46.360027 end: 4.2 read-feedback (duration 00:00:01) [common]
1177 01:56:46.360504 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/796008
1178 01:56:48.391668 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/796008
1179 01:56:48.392590 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.