Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:33:25.219685 lava-dispatcher, installed at version: 2024.01
2 01:33:25.220548 start: 0 validate
3 01:33:25.221017 Start time: 2024-10-03 01:33:25.220987+00:00 (UTC)
4 01:33:25.221601 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:33:25.222157 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:33:25.263076 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:33:25.263643 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:33:25.299282 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:33:25.299937 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:33:25.333008 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:33:25.333536 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 01:33:25.380912 validate duration: 0.16
14 01:33:25.381771 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:33:25.382109 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:33:25.382426 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:33:25.383036 Not decompressing ramdisk as can be used compressed.
18 01:33:25.383478 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:33:25.383765 saving as /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/ramdisk/rootfs.cpio.gz
20 01:33:25.384068 total size: 47897469 (45 MB)
21 01:33:25.426419 progress 0 % (0 MB)
22 01:33:25.457860 progress 5 % (2 MB)
23 01:33:25.487393 progress 10 % (4 MB)
24 01:33:25.516765 progress 15 % (6 MB)
25 01:33:25.546436 progress 20 % (9 MB)
26 01:33:25.575827 progress 25 % (11 MB)
27 01:33:25.605107 progress 30 % (13 MB)
28 01:33:25.634520 progress 35 % (16 MB)
29 01:33:25.664133 progress 40 % (18 MB)
30 01:33:25.693443 progress 45 % (20 MB)
31 01:33:25.723107 progress 50 % (22 MB)
32 01:33:25.752541 progress 55 % (25 MB)
33 01:33:25.782477 progress 60 % (27 MB)
34 01:33:25.812092 progress 65 % (29 MB)
35 01:33:25.841729 progress 70 % (32 MB)
36 01:33:25.870939 progress 75 % (34 MB)
37 01:33:25.900389 progress 80 % (36 MB)
38 01:33:25.929584 progress 85 % (38 MB)
39 01:33:25.959617 progress 90 % (41 MB)
40 01:33:25.989041 progress 95 % (43 MB)
41 01:33:26.017044 progress 100 % (45 MB)
42 01:33:26.017849 45 MB downloaded in 0.63 s (72.08 MB/s)
43 01:33:26.018428 end: 1.1.1 http-download (duration 00:00:01) [common]
45 01:33:26.019356 end: 1.1 download-retry (duration 00:00:01) [common]
46 01:33:26.019672 start: 1.2 download-retry (timeout 00:09:59) [common]
47 01:33:26.019961 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 01:33:26.020491 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/kernel/Image
49 01:33:26.020749 saving as /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/kernel/Image
50 01:33:26.020964 total size: 45713920 (43 MB)
51 01:33:26.021180 No compression specified
52 01:33:26.056623 progress 0 % (0 MB)
53 01:33:26.085841 progress 5 % (2 MB)
54 01:33:26.114118 progress 10 % (4 MB)
55 01:33:26.142967 progress 15 % (6 MB)
56 01:33:26.171542 progress 20 % (8 MB)
57 01:33:26.199720 progress 25 % (10 MB)
58 01:33:26.228011 progress 30 % (13 MB)
59 01:33:26.256668 progress 35 % (15 MB)
60 01:33:26.285837 progress 40 % (17 MB)
61 01:33:26.314318 progress 45 % (19 MB)
62 01:33:26.343255 progress 50 % (21 MB)
63 01:33:26.372289 progress 55 % (24 MB)
64 01:33:26.401472 progress 60 % (26 MB)
65 01:33:26.430144 progress 65 % (28 MB)
66 01:33:26.458866 progress 70 % (30 MB)
67 01:33:26.487655 progress 75 % (32 MB)
68 01:33:26.516196 progress 80 % (34 MB)
69 01:33:26.544320 progress 85 % (37 MB)
70 01:33:26.572645 progress 90 % (39 MB)
71 01:33:26.601430 progress 95 % (41 MB)
72 01:33:26.628973 progress 100 % (43 MB)
73 01:33:26.629512 43 MB downloaded in 0.61 s (71.64 MB/s)
74 01:33:26.629990 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:33:26.630808 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:33:26.631081 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:33:26.631362 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:33:26.631833 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:33:26.632129 saving as /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:33:26.632340 total size: 53209 (0 MB)
82 01:33:26.632552 No compression specified
83 01:33:26.669936 progress 61 % (0 MB)
84 01:33:26.670782 progress 100 % (0 MB)
85 01:33:26.671305 0 MB downloaded in 0.04 s (1.30 MB/s)
86 01:33:26.671784 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:33:26.672647 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:33:26.672911 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:33:26.673173 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:33:26.673631 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/modules.tar.xz
92 01:33:26.673870 saving as /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/modules/modules.tar
93 01:33:26.674073 total size: 11617124 (11 MB)
94 01:33:26.674282 Using unxz to decompress xz
95 01:33:26.712139 progress 0 % (0 MB)
96 01:33:26.783709 progress 5 % (0 MB)
97 01:33:26.864855 progress 10 % (1 MB)
98 01:33:26.953572 progress 15 % (1 MB)
99 01:33:27.032945 progress 20 % (2 MB)
100 01:33:27.116702 progress 25 % (2 MB)
101 01:33:27.197648 progress 30 % (3 MB)
102 01:33:27.278535 progress 35 % (3 MB)
103 01:33:27.352803 progress 40 % (4 MB)
104 01:33:27.430121 progress 45 % (5 MB)
105 01:33:27.509877 progress 50 % (5 MB)
106 01:33:27.582401 progress 55 % (6 MB)
107 01:33:27.669533 progress 60 % (6 MB)
108 01:33:27.756789 progress 65 % (7 MB)
109 01:33:27.839863 progress 70 % (7 MB)
110 01:33:27.938113 progress 75 % (8 MB)
111 01:33:28.053596 progress 80 % (8 MB)
112 01:33:28.153923 progress 85 % (9 MB)
113 01:33:28.246156 progress 90 % (10 MB)
114 01:33:28.329818 progress 95 % (10 MB)
115 01:33:28.411085 progress 100 % (11 MB)
116 01:33:28.424305 11 MB downloaded in 1.75 s (6.33 MB/s)
117 01:33:28.425313 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:33:28.427113 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:33:28.427712 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 01:33:28.428358 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 01:33:28.428931 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:33:28.429500 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 01:33:28.430550 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m
125 01:33:28.431507 makedir: /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin
126 01:33:28.432279 makedir: /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/tests
127 01:33:28.432996 makedir: /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/results
128 01:33:28.433691 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-add-keys
129 01:33:28.434786 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-add-sources
130 01:33:28.435854 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-background-process-start
131 01:33:28.437154 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-background-process-stop
132 01:33:28.438305 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-common-functions
133 01:33:28.439357 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-echo-ipv4
134 01:33:28.440462 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-install-packages
135 01:33:28.441518 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-installed-packages
136 01:33:28.442581 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-os-build
137 01:33:28.443694 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-probe-channel
138 01:33:28.444829 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-probe-ip
139 01:33:28.445911 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-target-ip
140 01:33:28.447005 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-target-mac
141 01:33:28.448204 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-target-storage
142 01:33:28.449480 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-test-case
143 01:33:28.450517 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-test-event
144 01:33:28.451533 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-test-feedback
145 01:33:28.452526 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-test-raise
146 01:33:28.453456 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-test-reference
147 01:33:28.454348 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-test-runner
148 01:33:28.455236 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-test-set
149 01:33:28.456139 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-test-shell
150 01:33:28.456697 Updating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-install-packages (oe)
151 01:33:28.457284 Updating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/bin/lava-installed-packages (oe)
152 01:33:28.457762 Creating /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/environment
153 01:33:28.458180 LAVA metadata
154 01:33:28.458444 - LAVA_JOB_ID=795665
155 01:33:28.458666 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:33:28.459047 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:33:28.460180 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:33:28.460535 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:33:28.460750 skipped lava-vland-overlay
160 01:33:28.460999 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:33:28.461264 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:33:28.461485 skipped lava-multinode-overlay
163 01:33:28.461731 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:33:28.461986 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:33:28.462243 Loading test definitions
166 01:33:28.462529 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:33:28.462757 Using /lava-795665 at stage 0
168 01:33:28.463967 uuid=795665_1.5.2.4.1 testdef=None
169 01:33:28.464325 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:33:28.464596 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:33:28.466413 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:33:28.467261 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:33:28.469636 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:33:28.470539 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:33:28.472833 runner path: /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/0/tests/0_igt-gpu-panfrost test_uuid 795665_1.5.2.4.1
178 01:33:28.473500 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:33:28.474343 Creating lava-test-runner.conf files
181 01:33:28.474556 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795665/lava-overlay-icyq3d7m/lava-795665/0 for stage 0
182 01:33:28.474994 - 0_igt-gpu-panfrost
183 01:33:28.475374 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:33:28.475664 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:33:28.499905 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:33:28.500375 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:33:28.500641 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:33:28.500909 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:33:28.501172 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:33:35.546289 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 01:33:35.546739 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 01:33:35.546985 extracting modules file /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795665/extract-overlay-ramdisk-14onwjpt/ramdisk
193 01:33:37.066743 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 01:33:37.067249 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 01:33:37.067533 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795665/compress-overlay-swqb7yg2/overlay-1.5.2.5.tar.gz to ramdisk
196 01:33:37.067752 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795665/compress-overlay-swqb7yg2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795665/extract-overlay-ramdisk-14onwjpt/ramdisk
197 01:33:37.114375 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:33:37.114873 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 01:33:37.115221 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 01:33:37.115500 Converting downloaded kernel to a uImage
201 01:33:37.115853 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/kernel/Image /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/kernel/uImage
202 01:33:37.599477 output: Image Name:
203 01:33:37.599903 output: Created: Thu Oct 3 01:33:37 2024
204 01:33:37.600199 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:33:37.600427 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 01:33:37.600655 output: Load Address: 01080000
207 01:33:37.600882 output: Entry Point: 01080000
208 01:33:37.601111 output:
209 01:33:37.601455 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:33:37.601721 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:33:37.601985 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 01:33:37.602238 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:33:37.602493 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 01:33:37.602756 Building ramdisk /var/lib/lava/dispatcher/tmp/795665/extract-overlay-ramdisk-14onwjpt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795665/extract-overlay-ramdisk-14onwjpt/ramdisk
215 01:33:44.227930 >> 502360 blocks
216 01:34:05.366638 Adding RAMdisk u-boot header.
217 01:34:05.367260 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795665/extract-overlay-ramdisk-14onwjpt/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795665/extract-overlay-ramdisk-14onwjpt/ramdisk.cpio.gz.uboot
218 01:34:06.045046 output: Image Name:
219 01:34:06.045466 output: Created: Thu Oct 3 01:34:05 2024
220 01:34:06.045675 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:34:06.045879 output: Data Size: 65705393 Bytes = 64165.42 KiB = 62.66 MiB
222 01:34:06.046077 output: Load Address: 00000000
223 01:34:06.046278 output: Entry Point: 00000000
224 01:34:06.046475 output:
225 01:34:06.047131 rename /var/lib/lava/dispatcher/tmp/795665/extract-overlay-ramdisk-14onwjpt/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/ramdisk/ramdisk.cpio.gz.uboot
226 01:34:06.047566 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 01:34:06.047852 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 01:34:06.048377 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 01:34:06.048897 No LXC device requested
230 01:34:06.049473 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:34:06.050031 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 01:34:06.050573 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:34:06.051023 Checking files for TFTP limit of 4294967296 bytes.
234 01:34:06.053967 end: 1 tftp-deploy (duration 00:00:41) [common]
235 01:34:06.054616 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:34:06.055194 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:34:06.055740 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:34:06.056337 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:34:06.056920 Using kernel file from prepare-kernel: 795665/tftp-deploy-7e4nj5s5/kernel/uImage
240 01:34:06.057607 substitutions:
241 01:34:06.058062 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:34:06.058502 - {DTB_ADDR}: 0x01070000
243 01:34:06.058940 - {DTB}: 795665/tftp-deploy-7e4nj5s5/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:34:06.059375 - {INITRD}: 795665/tftp-deploy-7e4nj5s5/ramdisk/ramdisk.cpio.gz.uboot
245 01:34:06.059809 - {KERNEL_ADDR}: 0x01080000
246 01:34:06.060276 - {KERNEL}: 795665/tftp-deploy-7e4nj5s5/kernel/uImage
247 01:34:06.060714 - {LAVA_MAC}: None
248 01:34:06.061191 - {PRESEED_CONFIG}: None
249 01:34:06.061626 - {PRESEED_LOCAL}: None
250 01:34:06.062056 - {RAMDISK_ADDR}: 0x08000000
251 01:34:06.062481 - {RAMDISK}: 795665/tftp-deploy-7e4nj5s5/ramdisk/ramdisk.cpio.gz.uboot
252 01:34:06.062916 - {ROOT_PART}: None
253 01:34:06.063344 - {ROOT}: None
254 01:34:06.063775 - {SERVER_IP}: 192.168.6.2
255 01:34:06.064240 - {TEE_ADDR}: 0x83000000
256 01:34:06.064672 - {TEE}: None
257 01:34:06.065102 Parsed boot commands:
258 01:34:06.065519 - setenv autoload no
259 01:34:06.065942 - setenv initrd_high 0xffffffff
260 01:34:06.066365 - setenv fdt_high 0xffffffff
261 01:34:06.066786 - dhcp
262 01:34:06.067214 - setenv serverip 192.168.6.2
263 01:34:06.067638 - tftpboot 0x01080000 795665/tftp-deploy-7e4nj5s5/kernel/uImage
264 01:34:06.068127 - tftpboot 0x08000000 795665/tftp-deploy-7e4nj5s5/ramdisk/ramdisk.cpio.gz.uboot
265 01:34:06.068562 - tftpboot 0x01070000 795665/tftp-deploy-7e4nj5s5/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:34:06.068994 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:34:06.069429 - bootm 0x01080000 0x08000000 0x01070000
268 01:34:06.069987 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:34:06.071629 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:34:06.072152 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:34:06.087785 Setting prompt string to ['lava-test: # ']
273 01:34:06.089481 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:34:06.090138 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:34:06.090741 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:34:06.091454 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:34:06.092787 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:34:06.130369 >> OK - accepted request
279 01:34:06.133237 Returned 0 in 0 seconds
280 01:34:06.234436 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:34:06.236270 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:34:06.236910 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:34:06.237457 Setting prompt string to ['Hit any key to stop autoboot']
285 01:34:06.237943 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:34:06.239696 Trying 192.168.56.21...
287 01:34:06.240274 Connected to conserv1.
288 01:34:06.240737 Escape character is '^]'.
289 01:34:06.241199
290 01:34:06.241665 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 01:34:06.242154
292 01:34:13.783606 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:34:13.784341 bl2_stage_init 0x01
294 01:34:13.784831 bl2_stage_init 0x81
295 01:34:13.789231 hw id: 0x0000 - pwm id 0x01
296 01:34:13.789748 bl2_stage_init 0xc1
297 01:34:13.790196 bl2_stage_init 0x02
298 01:34:13.790650
299 01:34:13.795067 L0:00000000
300 01:34:13.795605 L1:00000703
301 01:34:13.796089 L2:00008067
302 01:34:13.796532 L3:15000000
303 01:34:13.796979 S1:00000000
304 01:34:13.801212 B2:20282000
305 01:34:13.801724 B1:a0f83180
306 01:34:13.802167
307 01:34:13.802606 TE: 71233
308 01:34:13.803041
309 01:34:13.806838 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:34:13.807337
311 01:34:13.807780 Board ID = 1
312 01:34:13.812479 Set cpu clk to 24M
313 01:34:13.812965 Set clk81 to 24M
314 01:34:13.813400 Use GP1_pll as DSU clk.
315 01:34:13.818326 DSU clk: 1200 Mhz
316 01:34:13.818804 CPU clk: 1200 MHz
317 01:34:13.819244 Set clk81 to 166.6M
318 01:34:13.823928 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:34:13.829202 board id: 1
320 01:34:13.834456 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:34:13.845738 fw parse done
322 01:34:13.850653 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:34:13.894294 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:34:13.905703 PIEI prepare done
325 01:34:13.906216 fastboot data load
326 01:34:13.906664 fastboot data verify
327 01:34:13.911390 verify result: 266
328 01:34:13.916968 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:34:13.917449 LPDDR4 probe
330 01:34:13.917889 ddr clk to 1584MHz
331 01:34:13.924455 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:34:13.962105
333 01:34:13.962658 dmc_version 0001
334 01:34:13.968927 Check phy result
335 01:34:13.975690 INFO : End of CA training
336 01:34:13.976286 INFO : End of initialization
337 01:34:13.981292 INFO : Training has run successfully!
338 01:34:13.981986 Check phy result
339 01:34:13.986853 INFO : End of initialization
340 01:34:13.987366 INFO : End of read enable training
341 01:34:13.990323 INFO : End of fine write leveling
342 01:34:13.995792 INFO : End of Write leveling coarse delay
343 01:34:14.001359 INFO : Training has run successfully!
344 01:34:14.001846 Check phy result
345 01:34:14.002300 INFO : End of initialization
346 01:34:14.006954 INFO : End of read dq deskew training
347 01:34:14.010478 INFO : End of MPR read delay center optimization
348 01:34:14.015893 INFO : End of write delay center optimization
349 01:34:14.021661 INFO : End of read delay center optimization
350 01:34:14.022169 INFO : End of max read latency training
351 01:34:14.027160 INFO : Training has run successfully!
352 01:34:14.027683 1D training succeed
353 01:34:14.034705 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:34:14.080440 Check phy result
355 01:34:14.082884 INFO : End of initialization
356 01:34:14.110101 INFO : End of 2D read delay Voltage center optimization
357 01:34:14.134180 INFO : End of 2D read delay Voltage center optimization
358 01:34:14.190974 INFO : End of 2D write delay Voltage center optimization
359 01:34:14.245812 INFO : End of 2D write delay Voltage center optimization
360 01:34:14.251341 INFO : Training has run successfully!
361 01:34:14.251803
362 01:34:14.252113 channel==0
363 01:34:14.256969 RxClkDly_Margin_A0==78 ps 8
364 01:34:14.257301 TxDqDly_Margin_A0==88 ps 9
365 01:34:14.260372 RxClkDly_Margin_A1==78 ps 8
366 01:34:14.263805 TxDqDly_Margin_A1==98 ps 10
367 01:34:14.264126 TrainedVREFDQ_A0==74
368 01:34:14.264356 TrainedVREFDQ_A1==75
369 01:34:14.269315 VrefDac_Margin_A0==24
370 01:34:14.269617 DeviceVref_Margin_A0==40
371 01:34:14.274878 VrefDac_Margin_A1==23
372 01:34:14.275188 DeviceVref_Margin_A1==39
373 01:34:14.275417
374 01:34:14.275641
375 01:34:14.275854 channel==1
376 01:34:14.280505 RxClkDly_Margin_A0==88 ps 9
377 01:34:14.280796 TxDqDly_Margin_A0==88 ps 9
378 01:34:14.286141 RxClkDly_Margin_A1==78 ps 8
379 01:34:14.286433 TxDqDly_Margin_A1==98 ps 10
380 01:34:14.286654 TrainedVREFDQ_A0==75
381 01:34:14.291824 TrainedVREFDQ_A1==78
382 01:34:14.292247 VrefDac_Margin_A0==23
383 01:34:14.297462 DeviceVref_Margin_A0==39
384 01:34:14.297844 VrefDac_Margin_A1==22
385 01:34:14.298087 DeviceVref_Margin_A1==36
386 01:34:14.298304
387 01:34:14.306342 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:34:14.306706
389 01:34:14.332213 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 01:34:14.338061 2D training succeed
391 01:34:14.341160 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:34:14.346696 auto size-- 65535DDR cs0 size: 2048MB
393 01:34:14.347029 DDR cs1 size: 2048MB
394 01:34:14.352271 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:34:14.352568 cs0 DataBus test pass
396 01:34:14.357859 cs1 DataBus test pass
397 01:34:14.358193 cs0 AddrBus test pass
398 01:34:14.358414 cs1 AddrBus test pass
399 01:34:14.358635
400 01:34:14.363474 100bdlr_step_size ps== 485
401 01:34:14.363806 result report
402 01:34:14.370337 boot times 0Enable ddr reg access
403 01:34:14.373351 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:34:14.386915 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:34:15.046210 bl2z: ptr: 05129330, size: 00001e40
406 01:34:15.054604 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:34:15.055186 MVN_1=0x00000000
408 01:34:15.055568 MVN_2=0x00000000
409 01:34:15.066027 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:34:15.066598 OPS=0x04
411 01:34:15.067077 ring efuse init
412 01:34:15.071792 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:34:15.072214 [0.017354 Inits done]
414 01:34:15.072452 secure task start!
415 01:34:15.078299 high task start!
416 01:34:15.078733 low task start!
417 01:34:15.078979 run into bl31
418 01:34:15.087969 NOTICE: BL31: v1.3(release):4fc40b1
419 01:34:15.094868 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:34:15.095231 NOTICE: BL31: G12A normal boot!
421 01:34:15.111141 NOTICE: BL31: BL33 decompress pass
422 01:34:15.116721 ERROR: Error initializing runtime service opteed_fast
423 01:34:17.835364 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:34:17.836092 bl2_stage_init 0x01
425 01:34:17.836575 bl2_stage_init 0x81
426 01:34:17.840895 hw id: 0x0000 - pwm id 0x01
427 01:34:17.841424 bl2_stage_init 0xc1
428 01:34:17.844828 bl2_stage_init 0x02
429 01:34:17.845381
430 01:34:17.845886 L0:00000000
431 01:34:17.846368 L1:00000703
432 01:34:17.850311 L2:00008067
433 01:34:17.850813 L3:15000000
434 01:34:17.851250 S1:00000000
435 01:34:17.851682 B2:20282000
436 01:34:17.852152 B1:a0f83180
437 01:34:17.852587
438 01:34:17.855946 TE: 72871
439 01:34:17.856487
440 01:34:17.861515 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:34:17.862004
442 01:34:17.862439 Board ID = 1
443 01:34:17.862862 Set cpu clk to 24M
444 01:34:17.867114 Set clk81 to 24M
445 01:34:17.867588 Use GP1_pll as DSU clk.
446 01:34:17.868051 DSU clk: 1200 Mhz
447 01:34:17.872707 CPU clk: 1200 MHz
448 01:34:17.872945 Set clk81 to 166.6M
449 01:34:17.878297 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:34:17.878840 board id: 1
451 01:34:17.887215 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:34:17.898119 fw parse done
453 01:34:17.904350 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:34:17.947361 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:34:17.958425 PIEI prepare done
456 01:34:17.958927 fastboot data load
457 01:34:17.959363 fastboot data verify
458 01:34:17.964008 verify result: 266
459 01:34:17.969592 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:34:17.970065 LPDDR4 probe
461 01:34:17.970498 ddr clk to 1584MHz
462 01:34:17.977450 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 01:34:18.015428
464 01:34:18.016062 dmc_version 0001
465 01:34:18.022430 Check phy result
466 01:34:18.028522 INFO : End of CA training
467 01:34:18.028996 INFO : End of initialization
468 01:34:18.034007 INFO : Training has run successfully!
469 01:34:18.034558 Check phy result
470 01:34:18.039551 INFO : End of initialization
471 01:34:18.040120 INFO : End of read enable training
472 01:34:18.042846 INFO : End of fine write leveling
473 01:34:18.048339 INFO : End of Write leveling coarse delay
474 01:34:18.054063 INFO : Training has run successfully!
475 01:34:18.054661 Check phy result
476 01:34:18.055120 INFO : End of initialization
477 01:34:18.059567 INFO : End of read dq deskew training
478 01:34:18.065153 INFO : End of MPR read delay center optimization
479 01:34:18.065647 INFO : End of write delay center optimization
480 01:34:18.070807 INFO : End of read delay center optimization
481 01:34:18.076447 INFO : End of max read latency training
482 01:34:18.076925 INFO : Training has run successfully!
483 01:34:18.081984 1D training succeed
484 01:34:18.088709 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 01:34:18.135766 Check phy result
486 01:34:18.136414 INFO : End of initialization
487 01:34:18.163502 INFO : End of 2D read delay Voltage center optimization
488 01:34:18.187199 INFO : End of 2D read delay Voltage center optimization
489 01:34:18.244138 INFO : End of 2D write delay Voltage center optimization
490 01:34:18.298440 INFO : End of 2D write delay Voltage center optimization
491 01:34:18.303874 INFO : Training has run successfully!
492 01:34:18.304381
493 01:34:18.304641 channel==0
494 01:34:18.309430 RxClkDly_Margin_A0==78 ps 8
495 01:34:18.309785 TxDqDly_Margin_A0==88 ps 9
496 01:34:18.315249 RxClkDly_Margin_A1==88 ps 9
497 01:34:18.315721 TxDqDly_Margin_A1==88 ps 9
498 01:34:18.316102 TrainedVREFDQ_A0==74
499 01:34:18.320679 TrainedVREFDQ_A1==75
500 01:34:18.321027 VrefDac_Margin_A0==23
501 01:34:18.321251 DeviceVref_Margin_A0==40
502 01:34:18.326276 VrefDac_Margin_A1==23
503 01:34:18.326659 DeviceVref_Margin_A1==39
504 01:34:18.326891
505 01:34:18.327111
506 01:34:18.327321 channel==1
507 01:34:18.331862 RxClkDly_Margin_A0==78 ps 8
508 01:34:18.332261 TxDqDly_Margin_A0==98 ps 10
509 01:34:18.337466 RxClkDly_Margin_A1==78 ps 8
510 01:34:18.337825 TxDqDly_Margin_A1==88 ps 9
511 01:34:18.343224 TrainedVREFDQ_A0==75
512 01:34:18.343775 TrainedVREFDQ_A1==77
513 01:34:18.344174 VrefDac_Margin_A0==22
514 01:34:18.348738 DeviceVref_Margin_A0==39
515 01:34:18.349086 VrefDac_Margin_A1==22
516 01:34:18.349310 DeviceVref_Margin_A1==37
517 01:34:18.354305
518 01:34:18.354683 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 01:34:18.354918
520 01:34:18.387957 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000061
521 01:34:18.388429 2D training succeed
522 01:34:18.393446 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 01:34:18.399252 auto size-- 65535DDR cs0 size: 2048MB
524 01:34:18.399633 DDR cs1 size: 2048MB
525 01:34:18.404759 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 01:34:18.405115 cs0 DataBus test pass
527 01:34:18.410470 cs1 DataBus test pass
528 01:34:18.410840 cs0 AddrBus test pass
529 01:34:18.411085 cs1 AddrBus test pass
530 01:34:18.411312
531 01:34:18.415912 100bdlr_step_size ps== 478
532 01:34:18.416294 result report
533 01:34:18.421519 boot times 0Enable ddr reg access
534 01:34:18.426595 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 01:34:18.440478 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 01:34:19.099858 bl2z: ptr: 05129330, size: 00001e40
537 01:34:19.109136 0.0;M3 CHK:0;cm4_sp_mode 0
538 01:34:19.109689 MVN_1=0x00000000
539 01:34:19.110119 MVN_2=0x00000000
540 01:34:19.120319 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 01:34:19.120859 OPS=0x04
542 01:34:19.121292 ring efuse init
543 01:34:19.123187 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 01:34:19.128630 [0.017354 Inits done]
545 01:34:19.129157 secure task start!
546 01:34:19.129579 high task start!
547 01:34:19.129990 low task start!
548 01:34:19.132031 run into bl31
549 01:34:19.141728 NOTICE: BL31: v1.3(release):4fc40b1
550 01:34:19.148549 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 01:34:19.149075 NOTICE: BL31: G12A normal boot!
552 01:34:19.165538 NOTICE: BL31: BL33 decompress pass
553 01:34:19.169749 ERROR: Error initializing runtime service opteed_fast
554 01:34:20.533502 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 01:34:20.534075 bl2_stage_init 0x01
556 01:34:20.534336 bl2_stage_init 0x81
557 01:34:20.539088 hw id: 0x0000 - pwm id 0x01
558 01:34:20.539423 bl2_stage_init 0xc1
559 01:34:20.539640 bl2_stage_init 0x02
560 01:34:20.539841
561 01:34:20.544725 L0:00000000
562 01:34:20.545033 L1:00000703
563 01:34:20.545247 L2:00008067
564 01:34:20.545464 L3:15000000
565 01:34:20.545671 S1:00000000
566 01:34:20.550356 B2:20282000
567 01:34:20.550761 B1:a0f83180
568 01:34:20.551098
569 01:34:20.551421 TE: 71363
570 01:34:20.551742
571 01:34:20.555929 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 01:34:20.556255
573 01:34:20.561586 Board ID = 1
574 01:34:20.561992 Set cpu clk to 24M
575 01:34:20.562306 Set clk81 to 24M
576 01:34:20.567074 Use GP1_pll as DSU clk.
577 01:34:20.567347 DSU clk: 1200 Mhz
578 01:34:20.567561 CPU clk: 1200 MHz
579 01:34:20.567768 Set clk81 to 166.6M
580 01:34:20.578659 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 01:34:20.579112 board id: 1
582 01:34:20.583723 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 01:34:20.595688 fw parse done
584 01:34:20.601575 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 01:34:20.643813 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 01:34:20.655814 PIEI prepare done
587 01:34:20.656313 fastboot data load
588 01:34:20.656744 fastboot data verify
589 01:34:20.661431 verify result: 266
590 01:34:20.667095 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 01:34:20.667570 LPDDR4 probe
592 01:34:20.668022 ddr clk to 1584MHz
593 01:34:20.674156 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 01:34:20.715132
595 01:34:20.715610 dmc_version 0001
596 01:34:20.718759 Check phy result
597 01:34:20.725738 INFO : End of CA training
598 01:34:20.726205 INFO : End of initialization
599 01:34:20.731321 INFO : Training has run successfully!
600 01:34:20.731776 Check phy result
601 01:34:20.737014 INFO : End of initialization
602 01:34:20.737489 INFO : End of read enable training
603 01:34:20.742506 INFO : End of fine write leveling
604 01:34:20.748121 INFO : End of Write leveling coarse delay
605 01:34:20.748575 INFO : Training has run successfully!
606 01:34:20.748993 Check phy result
607 01:34:20.753758 INFO : End of initialization
608 01:34:20.754220 INFO : End of read dq deskew training
609 01:34:20.759315 INFO : End of MPR read delay center optimization
610 01:34:20.765075 INFO : End of write delay center optimization
611 01:34:20.770517 INFO : End of read delay center optimization
612 01:34:20.770975 INFO : End of max read latency training
613 01:34:20.776221 INFO : Training has run successfully!
614 01:34:20.776678 1D training succeed
615 01:34:20.784490 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 01:34:20.832751 Check phy result
617 01:34:20.833245 INFO : End of initialization
618 01:34:20.861426 INFO : End of 2D read delay Voltage center optimization
619 01:34:20.884544 INFO : End of 2D read delay Voltage center optimization
620 01:34:20.940977 INFO : End of 2D write delay Voltage center optimization
621 01:34:20.996055 INFO : End of 2D write delay Voltage center optimization
622 01:34:21.001650 INFO : Training has run successfully!
623 01:34:21.002097
624 01:34:21.002517 channel==0
625 01:34:21.007077 RxClkDly_Margin_A0==88 ps 9
626 01:34:21.007527 TxDqDly_Margin_A0==98 ps 10
627 01:34:21.012671 RxClkDly_Margin_A1==88 ps 9
628 01:34:21.013157 TxDqDly_Margin_A1==98 ps 10
629 01:34:21.013578 TrainedVREFDQ_A0==74
630 01:34:21.018259 TrainedVREFDQ_A1==75
631 01:34:21.018719 VrefDac_Margin_A0==23
632 01:34:21.019131 DeviceVref_Margin_A0==40
633 01:34:21.023875 VrefDac_Margin_A1==23
634 01:34:21.024353 DeviceVref_Margin_A1==39
635 01:34:21.024771
636 01:34:21.025178
637 01:34:21.029621 channel==1
638 01:34:21.030095 RxClkDly_Margin_A0==88 ps 9
639 01:34:21.030509 TxDqDly_Margin_A0==88 ps 9
640 01:34:21.035275 RxClkDly_Margin_A1==78 ps 8
641 01:34:21.035838 TxDqDly_Margin_A1==78 ps 8
642 01:34:21.040691 TrainedVREFDQ_A0==75
643 01:34:21.041222 TrainedVREFDQ_A1==75
644 01:34:21.041643 VrefDac_Margin_A0==22
645 01:34:21.046373 DeviceVref_Margin_A0==39
646 01:34:21.046842 VrefDac_Margin_A1==22
647 01:34:21.051841 DeviceVref_Margin_A1==38
648 01:34:21.052322
649 01:34:21.052731 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 01:34:21.053135
651 01:34:21.085569 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 01:34:21.086092 2D training succeed
653 01:34:21.091180 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 01:34:21.096671 auto size-- 65535DDR cs0 size: 2048MB
655 01:34:21.097173 DDR cs1 size: 2048MB
656 01:34:21.102274 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 01:34:21.102732 cs0 DataBus test pass
658 01:34:21.107897 cs1 DataBus test pass
659 01:34:21.108384 cs0 AddrBus test pass
660 01:34:21.108801 cs1 AddrBus test pass
661 01:34:21.109200
662 01:34:21.113620 100bdlr_step_size ps== 485
663 01:34:21.114098 result report
664 01:34:21.119150 boot times 0Enable ddr reg access
665 01:34:21.123502 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 01:34:21.137200 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 01:34:21.797624 bl2z: ptr: 05129330, size: 00001e40
668 01:34:21.807205 0.0;M3 CHK:0;cm4_sp_mode 0
669 01:34:21.807754 MVN_1=0x00000000
670 01:34:21.808292 MVN_2=0x00000000
671 01:34:21.818711 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 01:34:21.819221 OPS=0x04
673 01:34:21.819653 ring efuse init
674 01:34:21.824263 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 01:34:21.824774 [0.017354 Inits done]
676 01:34:21.825195 secure task start!
677 01:34:21.831783 high task start!
678 01:34:21.832330 low task start!
679 01:34:21.832755 run into bl31
680 01:34:21.840417 NOTICE: BL31: v1.3(release):4fc40b1
681 01:34:21.848247 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 01:34:21.848778 NOTICE: BL31: G12A normal boot!
683 01:34:21.863829 NOTICE: BL31: BL33 decompress pass
684 01:34:21.869493 ERROR: Error initializing runtime service opteed_fast
685 01:34:22.664986
686 01:34:22.665601
687 01:34:22.670308 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 01:34:22.670765
689 01:34:22.673891 Model: Libre Computer AML-S905D3-CC Solitude
690 01:34:22.821029 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 01:34:22.836230 DRAM: 2 GiB (effective 3.8 GiB)
692 01:34:22.937257 Core: 406 devices, 33 uclasses, devicetree: separate
693 01:34:22.943150 WDT: Not starting watchdog@f0d0
694 01:34:22.968131 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 01:34:22.980409 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 01:34:22.985454 ** Bad device specification mmc 0 **
697 01:34:22.995394 Card did not respond to voltage select! : -110
698 01:34:23.003078 ** Bad device specification mmc 0 **
699 01:34:23.003600 Couldn't find partition mmc 0
700 01:34:23.011390 Card did not respond to voltage select! : -110
701 01:34:23.016911 ** Bad device specification mmc 0 **
702 01:34:23.017371 Couldn't find partition mmc 0
703 01:34:23.021982 Error: could not access storage.
704 01:34:23.319545 Net: eth0: ethernet@ff3f0000
705 01:34:23.320204 starting USB...
706 01:34:23.564230 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 01:34:23.564814 Starting the controller
708 01:34:23.571150 USB XHCI 1.10
709 01:34:25.125183 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 01:34:25.133534 scanning usb for storage devices... 0 Storage Device(s) found
712 01:34:25.185117 Hit any key to stop autoboot: 1
713 01:34:25.186076 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 01:34:25.186734 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 01:34:25.187243 Setting prompt string to ['=>']
716 01:34:25.187742 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 01:34:25.199452 0
718 01:34:25.200403 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 01:34:25.301797 => setenv autoload no
721 01:34:25.302646 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 01:34:25.307666 setenv autoload no
724 01:34:25.409428 => setenv initrd_high 0xffffffff
725 01:34:25.410214 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 01:34:25.414410 setenv initrd_high 0xffffffff
728 01:34:25.515900 => setenv fdt_high 0xffffffff
729 01:34:25.516715 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 01:34:25.521477 setenv fdt_high 0xffffffff
732 01:34:25.622951 => dhcp
733 01:34:25.623702 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 01:34:25.628067 dhcp
735 01:34:26.083365 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 01:34:26.084104 Speed: 1000, full duplex
737 01:34:26.084657 BOOTP broadcast 1
738 01:34:26.331736 BOOTP broadcast 2
739 01:34:26.832797 BOOTP broadcast 3
740 01:34:27.833806 BOOTP broadcast 4
741 01:34:29.834712 BOOTP broadcast 5
742 01:34:29.851703 DHCP client bound to address 192.168.6.12 (3767 ms)
744 01:34:29.953293 => setenv serverip 192.168.6.2
745 01:34:29.954015 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
746 01:34:29.958543 setenv serverip 192.168.6.2
748 01:34:30.059928 => tftpboot 0x01080000 795665/tftp-deploy-7e4nj5s5/kernel/uImage
749 01:34:30.060687 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
750 01:34:30.067526 tftpboot 0x01080000 795665/tftp-deploy-7e4nj5s5/kernel/uImage
751 01:34:30.068026 Speed: 1000, full duplex
752 01:34:30.068463 Using ethernet@ff3f0000 device
753 01:34:30.073107 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
754 01:34:30.078535 Filename '795665/tftp-deploy-7e4nj5s5/kernel/uImage'.
755 01:34:30.082527 Load address: 0x1080000
756 01:34:38.179760 Loading: *########################################### UDP wrong checksum 000000ff 0000e1c5
757 01:34:38.219648 UDP wrong checksum 000000ff 000071b8
758 01:34:40.896141 T ####### 43.6 MiB
759 01:34:40.896816 4 MiB/s
760 01:34:40.897304 done
761 01:34:40.900219 Bytes transferred = 45713984 (2b98a40 hex)
763 01:34:41.001917 => tftpboot 0x08000000 795665/tftp-deploy-7e4nj5s5/ramdisk/ramdisk.cpio.gz.uboot
764 01:34:41.002681 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
765 01:34:41.009516 tftpboot 0x08000000 795665/tftp-deploy-7e4nj5s5/ramdisk/ramdisk.cpio.gz.uboot
766 01:34:41.010033 Speed: 1000, full duplex
767 01:34:41.010480 Using ethernet@ff3f0000 device
768 01:34:41.014973 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
769 01:34:41.024791 Filename '795665/tftp-deploy-7e4nj5s5/ramdisk/ramdisk.cpio.gz.uboot'.
770 01:34:41.025337 Load address: 0x8000000
771 01:34:48.517720 Loading: *################################################# UDP wrong checksum 0000000f 000027c8
772 01:34:52.724440 UDP wrong checksum 000000ff 0000392c
773 01:34:52.734016 UDP wrong checksum 000000ff 0000cd1e
774 01:34:53.518429 T UDP wrong checksum 0000000f 000027c8
775 01:35:03.520685 T T UDP wrong checksum 0000000f 000027c8
776 01:35:23.524339 T T T UDP wrong checksum 0000000f 000027c8
777 01:35:31.884967 T T UDP wrong checksum 000000ff 0000ad4d
778 01:35:31.918950 UDP wrong checksum 000000ff 00004640
779 01:35:34.091858 T UDP wrong checksum 000000ff 0000a212
780 01:35:34.122093 UDP wrong checksum 000000ff 00002805
781 01:35:43.529480 T
782 01:35:43.530105 Retry count exceeded; starting again
784 01:35:43.531635 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
787 01:35:43.533776 end: 2.4 uboot-commands (duration 00:01:37) [common]
789 01:35:43.535259 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
791 01:35:43.536424 end: 2 uboot-action (duration 00:01:37) [common]
793 01:35:43.538098 Cleaning after the job
794 01:35:43.538711 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/ramdisk
795 01:35:43.540015 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/kernel
796 01:35:43.571205 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/dtb
797 01:35:43.572600 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795665/tftp-deploy-7e4nj5s5/modules
798 01:35:43.579522 start: 4.1 power-off (timeout 00:00:30) [common]
799 01:35:43.580645 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
800 01:35:43.615874 >> OK - accepted request
801 01:35:43.617887 Returned 0 in 0 seconds
802 01:35:43.719072 end: 4.1 power-off (duration 00:00:00) [common]
804 01:35:43.720872 start: 4.2 read-feedback (timeout 00:10:00) [common]
805 01:35:43.722050 Listened to connection for namespace 'common' for up to 1s
806 01:35:44.722809 Finalising connection for namespace 'common'
807 01:35:44.723598 Disconnecting from shell: Finalise
808 01:35:44.724238 =>
809 01:35:44.825326 end: 4.2 read-feedback (duration 00:00:01) [common]
810 01:35:44.826088 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795665
811 01:35:45.503397 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795665
812 01:35:45.504044 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.