Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:17:13.925197 lava-dispatcher, installed at version: 2024.01
2 01:17:13.925939 start: 0 validate
3 01:17:13.926401 Start time: 2024-10-03 01:17:13.926372+00:00 (UTC)
4 01:17:13.926946 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:17:13.927482 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:17:13.972134 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:17:13.972680 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:17:14.005890 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:17:14.006525 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:17:14.040403 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:17:14.040903 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:17:14.072468 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:17:14.072971 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:17:14.115384 validate duration: 0.19
16 01:17:14.116896 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:17:14.117484 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:17:14.118082 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:17:14.119027 Not decompressing ramdisk as can be used compressed.
20 01:17:14.119785 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:17:14.120331 saving as /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/ramdisk/initrd.cpio.gz
22 01:17:14.120833 total size: 5628140 (5 MB)
23 01:17:14.164289 progress 0 % (0 MB)
24 01:17:14.172325 progress 5 % (0 MB)
25 01:17:14.180779 progress 10 % (0 MB)
26 01:17:14.187798 progress 15 % (0 MB)
27 01:17:14.195738 progress 20 % (1 MB)
28 01:17:14.199629 progress 25 % (1 MB)
29 01:17:14.203719 progress 30 % (1 MB)
30 01:17:14.207856 progress 35 % (1 MB)
31 01:17:14.211496 progress 40 % (2 MB)
32 01:17:14.215528 progress 45 % (2 MB)
33 01:17:14.219279 progress 50 % (2 MB)
34 01:17:14.223377 progress 55 % (2 MB)
35 01:17:14.227377 progress 60 % (3 MB)
36 01:17:14.230976 progress 65 % (3 MB)
37 01:17:14.235010 progress 70 % (3 MB)
38 01:17:14.238614 progress 75 % (4 MB)
39 01:17:14.242581 progress 80 % (4 MB)
40 01:17:14.246256 progress 85 % (4 MB)
41 01:17:14.250304 progress 90 % (4 MB)
42 01:17:14.254087 progress 95 % (5 MB)
43 01:17:14.257483 progress 100 % (5 MB)
44 01:17:14.258159 5 MB downloaded in 0.14 s (39.09 MB/s)
45 01:17:14.258734 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:17:14.259683 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:17:14.260023 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:17:14.260360 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:17:14.260856 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/kernel/Image
51 01:17:14.261108 saving as /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/kernel/Image
52 01:17:14.261320 total size: 45713920 (43 MB)
53 01:17:14.261534 No compression specified
54 01:17:14.301943 progress 0 % (0 MB)
55 01:17:14.331690 progress 5 % (2 MB)
56 01:17:14.360458 progress 10 % (4 MB)
57 01:17:14.389099 progress 15 % (6 MB)
58 01:17:14.417853 progress 20 % (8 MB)
59 01:17:14.445867 progress 25 % (10 MB)
60 01:17:14.474293 progress 30 % (13 MB)
61 01:17:14.502934 progress 35 % (15 MB)
62 01:17:14.531420 progress 40 % (17 MB)
63 01:17:14.560135 progress 45 % (19 MB)
64 01:17:14.588679 progress 50 % (21 MB)
65 01:17:14.617575 progress 55 % (24 MB)
66 01:17:14.646066 progress 60 % (26 MB)
67 01:17:14.674555 progress 65 % (28 MB)
68 01:17:14.704327 progress 70 % (30 MB)
69 01:17:14.732896 progress 75 % (32 MB)
70 01:17:14.761553 progress 80 % (34 MB)
71 01:17:14.790269 progress 85 % (37 MB)
72 01:17:14.818507 progress 90 % (39 MB)
73 01:17:14.847126 progress 95 % (41 MB)
74 01:17:14.874772 progress 100 % (43 MB)
75 01:17:14.875315 43 MB downloaded in 0.61 s (71.01 MB/s)
76 01:17:14.875799 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:17:14.876653 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:17:14.876931 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:17:14.877196 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:17:14.877671 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:17:14.877944 saving as /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:17:14.878154 total size: 54703 (0 MB)
84 01:17:14.878366 No compression specified
85 01:17:14.919231 progress 59 % (0 MB)
86 01:17:14.920154 progress 100 % (0 MB)
87 01:17:14.920724 0 MB downloaded in 0.04 s (1.23 MB/s)
88 01:17:14.921211 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:17:14.922038 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:17:14.922307 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:17:14.922574 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:17:14.923117 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:17:14.923393 saving as /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/nfsrootfs/full.rootfs.tar
95 01:17:14.923603 total size: 474398908 (452 MB)
96 01:17:14.923817 Using unxz to decompress xz
97 01:17:14.960377 progress 0 % (0 MB)
98 01:17:16.072484 progress 5 % (22 MB)
99 01:17:17.551180 progress 10 % (45 MB)
100 01:17:18.020483 progress 15 % (67 MB)
101 01:17:18.855128 progress 20 % (90 MB)
102 01:17:19.399494 progress 25 % (113 MB)
103 01:17:19.770933 progress 30 % (135 MB)
104 01:17:20.380891 progress 35 % (158 MB)
105 01:17:21.219787 progress 40 % (181 MB)
106 01:17:21.955795 progress 45 % (203 MB)
107 01:17:22.555178 progress 50 % (226 MB)
108 01:17:23.197435 progress 55 % (248 MB)
109 01:17:24.389334 progress 60 % (271 MB)
110 01:17:25.795811 progress 65 % (294 MB)
111 01:17:27.392679 progress 70 % (316 MB)
112 01:17:30.512242 progress 75 % (339 MB)
113 01:17:32.972787 progress 80 % (361 MB)
114 01:17:35.877734 progress 85 % (384 MB)
115 01:17:39.058117 progress 90 % (407 MB)
116 01:17:42.255925 progress 95 % (429 MB)
117 01:17:45.438020 progress 100 % (452 MB)
118 01:17:45.452041 452 MB downloaded in 30.53 s (14.82 MB/s)
119 01:17:45.453042 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:17:45.454809 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:17:45.455381 start: 1.5 download-retry (timeout 00:09:29) [common]
123 01:17:45.455946 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 01:17:45.457075 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/modules.tar.xz
125 01:17:45.457615 saving as /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/modules/modules.tar
126 01:17:45.458092 total size: 11617124 (11 MB)
127 01:17:45.458566 Using unxz to decompress xz
128 01:17:45.499916 progress 0 % (0 MB)
129 01:17:45.568842 progress 5 % (0 MB)
130 01:17:45.646345 progress 10 % (1 MB)
131 01:17:45.732481 progress 15 % (1 MB)
132 01:17:45.809001 progress 20 % (2 MB)
133 01:17:45.891524 progress 25 % (2 MB)
134 01:17:45.971270 progress 30 % (3 MB)
135 01:17:46.050964 progress 35 % (3 MB)
136 01:17:46.124612 progress 40 % (4 MB)
137 01:17:46.201002 progress 45 % (5 MB)
138 01:17:46.278418 progress 50 % (5 MB)
139 01:17:46.351962 progress 55 % (6 MB)
140 01:17:46.438372 progress 60 % (6 MB)
141 01:17:46.525202 progress 65 % (7 MB)
142 01:17:46.607582 progress 70 % (7 MB)
143 01:17:46.700646 progress 75 % (8 MB)
144 01:17:46.796288 progress 80 % (8 MB)
145 01:17:46.878012 progress 85 % (9 MB)
146 01:17:46.953556 progress 90 % (10 MB)
147 01:17:47.025877 progress 95 % (10 MB)
148 01:17:47.102139 progress 100 % (11 MB)
149 01:17:47.114211 11 MB downloaded in 1.66 s (6.69 MB/s)
150 01:17:47.115319 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:17:47.117196 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:17:47.117775 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 01:17:47.118345 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 01:18:02.889022 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/795638/extract-nfsrootfs-joqbpxw2
156 01:18:02.889621 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:18:02.889957 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 01:18:02.890764 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i
159 01:18:02.891496 makedir: /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin
160 01:18:02.892040 makedir: /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/tests
161 01:18:02.892508 makedir: /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/results
162 01:18:02.892871 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-add-keys
163 01:18:02.893561 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-add-sources
164 01:18:02.894225 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-background-process-start
165 01:18:02.894786 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-background-process-stop
166 01:18:02.895445 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-common-functions
167 01:18:02.896044 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-echo-ipv4
168 01:18:02.896672 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-install-packages
169 01:18:02.897275 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-installed-packages
170 01:18:02.897822 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-os-build
171 01:18:02.898352 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-probe-channel
172 01:18:02.898875 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-probe-ip
173 01:18:02.899400 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-target-ip
174 01:18:02.899932 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-target-mac
175 01:18:02.900577 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-target-storage
176 01:18:02.901225 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-test-case
177 01:18:02.901837 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-test-event
178 01:18:02.902381 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-test-feedback
179 01:18:02.902931 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-test-raise
180 01:18:02.903600 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-test-reference
181 01:18:02.904217 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-test-runner
182 01:18:02.904789 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-test-set
183 01:18:02.905347 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-test-shell
184 01:18:02.905897 Updating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-install-packages (oe)
185 01:18:02.906495 Updating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/bin/lava-installed-packages (oe)
186 01:18:02.907033 Creating /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/environment
187 01:18:02.907466 LAVA metadata
188 01:18:02.907759 - LAVA_JOB_ID=795638
189 01:18:02.908007 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:18:02.908439 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 01:18:02.909543 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:18:02.909935 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 01:18:02.910152 skipped lava-vland-overlay
194 01:18:02.910399 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:18:02.910662 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 01:18:02.910890 skipped lava-multinode-overlay
197 01:18:02.911139 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:18:02.911397 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 01:18:02.911666 Loading test definitions
200 01:18:02.911965 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 01:18:02.912238 Using /lava-795638 at stage 0
202 01:18:02.913597 uuid=795638_1.6.2.4.1 testdef=None
203 01:18:02.913981 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:18:02.914261 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 01:18:02.916453 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:18:02.917335 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 01:18:02.919814 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:18:02.920817 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 01:18:02.924939 runner path: /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 795638_1.6.2.4.1
212 01:18:02.925682 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:18:02.926486 Creating lava-test-runner.conf files
215 01:18:02.926692 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795638/lava-overlay-5khx1y1i/lava-795638/0 for stage 0
216 01:18:02.927131 - 0_v4l2-decoder-conformance-h264
217 01:18:02.927537 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:18:02.927831 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 01:18:02.951449 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:18:02.951928 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 01:18:02.952245 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:18:02.952531 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:18:02.952803 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 01:18:03.708581 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:18:03.709081 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 01:18:03.709357 extracting modules file /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795638/extract-nfsrootfs-joqbpxw2
227 01:18:05.099864 extracting modules file /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795638/extract-overlay-ramdisk-4ccduw4r/ramdisk
228 01:18:06.560099 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:18:06.560556 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 01:18:06.560831 [common] Applying overlay to NFS
231 01:18:06.561048 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795638/compress-overlay-ep2miw88/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795638/extract-nfsrootfs-joqbpxw2
232 01:18:06.592957 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:18:06.593445 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 01:18:06.593774 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 01:18:06.594033 Converting downloaded kernel to a uImage
236 01:18:06.594391 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/kernel/Image /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/kernel/uImage
237 01:18:07.081955 output: Image Name:
238 01:18:07.082388 output: Created: Thu Oct 3 01:18:06 2024
239 01:18:07.082600 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:18:07.082806 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 01:18:07.083010 output: Load Address: 01080000
242 01:18:07.083212 output: Entry Point: 01080000
243 01:18:07.083411 output:
244 01:18:07.083748 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 01:18:07.084057 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 01:18:07.084340 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 01:18:07.084598 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:18:07.084857 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 01:18:07.085114 Building ramdisk /var/lib/lava/dispatcher/tmp/795638/extract-overlay-ramdisk-4ccduw4r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795638/extract-overlay-ramdisk-4ccduw4r/ramdisk
250 01:18:09.271565 >> 166772 blocks
251 01:18:17.106352 Adding RAMdisk u-boot header.
252 01:18:17.106783 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795638/extract-overlay-ramdisk-4ccduw4r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795638/extract-overlay-ramdisk-4ccduw4r/ramdisk.cpio.gz.uboot
253 01:18:17.351935 output: Image Name:
254 01:18:17.352660 output: Created: Thu Oct 3 01:18:17 2024
255 01:18:17.353158 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:18:17.353620 output: Data Size: 23422289 Bytes = 22873.33 KiB = 22.34 MiB
257 01:18:17.354068 output: Load Address: 00000000
258 01:18:17.354508 output: Entry Point: 00000000
259 01:18:17.354951 output:
260 01:18:17.356041 rename /var/lib/lava/dispatcher/tmp/795638/extract-overlay-ramdisk-4ccduw4r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/ramdisk/ramdisk.cpio.gz.uboot
261 01:18:17.356844 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:18:17.357471 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 01:18:17.358072 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 01:18:17.358596 No LXC device requested
265 01:18:17.359165 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:18:17.359749 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 01:18:17.360350 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:18:17.360853 Checking files for TFTP limit of 4294967296 bytes.
269 01:18:17.363862 end: 1 tftp-deploy (duration 00:01:03) [common]
270 01:18:17.364562 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:18:17.365165 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:18:17.365733 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:18:17.366303 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:18:17.366897 Using kernel file from prepare-kernel: 795638/tftp-deploy-hgj14k1l/kernel/uImage
275 01:18:17.367606 substitutions:
276 01:18:17.368101 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:18:17.368567 - {DTB_ADDR}: 0x01070000
278 01:18:17.369023 - {DTB}: 795638/tftp-deploy-hgj14k1l/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:18:17.369476 - {INITRD}: 795638/tftp-deploy-hgj14k1l/ramdisk/ramdisk.cpio.gz.uboot
280 01:18:17.369924 - {KERNEL_ADDR}: 0x01080000
281 01:18:17.370370 - {KERNEL}: 795638/tftp-deploy-hgj14k1l/kernel/uImage
282 01:18:17.370817 - {LAVA_MAC}: None
283 01:18:17.371307 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/795638/extract-nfsrootfs-joqbpxw2
284 01:18:17.371760 - {NFS_SERVER_IP}: 192.168.6.2
285 01:18:17.372246 - {PRESEED_CONFIG}: None
286 01:18:17.372694 - {PRESEED_LOCAL}: None
287 01:18:17.373138 - {RAMDISK_ADDR}: 0x08000000
288 01:18:17.373575 - {RAMDISK}: 795638/tftp-deploy-hgj14k1l/ramdisk/ramdisk.cpio.gz.uboot
289 01:18:17.374012 - {ROOT_PART}: None
290 01:18:17.374450 - {ROOT}: None
291 01:18:17.374885 - {SERVER_IP}: 192.168.6.2
292 01:18:17.375322 - {TEE_ADDR}: 0x83000000
293 01:18:17.376311 - {TEE}: None
294 01:18:17.376785 Parsed boot commands:
295 01:18:17.377221 - setenv autoload no
296 01:18:17.377664 - setenv initrd_high 0xffffffff
297 01:18:17.378126 - setenv fdt_high 0xffffffff
298 01:18:17.378570 - dhcp
299 01:18:17.379218 - setenv serverip 192.168.6.2
300 01:18:17.379711 - tftpboot 0x01080000 795638/tftp-deploy-hgj14k1l/kernel/uImage
301 01:18:17.380214 - tftpboot 0x08000000 795638/tftp-deploy-hgj14k1l/ramdisk/ramdisk.cpio.gz.uboot
302 01:18:17.380675 - tftpboot 0x01070000 795638/tftp-deploy-hgj14k1l/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:18:17.381121 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/795638/extract-nfsrootfs-joqbpxw2,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:18:17.381578 - bootm 0x01080000 0x08000000 0x01070000
305 01:18:17.382167 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:18:17.383863 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:18:17.384416 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:18:17.399607 Setting prompt string to ['lava-test: # ']
310 01:18:17.401273 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:18:17.401932 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:18:17.402888 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:18:17.403565 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:18:17.404857 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:18:17.446585 >> OK - accepted request
316 01:18:17.448932 Returned 0 in 0 seconds
317 01:18:17.549894 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:18:17.551798 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:18:17.552600 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:18:17.553241 Setting prompt string to ['Hit any key to stop autoboot']
322 01:18:17.553787 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:18:17.555571 Trying 192.168.56.21...
324 01:18:17.556153 Connected to conserv1.
325 01:18:17.556666 Escape character is '^]'.
326 01:18:17.557166
327 01:18:17.557649 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:18:17.558151
329 01:18:29.379532 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:18:29.380224 bl2_stage_init 0x01
331 01:18:29.380639 bl2_stage_init 0x81
332 01:18:29.384962 hw id: 0x0000 - pwm id 0x01
333 01:18:29.385278 bl2_stage_init 0xc1
334 01:18:29.385481 bl2_stage_init 0x02
335 01:18:29.385677
336 01:18:29.390967 L0:00000000
337 01:18:29.391256 L1:20000703
338 01:18:29.391491 L2:00008067
339 01:18:29.391703 L3:14000000
340 01:18:29.396128 B2:00402000
341 01:18:29.396647 B1:e0f83180
342 01:18:29.397088
343 01:18:29.397504 TE: 58124
344 01:18:29.397911
345 01:18:29.401833 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:18:29.402325
347 01:18:29.402722 Board ID = 1
348 01:18:29.407350 Set A53 clk to 24M
349 01:18:29.407665 Set A73 clk to 24M
350 01:18:29.407888 Set clk81 to 24M
351 01:18:29.412901 A53 clk: 1200 MHz
352 01:18:29.413194 A73 clk: 1200 MHz
353 01:18:29.413413 CLK81: 166.6M
354 01:18:29.413618 smccc: 00012a91
355 01:18:29.418436 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:18:29.424080 board id: 1
357 01:18:29.428986 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:18:29.440552 fw parse done
359 01:18:29.445602 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:18:29.489147 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:18:29.500225 PIEI prepare done
362 01:18:29.500518 fastboot data load
363 01:18:29.500739 fastboot data verify
364 01:18:29.506081 verify result: 266
365 01:18:29.511262 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:18:29.511721 LPDDR4 probe
367 01:18:29.512163 ddr clk to 1584MHz
368 01:18:29.518504 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:18:29.556151
370 01:18:29.556687 dmc_version 0001
371 01:18:29.562416 Check phy result
372 01:18:29.569149 INFO : End of CA training
373 01:18:29.569601 INFO : End of initialization
374 01:18:29.574829 INFO : Training has run successfully!
375 01:18:29.575272 Check phy result
376 01:18:29.580254 INFO : End of initialization
377 01:18:29.580565 INFO : End of read enable training
378 01:18:29.583606 INFO : End of fine write leveling
379 01:18:29.589041 INFO : End of Write leveling coarse delay
380 01:18:29.594751 INFO : Training has run successfully!
381 01:18:29.595029 Check phy result
382 01:18:29.595245 INFO : End of initialization
383 01:18:29.604634 INFO : End of read dq deskew training
384 01:18:29.605967 INFO : End of MPR read delay center optimization
385 01:18:29.606203 INFO : End of write delay center optimization
386 01:18:29.612284 INFO : End of read delay center optimization
387 01:18:29.617082 INFO : End of max read latency training
388 01:18:29.617311 INFO : Training has run successfully!
389 01:18:29.622774 1D training succeed
390 01:18:29.628325 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:18:29.675643 Check phy result
392 01:18:29.676325 INFO : End of initialization
393 01:18:29.698807 INFO : End of 2D read delay Voltage center optimization
394 01:18:29.718443 INFO : End of 2D read delay Voltage center optimization
395 01:18:29.770966 INFO : End of 2D write delay Voltage center optimization
396 01:18:29.820817 INFO : End of 2D write delay Voltage center optimization
397 01:18:29.826112 INFO : Training has run successfully!
398 01:18:29.826433
399 01:18:29.826665 channel==0
400 01:18:29.831813 RxClkDly_Margin_A0==88 ps 9
401 01:18:29.832195 TxDqDly_Margin_A0==98 ps 10
402 01:18:29.834964 RxClkDly_Margin_A1==88 ps 9
403 01:18:29.835243 TxDqDly_Margin_A1==98 ps 10
404 01:18:29.840606 TrainedVREFDQ_A0==74
405 01:18:29.840977 TrainedVREFDQ_A1==74
406 01:18:29.846267 VrefDac_Margin_A0==25
407 01:18:29.846564 DeviceVref_Margin_A0==40
408 01:18:29.846778 VrefDac_Margin_A1==24
409 01:18:29.851755 DeviceVref_Margin_A1==40
410 01:18:29.852064
411 01:18:29.852282
412 01:18:29.852487 channel==1
413 01:18:29.852696 RxClkDly_Margin_A0==98 ps 10
414 01:18:29.857333 TxDqDly_Margin_A0==98 ps 10
415 01:18:29.857627 RxClkDly_Margin_A1==88 ps 9
416 01:18:29.863007 TxDqDly_Margin_A1==88 ps 9
417 01:18:29.863342 TrainedVREFDQ_A0==77
418 01:18:29.863572 TrainedVREFDQ_A1==77
419 01:18:29.868581 VrefDac_Margin_A0==22
420 01:18:29.869037 DeviceVref_Margin_A0==37
421 01:18:29.874165 VrefDac_Margin_A1==24
422 01:18:29.874602 DeviceVref_Margin_A1==37
423 01:18:29.874994
424 01:18:29.879867 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:18:29.880334
426 01:18:29.907803 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:18:29.913344 2D training succeed
428 01:18:29.918903 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:18:29.919465 auto size-- 65535DDR cs0 size: 2048MB
430 01:18:29.924524 DDR cs1 size: 2048MB
431 01:18:29.924915 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:18:29.930193 cs0 DataBus test pass
433 01:18:29.930730 cs1 DataBus test pass
434 01:18:29.931191 cs0 AddrBus test pass
435 01:18:29.935765 cs1 AddrBus test pass
436 01:18:29.936291
437 01:18:29.936702 100bdlr_step_size ps== 420
438 01:18:29.937111 result report
439 01:18:29.941284 boot times 0Enable ddr reg access
440 01:18:29.948138 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:18:29.962567 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:18:30.536453 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:18:30.537094 MVN_1=0x00000000
444 01:18:30.541572 MVN_2=0x00000000
445 01:18:30.547476 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:18:30.548063 OPS=0x10
447 01:18:30.548487 ring efuse init
448 01:18:30.548887 chipver efuse init
449 01:18:30.553021 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:18:30.558580 [0.018961 Inits done]
451 01:18:30.559030 secure task start!
452 01:18:30.559425 high task start!
453 01:18:30.562108 low task start!
454 01:18:30.562575 run into bl31
455 01:18:30.569778 NOTICE: BL31: v1.3(release):4fc40b1
456 01:18:30.576737 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:18:30.577250 NOTICE: BL31: G12A normal boot!
458 01:18:30.603035 NOTICE: BL31: BL33 decompress pass
459 01:18:30.608487 ERROR: Error initializing runtime service opteed_fast
460 01:18:31.841904
461 01:18:31.842316
462 01:18:31.848961 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:18:31.849262
464 01:18:31.849472 Model: Libre Computer AML-A311D-CC Alta
465 01:18:32.058764 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:18:32.081674 DRAM: 2 GiB (effective 3.8 GiB)
467 01:18:32.224608 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:18:32.229518 WDT: Not starting watchdog@f0d0
469 01:18:32.262774 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:18:32.275201 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:18:32.279294 ** Bad device specification mmc 0 **
472 01:18:32.290515 Card did not respond to voltage select! : -110
473 01:18:32.297534 ** Bad device specification mmc 0 **
474 01:18:32.297842 Couldn't find partition mmc 0
475 01:18:32.306512 Card did not respond to voltage select! : -110
476 01:18:32.312023 ** Bad device specification mmc 0 **
477 01:18:32.312350 Couldn't find partition mmc 0
478 01:18:32.316152 Error: could not access storage.
479 01:18:33.579734 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:18:33.580194 bl2_stage_init 0x01
481 01:18:33.580431 bl2_stage_init 0x81
482 01:18:33.585268 hw id: 0x0000 - pwm id 0x01
483 01:18:33.585576 bl2_stage_init 0xc1
484 01:18:33.585796 bl2_stage_init 0x02
485 01:18:33.586006
486 01:18:33.590777 L0:00000000
487 01:18:33.591082 L1:20000703
488 01:18:33.591302 L2:00008067
489 01:18:33.591510 L3:14000000
490 01:18:33.596368 B2:00402000
491 01:18:33.596686 B1:e0f83180
492 01:18:33.596898
493 01:18:33.597104 TE: 58167
494 01:18:33.597328
495 01:18:33.601995 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:18:33.602325
497 01:18:33.602547 Board ID = 1
498 01:18:33.607605 Set A53 clk to 24M
499 01:18:33.607921 Set A73 clk to 24M
500 01:18:33.608180 Set clk81 to 24M
501 01:18:33.613241 A53 clk: 1200 MHz
502 01:18:33.613566 A73 clk: 1200 MHz
503 01:18:33.613781 CLK81: 166.6M
504 01:18:33.614000 smccc: 00012abe
505 01:18:33.618805 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:18:33.624389 board id: 1
507 01:18:33.630344 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:18:33.641044 fw parse done
509 01:18:33.646878 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:18:33.689557 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:18:33.700455 PIEI prepare done
512 01:18:33.700833 fastboot data load
513 01:18:33.701084 fastboot data verify
514 01:18:33.706224 verify result: 266
515 01:18:33.711780 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:18:33.712156 LPDDR4 probe
517 01:18:33.712391 ddr clk to 1584MHz
518 01:18:33.719730 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:18:33.756118
520 01:18:33.756507 dmc_version 0001
521 01:18:33.762633 Check phy result
522 01:18:33.769446 INFO : End of CA training
523 01:18:33.769803 INFO : End of initialization
524 01:18:33.775140 INFO : Training has run successfully!
525 01:18:33.775482 Check phy result
526 01:18:33.780668 INFO : End of initialization
527 01:18:33.780983 INFO : End of read enable training
528 01:18:33.786333 INFO : End of fine write leveling
529 01:18:33.791857 INFO : End of Write leveling coarse delay
530 01:18:33.792252 INFO : Training has run successfully!
531 01:18:33.792478 Check phy result
532 01:18:33.797447 INFO : End of initialization
533 01:18:33.797788 INFO : End of read dq deskew training
534 01:18:33.803044 INFO : End of MPR read delay center optimization
535 01:18:33.808628 INFO : End of write delay center optimization
536 01:18:33.814314 INFO : End of read delay center optimization
537 01:18:33.814619 INFO : End of max read latency training
538 01:18:33.819837 INFO : Training has run successfully!
539 01:18:33.820186 1D training succeed
540 01:18:33.829023 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:18:33.876797 Check phy result
542 01:18:33.877204 INFO : End of initialization
543 01:18:33.898461 INFO : End of 2D read delay Voltage center optimization
544 01:18:33.918524 INFO : End of 2D read delay Voltage center optimization
545 01:18:33.970232 INFO : End of 2D write delay Voltage center optimization
546 01:18:34.019585 INFO : End of 2D write delay Voltage center optimization
547 01:18:34.025088 INFO : Training has run successfully!
548 01:18:34.025399
549 01:18:34.025620 channel==0
550 01:18:34.030696 RxClkDly_Margin_A0==88 ps 9
551 01:18:34.030992 TxDqDly_Margin_A0==98 ps 10
552 01:18:34.036363 RxClkDly_Margin_A1==88 ps 9
553 01:18:34.036659 TxDqDly_Margin_A1==98 ps 10
554 01:18:34.036881 TrainedVREFDQ_A0==74
555 01:18:34.041831 TrainedVREFDQ_A1==74
556 01:18:34.042117 VrefDac_Margin_A0==25
557 01:18:34.042329 DeviceVref_Margin_A0==40
558 01:18:34.047423 VrefDac_Margin_A1==26
559 01:18:34.047693 DeviceVref_Margin_A1==40
560 01:18:34.047905
561 01:18:34.048146
562 01:18:34.053080 channel==1
563 01:18:34.053361 RxClkDly_Margin_A0==98 ps 10
564 01:18:34.053571 TxDqDly_Margin_A0==98 ps 10
565 01:18:34.058631 RxClkDly_Margin_A1==88 ps 9
566 01:18:34.058917 TxDqDly_Margin_A1==88 ps 9
567 01:18:34.064308 TrainedVREFDQ_A0==77
568 01:18:34.064570 TrainedVREFDQ_A1==77
569 01:18:34.064783 VrefDac_Margin_A0==22
570 01:18:34.069843 DeviceVref_Margin_A0==37
571 01:18:34.070153 VrefDac_Margin_A1==24
572 01:18:34.075522 DeviceVref_Margin_A1==37
573 01:18:34.076154
574 01:18:34.076639 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:18:34.077124
576 01:18:34.109222 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 01:18:34.109880 2D training succeed
578 01:18:34.114791 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:18:34.120505 auto size-- 65535DDR cs0 size: 2048MB
580 01:18:34.121098 DDR cs1 size: 2048MB
581 01:18:34.125980 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:18:34.126548 cs0 DataBus test pass
583 01:18:34.131571 cs1 DataBus test pass
584 01:18:34.132216 cs0 AddrBus test pass
585 01:18:34.132704 cs1 AddrBus test pass
586 01:18:34.133185
587 01:18:34.137295 100bdlr_step_size ps== 420
588 01:18:34.137879 result report
589 01:18:34.142791 boot times 0Enable ddr reg access
590 01:18:34.148027 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:18:34.161465 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:18:34.733538 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:18:34.734210 MVN_1=0x00000000
594 01:18:34.739126 MVN_2=0x00000000
595 01:18:34.744873 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:18:34.745586 OPS=0x10
597 01:18:34.746053 ring efuse init
598 01:18:34.746493 chipver efuse init
599 01:18:34.752934 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:18:34.753515 [0.018960 Inits done]
601 01:18:34.759544 secure task start!
602 01:18:34.760099 high task start!
603 01:18:34.760547 low task start!
604 01:18:34.760979 run into bl31
605 01:18:34.767170 NOTICE: BL31: v1.3(release):4fc40b1
606 01:18:34.774051 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:18:34.774577 NOTICE: BL31: G12A normal boot!
608 01:18:34.800507 NOTICE: BL31: BL33 decompress pass
609 01:18:34.805073 ERROR: Error initializing runtime service opteed_fast
610 01:18:36.038910
611 01:18:36.039335
612 01:18:36.047259 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:18:36.047717
614 01:18:36.048075 Model: Libre Computer AML-A311D-CC Alta
615 01:18:36.254800 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:18:36.279194 DRAM: 2 GiB (effective 3.8 GiB)
617 01:18:36.422098 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:18:36.426993 WDT: Not starting watchdog@f0d0
619 01:18:36.460318 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:18:36.472998 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:18:36.476716 ** Bad device specification mmc 0 **
622 01:18:36.488028 Card did not respond to voltage select! : -110
623 01:18:36.494690 ** Bad device specification mmc 0 **
624 01:18:36.495040 Couldn't find partition mmc 0
625 01:18:36.504081 Card did not respond to voltage select! : -110
626 01:18:36.509668 ** Bad device specification mmc 0 **
627 01:18:36.510002 Couldn't find partition mmc 0
628 01:18:36.513654 Error: could not access storage.
629 01:18:36.856209 Net: eth0: ethernet@ff3f0000
630 01:18:36.856867 starting USB...
631 01:18:37.109030 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:18:37.109678 Starting the controller
633 01:18:37.114989 USB XHCI 1.10
634 01:18:38.829757 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:18:38.830428 bl2_stage_init 0x01
636 01:18:38.830897 bl2_stage_init 0x81
637 01:18:38.835350 hw id: 0x0000 - pwm id 0x01
638 01:18:38.835872 bl2_stage_init 0xc1
639 01:18:38.836392 bl2_stage_init 0x02
640 01:18:38.836849
641 01:18:38.841042 L0:00000000
642 01:18:38.841556 L1:20000703
643 01:18:38.842008 L2:00008067
644 01:18:38.842445 L3:14000000
645 01:18:38.846532 B2:00402000
646 01:18:38.847047 B1:e0f83180
647 01:18:38.847501
648 01:18:38.847953 TE: 58167
649 01:18:38.848444
650 01:18:38.852127 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:18:38.852652
652 01:18:38.853102 Board ID = 1
653 01:18:38.857778 Set A53 clk to 24M
654 01:18:38.858296 Set A73 clk to 24M
655 01:18:38.858750 Set clk81 to 24M
656 01:18:38.863330 A53 clk: 1200 MHz
657 01:18:38.863848 A73 clk: 1200 MHz
658 01:18:38.864345 CLK81: 166.6M
659 01:18:38.864795 smccc: 00012abe
660 01:18:38.869015 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:18:38.874512 board id: 1
662 01:18:38.880399 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:18:38.891071 fw parse done
664 01:18:38.897092 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:18:38.939619 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:18:38.950558 PIEI prepare done
667 01:18:38.951078 fastboot data load
668 01:18:38.951532 fastboot data verify
669 01:18:38.956260 verify result: 266
670 01:18:38.961842 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:18:38.962355 LPDDR4 probe
672 01:18:38.962804 ddr clk to 1584MHz
673 01:18:38.969834 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:18:39.007048
675 01:18:39.007616 dmc_version 0001
676 01:18:39.013752 Check phy result
677 01:18:39.019625 INFO : End of CA training
678 01:18:39.020208 INFO : End of initialization
679 01:18:39.025222 INFO : Training has run successfully!
680 01:18:39.025757 Check phy result
681 01:18:39.030855 INFO : End of initialization
682 01:18:39.031366 INFO : End of read enable training
683 01:18:39.034108 INFO : End of fine write leveling
684 01:18:39.039699 INFO : End of Write leveling coarse delay
685 01:18:39.045243 INFO : Training has run successfully!
686 01:18:39.045783 Check phy result
687 01:18:39.046285 INFO : End of initialization
688 01:18:39.050837 INFO : End of read dq deskew training
689 01:18:39.056425 INFO : End of MPR read delay center optimization
690 01:18:39.056940 INFO : End of write delay center optimization
691 01:18:39.062105 INFO : End of read delay center optimization
692 01:18:39.067608 INFO : End of max read latency training
693 01:18:39.068178 INFO : Training has run successfully!
694 01:18:39.073212 1D training succeed
695 01:18:39.079210 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:18:39.126840 Check phy result
697 01:18:39.127387 INFO : End of initialization
698 01:18:39.148400 INFO : End of 2D read delay Voltage center optimization
699 01:18:39.168494 INFO : End of 2D read delay Voltage center optimization
700 01:18:39.220446 INFO : End of 2D write delay Voltage center optimization
701 01:18:39.269695 INFO : End of 2D write delay Voltage center optimization
702 01:18:39.275242 INFO : Training has run successfully!
703 01:18:39.275811
704 01:18:39.276354 channel==0
705 01:18:39.280835 RxClkDly_Margin_A0==88 ps 9
706 01:18:39.281364 TxDqDly_Margin_A0==98 ps 10
707 01:18:39.284247 RxClkDly_Margin_A1==88 ps 9
708 01:18:39.284772 TxDqDly_Margin_A1==98 ps 10
709 01:18:39.289735 TrainedVREFDQ_A0==74
710 01:18:39.290255 TrainedVREFDQ_A1==74
711 01:18:39.290710 VrefDac_Margin_A0==25
712 01:18:39.295354 DeviceVref_Margin_A0==40
713 01:18:39.295881 VrefDac_Margin_A1==25
714 01:18:39.300926 DeviceVref_Margin_A1==40
715 01:18:39.301444
716 01:18:39.301896
717 01:18:39.302337 channel==1
718 01:18:39.302772 RxClkDly_Margin_A0==98 ps 10
719 01:18:39.306534 TxDqDly_Margin_A0==98 ps 10
720 01:18:39.307050 RxClkDly_Margin_A1==88 ps 9
721 01:18:39.312246 TxDqDly_Margin_A1==88 ps 9
722 01:18:39.312783 TrainedVREFDQ_A0==77
723 01:18:39.313233 TrainedVREFDQ_A1==77
724 01:18:39.317715 VrefDac_Margin_A0==22
725 01:18:39.318223 DeviceVref_Margin_A0==37
726 01:18:39.323314 VrefDac_Margin_A1==24
727 01:18:39.323827 DeviceVref_Margin_A1==37
728 01:18:39.324315
729 01:18:39.328897 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:18:39.329410
731 01:18:39.356900 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 01:18:39.362543 2D training succeed
733 01:18:39.368223 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:18:39.368758 auto size-- 65535DDR cs0 size: 2048MB
735 01:18:39.373693 DDR cs1 size: 2048MB
736 01:18:39.374214 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:18:39.379333 cs0 DataBus test pass
738 01:18:39.379865 cs1 DataBus test pass
739 01:18:39.380376 cs0 AddrBus test pass
740 01:18:39.384924 cs1 AddrBus test pass
741 01:18:39.385441
742 01:18:39.385896 100bdlr_step_size ps== 420
743 01:18:39.386357 result report
744 01:18:39.390510 boot times 0Enable ddr reg access
745 01:18:39.398243 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:18:39.411573 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:18:39.983592 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:18:39.984325 MVN_1=0x00000000
749 01:18:39.989641 MVN_2=0x00000000
750 01:18:39.994734 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:18:39.995038 OPS=0x10
752 01:18:39.995244 ring efuse init
753 01:18:39.995444 chipver efuse init
754 01:18:40.000347 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:18:40.005970 [0.018960 Inits done]
756 01:18:40.006237 secure task start!
757 01:18:40.006444 high task start!
758 01:18:40.010533 low task start!
759 01:18:40.010792 run into bl31
760 01:18:40.017200 NOTICE: BL31: v1.3(release):4fc40b1
761 01:18:40.025034 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:18:40.025325 NOTICE: BL31: G12A normal boot!
763 01:18:40.050483 NOTICE: BL31: BL33 decompress pass
764 01:18:40.056168 ERROR: Error initializing runtime service opteed_fast
765 01:18:41.289197
766 01:18:41.289619
767 01:18:41.297510 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:18:41.297912
769 01:18:41.298226 Model: Libre Computer AML-A311D-CC Alta
770 01:18:41.506029 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:18:41.529301 DRAM: 2 GiB (effective 3.8 GiB)
772 01:18:41.672313 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:18:41.678241 WDT: Not starting watchdog@f0d0
774 01:18:41.710525 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:18:41.722957 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:18:41.727954 ** Bad device specification mmc 0 **
777 01:18:41.738150 Card did not respond to voltage select! : -110
778 01:18:41.745784 ** Bad device specification mmc 0 **
779 01:18:41.746060 Couldn't find partition mmc 0
780 01:18:41.754170 Card did not respond to voltage select! : -110
781 01:18:41.759728 ** Bad device specification mmc 0 **
782 01:18:41.760027 Couldn't find partition mmc 0
783 01:18:41.764689 Error: could not access storage.
784 01:18:42.107265 Net: eth0: ethernet@ff3f0000
785 01:18:42.107690 starting USB...
786 01:18:42.359608 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:18:42.360226 Starting the controller
788 01:18:42.366020 USB XHCI 1.10
789 01:18:44.531359 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:18:44.531762 bl2_stage_init 0x01
791 01:18:44.532024 bl2_stage_init 0x81
792 01:18:44.537013 hw id: 0x0000 - pwm id 0x01
793 01:18:44.537286 bl2_stage_init 0xc1
794 01:18:44.537496 bl2_stage_init 0x02
795 01:18:44.537709
796 01:18:44.542494 L0:00000000
797 01:18:44.542757 L1:20000703
798 01:18:44.542960 L2:00008067
799 01:18:44.543165 L3:14000000
800 01:18:44.548108 B2:00402000
801 01:18:44.548359 B1:e0f83180
802 01:18:44.548558
803 01:18:44.548755 TE: 58124
804 01:18:44.548949
805 01:18:44.553737 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:18:44.554095
807 01:18:44.554401 Board ID = 1
808 01:18:44.559290 Set A53 clk to 24M
809 01:18:44.559679 Set A73 clk to 24M
810 01:18:44.560009 Set clk81 to 24M
811 01:18:44.565021 A53 clk: 1200 MHz
812 01:18:44.565368 A73 clk: 1200 MHz
813 01:18:44.565669 CLK81: 166.6M
814 01:18:44.565968 smccc: 00012a92
815 01:18:44.570427 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:18:44.576202 board id: 1
817 01:18:44.582151 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:18:44.592617 fw parse done
819 01:18:44.598529 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:18:44.641093 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:18:44.652014 PIEI prepare done
822 01:18:44.652275 fastboot data load
823 01:18:44.652482 fastboot data verify
824 01:18:44.657668 verify result: 266
825 01:18:44.663188 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:18:44.663448 LPDDR4 probe
827 01:18:44.663653 ddr clk to 1584MHz
828 01:18:44.671203 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:18:44.708562
830 01:18:44.708870 dmc_version 0001
831 01:18:44.715138 Check phy result
832 01:18:44.720985 INFO : End of CA training
833 01:18:44.721361 INFO : End of initialization
834 01:18:44.726726 INFO : Training has run successfully!
835 01:18:44.727003 Check phy result
836 01:18:44.732222 INFO : End of initialization
837 01:18:44.732481 INFO : End of read enable training
838 01:18:44.737807 INFO : End of fine write leveling
839 01:18:44.743451 INFO : End of Write leveling coarse delay
840 01:18:44.743781 INFO : Training has run successfully!
841 01:18:44.744030 Check phy result
842 01:18:44.749073 INFO : End of initialization
843 01:18:44.749438 INFO : End of read dq deskew training
844 01:18:44.754779 INFO : End of MPR read delay center optimization
845 01:18:44.760270 INFO : End of write delay center optimization
846 01:18:44.765822 INFO : End of read delay center optimization
847 01:18:44.766135 INFO : End of max read latency training
848 01:18:44.771453 INFO : Training has run successfully!
849 01:18:44.771794 1D training succeed
850 01:18:44.780778 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:18:44.828301 Check phy result
852 01:18:44.828682 INFO : End of initialization
853 01:18:44.850882 INFO : End of 2D read delay Voltage center optimization
854 01:18:44.871113 INFO : End of 2D read delay Voltage center optimization
855 01:18:44.923151 INFO : End of 2D write delay Voltage center optimization
856 01:18:44.972562 INFO : End of 2D write delay Voltage center optimization
857 01:18:44.978045 INFO : Training has run successfully!
858 01:18:44.978450
859 01:18:44.978686 channel==0
860 01:18:44.983713 RxClkDly_Margin_A0==88 ps 9
861 01:18:44.984036 TxDqDly_Margin_A0==98 ps 10
862 01:18:44.987324 RxClkDly_Margin_A1==78 ps 8
863 01:18:44.987573 TxDqDly_Margin_A1==98 ps 10
864 01:18:44.992963 TrainedVREFDQ_A0==74
865 01:18:44.993271 TrainedVREFDQ_A1==74
866 01:18:44.993497 VrefDac_Margin_A0==25
867 01:18:44.998556 DeviceVref_Margin_A0==40
868 01:18:44.998826 VrefDac_Margin_A1==26
869 01:18:45.004123 DeviceVref_Margin_A1==40
870 01:18:45.004386
871 01:18:45.004605
872 01:18:45.004814 channel==1
873 01:18:45.005018 RxClkDly_Margin_A0==98 ps 10
874 01:18:45.009711 TxDqDly_Margin_A0==98 ps 10
875 01:18:45.009967 RxClkDly_Margin_A1==98 ps 10
876 01:18:45.015316 TxDqDly_Margin_A1==88 ps 9
877 01:18:45.015574 TrainedVREFDQ_A0==77
878 01:18:45.015791 TrainedVREFDQ_A1==77
879 01:18:45.020913 VrefDac_Margin_A0==22
880 01:18:45.021176 DeviceVref_Margin_A0==37
881 01:18:45.021391 VrefDac_Margin_A1==22
882 01:18:45.026494 DeviceVref_Margin_A1==37
883 01:18:45.026747
884 01:18:45.032129 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:18:45.032399
886 01:18:45.060118 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 01:18:45.065730 2D training succeed
888 01:18:45.071341 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:18:45.071627 auto size-- 65535DDR cs0 size: 2048MB
890 01:18:45.076931 DDR cs1 size: 2048MB
891 01:18:45.077203 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:18:45.082520 cs0 DataBus test pass
893 01:18:45.082800 cs1 DataBus test pass
894 01:18:45.083020 cs0 AddrBus test pass
895 01:18:45.088136 cs1 AddrBus test pass
896 01:18:45.088408
897 01:18:45.088627 100bdlr_step_size ps== 420
898 01:18:45.088843 result report
899 01:18:45.093713 boot times 0Enable ddr reg access
900 01:18:45.101094 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:18:45.114592 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:18:45.688311 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:18:45.688959 MVN_1=0x00000000
904 01:18:45.693832 MVN_2=0x00000000
905 01:18:45.699562 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:18:45.700191 OPS=0x10
907 01:18:45.700668 ring efuse init
908 01:18:45.701118 chipver efuse init
909 01:18:45.707810 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:18:45.708402 [0.018961 Inits done]
911 01:18:45.708904 secure task start!
912 01:18:45.715308 high task start!
913 01:18:45.715894 low task start!
914 01:18:45.716417 run into bl31
915 01:18:45.721941 NOTICE: BL31: v1.3(release):4fc40b1
916 01:18:45.729741 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:18:45.730238 NOTICE: BL31: G12A normal boot!
918 01:18:45.755109 NOTICE: BL31: BL33 decompress pass
919 01:18:45.760790 ERROR: Error initializing runtime service opteed_fast
920 01:18:46.993764
921 01:18:46.994446
922 01:18:47.002105 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:18:47.002656
924 01:18:47.003122 Model: Libre Computer AML-A311D-CC Alta
925 01:18:47.210616 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:18:47.233960 DRAM: 2 GiB (effective 3.8 GiB)
927 01:18:47.377038 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:18:47.382753 WDT: Not starting watchdog@f0d0
929 01:18:47.415183 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:18:47.427465 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:18:47.432536 ** Bad device specification mmc 0 **
932 01:18:47.442930 Card did not respond to voltage select! : -110
933 01:18:47.450458 ** Bad device specification mmc 0 **
934 01:18:47.450837 Couldn't find partition mmc 0
935 01:18:47.458753 Card did not respond to voltage select! : -110
936 01:18:47.464297 ** Bad device specification mmc 0 **
937 01:18:47.464672 Couldn't find partition mmc 0
938 01:18:47.469385 Error: could not access storage.
939 01:18:47.811846 Net: eth0: ethernet@ff3f0000
940 01:18:47.812455 starting USB...
941 01:18:48.063703 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:18:48.064156 Starting the controller
943 01:18:48.069688 USB XHCI 1.10
944 01:18:49.624626 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 01:18:49.632975 scanning usb for storage devices... 0 Storage Device(s) found
947 01:18:49.684076 Hit any key to stop autoboot: 1
948 01:18:49.685098 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 01:18:49.685477 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 01:18:49.685740 Setting prompt string to ['=>']
951 01:18:49.685998 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 01:18:49.700467 0
953 01:18:49.701155 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 01:18:49.701457 Sending with 10 millisecond of delay
956 01:18:50.835918 => setenv autoload no
957 01:18:50.846581 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 01:18:50.849374 setenv autoload no
959 01:18:50.849911 Sending with 10 millisecond of delay
961 01:18:52.646969 => setenv initrd_high 0xffffffff
962 01:18:52.657810 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 01:18:52.658788 setenv initrd_high 0xffffffff
964 01:18:52.659560 Sending with 10 millisecond of delay
966 01:18:54.276495 => setenv fdt_high 0xffffffff
967 01:18:54.287313 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 01:18:54.288245 setenv fdt_high 0xffffffff
969 01:18:54.289010 Sending with 10 millisecond of delay
971 01:18:54.580998 => dhcp
972 01:18:54.591852 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 01:18:54.592895 dhcp
974 01:18:54.593385 Speed: 1000, full duplex
975 01:18:54.593837 BOOTP broadcast 1
976 01:18:54.840304 BOOTP broadcast 2
977 01:18:54.853548 DHCP client bound to address 192.168.6.33 (262 ms)
978 01:18:54.854362 Sending with 10 millisecond of delay
980 01:18:56.531132 => setenv serverip 192.168.6.2
981 01:18:56.542020 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
982 01:18:56.543073 setenv serverip 192.168.6.2
983 01:18:56.543824 Sending with 10 millisecond of delay
985 01:19:00.269886 => tftpboot 0x01080000 795638/tftp-deploy-hgj14k1l/kernel/uImage
986 01:19:00.280497 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
987 01:19:00.281132 tftpboot 0x01080000 795638/tftp-deploy-hgj14k1l/kernel/uImage
988 01:19:00.281385 Speed: 1000, full duplex
989 01:19:00.281600 Using ethernet@ff3f0000 device
990 01:19:00.283480 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
991 01:19:00.289065 Filename '795638/tftp-deploy-hgj14k1l/kernel/uImage'.
992 01:19:00.293947 Load address: 0x1080000
993 01:19:04.118263 Loading: *################################################## 43.6 MiB
994 01:19:04.119919 11.4 MiB/s
995 01:19:04.120250 done
996 01:19:04.121718 Bytes transferred = 45713984 (2b98a40 hex)
997 01:19:04.122243 Sending with 10 millisecond of delay
999 01:19:08.809618 => tftpboot 0x08000000 795638/tftp-deploy-hgj14k1l/ramdisk/ramdisk.cpio.gz.uboot
1000 01:19:08.820445 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1001 01:19:08.821394 tftpboot 0x08000000 795638/tftp-deploy-hgj14k1l/ramdisk/ramdisk.cpio.gz.uboot
1002 01:19:08.821889 Speed: 1000, full duplex
1003 01:19:08.822297 Using ethernet@ff3f0000 device
1004 01:19:08.823088 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1005 01:19:08.833960 Filename '795638/tftp-deploy-hgj14k1l/ramdisk/ramdisk.cpio.gz.uboot'.
1006 01:19:08.834470 Load address: 0x8000000
1007 01:19:11.124259 Loading: *################################################# UDP wrong checksum 00000005 0000195f
1008 01:19:16.126601 T UDP wrong checksum 00000005 0000195f
1009 01:19:26.128507 T T UDP wrong checksum 00000005 0000195f
1010 01:19:35.406005 T UDP wrong checksum 000000ff 000006a6
1011 01:19:35.413653 UDP wrong checksum 000000ff 00008998
1012 01:19:46.132519 T T T UDP wrong checksum 00000005 0000195f
1013 01:20:02.674749 T T T UDP wrong checksum 000000ff 000054df
1014 01:20:02.705069 UDP wrong checksum 000000ff 0000e6d1
1015 01:20:06.095273 UDP wrong checksum 000000ff 000081f5
1016 01:20:06.104867 UDP wrong checksum 000000ff 000005e8
1017 01:20:06.136652
1018 01:20:06.137244 Retry count exceeded; starting again
1020 01:20:06.138748 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1023 01:20:06.140858 end: 2.4 uboot-commands (duration 00:01:49) [common]
1025 01:20:06.142441 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1027 01:20:06.143607 end: 2 uboot-action (duration 00:01:49) [common]
1029 01:20:06.145357 Cleaning after the job
1030 01:20:06.145980 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/ramdisk
1031 01:20:06.147388 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/kernel
1032 01:20:06.156941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/dtb
1033 01:20:06.158351 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/nfsrootfs
1034 01:20:06.239671 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795638/tftp-deploy-hgj14k1l/modules
1035 01:20:06.257405 start: 4.1 power-off (timeout 00:00:30) [common]
1036 01:20:06.258070 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1037 01:20:06.293083 >> OK - accepted request
1038 01:20:06.295085 Returned 0 in 0 seconds
1039 01:20:06.395923 end: 4.1 power-off (duration 00:00:00) [common]
1041 01:20:06.396986 start: 4.2 read-feedback (timeout 00:10:00) [common]
1042 01:20:06.397666 Listened to connection for namespace 'common' for up to 1s
1043 01:20:07.398604 Finalising connection for namespace 'common'
1044 01:20:07.399094 Disconnecting from shell: Finalise
1045 01:20:07.399383 =>
1046 01:20:07.500181 end: 4.2 read-feedback (duration 00:00:01) [common]
1047 01:20:07.500939 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795638
1048 01:20:10.174386 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795638
1049 01:20:10.174988 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.