Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:26:14.142889 lava-dispatcher, installed at version: 2024.01
2 01:26:14.143621 start: 0 validate
3 01:26:14.144110 Start time: 2024-10-03 01:26:14.144081+00:00 (UTC)
4 01:26:14.144669 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:26:14.145213 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:26:14.188478 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:26:14.189016 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:26:14.215830 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:26:14.216455 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:26:14.243902 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:26:14.244412 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:26:14.276217 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:26:14.276706 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc1-46-g7ec462100ef91%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:26:14.314819 validate duration: 0.17
16 01:26:14.315663 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:26:14.316003 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:26:14.316339 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:26:14.316925 Not decompressing ramdisk as can be used compressed.
20 01:26:14.317361 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:26:14.317648 saving as /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/ramdisk/initrd.cpio.gz
22 01:26:14.317915 total size: 5628140 (5 MB)
23 01:26:14.355651 progress 0 % (0 MB)
24 01:26:14.363905 progress 5 % (0 MB)
25 01:26:14.371609 progress 10 % (0 MB)
26 01:26:14.378622 progress 15 % (0 MB)
27 01:26:14.383283 progress 20 % (1 MB)
28 01:26:14.386868 progress 25 % (1 MB)
29 01:26:14.390733 progress 30 % (1 MB)
30 01:26:14.394858 progress 35 % (1 MB)
31 01:26:14.398446 progress 40 % (2 MB)
32 01:26:14.402382 progress 45 % (2 MB)
33 01:26:14.405888 progress 50 % (2 MB)
34 01:26:14.409824 progress 55 % (2 MB)
35 01:26:14.413752 progress 60 % (3 MB)
36 01:26:14.417263 progress 65 % (3 MB)
37 01:26:14.421304 progress 70 % (3 MB)
38 01:26:14.424867 progress 75 % (4 MB)
39 01:26:14.428726 progress 80 % (4 MB)
40 01:26:14.432134 progress 85 % (4 MB)
41 01:26:14.435775 progress 90 % (4 MB)
42 01:26:14.439401 progress 95 % (5 MB)
43 01:26:14.442681 progress 100 % (5 MB)
44 01:26:14.443321 5 MB downloaded in 0.13 s (42.81 MB/s)
45 01:26:14.443883 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:26:14.444806 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:26:14.445106 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:26:14.445379 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:26:14.445859 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/kernel/Image
51 01:26:14.446107 saving as /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/kernel/Image
52 01:26:14.446320 total size: 45713920 (43 MB)
53 01:26:14.446531 No compression specified
54 01:26:14.482901 progress 0 % (0 MB)
55 01:26:14.510662 progress 5 % (2 MB)
56 01:26:14.538221 progress 10 % (4 MB)
57 01:26:14.565691 progress 15 % (6 MB)
58 01:26:14.593728 progress 20 % (8 MB)
59 01:26:14.620860 progress 25 % (10 MB)
60 01:26:14.648854 progress 30 % (13 MB)
61 01:26:14.676890 progress 35 % (15 MB)
62 01:26:14.705744 progress 40 % (17 MB)
63 01:26:14.734397 progress 45 % (19 MB)
64 01:26:14.763450 progress 50 % (21 MB)
65 01:26:14.792473 progress 55 % (24 MB)
66 01:26:14.821044 progress 60 % (26 MB)
67 01:26:14.848950 progress 65 % (28 MB)
68 01:26:14.877146 progress 70 % (30 MB)
69 01:26:14.905413 progress 75 % (32 MB)
70 01:26:14.933580 progress 80 % (34 MB)
71 01:26:14.961381 progress 85 % (37 MB)
72 01:26:14.989493 progress 90 % (39 MB)
73 01:26:15.017422 progress 95 % (41 MB)
74 01:26:15.044295 progress 100 % (43 MB)
75 01:26:15.044870 43 MB downloaded in 0.60 s (72.84 MB/s)
76 01:26:15.045358 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:26:15.046186 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:26:15.046466 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:26:15.046740 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:26:15.047217 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:26:15.047469 saving as /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:26:15.047678 total size: 54703 (0 MB)
84 01:26:15.047888 No compression specified
85 01:26:15.087016 progress 59 % (0 MB)
86 01:26:15.087933 progress 100 % (0 MB)
87 01:26:15.088579 0 MB downloaded in 0.04 s (1.28 MB/s)
88 01:26:15.089108 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:26:15.090001 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:26:15.090300 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:26:15.090599 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:26:15.091065 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:26:15.091329 saving as /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/nfsrootfs/full.rootfs.tar
95 01:26:15.091550 total size: 474398908 (452 MB)
96 01:26:15.091778 Using unxz to decompress xz
97 01:26:15.133007 progress 0 % (0 MB)
98 01:26:16.233576 progress 5 % (22 MB)
99 01:26:17.673152 progress 10 % (45 MB)
100 01:26:18.107541 progress 15 % (67 MB)
101 01:26:18.895459 progress 20 % (90 MB)
102 01:26:19.424824 progress 25 % (113 MB)
103 01:26:19.785150 progress 30 % (135 MB)
104 01:26:20.392067 progress 35 % (158 MB)
105 01:26:21.328870 progress 40 % (181 MB)
106 01:26:22.199745 progress 45 % (203 MB)
107 01:26:22.910138 progress 50 % (226 MB)
108 01:26:23.555857 progress 55 % (248 MB)
109 01:26:24.763474 progress 60 % (271 MB)
110 01:26:26.269184 progress 65 % (294 MB)
111 01:26:27.938330 progress 70 % (316 MB)
112 01:26:31.033987 progress 75 % (339 MB)
113 01:26:33.482842 progress 80 % (361 MB)
114 01:26:36.370747 progress 85 % (384 MB)
115 01:26:39.526835 progress 90 % (407 MB)
116 01:26:42.716992 progress 95 % (429 MB)
117 01:26:45.933547 progress 100 % (452 MB)
118 01:26:45.946911 452 MB downloaded in 30.86 s (14.66 MB/s)
119 01:26:45.947839 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:26:45.949517 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:26:45.950037 start: 1.5 download-retry (timeout 00:09:28) [common]
123 01:26:45.950548 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 01:26:45.951338 downloading http://storage.kernelci.org/mainline/master/v6.12-rc1-46-g7ec462100ef91/arm64/defconfig/gcc-12/modules.tar.xz
125 01:26:45.951797 saving as /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/modules/modules.tar
126 01:26:45.952241 total size: 11617124 (11 MB)
127 01:26:45.952662 Using unxz to decompress xz
128 01:26:45.994800 progress 0 % (0 MB)
129 01:26:46.063779 progress 5 % (0 MB)
130 01:26:46.141513 progress 10 % (1 MB)
131 01:26:46.229582 progress 15 % (1 MB)
132 01:26:46.306366 progress 20 % (2 MB)
133 01:26:46.389175 progress 25 % (2 MB)
134 01:26:46.468889 progress 30 % (3 MB)
135 01:26:46.549115 progress 35 % (3 MB)
136 01:26:46.622409 progress 40 % (4 MB)
137 01:26:46.698856 progress 45 % (5 MB)
138 01:26:46.776368 progress 50 % (5 MB)
139 01:26:46.849172 progress 55 % (6 MB)
140 01:26:46.933597 progress 60 % (6 MB)
141 01:26:47.019768 progress 65 % (7 MB)
142 01:26:47.104391 progress 70 % (7 MB)
143 01:26:47.197276 progress 75 % (8 MB)
144 01:26:47.292958 progress 80 % (8 MB)
145 01:26:47.374387 progress 85 % (9 MB)
146 01:26:47.449442 progress 90 % (10 MB)
147 01:26:47.523359 progress 95 % (10 MB)
148 01:26:47.599654 progress 100 % (11 MB)
149 01:26:47.611795 11 MB downloaded in 1.66 s (6.68 MB/s)
150 01:26:47.612785 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:26:47.614554 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:26:47.615126 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 01:26:47.615695 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 01:27:03.174824 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/795640/extract-nfsrootfs-pwc5nl0d
156 01:27:03.175448 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:27:03.175739 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 01:27:03.176538 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl
159 01:27:03.177009 makedir: /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin
160 01:27:03.177342 makedir: /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/tests
161 01:27:03.177672 makedir: /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/results
162 01:27:03.178029 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-add-keys
163 01:27:03.178567 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-add-sources
164 01:27:03.179221 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-background-process-start
165 01:27:03.179746 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-background-process-stop
166 01:27:03.180313 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-common-functions
167 01:27:03.180813 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-echo-ipv4
168 01:27:03.181297 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-install-packages
169 01:27:03.181886 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-installed-packages
170 01:27:03.182399 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-os-build
171 01:27:03.182885 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-probe-channel
172 01:27:03.183366 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-probe-ip
173 01:27:03.183837 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-target-ip
174 01:27:03.184364 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-target-mac
175 01:27:03.184878 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-target-storage
176 01:27:03.185382 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-test-case
177 01:27:03.185866 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-test-event
178 01:27:03.186340 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-test-feedback
179 01:27:03.186822 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-test-raise
180 01:27:03.187295 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-test-reference
181 01:27:03.187787 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-test-runner
182 01:27:03.188324 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-test-set
183 01:27:03.188814 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-test-shell
184 01:27:03.189331 Updating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-install-packages (oe)
185 01:27:03.189866 Updating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/bin/lava-installed-packages (oe)
186 01:27:03.190304 Creating /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/environment
187 01:27:03.190674 LAVA metadata
188 01:27:03.190938 - LAVA_JOB_ID=795640
189 01:27:03.191154 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:27:03.191521 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 01:27:03.192526 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:27:03.192852 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 01:27:03.193059 skipped lava-vland-overlay
194 01:27:03.193299 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:27:03.193554 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 01:27:03.193771 skipped lava-multinode-overlay
197 01:27:03.194012 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:27:03.194263 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 01:27:03.194512 Loading test definitions
200 01:27:03.194789 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 01:27:03.195008 Using /lava-795640 at stage 0
202 01:27:03.196199 uuid=795640_1.6.2.4.1 testdef=None
203 01:27:03.196517 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:27:03.196781 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 01:27:03.198526 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:27:03.199328 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 01:27:03.201513 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:27:03.202361 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 01:27:03.204488 runner path: /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 795640_1.6.2.4.1
212 01:27:03.205101 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:27:03.205874 Creating lava-test-runner.conf files
215 01:27:03.206078 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/795640/lava-overlay-w96v3jbl/lava-795640/0 for stage 0
216 01:27:03.206422 - 0_v4l2-decoder-conformance-vp9
217 01:27:03.206769 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:27:03.207044 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 01:27:03.228827 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:27:03.229247 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 01:27:03.229508 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:27:03.229774 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:27:03.230038 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 01:27:03.871203 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:27:03.871664 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 01:27:03.871915 extracting modules file /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795640/extract-nfsrootfs-pwc5nl0d
227 01:27:05.312103 extracting modules file /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/modules/modules.tar to /var/lib/lava/dispatcher/tmp/795640/extract-overlay-ramdisk-7qdp0ywq/ramdisk
228 01:27:06.790127 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:27:06.790627 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 01:27:06.790917 [common] Applying overlay to NFS
231 01:27:06.791138 [common] Applying overlay /var/lib/lava/dispatcher/tmp/795640/compress-overlay-xa18v65b/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/795640/extract-nfsrootfs-pwc5nl0d
232 01:27:06.823539 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:27:06.824067 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 01:27:06.824363 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 01:27:06.824616 Converting downloaded kernel to a uImage
236 01:27:06.824961 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/kernel/Image /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/kernel/uImage
237 01:27:07.331755 output: Image Name:
238 01:27:07.332240 output: Created: Thu Oct 3 01:27:06 2024
239 01:27:07.332460 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:27:07.332669 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 01:27:07.332871 output: Load Address: 01080000
242 01:27:07.333071 output: Entry Point: 01080000
243 01:27:07.333268 output:
244 01:27:07.333613 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 01:27:07.333903 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 01:27:07.334179 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 01:27:07.334437 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:27:07.334699 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 01:27:07.334960 Building ramdisk /var/lib/lava/dispatcher/tmp/795640/extract-overlay-ramdisk-7qdp0ywq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/795640/extract-overlay-ramdisk-7qdp0ywq/ramdisk
250 01:27:09.642654 >> 166772 blocks
251 01:27:17.364034 Adding RAMdisk u-boot header.
252 01:27:17.364481 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/795640/extract-overlay-ramdisk-7qdp0ywq/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/795640/extract-overlay-ramdisk-7qdp0ywq/ramdisk.cpio.gz.uboot
253 01:27:17.615836 output: Image Name:
254 01:27:17.616415 output: Created: Thu Oct 3 01:27:17 2024
255 01:27:17.616840 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:27:17.617247 output: Data Size: 23421639 Bytes = 22872.69 KiB = 22.34 MiB
257 01:27:17.617646 output: Load Address: 00000000
258 01:27:17.618039 output: Entry Point: 00000000
259 01:27:17.618429 output:
260 01:27:17.619373 rename /var/lib/lava/dispatcher/tmp/795640/extract-overlay-ramdisk-7qdp0ywq/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/ramdisk/ramdisk.cpio.gz.uboot
261 01:27:17.620110 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:27:17.620662 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 01:27:17.621184 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 01:27:17.621648 No LXC device requested
265 01:27:17.622151 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:27:17.622656 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 01:27:17.623148 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:27:17.623557 Checking files for TFTP limit of 4294967296 bytes.
269 01:27:17.626229 end: 1 tftp-deploy (duration 00:01:03) [common]
270 01:27:17.626816 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:27:17.627338 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:27:17.627831 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:27:17.628374 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:27:17.628900 Using kernel file from prepare-kernel: 795640/tftp-deploy-xuz4z133/kernel/uImage
275 01:27:17.629525 substitutions:
276 01:27:17.629927 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:27:17.630325 - {DTB_ADDR}: 0x01070000
278 01:27:17.630722 - {DTB}: 795640/tftp-deploy-xuz4z133/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:27:17.631119 - {INITRD}: 795640/tftp-deploy-xuz4z133/ramdisk/ramdisk.cpio.gz.uboot
280 01:27:17.631512 - {KERNEL_ADDR}: 0x01080000
281 01:27:17.631899 - {KERNEL}: 795640/tftp-deploy-xuz4z133/kernel/uImage
282 01:27:17.632321 - {LAVA_MAC}: None
283 01:27:17.632751 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/795640/extract-nfsrootfs-pwc5nl0d
284 01:27:17.633146 - {NFS_SERVER_IP}: 192.168.6.2
285 01:27:17.633534 - {PRESEED_CONFIG}: None
286 01:27:17.633921 - {PRESEED_LOCAL}: None
287 01:27:17.634308 - {RAMDISK_ADDR}: 0x08000000
288 01:27:17.634692 - {RAMDISK}: 795640/tftp-deploy-xuz4z133/ramdisk/ramdisk.cpio.gz.uboot
289 01:27:17.635078 - {ROOT_PART}: None
290 01:27:17.635465 - {ROOT}: None
291 01:27:17.635850 - {SERVER_IP}: 192.168.6.2
292 01:27:17.636267 - {TEE_ADDR}: 0x83000000
293 01:27:17.636657 - {TEE}: None
294 01:27:17.637046 Parsed boot commands:
295 01:27:17.637420 - setenv autoload no
296 01:27:17.637804 - setenv initrd_high 0xffffffff
297 01:27:17.638186 - setenv fdt_high 0xffffffff
298 01:27:17.638564 - dhcp
299 01:27:17.638945 - setenv serverip 192.168.6.2
300 01:27:17.639325 - tftpboot 0x01080000 795640/tftp-deploy-xuz4z133/kernel/uImage
301 01:27:17.639707 - tftpboot 0x08000000 795640/tftp-deploy-xuz4z133/ramdisk/ramdisk.cpio.gz.uboot
302 01:27:17.640113 - tftpboot 0x01070000 795640/tftp-deploy-xuz4z133/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:27:17.640499 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/795640/extract-nfsrootfs-pwc5nl0d,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:27:17.640893 - bootm 0x01080000 0x08000000 0x01070000
305 01:27:17.641387 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:27:17.642856 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:27:17.643270 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:27:17.659717 Setting prompt string to ['lava-test: # ']
310 01:27:17.661222 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:27:17.661798 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:27:17.662335 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:27:17.662856 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:27:17.664007 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:27:17.701018 >> OK - accepted request
316 01:27:17.703095 Returned 0 in 0 seconds
317 01:27:17.804373 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:27:17.806039 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:27:17.806594 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:27:17.807106 Setting prompt string to ['Hit any key to stop autoboot']
322 01:27:17.807560 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:27:17.809132 Trying 192.168.56.21...
324 01:27:17.809614 Connected to conserv1.
325 01:27:17.810021 Escape character is '^]'.
326 01:27:17.810435
327 01:27:17.810849 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 01:27:17.811267
329 01:27:28.643454 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:27:28.644102 bl2_stage_init 0x01
331 01:27:28.644529 bl2_stage_init 0x81
332 01:27:28.648868 hw id: 0x0000 - pwm id 0x01
333 01:27:28.649373 bl2_stage_init 0xc1
334 01:27:28.649786 bl2_stage_init 0x02
335 01:27:28.650183
336 01:27:28.654370 L0:00000000
337 01:27:28.654962 L1:20000703
338 01:27:28.655395 L2:00008067
339 01:27:28.655789 L3:14000000
340 01:27:28.657312 B2:00402000
341 01:27:28.657786 B1:e0f83180
342 01:27:28.658186
343 01:27:28.658578 TE: 58167
344 01:27:28.658968
345 01:27:28.668394 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:27:28.668874
347 01:27:28.669280 Board ID = 1
348 01:27:28.669677 Set A53 clk to 24M
349 01:27:28.670063 Set A73 clk to 24M
350 01:27:28.674123 Set clk81 to 24M
351 01:27:28.674591 A53 clk: 1200 MHz
352 01:27:28.674993 A73 clk: 1200 MHz
353 01:27:28.677538 CLK81: 166.6M
354 01:27:28.677997 smccc: 00012abe
355 01:27:28.683077 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:27:28.688770 board id: 1
357 01:27:28.693954 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:27:28.704566 fw parse done
359 01:27:28.711935 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:27:28.753280 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:27:28.764270 PIEI prepare done
362 01:27:28.764735 fastboot data load
363 01:27:28.765135 fastboot data verify
364 01:27:28.769759 verify result: 266
365 01:27:28.775321 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:27:28.775777 LPDDR4 probe
367 01:27:28.776229 ddr clk to 1584MHz
368 01:27:28.783314 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:27:28.820931
370 01:27:28.821411 dmc_version 0001
371 01:27:28.827654 Check phy result
372 01:27:28.833538 INFO : End of CA training
373 01:27:28.834000 INFO : End of initialization
374 01:27:28.838999 INFO : Training has run successfully!
375 01:27:28.839458 Check phy result
376 01:27:28.844389 INFO : End of initialization
377 01:27:28.844829 INFO : End of read enable training
378 01:27:28.849885 INFO : End of fine write leveling
379 01:27:28.855486 INFO : End of Write leveling coarse delay
380 01:27:28.855905 INFO : Training has run successfully!
381 01:27:28.856329 Check phy result
382 01:27:28.861094 INFO : End of initialization
383 01:27:28.861547 INFO : End of read dq deskew training
384 01:27:28.866674 INFO : End of MPR read delay center optimization
385 01:27:28.872289 INFO : End of write delay center optimization
386 01:27:28.877879 INFO : End of read delay center optimization
387 01:27:28.878306 INFO : End of max read latency training
388 01:27:28.883599 INFO : Training has run successfully!
389 01:27:28.884074 1D training succeed
390 01:27:28.892693 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:27:28.940383 Check phy result
392 01:27:28.940924 INFO : End of initialization
393 01:27:28.962100 INFO : End of 2D read delay Voltage center optimization
394 01:27:28.982399 INFO : End of 2D read delay Voltage center optimization
395 01:27:29.034413 INFO : End of 2D write delay Voltage center optimization
396 01:27:29.083830 INFO : End of 2D write delay Voltage center optimization
397 01:27:29.089330 INFO : Training has run successfully!
398 01:27:29.089761
399 01:27:29.090168 channel==0
400 01:27:29.094864 RxClkDly_Margin_A0==88 ps 9
401 01:27:29.095292 TxDqDly_Margin_A0==98 ps 10
402 01:27:29.098284 RxClkDly_Margin_A1==88 ps 9
403 01:27:29.098704 TxDqDly_Margin_A1==88 ps 9
404 01:27:29.103922 TrainedVREFDQ_A0==74
405 01:27:29.104368 TrainedVREFDQ_A1==74
406 01:27:29.104763 VrefDac_Margin_A0==25
407 01:27:29.109799 DeviceVref_Margin_A0==40
408 01:27:29.110214 VrefDac_Margin_A1==25
409 01:27:29.115064 DeviceVref_Margin_A1==40
410 01:27:29.115477
411 01:27:29.115867
412 01:27:29.116289 channel==1
413 01:27:29.116678 RxClkDly_Margin_A0==88 ps 9
414 01:27:29.121126 TxDqDly_Margin_A0==88 ps 9
415 01:27:29.121552 RxClkDly_Margin_A1==98 ps 10
416 01:27:29.126340 TxDqDly_Margin_A1==98 ps 10
417 01:27:29.126761 TrainedVREFDQ_A0==77
418 01:27:29.127155 TrainedVREFDQ_A1==77
419 01:27:29.131905 VrefDac_Margin_A0==22
420 01:27:29.132351 DeviceVref_Margin_A0==37
421 01:27:29.137526 VrefDac_Margin_A1==22
422 01:27:29.137939 DeviceVref_Margin_A1==37
423 01:27:29.138326
424 01:27:29.143058 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:27:29.143474
426 01:27:29.170971 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 01:27:29.176615 2D training succeed
428 01:27:29.182144 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:27:29.182596 auto size-- 65535DDR cs0 size: 2048MB
430 01:27:29.187882 DDR cs1 size: 2048MB
431 01:27:29.188348 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:27:29.193331 cs0 DataBus test pass
433 01:27:29.193791 cs1 DataBus test pass
434 01:27:29.194192 cs0 AddrBus test pass
435 01:27:29.198978 cs1 AddrBus test pass
436 01:27:29.199426
437 01:27:29.199825 100bdlr_step_size ps== 420
438 01:27:29.200264 result report
439 01:27:29.204636 boot times 0Enable ddr reg access
440 01:27:29.212097 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:27:29.225572 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:27:29.799195 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:27:29.799621 MVN_1=0x00000000
444 01:27:29.804698 MVN_2=0x00000000
445 01:27:29.810345 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:27:29.810649 OPS=0x10
447 01:27:29.810857 ring efuse init
448 01:27:29.811061 chipver efuse init
449 01:27:29.818626 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:27:29.818949 [0.018960 Inits done]
451 01:27:29.825986 secure task start!
452 01:27:29.826300 high task start!
453 01:27:29.826507 low task start!
454 01:27:29.826707 run into bl31
455 01:27:29.832776 NOTICE: BL31: v1.3(release):4fc40b1
456 01:27:29.840341 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:27:29.840680 NOTICE: BL31: G12A normal boot!
458 01:27:29.866120 NOTICE: BL31: BL33 decompress pass
459 01:27:29.871493 ERROR: Error initializing runtime service opteed_fast
460 01:27:31.104582
461 01:27:31.105175
462 01:27:31.112141 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:27:31.112621
464 01:27:31.113041 Model: Libre Computer AML-A311D-CC Alta
465 01:27:31.320977 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:27:31.343947 DRAM: 2 GiB (effective 3.8 GiB)
467 01:27:31.487894 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:27:31.493084 WDT: Not starting watchdog@f0d0
469 01:27:31.525876 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:27:31.538425 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:27:31.542636 ** Bad device specification mmc 0 **
472 01:27:31.553700 Card did not respond to voltage select! : -110
473 01:27:31.560565 ** Bad device specification mmc 0 **
474 01:27:31.561007 Couldn't find partition mmc 0
475 01:27:31.569756 Card did not respond to voltage select! : -110
476 01:27:31.575294 ** Bad device specification mmc 0 **
477 01:27:31.575725 Couldn't find partition mmc 0
478 01:27:31.579917 Error: could not access storage.
479 01:27:32.843663 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:27:32.844269 bl2_stage_init 0x01
481 01:27:32.844698 bl2_stage_init 0x81
482 01:27:32.849239 hw id: 0x0000 - pwm id 0x01
483 01:27:32.849711 bl2_stage_init 0xc1
484 01:27:32.850137 bl2_stage_init 0x02
485 01:27:32.850549
486 01:27:32.854789 L0:00000000
487 01:27:32.855224 L1:20000703
488 01:27:32.855637 L2:00008067
489 01:27:32.856071 L3:14000000
490 01:27:32.860413 B2:00402000
491 01:27:32.860846 B1:e0f83180
492 01:27:32.861249
493 01:27:32.861651 TE: 58167
494 01:27:32.862055
495 01:27:32.866065 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:27:32.866497
497 01:27:32.866905 Board ID = 1
498 01:27:32.871600 Set A53 clk to 24M
499 01:27:32.872093 Set A73 clk to 24M
500 01:27:32.872509 Set clk81 to 24M
501 01:27:32.877210 A53 clk: 1200 MHz
502 01:27:32.877671 A73 clk: 1200 MHz
503 01:27:32.878080 CLK81: 166.6M
504 01:27:32.878478 smccc: 00012abe
505 01:27:32.882792 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:27:32.888381 board id: 1
507 01:27:32.893804 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:27:32.904935 fw parse done
509 01:27:32.909945 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:27:32.952616 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:27:32.964433 PIEI prepare done
512 01:27:32.964927 fastboot data load
513 01:27:32.965508 fastboot data verify
514 01:27:32.970129 verify result: 266
515 01:27:32.975689 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:27:32.976170 LPDDR4 probe
517 01:27:32.976581 ddr clk to 1584MHz
518 01:27:32.983658 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:27:33.020058
520 01:27:33.020528 dmc_version 0001
521 01:27:33.027345 Check phy result
522 01:27:33.033500 INFO : End of CA training
523 01:27:33.033963 INFO : End of initialization
524 01:27:33.039148 INFO : Training has run successfully!
525 01:27:33.039615 Check phy result
526 01:27:33.044750 INFO : End of initialization
527 01:27:33.045300 INFO : End of read enable training
528 01:27:33.050376 INFO : End of fine write leveling
529 01:27:33.056050 INFO : End of Write leveling coarse delay
530 01:27:33.056589 INFO : Training has run successfully!
531 01:27:33.057057 Check phy result
532 01:27:33.061619 INFO : End of initialization
533 01:27:33.062140 INFO : End of read dq deskew training
534 01:27:33.067225 INFO : End of MPR read delay center optimization
535 01:27:33.072764 INFO : End of write delay center optimization
536 01:27:33.078361 INFO : End of read delay center optimization
537 01:27:33.078892 INFO : End of max read latency training
538 01:27:33.083976 INFO : Training has run successfully!
539 01:27:33.084557 1D training succeed
540 01:27:33.092243 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:27:33.139883 Check phy result
542 01:27:33.140470 INFO : End of initialization
543 01:27:33.161535 INFO : End of 2D read delay Voltage center optimization
544 01:27:33.182397 INFO : End of 2D read delay Voltage center optimization
545 01:27:33.234107 INFO : End of 2D write delay Voltage center optimization
546 01:27:33.283665 INFO : End of 2D write delay Voltage center optimization
547 01:27:33.289213 INFO : Training has run successfully!
548 01:27:33.289808
549 01:27:33.290284 channel==0
550 01:27:33.294815 RxClkDly_Margin_A0==88 ps 9
551 01:27:33.295393 TxDqDly_Margin_A0==98 ps 10
552 01:27:33.298089 RxClkDly_Margin_A1==88 ps 9
553 01:27:33.298668 TxDqDly_Margin_A1==88 ps 9
554 01:27:33.304117 TrainedVREFDQ_A0==74
555 01:27:33.304696 TrainedVREFDQ_A1==74
556 01:27:33.305172 VrefDac_Margin_A0==25
557 01:27:33.309299 DeviceVref_Margin_A0==40
558 01:27:33.309853 VrefDac_Margin_A1==25
559 01:27:33.314885 DeviceVref_Margin_A1==40
560 01:27:33.315435
561 01:27:33.315899
562 01:27:33.316408 channel==1
563 01:27:33.316869 RxClkDly_Margin_A0==98 ps 10
564 01:27:33.320486 TxDqDly_Margin_A0==98 ps 10
565 01:27:33.321040 RxClkDly_Margin_A1==98 ps 10
566 01:27:33.326076 TxDqDly_Margin_A1==88 ps 9
567 01:27:33.326632 TrainedVREFDQ_A0==77
568 01:27:33.327096 TrainedVREFDQ_A1==77
569 01:27:33.331661 VrefDac_Margin_A0==22
570 01:27:33.332244 DeviceVref_Margin_A0==37
571 01:27:33.337270 VrefDac_Margin_A1==22
572 01:27:33.337819 DeviceVref_Margin_A1==37
573 01:27:33.338279
574 01:27:33.342876 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:27:33.343430
576 01:27:33.370838 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 01:27:33.376470 2D training succeed
578 01:27:33.382109 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:27:33.382671 auto size-- 65535DDR cs0 size: 2048MB
580 01:27:33.387694 DDR cs1 size: 2048MB
581 01:27:33.388322 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:27:33.393259 cs0 DataBus test pass
583 01:27:33.393813 cs1 DataBus test pass
584 01:27:33.394277 cs0 AddrBus test pass
585 01:27:33.398894 cs1 AddrBus test pass
586 01:27:33.399444
587 01:27:33.399917 100bdlr_step_size ps== 420
588 01:27:33.400436 result report
589 01:27:33.404500 boot times 0Enable ddr reg access
590 01:27:33.412126 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:27:33.425492 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:27:33.997429 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:27:33.997864 MVN_1=0x00000000
594 01:27:34.004214 MVN_2=0x00000000
595 01:27:34.008697 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:27:34.009311 OPS=0x10
597 01:27:34.009833 ring efuse init
598 01:27:34.010433 chipver efuse init
599 01:27:34.016804 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:27:34.017137 [0.018961 Inits done]
601 01:27:34.023457 secure task start!
602 01:27:34.024090 high task start!
603 01:27:34.024615 low task start!
604 01:27:34.025118 run into bl31
605 01:27:34.031016 NOTICE: BL31: v1.3(release):4fc40b1
606 01:27:34.037911 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:27:34.038499 NOTICE: BL31: G12A normal boot!
608 01:27:34.064226 NOTICE: BL31: BL33 decompress pass
609 01:27:34.068924 ERROR: Error initializing runtime service opteed_fast
610 01:27:35.303260
611 01:27:35.304164
612 01:27:35.311003 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:27:35.311614
614 01:27:35.312103 Model: Libre Computer AML-A311D-CC Alta
615 01:27:35.519296 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:27:35.543177 DRAM: 2 GiB (effective 3.8 GiB)
617 01:27:35.686115 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:27:35.691677 WDT: Not starting watchdog@f0d0
619 01:27:35.724369 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:27:35.736607 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:27:35.740886 ** Bad device specification mmc 0 **
622 01:27:35.751960 Card did not respond to voltage select! : -110
623 01:27:35.758768 ** Bad device specification mmc 0 **
624 01:27:35.759451 Couldn't find partition mmc 0
625 01:27:35.767934 Card did not respond to voltage select! : -110
626 01:27:35.773494 ** Bad device specification mmc 0 **
627 01:27:35.773888 Couldn't find partition mmc 0
628 01:27:35.777518 Error: could not access storage.
629 01:27:36.120455 Net: eth0: ethernet@ff3f0000
630 01:27:36.121097 starting USB...
631 01:27:36.372864 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:27:36.373459 Starting the controller
633 01:27:36.379571 USB XHCI 1.10
634 01:27:38.095483 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:27:38.096114 bl2_stage_init 0x01
636 01:27:38.096541 bl2_stage_init 0x81
637 01:27:38.100958 hw id: 0x0000 - pwm id 0x01
638 01:27:38.101411 bl2_stage_init 0xc1
639 01:27:38.101821 bl2_stage_init 0x02
640 01:27:38.102224
641 01:27:38.106604 L0:00000000
642 01:27:38.107057 L1:20000703
643 01:27:38.107468 L2:00008067
644 01:27:38.107867 L3:14000000
645 01:27:38.112259 B2:00402000
646 01:27:38.112691 B1:e0f83180
647 01:27:38.113096
648 01:27:38.113497 TE: 58159
649 01:27:38.113896
650 01:27:38.117769 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:27:38.118210
652 01:27:38.118618 Board ID = 1
653 01:27:38.123473 Set A53 clk to 24M
654 01:27:38.123944 Set A73 clk to 24M
655 01:27:38.124246 Set clk81 to 24M
656 01:27:38.128928 A53 clk: 1200 MHz
657 01:27:38.129197 A73 clk: 1200 MHz
658 01:27:38.129434 CLK81: 166.6M
659 01:27:38.129668 smccc: 00012ab5
660 01:27:38.134575 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:27:38.140322 board id: 1
662 01:27:38.145845 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:27:38.156648 fw parse done
664 01:27:38.162352 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:27:38.204379 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:27:38.216217 PIEI prepare done
667 01:27:38.216530 fastboot data load
668 01:27:38.216774 fastboot data verify
669 01:27:38.221842 verify result: 266
670 01:27:38.227391 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:27:38.227677 LPDDR4 probe
672 01:27:38.227921 ddr clk to 1584MHz
673 01:27:38.234427 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:27:38.272716
675 01:27:38.273059 dmc_version 0001
676 01:27:38.278977 Check phy result
677 01:27:38.285288 INFO : End of CA training
678 01:27:38.285781 INFO : End of initialization
679 01:27:38.290747 INFO : Training has run successfully!
680 01:27:38.291018 Check phy result
681 01:27:38.296385 INFO : End of initialization
682 01:27:38.296648 INFO : End of read enable training
683 01:27:38.301945 INFO : End of fine write leveling
684 01:27:38.307565 INFO : End of Write leveling coarse delay
685 01:27:38.307833 INFO : Training has run successfully!
686 01:27:38.308083 Check phy result
687 01:27:38.313254 INFO : End of initialization
688 01:27:38.313518 INFO : End of read dq deskew training
689 01:27:38.318776 INFO : End of MPR read delay center optimization
690 01:27:38.324436 INFO : End of write delay center optimization
691 01:27:38.329905 INFO : End of read delay center optimization
692 01:27:38.330168 INFO : End of max read latency training
693 01:27:38.335596 INFO : Training has run successfully!
694 01:27:38.335870 1D training succeed
695 01:27:38.343771 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:27:38.392244 Check phy result
697 01:27:38.392811 INFO : End of initialization
698 01:27:38.413375 INFO : End of 2D read delay Voltage center optimization
699 01:27:38.432720 INFO : End of 2D read delay Voltage center optimization
700 01:27:38.485463 INFO : End of 2D write delay Voltage center optimization
701 01:27:38.535035 INFO : End of 2D write delay Voltage center optimization
702 01:27:38.540739 INFO : Training has run successfully!
703 01:27:38.541397
704 01:27:38.542853 channel==0
705 01:27:38.546232 RxClkDly_Margin_A0==88 ps 9
706 01:27:38.546781 TxDqDly_Margin_A0==98 ps 10
707 01:27:38.551920 RxClkDly_Margin_A1==78 ps 8
708 01:27:38.552471 TxDqDly_Margin_A1==88 ps 9
709 01:27:38.552921 TrainedVREFDQ_A0==74
710 01:27:38.557453 TrainedVREFDQ_A1==74
711 01:27:38.557962 VrefDac_Margin_A0==25
712 01:27:38.558402 DeviceVref_Margin_A0==40
713 01:27:38.563021 VrefDac_Margin_A1==25
714 01:27:38.563533 DeviceVref_Margin_A1==40
715 01:27:38.563975
716 01:27:38.564449
717 01:27:38.564879 channel==1
718 01:27:38.568698 RxClkDly_Margin_A0==98 ps 10
719 01:27:38.569211 TxDqDly_Margin_A0==88 ps 9
720 01:27:38.574323 RxClkDly_Margin_A1==88 ps 9
721 01:27:38.574836 TxDqDly_Margin_A1==88 ps 9
722 01:27:38.579822 TrainedVREFDQ_A0==77
723 01:27:38.580377 TrainedVREFDQ_A1==77
724 01:27:38.580822 VrefDac_Margin_A0==23
725 01:27:38.585483 DeviceVref_Margin_A0==37
726 01:27:38.585999 VrefDac_Margin_A1==24
727 01:27:38.591091 DeviceVref_Margin_A1==37
728 01:27:38.591617
729 01:27:38.592092 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:27:38.592530
731 01:27:38.624759 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000019 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 01:27:38.625338 2D training succeed
733 01:27:38.630302 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:27:38.635781 auto size-- 65535DDR cs0 size: 2048MB
735 01:27:38.636355 DDR cs1 size: 2048MB
736 01:27:38.641391 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:27:38.641937 cs0 DataBus test pass
738 01:27:38.646992 cs1 DataBus test pass
739 01:27:38.647530 cs0 AddrBus test pass
740 01:27:38.648026 cs1 AddrBus test pass
741 01:27:38.648493
742 01:27:38.652579 100bdlr_step_size ps== 420
743 01:27:38.653127 result report
744 01:27:38.658169 boot times 0Enable ddr reg access
745 01:27:38.663101 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:27:38.676855 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:27:39.250461 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:27:39.251110 MVN_1=0x00000000
749 01:27:39.255910 MVN_2=0x00000000
750 01:27:39.261641 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:27:39.262198 OPS=0x10
752 01:27:39.262637 ring efuse init
753 01:27:39.263062 chipver efuse init
754 01:27:39.269927 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:27:39.270457 [0.018960 Inits done]
756 01:27:39.270895 secure task start!
757 01:27:39.276948 high task start!
758 01:27:39.277451 low task start!
759 01:27:39.277899 run into bl31
760 01:27:39.284100 NOTICE: BL31: v1.3(release):4fc40b1
761 01:27:39.291943 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:27:39.292489 NOTICE: BL31: G12A normal boot!
763 01:27:39.317187 NOTICE: BL31: BL33 decompress pass
764 01:27:39.322367 ERROR: Error initializing runtime service opteed_fast
765 01:27:40.555809
766 01:27:40.556543
767 01:27:40.564201 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:27:40.564728
769 01:27:40.565187 Model: Libre Computer AML-A311D-CC Alta
770 01:27:40.772610 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:27:40.795291 DRAM: 2 GiB (effective 3.8 GiB)
772 01:27:40.938948 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:27:40.944219 WDT: Not starting watchdog@f0d0
774 01:27:40.977088 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:27:40.989585 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:27:40.993804 ** Bad device specification mmc 0 **
777 01:27:41.004903 Card did not respond to voltage select! : -110
778 01:27:41.012335 ** Bad device specification mmc 0 **
779 01:27:41.012879 Couldn't find partition mmc 0
780 01:27:41.020868 Card did not respond to voltage select! : -110
781 01:27:41.026406 ** Bad device specification mmc 0 **
782 01:27:41.026914 Couldn't find partition mmc 0
783 01:27:41.030515 Error: could not access storage.
784 01:27:41.372944 Net: eth0: ethernet@ff3f0000
785 01:27:41.373542 starting USB...
786 01:27:41.625703 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:27:41.626250 Starting the controller
788 01:27:41.632769 USB XHCI 1.10
789 01:27:43.794253 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:27:43.794884 bl2_stage_init 0x01
791 01:27:43.795359 bl2_stage_init 0x81
792 01:27:43.799857 hw id: 0x0000 - pwm id 0x01
793 01:27:43.800418 bl2_stage_init 0xc1
794 01:27:43.800881 bl2_stage_init 0x02
795 01:27:43.801334
796 01:27:43.805346 L0:00000000
797 01:27:43.805855 L1:20000703
798 01:27:43.806309 L2:00008067
799 01:27:43.806752 L3:14000000
800 01:27:43.810836 B2:00402000
801 01:27:43.811338 B1:e0f83180
802 01:27:43.811787
803 01:27:43.812283 TE: 58159
804 01:27:43.812729
805 01:27:43.816512 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:27:43.817019
807 01:27:43.817468 Board ID = 1
808 01:27:43.822099 Set A53 clk to 24M
809 01:27:43.822600 Set A73 clk to 24M
810 01:27:43.823051 Set clk81 to 24M
811 01:27:43.827749 A53 clk: 1200 MHz
812 01:27:43.828281 A73 clk: 1200 MHz
813 01:27:43.828738 CLK81: 166.6M
814 01:27:43.829198 smccc: 00012ab5
815 01:27:43.833246 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:27:43.838907 board id: 1
817 01:27:43.844963 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:27:43.855396 fw parse done
819 01:27:43.861396 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:27:43.904115 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:27:43.914860 PIEI prepare done
822 01:27:43.915371 fastboot data load
823 01:27:43.916057 fastboot data verify
824 01:27:43.920605 verify result: 266
825 01:27:43.926184 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:27:43.926714 LPDDR4 probe
827 01:27:43.927171 ddr clk to 1584MHz
828 01:27:43.934192 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:27:43.971432
830 01:27:43.971948 dmc_version 0001
831 01:27:43.978134 Check phy result
832 01:27:43.984021 INFO : End of CA training
833 01:27:43.984531 INFO : End of initialization
834 01:27:43.989552 INFO : Training has run successfully!
835 01:27:43.990061 Check phy result
836 01:27:43.995170 INFO : End of initialization
837 01:27:43.995670 INFO : End of read enable training
838 01:27:43.998463 INFO : End of fine write leveling
839 01:27:44.004051 INFO : End of Write leveling coarse delay
840 01:27:44.010632 INFO : Training has run successfully!
841 01:27:44.011148 Check phy result
842 01:27:44.013551 INFO : End of initialization
843 01:27:44.014054 INFO : End of read dq deskew training
844 01:27:44.019226 INFO : End of MPR read delay center optimization
845 01:27:44.024671 INFO : End of write delay center optimization
846 01:27:44.025172 INFO : End of read delay center optimization
847 01:27:44.030274 INFO : End of max read latency training
848 01:27:44.036345 INFO : Training has run successfully!
849 01:27:44.036869 1D training succeed
850 01:27:44.043628 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:27:44.092548 Check phy result
852 01:27:44.093071 INFO : End of initialization
853 01:27:44.113765 INFO : End of 2D read delay Voltage center optimization
854 01:27:44.132921 INFO : End of 2D read delay Voltage center optimization
855 01:27:44.184896 INFO : End of 2D write delay Voltage center optimization
856 01:27:44.234053 INFO : End of 2D write delay Voltage center optimization
857 01:27:44.239641 INFO : Training has run successfully!
858 01:27:44.240182
859 01:27:44.240643 channel==0
860 01:27:44.245257 RxClkDly_Margin_A0==88 ps 9
861 01:27:44.245769 TxDqDly_Margin_A0==98 ps 10
862 01:27:44.250970 RxClkDly_Margin_A1==88 ps 9
863 01:27:44.251485 TxDqDly_Margin_A1==98 ps 10
864 01:27:44.251958 TrainedVREFDQ_A0==74
865 01:27:44.256471 TrainedVREFDQ_A1==75
866 01:27:44.257010 VrefDac_Margin_A0==25
867 01:27:44.257467 DeviceVref_Margin_A0==40
868 01:27:44.262010 VrefDac_Margin_A1==25
869 01:27:44.262521 DeviceVref_Margin_A1==39
870 01:27:44.262954
871 01:27:44.263379
872 01:27:44.267643 channel==1
873 01:27:44.268173 RxClkDly_Margin_A0==98 ps 10
874 01:27:44.268613 TxDqDly_Margin_A0==98 ps 10
875 01:27:44.273282 RxClkDly_Margin_A1==98 ps 10
876 01:27:44.273791 TxDqDly_Margin_A1==98 ps 10
877 01:27:44.278871 TrainedVREFDQ_A0==77
878 01:27:44.279366 TrainedVREFDQ_A1==77
879 01:27:44.279802 VrefDac_Margin_A0==22
880 01:27:44.284352 DeviceVref_Margin_A0==37
881 01:27:44.284846 VrefDac_Margin_A1==22
882 01:27:44.289963 DeviceVref_Margin_A1==37
883 01:27:44.290454
884 01:27:44.290883 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:27:44.295555
886 01:27:44.323567 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 01:27:44.324143 2D training succeed
888 01:27:44.329148 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:27:44.334738 auto size-- 65535DDR cs0 size: 2048MB
890 01:27:44.335230 DDR cs1 size: 2048MB
891 01:27:44.340355 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:27:44.340851 cs0 DataBus test pass
893 01:27:44.345909 cs1 DataBus test pass
894 01:27:44.346399 cs0 AddrBus test pass
895 01:27:44.346833 cs1 AddrBus test pass
896 01:27:44.347260
897 01:27:44.351515 100bdlr_step_size ps== 420
898 01:27:44.352043 result report
899 01:27:44.357170 boot times 0Enable ddr reg access
900 01:27:44.362649 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:27:44.376111 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:27:44.948292 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:27:44.948894 MVN_1=0x00000000
904 01:27:44.953861 MVN_2=0x00000000
905 01:27:44.959586 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:27:44.960141 OPS=0x10
907 01:27:44.960610 ring efuse init
908 01:27:44.961058 chipver efuse init
909 01:27:44.965097 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:27:44.970677 [0.018960 Inits done]
911 01:27:44.971177 secure task start!
912 01:27:44.971630 high task start!
913 01:27:44.975289 low task start!
914 01:27:44.975793 run into bl31
915 01:27:44.981992 NOTICE: BL31: v1.3(release):4fc40b1
916 01:27:44.989837 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:27:44.990349 NOTICE: BL31: G12A normal boot!
918 01:27:45.015134 NOTICE: BL31: BL33 decompress pass
919 01:27:45.020822 ERROR: Error initializing runtime service opteed_fast
920 01:27:46.253762
921 01:27:46.254419
922 01:27:46.262153 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:27:46.262672
924 01:27:46.263134 Model: Libre Computer AML-A311D-CC Alta
925 01:27:46.470534 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:27:46.493944 DRAM: 2 GiB (effective 3.8 GiB)
927 01:27:46.636881 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:27:46.642799 WDT: Not starting watchdog@f0d0
929 01:27:46.675015 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:27:46.687526 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:27:46.692428 ** Bad device specification mmc 0 **
932 01:27:46.702684 Card did not respond to voltage select! : -110
933 01:27:46.710470 ** Bad device specification mmc 0 **
934 01:27:46.710966 Couldn't find partition mmc 0
935 01:27:46.718765 Card did not respond to voltage select! : -110
936 01:27:46.724275 ** Bad device specification mmc 0 **
937 01:27:46.724779 Couldn't find partition mmc 0
938 01:27:46.729317 Error: could not access storage.
939 01:27:47.071939 Net: eth0: ethernet@ff3f0000
940 01:27:47.072557 starting USB...
941 01:27:47.323722 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:27:47.324322 Starting the controller
943 01:27:47.330621 USB XHCI 1.10
944 01:27:49.193998 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 01:27:49.194632 bl2_stage_init 0x01
946 01:27:49.195097 bl2_stage_init 0x81
947 01:27:49.199652 hw id: 0x0000 - pwm id 0x01
948 01:27:49.200240 bl2_stage_init 0xc1
949 01:27:49.200703 bl2_stage_init 0x02
950 01:27:49.201155
951 01:27:49.205131 L0:00000000
952 01:27:49.205651 L1:20000703
953 01:27:49.206104 L2:00008067
954 01:27:49.206547 L3:14000000
955 01:27:49.210659 B2:00402000
956 01:27:49.211175 B1:e0f83180
957 01:27:49.211621
958 01:27:49.212105 TE: 58124
959 01:27:49.212558
960 01:27:49.216326 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 01:27:49.216836
962 01:27:49.217291 Board ID = 1
963 01:27:49.221953 Set A53 clk to 24M
964 01:27:49.222450 Set A73 clk to 24M
965 01:27:49.222898 Set clk81 to 24M
966 01:27:49.227499 A53 clk: 1200 MHz
967 01:27:49.228027 A73 clk: 1200 MHz
968 01:27:49.228482 CLK81: 166.6M
969 01:27:49.228924 smccc: 00012a92
970 01:27:49.233817 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 01:27:49.238662 board id: 1
972 01:27:49.244468 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 01:27:49.255871 fw parse done
974 01:27:49.261198 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 01:27:49.303726 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 01:27:49.314666 PIEI prepare done
977 01:27:49.315160 fastboot data load
978 01:27:49.315594 fastboot data verify
979 01:27:49.320316 verify result: 266
980 01:27:49.325886 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 01:27:49.326379 LPDDR4 probe
982 01:27:49.326811 ddr clk to 1584MHz
983 01:27:49.333946 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 01:27:49.371079
985 01:27:49.371575 dmc_version 0001
986 01:27:49.377776 Check phy result
987 01:27:49.383639 INFO : End of CA training
988 01:27:49.384157 INFO : End of initialization
989 01:27:49.389220 INFO : Training has run successfully!
990 01:27:49.389722 Check phy result
991 01:27:49.394919 INFO : End of initialization
992 01:27:49.395429 INFO : End of read enable training
993 01:27:49.400402 INFO : End of fine write leveling
994 01:27:49.406072 INFO : End of Write leveling coarse delay
995 01:27:49.406572 INFO : Training has run successfully!
996 01:27:49.407018 Check phy result
997 01:27:49.411691 INFO : End of initialization
998 01:27:49.412229 INFO : End of read dq deskew training
999 01:27:49.417201 INFO : End of MPR read delay center optimization
1000 01:27:49.422910 INFO : End of write delay center optimization
1001 01:27:49.428399 INFO : End of read delay center optimization
1002 01:27:49.428897 INFO : End of max read latency training
1003 01:27:49.434033 INFO : Training has run successfully!
1004 01:27:49.434528 1D training succeed
1005 01:27:49.443176 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 01:27:49.490775 Check phy result
1007 01:27:49.491271 INFO : End of initialization
1008 01:27:49.512510 INFO : End of 2D read delay Voltage center optimization
1009 01:27:49.532835 INFO : End of 2D read delay Voltage center optimization
1010 01:27:49.584873 INFO : End of 2D write delay Voltage center optimization
1011 01:27:49.634215 INFO : End of 2D write delay Voltage center optimization
1012 01:27:49.639829 INFO : Training has run successfully!
1013 01:27:49.640389
1014 01:27:49.640851 channel==0
1015 01:27:49.645435 RxClkDly_Margin_A0==88 ps 9
1016 01:27:49.645950 TxDqDly_Margin_A0==98 ps 10
1017 01:27:49.651068 RxClkDly_Margin_A1==88 ps 9
1018 01:27:49.651585 TxDqDly_Margin_A1==98 ps 10
1019 01:27:49.652078 TrainedVREFDQ_A0==74
1020 01:27:49.656592 TrainedVREFDQ_A1==74
1021 01:27:49.657111 VrefDac_Margin_A0==25
1022 01:27:49.657570 DeviceVref_Margin_A0==40
1023 01:27:49.662346 VrefDac_Margin_A1==25
1024 01:27:49.662867 DeviceVref_Margin_A1==40
1025 01:27:49.663323
1026 01:27:49.663770
1027 01:27:49.667887 channel==1
1028 01:27:49.668418 RxClkDly_Margin_A0==98 ps 10
1029 01:27:49.668873 TxDqDly_Margin_A0==98 ps 10
1030 01:27:49.673491 RxClkDly_Margin_A1==88 ps 9
1031 01:27:49.673991 TxDqDly_Margin_A1==108 ps 11
1032 01:27:49.678991 TrainedVREFDQ_A0==77
1033 01:27:49.679491 TrainedVREFDQ_A1==78
1034 01:27:49.679946 VrefDac_Margin_A0==22
1035 01:27:49.684663 DeviceVref_Margin_A0==37
1036 01:27:49.685163 VrefDac_Margin_A1==24
1037 01:27:49.690268 DeviceVref_Margin_A1==36
1038 01:27:49.690783
1039 01:27:49.691239 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 01:27:49.695796
1041 01:27:49.723717 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 01:27:49.724317 2D training succeed
1043 01:27:49.729370 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 01:27:49.734908 auto size-- 65535DDR cs0 size: 2048MB
1045 01:27:49.735419 DDR cs1 size: 2048MB
1046 01:27:49.740521 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 01:27:49.741033 cs0 DataBus test pass
1048 01:27:49.746137 cs1 DataBus test pass
1049 01:27:49.746647 cs0 AddrBus test pass
1050 01:27:49.747098 cs1 AddrBus test pass
1051 01:27:49.747534
1052 01:27:49.751701 100bdlr_step_size ps== 420
1053 01:27:49.752264 result report
1054 01:27:49.757284 boot times 0Enable ddr reg access
1055 01:27:49.762950 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 01:27:49.776332 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 01:27:50.350062 0.0;M3 CHK:0;cm4_sp_mode 0
1058 01:27:50.350676 MVN_1=0x00000000
1059 01:27:50.355456 MVN_2=0x00000000
1060 01:27:50.361205 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 01:27:50.361727 OPS=0x10
1062 01:27:50.362186 ring efuse init
1063 01:27:50.362634 chipver efuse init
1064 01:27:50.366996 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 01:27:50.372501 [0.018961 Inits done]
1066 01:27:50.372995 secure task start!
1067 01:27:50.373447 high task start!
1068 01:27:50.377033 low task start!
1069 01:27:50.377526 run into bl31
1070 01:27:50.383662 NOTICE: BL31: v1.3(release):4fc40b1
1071 01:27:50.391473 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 01:27:50.392009 NOTICE: BL31: G12A normal boot!
1073 01:27:50.416977 NOTICE: BL31: BL33 decompress pass
1074 01:27:50.422538 ERROR: Error initializing runtime service opteed_fast
1075 01:27:51.655353
1076 01:27:51.656014
1077 01:27:51.662930 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 01:27:51.663456
1079 01:27:51.663919 Model: Libre Computer AML-A311D-CC Alta
1080 01:27:51.872368 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 01:27:51.895309 DRAM: 2 GiB (effective 3.8 GiB)
1082 01:27:52.038577 Core: 408 devices, 31 uclasses, devicetree: separate
1083 01:27:52.043526 WDT: Not starting watchdog@f0d0
1084 01:27:52.076742 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 01:27:52.089152 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 01:27:52.094028 ** Bad device specification mmc 0 **
1087 01:27:52.104509 Card did not respond to voltage select! : -110
1088 01:27:52.111741 ** Bad device specification mmc 0 **
1089 01:27:52.112280 Couldn't find partition mmc 0
1090 01:27:52.120500 Card did not respond to voltage select! : -110
1091 01:27:52.126062 ** Bad device specification mmc 0 **
1092 01:27:52.126567 Couldn't find partition mmc 0
1093 01:27:52.130907 Error: could not access storage.
1094 01:27:52.473192 Net: eth0: ethernet@ff3f0000
1095 01:27:52.473757 starting USB...
1096 01:27:52.725386 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 01:27:52.725945 Starting the controller
1098 01:27:52.731420 USB XHCI 1.10
1099 01:27:54.286315 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 01:27:54.293768 scanning usb for storage devices... 0 Storage Device(s) found
1102 01:27:54.345541 Hit any key to stop autoboot: 1
1103 01:27:54.346597 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 01:27:54.347247 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 01:27:54.347751 Setting prompt string to ['=>']
1106 01:27:54.348320 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 01:27:54.351210 0
1108 01:27:54.352164 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 01:27:54.352693 Sending with 10 millisecond of delay
1111 01:27:55.488231 => setenv autoload no
1112 01:27:55.499918 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 01:27:55.505374 setenv autoload no
1114 01:27:55.506230 Sending with 10 millisecond of delay
1116 01:27:57.304082 => setenv initrd_high 0xffffffff
1117 01:27:57.314965 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 01:27:57.315534 setenv initrd_high 0xffffffff
1119 01:27:57.316044 Sending with 10 millisecond of delay
1121 01:27:58.932708 => setenv fdt_high 0xffffffff
1122 01:27:58.943402 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1123 01:27:58.944156 setenv fdt_high 0xffffffff
1124 01:27:58.944714 Sending with 10 millisecond of delay
1126 01:27:59.236377 => dhcp
1127 01:27:59.247047 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 01:27:59.247706 dhcp
1129 01:27:59.248085 Speed: 1000, full duplex
1130 01:27:59.248441 BOOTP broadcast 1
1131 01:27:59.493923 BOOTP broadcast 2
1132 01:27:59.525336 DHCP client bound to address 192.168.6.33 (278 ms)
1133 01:27:59.526272 Sending with 10 millisecond of delay
1135 01:28:01.204156 => setenv serverip 192.168.6.2
1136 01:28:01.215001 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1137 01:28:01.215920 setenv serverip 192.168.6.2
1138 01:28:01.216722 Sending with 10 millisecond of delay
1140 01:28:04.941999 => tftpboot 0x01080000 795640/tftp-deploy-xuz4z133/kernel/uImage
1141 01:28:04.952865 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1142 01:28:04.953766 tftpboot 0x01080000 795640/tftp-deploy-xuz4z133/kernel/uImage
1143 01:28:04.954251 Speed: 1000, full duplex
1144 01:28:04.954693 Using ethernet@ff3f0000 device
1145 01:28:04.955802 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 01:28:04.961323 Filename '795640/tftp-deploy-xuz4z133/kernel/uImage'.
1147 01:28:04.965000 Load address: 0x1080000
1148 01:28:05.827500 Loading: *########### UDP wrong checksum 000000ff 0000b33a
1149 01:28:05.905886 # UDP wrong checksum 000000ff 00003a2d
1150 01:28:09.888903 ###################################### 43.6 MiB
1151 01:28:09.889531 8.8 MiB/s
1152 01:28:09.890003 done
1153 01:28:09.893004 Bytes transferred = 45713984 (2b98a40 hex)
1154 01:28:09.893820 Sending with 10 millisecond of delay
1156 01:28:14.580962 => tftpboot 0x08000000 795640/tftp-deploy-xuz4z133/ramdisk/ramdisk.cpio.gz.uboot
1157 01:28:14.591854 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1158 01:28:14.592882 tftpboot 0x08000000 795640/tftp-deploy-xuz4z133/ramdisk/ramdisk.cpio.gz.uboot
1159 01:28:14.593363 Speed: 1000, full duplex
1160 01:28:14.593815 Using ethernet@ff3f0000 device
1161 01:28:14.595165 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1162 01:28:14.606845 Filename '795640/tftp-deploy-xuz4z133/ramdisk/ramdisk.cpio.gz.uboot'.
1163 01:28:14.607233 Load address: 0x8000000
1164 01:28:17.416950 Loading: *################################################# UDP wrong checksum 00000005 00006e3d
1165 01:28:22.417526 T UDP wrong checksum 00000005 00006e3d
1166 01:28:32.418310 T T UDP wrong checksum 00000005 00006e3d
1167 01:28:40.165291 T UDP wrong checksum 000000ff 0000e77e
1168 01:28:40.179273 UDP wrong checksum 000000ff 00007171
1169 01:28:52.422789 T T T UDP wrong checksum 00000005 00006e3d
1170 01:28:56.500381 UDP wrong checksum 000000ff 00001652
1171 01:28:56.530230 UDP wrong checksum 000000ff 0000ae44
1172 01:29:00.200392 T UDP wrong checksum 000000ff 000094b4
1173 01:29:00.230443 UDP wrong checksum 000000ff 00002ea7
1174 01:29:12.427528 T T
1175 01:29:12.428263 Retry count exceeded; starting again
1177 01:29:12.429863 end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
1180 01:29:12.431949 end: 2.4 uboot-commands (duration 00:01:55) [common]
1182 01:29:12.433552 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1184 01:29:12.434648 end: 2 uboot-action (duration 00:01:55) [common]
1186 01:29:12.436328 Cleaning after the job
1187 01:29:12.436923 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/ramdisk
1188 01:29:12.438145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/kernel
1189 01:29:12.458591 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/dtb
1190 01:29:12.459889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/nfsrootfs
1191 01:29:12.517996 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/795640/tftp-deploy-xuz4z133/modules
1192 01:29:12.524941 start: 4.1 power-off (timeout 00:00:30) [common]
1193 01:29:12.525527 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1194 01:29:12.557079 >> OK - accepted request
1195 01:29:12.559024 Returned 0 in 0 seconds
1196 01:29:12.660315 end: 4.1 power-off (duration 00:00:00) [common]
1198 01:29:12.661296 start: 4.2 read-feedback (timeout 00:10:00) [common]
1199 01:29:12.661944 Listened to connection for namespace 'common' for up to 1s
1200 01:29:13.662865 Finalising connection for namespace 'common'
1201 01:29:13.663343 Disconnecting from shell: Finalise
1202 01:29:13.663644 =>
1203 01:29:13.764344 end: 4.2 read-feedback (duration 00:00:01) [common]
1204 01:29:13.764981 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/795640
1205 01:29:18.611337 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/795640
1206 01:29:18.612026 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.