Boot log: beaglebone-black

    1 23:01:08.494438  lava-dispatcher, installed at version: 2024.01
    2 23:01:08.495193  start: 0 validate
    3 23:01:08.495628  Start time: 2024-10-10 23:01:08.495600+00:00 (UTC)
    4 23:01:08.496148  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    5 23:01:08.496683  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
    6 23:01:08.540872  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    7 23:01:08.541425  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-205-g1d227fcc72223%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fkernel%2FzImage exists
    8 23:01:08.573700  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    9 23:01:08.574314  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-205-g1d227fcc72223%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
   10 23:01:08.612177  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   11 23:01:08.612668  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
   12 23:01:08.645554  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   13 23:01:08.646048  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-205-g1d227fcc72223%2Farm%2Fmulti_v7_defconfig%2Fclang-16%2Fmodules.tar.xz exists
   14 23:01:08.686320  validate duration: 0.19
   16 23:01:08.687873  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 23:01:08.688529  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 23:01:08.689115  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 23:01:08.690075  Not decompressing ramdisk as can be used compressed.
   20 23:01:08.690753  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
   21 23:01:08.691248  saving as /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/ramdisk/initrd.cpio.gz
   22 23:01:08.691762  total size: 4775763 (4 MB)
   23 23:01:08.734555  progress   0 % (0 MB)
   24 23:01:08.743326  progress   5 % (0 MB)
   25 23:01:08.751709  progress  10 % (0 MB)
   26 23:01:08.759737  progress  15 % (0 MB)
   27 23:01:08.764701  progress  20 % (0 MB)
   28 23:01:08.768647  progress  25 % (1 MB)
   29 23:01:08.772773  progress  30 % (1 MB)
   30 23:01:08.777275  progress  35 % (1 MB)
   31 23:01:08.781206  progress  40 % (1 MB)
   32 23:01:08.785254  progress  45 % (2 MB)
   33 23:01:08.789336  progress  50 % (2 MB)
   34 23:01:08.793825  progress  55 % (2 MB)
   35 23:01:08.797783  progress  60 % (2 MB)
   36 23:01:08.801580  progress  65 % (2 MB)
   37 23:01:08.806001  progress  70 % (3 MB)
   38 23:01:08.809996  progress  75 % (3 MB)
   39 23:01:08.814098  progress  80 % (3 MB)
   40 23:01:08.818190  progress  85 % (3 MB)
   41 23:01:08.822509  progress  90 % (4 MB)
   42 23:01:08.826267  progress  95 % (4 MB)
   43 23:01:08.829783  progress 100 % (4 MB)
   44 23:01:08.830573  4 MB downloaded in 0.14 s (32.81 MB/s)
   45 23:01:08.831217  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 23:01:08.832341  end: 1.1 download-retry (duration 00:00:00) [common]
   48 23:01:08.832711  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 23:01:08.833043  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 23:01:08.833610  downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-205-g1d227fcc72223/arm/multi_v7_defconfig/clang-16/kernel/zImage
   51 23:01:08.833924  saving as /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/kernel/zImage
   52 23:01:08.834179  total size: 12038656 (11 MB)
   53 23:01:08.834434  No compression specified
   54 23:01:08.871305  progress   0 % (0 MB)
   55 23:01:08.880504  progress   5 % (0 MB)
   56 23:01:08.889638  progress  10 % (1 MB)
   57 23:01:08.899233  progress  15 % (1 MB)
   58 23:01:08.908280  progress  20 % (2 MB)
   59 23:01:08.917595  progress  25 % (2 MB)
   60 23:01:08.927106  progress  30 % (3 MB)
   61 23:01:08.936144  progress  35 % (4 MB)
   62 23:01:08.945259  progress  40 % (4 MB)
   63 23:01:08.954824  progress  45 % (5 MB)
   64 23:01:08.963909  progress  50 % (5 MB)
   65 23:01:08.973623  progress  55 % (6 MB)
   66 23:01:08.982752  progress  60 % (6 MB)
   67 23:01:08.991851  progress  65 % (7 MB)
   68 23:01:09.001465  progress  70 % (8 MB)
   69 23:01:09.010474  progress  75 % (8 MB)
   70 23:01:09.019796  progress  80 % (9 MB)
   71 23:01:09.029381  progress  85 % (9 MB)
   72 23:01:09.038514  progress  90 % (10 MB)
   73 23:01:09.048055  progress  95 % (10 MB)
   74 23:01:09.057306  progress 100 % (11 MB)
   75 23:01:09.058341  11 MB downloaded in 0.22 s (51.22 MB/s)
   76 23:01:09.059241  end: 1.2.1 http-download (duration 00:00:00) [common]
   78 23:01:09.060546  end: 1.2 download-retry (duration 00:00:00) [common]
   79 23:01:09.060830  start: 1.3 download-retry (timeout 00:10:00) [common]
   80 23:01:09.061108  start: 1.3.1 http-download (timeout 00:10:00) [common]
   81 23:01:09.061570  downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-205-g1d227fcc72223/arm/multi_v7_defconfig/clang-16/dtbs/ti/omap/am335x-boneblack.dtb
   82 23:01:09.061848  saving as /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/dtb/am335x-boneblack.dtb
   83 23:01:09.062057  total size: 70568 (0 MB)
   84 23:01:09.062267  No compression specified
   85 23:01:09.096521  progress  46 % (0 MB)
   86 23:01:09.097360  progress  92 % (0 MB)
   87 23:01:09.098031  progress 100 % (0 MB)
   88 23:01:09.098427  0 MB downloaded in 0.04 s (1.85 MB/s)
   89 23:01:09.098892  end: 1.3.1 http-download (duration 00:00:00) [common]
   91 23:01:09.099707  end: 1.3 download-retry (duration 00:00:00) [common]
   92 23:01:09.099971  start: 1.4 download-retry (timeout 00:10:00) [common]
   93 23:01:09.100265  start: 1.4.1 http-download (timeout 00:10:00) [common]
   94 23:01:09.100717  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
   95 23:01:09.100976  saving as /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/nfsrootfs/full.rootfs.tar
   96 23:01:09.101184  total size: 117747780 (112 MB)
   97 23:01:09.101395  Using unxz to decompress xz
   98 23:01:09.136516  progress   0 % (0 MB)
   99 23:01:09.939906  progress   5 % (5 MB)
  100 23:01:10.671762  progress  10 % (11 MB)
  101 23:01:11.439628  progress  15 % (16 MB)
  102 23:01:12.155087  progress  20 % (22 MB)
  103 23:01:12.729582  progress  25 % (28 MB)
  104 23:01:13.531730  progress  30 % (33 MB)
  105 23:01:14.335123  progress  35 % (39 MB)
  106 23:01:14.665031  progress  40 % (44 MB)
  107 23:01:15.035328  progress  45 % (50 MB)
  108 23:01:15.683607  progress  50 % (56 MB)
  109 23:01:16.490471  progress  55 % (61 MB)
  110 23:01:17.216740  progress  60 % (67 MB)
  111 23:01:17.931383  progress  65 % (73 MB)
  112 23:01:18.693418  progress  70 % (78 MB)
  113 23:01:19.469760  progress  75 % (84 MB)
  114 23:01:20.216995  progress  80 % (89 MB)
  115 23:01:21.005772  progress  85 % (95 MB)
  116 23:01:21.868136  progress  90 % (101 MB)
  117 23:01:22.617642  progress  95 % (106 MB)
  118 23:01:23.423615  progress 100 % (112 MB)
  119 23:01:23.435976  112 MB downloaded in 14.33 s (7.83 MB/s)
  120 23:01:23.437228  end: 1.4.1 http-download (duration 00:00:14) [common]
  122 23:01:23.439406  end: 1.4 download-retry (duration 00:00:14) [common]
  123 23:01:23.440250  start: 1.5 download-retry (timeout 00:09:45) [common]
  124 23:01:23.441052  start: 1.5.1 http-download (timeout 00:09:45) [common]
  125 23:01:23.442174  downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-205-g1d227fcc72223/arm/multi_v7_defconfig/clang-16/modules.tar.xz
  126 23:01:23.442810  saving as /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/modules/modules.tar
  127 23:01:23.443409  total size: 6913216 (6 MB)
  128 23:01:23.444044  Using unxz to decompress xz
  129 23:01:23.490321  progress   0 % (0 MB)
  130 23:01:23.524182  progress   5 % (0 MB)
  131 23:01:23.578488  progress  10 % (0 MB)
  132 23:01:23.629141  progress  15 % (1 MB)
  133 23:01:23.682288  progress  20 % (1 MB)
  134 23:01:23.736117  progress  25 % (1 MB)
  135 23:01:23.791126  progress  30 % (2 MB)
  136 23:01:23.839871  progress  35 % (2 MB)
  137 23:01:23.893148  progress  40 % (2 MB)
  138 23:01:23.941838  progress  45 % (2 MB)
  139 23:01:23.993940  progress  50 % (3 MB)
  140 23:01:24.046288  progress  55 % (3 MB)
  141 23:01:24.093733  progress  60 % (3 MB)
  142 23:01:24.148603  progress  65 % (4 MB)
  143 23:01:24.194164  progress  70 % (4 MB)
  144 23:01:24.252211  progress  75 % (4 MB)
  145 23:01:24.300211  progress  80 % (5 MB)
  146 23:01:24.353320  progress  85 % (5 MB)
  147 23:01:24.401340  progress  90 % (5 MB)
  148 23:01:24.453865  progress  95 % (6 MB)
  149 23:01:24.501470  progress 100 % (6 MB)
  150 23:01:24.517778  6 MB downloaded in 1.07 s (6.14 MB/s)
  151 23:01:24.518965  end: 1.5.1 http-download (duration 00:00:01) [common]
  153 23:01:24.521217  end: 1.5 download-retry (duration 00:00:01) [common]
  154 23:01:24.521957  start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
  155 23:01:24.522680  start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
  156 23:01:40.566933  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1
  157 23:01:40.567551  end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
  158 23:01:40.567874  start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
  159 23:01:40.568558  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71
  160 23:01:40.569047  makedir: /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin
  161 23:01:40.569451  makedir: /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/tests
  162 23:01:40.569840  makedir: /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/results
  163 23:01:40.570214  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-add-keys
  164 23:01:40.570751  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-add-sources
  165 23:01:40.571253  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-background-process-start
  166 23:01:40.571764  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-background-process-stop
  167 23:01:40.572327  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-common-functions
  168 23:01:40.572821  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-echo-ipv4
  169 23:01:40.573301  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-install-packages
  170 23:01:40.573768  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-installed-packages
  171 23:01:40.574233  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-os-build
  172 23:01:40.574702  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-probe-channel
  173 23:01:40.575171  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-probe-ip
  174 23:01:40.575657  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-target-ip
  175 23:01:40.576161  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-target-mac
  176 23:01:40.576641  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-target-storage
  177 23:01:40.577123  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-test-case
  178 23:01:40.577688  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-test-event
  179 23:01:40.578170  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-test-feedback
  180 23:01:40.578637  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-test-raise
  181 23:01:40.579101  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-test-reference
  182 23:01:40.579592  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-test-runner
  183 23:01:40.580103  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-test-set
  184 23:01:40.580583  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-test-shell
  185 23:01:40.581064  Updating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-add-keys (debian)
  186 23:01:40.581585  Updating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-add-sources (debian)
  187 23:01:40.582082  Updating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-install-packages (debian)
  188 23:01:40.582588  Updating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-installed-packages (debian)
  189 23:01:40.583082  Updating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/bin/lava-os-build (debian)
  190 23:01:40.583510  Creating /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/environment
  191 23:01:40.583874  LAVA metadata
  192 23:01:40.584151  - LAVA_JOB_ID=837393
  193 23:01:40.584365  - LAVA_DISPATCHER_IP=192.168.6.2
  194 23:01:40.584718  start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
  195 23:01:40.585661  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  196 23:01:40.585969  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
  197 23:01:40.586174  skipped lava-vland-overlay
  198 23:01:40.586412  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  199 23:01:40.586664  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
  200 23:01:40.586879  skipped lava-multinode-overlay
  201 23:01:40.587119  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  202 23:01:40.587368  start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
  203 23:01:40.587611  Loading test definitions
  204 23:01:40.587881  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
  205 23:01:40.588118  Using /lava-837393 at stage 0
  206 23:01:40.589189  uuid=837393_1.6.2.4.1 testdef=None
  207 23:01:40.589490  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  208 23:01:40.589749  start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
  209 23:01:40.591274  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  211 23:01:40.592073  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
  212 23:01:40.594003  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  214 23:01:40.594817  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
  215 23:01:40.596691  runner path: /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/0/tests/0_timesync-off test_uuid 837393_1.6.2.4.1
  216 23:01:40.597230  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  218 23:01:40.598036  start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
  219 23:01:40.598256  Using /lava-837393 at stage 0
  220 23:01:40.598599  Fetching tests from https://github.com/kernelci/test-definitions.git
  221 23:01:40.598886  Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/0/tests/1_kselftest-dt'
  222 23:01:44.048728  Running '/usr/bin/git checkout kernelci.org
  223 23:01:44.119572  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
  224 23:01:44.121967  uuid=837393_1.6.2.4.5 testdef=None
  225 23:01:44.122581  end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
  227 23:01:44.124075  start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
  228 23:01:44.129430  end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
  230 23:01:44.131014  start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
  231 23:01:44.138177  end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
  233 23:01:44.139835  start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
  234 23:01:44.146787  runner path: /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/0/tests/1_kselftest-dt test_uuid 837393_1.6.2.4.5
  235 23:01:44.147300  BOARD='beaglebone-black'
  236 23:01:44.147714  BRANCH='mainline'
  237 23:01:44.148141  SKIPFILE='/dev/null'
  238 23:01:44.148544  SKIP_INSTALL='True'
  239 23:01:44.148935  TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc2-205-g1d227fcc72223/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz'
  240 23:01:44.149337  TST_CASENAME=''
  241 23:01:44.149731  TST_CMDFILES='dt'
  242 23:01:44.150700  end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
  244 23:01:44.152264  Creating lava-test-runner.conf files
  245 23:01:44.152675  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/837393/lava-overlay-j7i7wr71/lava-837393/0 for stage 0
  246 23:01:44.153353  - 0_timesync-off
  247 23:01:44.153819  - 1_kselftest-dt
  248 23:01:44.154453  end: 1.6.2.4 test-definition (duration 00:00:04) [common]
  249 23:01:44.155000  start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
  250 23:02:08.404887  end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
  251 23:02:08.405316  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
  252 23:02:08.405580  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  253 23:02:08.405849  end: 1.6.2 lava-overlay (duration 00:00:28) [common]
  254 23:02:08.406114  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
  255 23:02:08.764425  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  256 23:02:08.764884  start: 1.6.4 extract-modules (timeout 00:09:00) [common]
  257 23:02:08.765134  extracting modules file /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1
  258 23:02:09.645602  extracting modules file /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/837393/extract-overlay-ramdisk-b8qgr5rw/ramdisk
  259 23:02:10.549244  end: 1.6.4 extract-modules (duration 00:00:02) [common]
  260 23:02:10.549704  start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
  261 23:02:10.549987  [common] Applying overlay to NFS
  262 23:02:10.550203  [common] Applying overlay /var/lib/lava/dispatcher/tmp/837393/compress-overlay-ocmlvx5y/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1
  263 23:02:13.356087  end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
  264 23:02:13.356556  start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
  265 23:02:13.356833  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
  266 23:02:13.357113  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  267 23:02:13.357364  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  268 23:02:13.357626  start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
  269 23:02:13.357877  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  270 23:02:13.358134  start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
  271 23:02:13.358385  Building ramdisk /var/lib/lava/dispatcher/tmp/837393/extract-overlay-ramdisk-b8qgr5rw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/837393/extract-overlay-ramdisk-b8qgr5rw/ramdisk
  272 23:02:14.489843  >> 78968 blocks

  273 23:02:19.526650  Adding RAMdisk u-boot header.
  274 23:02:19.527360  mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/837393/extract-overlay-ramdisk-b8qgr5rw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/837393/extract-overlay-ramdisk-b8qgr5rw/ramdisk.cpio.gz.uboot
  275 23:02:19.699839  output: Image Name:   
  276 23:02:19.700535  output: Created:      Thu Oct 10 23:02:19 2024
  277 23:02:19.701029  output: Image Type:   ARM Linux RAMDisk Image (uncompressed)
  278 23:02:19.701493  output: Data Size:    15341159 Bytes = 14981.60 KiB = 14.63 MiB
  279 23:02:19.701947  output: Load Address: 00000000
  280 23:02:19.702391  output: Entry Point:  00000000
  281 23:02:19.702832  output: 
  282 23:02:19.704143  rename /var/lib/lava/dispatcher/tmp/837393/extract-overlay-ramdisk-b8qgr5rw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/ramdisk/ramdisk.cpio.gz.uboot
  283 23:02:19.704930  end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
  284 23:02:19.705542  end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
  285 23:02:19.706135  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
  286 23:02:19.706642  No LXC device requested
  287 23:02:19.707201  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  288 23:02:19.707770  start: 1.8 deploy-device-env (timeout 00:08:49) [common]
  289 23:02:19.708359  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  290 23:02:19.708823  Checking files for TFTP limit of 4294967296 bytes.
  291 23:02:19.711709  end: 1 tftp-deploy (duration 00:01:11) [common]
  292 23:02:19.712380  start: 2 uboot-action (timeout 00:05:00) [common]
  293 23:02:19.712976  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  294 23:02:19.713534  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  295 23:02:19.714098  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  296 23:02:19.714923  substitutions:
  297 23:02:19.715394  - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
  298 23:02:19.715850  - {DTB_ADDR}: 0x88000000
  299 23:02:19.716332  - {DTB}: 837393/tftp-deploy-ldrfha3p/dtb/am335x-boneblack.dtb
  300 23:02:19.716780  - {INITRD}: 837393/tftp-deploy-ldrfha3p/ramdisk/ramdisk.cpio.gz.uboot
  301 23:02:19.717223  - {KERNEL_ADDR}: 0x82000000
  302 23:02:19.717662  - {KERNEL}: 837393/tftp-deploy-ldrfha3p/kernel/zImage
  303 23:02:19.718100  - {LAVA_MAC}: None
  304 23:02:19.718587  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1
  305 23:02:19.719033  - {NFS_SERVER_IP}: 192.168.6.2
  306 23:02:19.719474  - {PRESEED_CONFIG}: None
  307 23:02:19.719909  - {PRESEED_LOCAL}: None
  308 23:02:19.720377  - {RAMDISK_ADDR}: 0x83000000
  309 23:02:19.720816  - {RAMDISK}: 837393/tftp-deploy-ldrfha3p/ramdisk/ramdisk.cpio.gz.uboot
  310 23:02:19.721254  - {ROOT_PART}: None
  311 23:02:19.721689  - {ROOT}: None
  312 23:02:19.722122  - {SERVER_IP}: 192.168.6.2
  313 23:02:19.722553  - {TEE_ADDR}: 0x83000000
  314 23:02:19.722981  - {TEE}: None
  315 23:02:19.723412  Parsed boot commands:
  316 23:02:19.723834  - setenv autoload no
  317 23:02:19.724296  - setenv initrd_high 0xffffffff
  318 23:02:19.724735  - setenv fdt_high 0xffffffff
  319 23:02:19.725162  - dhcp
  320 23:02:19.725586  - setenv serverip 192.168.6.2
  321 23:02:19.726015  - tftp 0x82000000 837393/tftp-deploy-ldrfha3p/kernel/zImage
  322 23:02:19.726444  - tftp 0x83000000 837393/tftp-deploy-ldrfha3p/ramdisk/ramdisk.cpio.gz.uboot
  323 23:02:19.726877  - setenv initrd_size ${filesize}
  324 23:02:19.727306  - tftp 0x88000000 837393/tftp-deploy-ldrfha3p/dtb/am335x-boneblack.dtb
  325 23:02:19.727734  - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  326 23:02:19.728211  - bootz 0x82000000 0x83000000 0x88000000
  327 23:02:19.728762  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  329 23:02:19.730410  start: 2.3 connect-device (timeout 00:05:00) [common]
  330 23:02:19.730877  [common] connect-device Connecting to device using 'telnet conserv1 3003'
  331 23:02:19.747910  Setting prompt string to ['lava-test: # ']
  332 23:02:19.749562  end: 2.3 connect-device (duration 00:00:00) [common]
  333 23:02:19.750240  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  334 23:02:19.750874  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  335 23:02:19.751483  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  336 23:02:19.752840  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
  337 23:02:19.787187  >> OK - accepted request

  338 23:02:19.789457  Returned 0 in 0 seconds
  339 23:02:19.890616  end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
  341 23:02:19.892431  end: 2.4.1 reset-device (duration 00:00:00) [common]
  342 23:02:19.893077  start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
  343 23:02:19.893651  Setting prompt string to ['Hit any key to stop autoboot']
  344 23:02:19.894159  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  345 23:02:19.895875  Trying 192.168.56.21...
  346 23:02:19.896470  Connected to conserv1.
  347 23:02:19.896935  Escape character is '^]'.
  348 23:02:19.897395  
  349 23:02:19.897872  ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
  350 23:02:19.898345  
  351 23:02:27.869744  
  352 23:02:27.870386  U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
  353 23:02:27.874561  Trying to boot from MMC1
  354 23:02:28.449119  
  355 23:02:28.449813  
  356 23:02:28.450293  U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
  357 23:02:28.450759  
  358 23:02:28.454550  CPU  : AM335X-GP rev 2.1
  359 23:02:28.455071  Model: TI AM335x BeagleBone Black
  360 23:02:28.457824  DRAM:  512 MiB
  361 23:02:28.541248  Core:  160 devices, 18 uclasses, devicetree: separate
  362 23:02:28.551517  WDT:   Started wdt@44e35000 with servicing (60s timeout)
  363 23:02:31.920933  7[r[999;999H[6n8NAND:  
  364 23:02:31.921795  U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
  365 23:02:31.925133  Trying to boot from MMC1
  366 23:02:32.498601  
  367 23:02:32.499363  
  368 23:02:32.499928  U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
  369 23:02:32.500632  
  370 23:02:32.503893  CPU  : AM335X-GP rev 2.1
  371 23:02:32.504534  Model: TI AM335x BeagleBone Black
  372 23:02:32.507110  DRAM:  512 MiB
  373 23:02:32.589848  Core:  160 devices, 18 uclasses, devicetree: separate
  374 23:02:32.600306  WDT:   Started wdt@44e35000 with servicing (60s timeout)
  375 23:02:34.619390  7[r[999;999H[6n8NAND:  
  376 23:02:34.619815  U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
  377 23:02:34.625047  Trying to boot from MMC1
  378 23:02:35.196818  
  379 23:02:35.197513  
  380 23:02:35.197853  U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
  381 23:02:35.198163  
  382 23:02:35.202297  CPU  : AM335X-GP rev 2.1
  383 23:02:35.202593  Model: TI AM335x BeagleBone Black
  384 23:02:35.206438  DRAM:  512 MiB
  385 23:02:35.288253  Core:  160 devices, 18 uclasses, devicetree: separate
  386 23:02:35.299189  WDT:   Started wdt@44e35000 with servicing (60s timeout)
  387 23:02:35.803562  7[r[999;999H[6n8NAND:  0 MiB
  388 23:02:35.814389  MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
  389 23:02:35.886064  Loading Environment from FAT... Unable to use mmc 0:1...
  390 23:02:35.907962  <ethaddr> not set. Validating first E-fuse MAC
  391 23:02:35.938524  Net:   eth2: ethernet@4a100000, eth3: usb_ether
  393 23:02:35.996337  Hit any key to stop autoboot:  2 
  394 23:02:35.997504  end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
  395 23:02:35.998122  start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
  396 23:02:35.998604  Setting prompt string to ['=>']
  397 23:02:35.999090  bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
  398 23:02:36.006431   0 
  399 23:02:36.007311  Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
  400 23:02:36.007790  Sending with 10 millisecond of delay
  402 23:02:37.142875  => setenv autoload no
  403 23:02:37.153684  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
  404 23:02:37.158595  setenv autoload no
  405 23:02:37.159315  Sending with 10 millisecond of delay
  407 23:02:38.956766  => setenv initrd_high 0xffffffff
  408 23:02:38.967560  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
  409 23:02:38.968477  setenv initrd_high 0xffffffff
  410 23:02:38.969196  Sending with 10 millisecond of delay
  412 23:02:40.585603  => setenv fdt_high 0xffffffff
  413 23:02:40.596464  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
  414 23:02:40.597402  setenv fdt_high 0xffffffff
  415 23:02:40.598162  Sending with 10 millisecond of delay
  417 23:02:40.890202  => dhcp
  418 23:02:40.901060  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
  419 23:02:40.902057  dhcp
  420 23:02:40.903473  link up on port 0, speed 100, full duplex
  421 23:02:40.904033  BOOTP broadcast 1
  422 23:02:41.155248  BOOTP broadcast 2
  423 23:02:41.192118  DHCP client bound to address 192.168.6.30 (286 ms)
  424 23:02:41.192989  Sending with 10 millisecond of delay
  426 23:02:42.870955  => setenv serverip 192.168.6.2
  427 23:02:42.881878  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
  428 23:02:42.882815  setenv serverip 192.168.6.2
  429 23:02:42.883556  Sending with 10 millisecond of delay
  431 23:02:46.367038  => tftp 0x82000000 837393/tftp-deploy-ldrfha3p/kernel/zImage
  432 23:02:46.377842  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
  433 23:02:46.378730  tftp 0x82000000 837393/tftp-deploy-ldrfha3p/kernel/zImage
  434 23:02:46.379210  link up on port 0, speed 100, full duplex
  435 23:02:46.382348  Using ethernet@4a100000 device
  436 23:02:46.387964  TFTP from server 192.168.6.2; our IP address is 192.168.6.30
  437 23:02:46.388772  Filename '837393/tftp-deploy-ldrfha3p/kernel/zImage'.
  438 23:02:46.394630  Load address: 0x82000000
  439 23:02:49.102332  Loading: *##################################################  11.5 MiB
  440 23:02:49.102963  	 4.2 MiB/s
  441 23:02:49.103396  done
  442 23:02:49.105895  Bytes transferred = 12038656 (b7b200 hex)
  443 23:02:49.106673  Sending with 10 millisecond of delay
  445 23:02:53.554523  => tftp 0x83000000 837393/tftp-deploy-ldrfha3p/ramdisk/ramdisk.cpio.gz.uboot
  446 23:02:53.565376  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
  447 23:02:53.566283  tftp 0x83000000 837393/tftp-deploy-ldrfha3p/ramdisk/ramdisk.cpio.gz.uboot
  448 23:02:53.566797  link up on port 0, speed 100, full duplex
  449 23:02:53.570148  Using ethernet@4a100000 device
  450 23:02:53.575688  TFTP from server 192.168.6.2; our IP address is 192.168.6.30
  451 23:02:53.583499  Filename '837393/tftp-deploy-ldrfha3p/ramdisk/ramdisk.cpio.gz.uboot'.
  452 23:02:53.584038  Load address: 0x83000000
  453 23:02:56.755809  Loading: *##################################################  14.6 MiB
  454 23:02:56.756469  	 4.6 MiB/s
  455 23:02:56.756901  done
  456 23:02:56.760112  Bytes transferred = 15341223 (ea16a7 hex)
  457 23:02:56.761303  Sending with 10 millisecond of delay
  459 23:02:58.621980  => setenv initrd_size ${filesize}
  460 23:02:58.632922  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
  461 23:02:58.633488  setenv initrd_size ${filesize}
  462 23:02:58.633945  Sending with 10 millisecond of delay
  464 23:03:02.781321  => tftp 0x88000000 837393/tftp-deploy-ldrfha3p/dtb/am335x-boneblack.dtb
  465 23:03:02.791883  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
  466 23:03:02.792442  tftp 0x88000000 837393/tftp-deploy-ldrfha3p/dtb/am335x-boneblack.dtb
  467 23:03:02.792674  link up on port 0, speed 100, full duplex
  468 23:03:02.796485  Using ethernet@4a100000 device
  469 23:03:02.802120  TFTP from server 192.168.6.2; our IP address is 192.168.6.30
  470 23:03:02.810293  Filename '837393/tftp-deploy-ldrfha3p/dtb/am335x-boneblack.dtb'.
  471 23:03:02.810557  Load address: 0x88000000
  472 23:03:02.824851  Loading: *##################################################  68.9 KiB
  473 23:03:02.830544  	 3.7 MiB/s
  474 23:03:02.830808  done
  475 23:03:02.834561  Bytes transferred = 70568 (113a8 hex)
  476 23:03:02.835022  Sending with 10 millisecond of delay
  478 23:03:16.009334  => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  479 23:03:16.020153  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
  480 23:03:16.021029  setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  481 23:03:16.021733  Sending with 10 millisecond of delay
  483 23:03:18.359876  => bootz 0x82000000 0x83000000 0x88000000
  484 23:03:18.370714  Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
  485 23:03:18.371277  bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
  486 23:03:18.372296  bootz 0x82000000 0x83000000 0x88000000
  487 23:03:18.372928  Kernel image @ 0x82000000 [ 0x000000 - 0xb7b200 ]
  488 23:03:18.373456  ## Loading init Ramdisk from Legacy Image at 83000000 ...
  489 23:03:18.378488     Image Name:   
  490 23:03:18.379120     Created:      2024-10-10  23:02:19 UTC
  491 23:03:18.384064     Image Type:   ARM Linux RAMDisk Image (uncompressed)
  492 23:03:18.389606     Data Size:    15341159 Bytes = 14.6 MiB
  493 23:03:18.390215     Load Address: 00000000
  494 23:03:18.395847     Entry Point:  00000000
  495 23:03:18.570301     Verifying Checksum ... OK
  496 23:03:18.571071  ## Flattened Device Tree blob at 88000000
  497 23:03:18.576732     Booting using the fdt blob at 0x88000000
  498 23:03:18.581721     Using Device Tree in place at 88000000, end 880143a7
  499 23:03:18.595385  
  500 23:03:18.596201  Starting kernel ...
  501 23:03:18.596881  
  502 23:03:18.598023  end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
  503 23:03:18.598937  start: 2.4.4 auto-login-action (timeout 00:04:01) [common]
  504 23:03:18.599668  Setting prompt string to ['Linux version [0-9]']
  505 23:03:18.600390  Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
  506 23:03:18.601066  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
  507 23:03:19.495110  [    0.000000] Booting Linux on physical CPU 0x0
  508 23:03:19.501098  start: 2.4.4.1 login-action (timeout 00:04:00) [common]
  509 23:03:19.501497  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
  510 23:03:19.501812  Setting prompt string to []
  511 23:03:19.502123  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
  512 23:03:19.502413  Using line separator: #'\n'#
  513 23:03:19.502665  No login prompt set.
  514 23:03:19.502933  Parsing kernel messages
  515 23:03:19.503179  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
  516 23:03:19.503684  [login-action] Waiting for messages, (timeout 00:04:00)
  517 23:03:19.503974  Waiting using forced prompt support (timeout 00:02:00)
  518 23:03:19.512148  [    0.000000] Linux version 6.12.0-rc2 (KernelCI@build-j341017-arm-clang-16-multi-v7-defconfig-9lr92) (Debian clang version 16.0.6 (15~deb12u1), Debian LLD 16.0.6) #1 SMP Thu Oct 10 22:15:17 UTC 2024
  519 23:03:19.523552  [    0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
  520 23:03:19.529294  [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  521 23:03:19.535100  [    0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
  522 23:03:19.540771  [    0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
  523 23:03:19.546483  [    0.000000] printk: legacy bootconsole [omap8250] enabled
  524 23:03:19.552213  [    0.000000] Memory policy: Data cache writeback
  525 23:03:19.559014  [    0.000000] efi: UEFI not found.
  526 23:03:19.559399  [    0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
  527 23:03:19.567746  [    0.000000] Zone ranges:
  528 23:03:19.573464  [    0.000000]   DMA      [mem 0x0000000080000000-0x000000009fdfffff]
  529 23:03:19.579222  [    0.000000]   Normal   empty
  530 23:03:19.579567  [    0.000000]   HighMem  empty
  531 23:03:19.584921  [    0.000000] Movable zone start for each node
  532 23:03:19.585236  [    0.000000] Early memory node ranges
  533 23:03:19.596440  [    0.000000]   node   0: [mem 0x0000000080000000-0x000000009fdfffff]
  534 23:03:19.600820  [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
  535 23:03:19.620241  [    0.000000] CPU: All CPU(s) started in SVC mode.
  536 23:03:19.625170  [    0.000000] AM335X ES2.1 (sgx neon)
  537 23:03:19.637818  [    0.000000] percpu: Embedded 17 pages/cpu s40716 r8192 d20724 u69632
  538 23:03:19.655431  [    0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
  539 23:03:19.667001  <6>[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
  540 23:03:19.672788  <6>[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
  541 23:03:19.678501  <6>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130560
  542 23:03:19.687684  <6>[    0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
  543 23:03:19.717914  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
  544 23:03:19.723926  <6>[    0.000000] trace event string verifier disabled
  545 23:03:19.724290  <6>[    0.000000] rcu: Hierarchical RCU implementation.
  546 23:03:19.732103  <6>[    0.000000] rcu: 	RCU event tracing is enabled.
  547 23:03:19.737783  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
  548 23:03:19.746354  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
  549 23:03:19.753587  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
  550 23:03:19.768414  <6>[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
  551 23:03:19.787554  <6>[    0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
  552 23:03:19.793329  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
  553 23:03:19.898095  <6>[    0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
  554 23:03:19.906592  <6>[    0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
  555 23:03:19.919104  <6>[    0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
  556 23:03:19.926665  <6>[    0.019221] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
  557 23:03:19.937150  <6>[    0.034464] Console: colour dummy device 80x30
  558 23:03:19.943145  Matched prompt #6: WARNING:
  559 23:03:19.943513  Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
  560 23:03:19.948636  <3>[    0.039363] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  561 23:03:19.954381  <3>[    0.046442] This ensures that you still see kernel messages. Please
  562 23:03:19.956659  <3>[    0.053167] update your kernel commandline.
  563 23:03:19.997840  <6>[    0.057784] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
  564 23:03:20.003613  <6>[    0.096226] CPU: Testing write buffer coherency: ok
  565 23:03:20.009552  <6>[    0.101596] CPU0: Spectre v2: using BPIALL workaround
  566 23:03:20.009887  <6>[    0.107061] pid_max: default: 32768 minimum: 301
  567 23:03:20.021073  <6>[    0.112258] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  568 23:03:20.028116  <6>[    0.120081] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
  569 23:03:20.035135  <6>[    0.129532] CPU0: thread -1, cpu 0, socket -1, mpidr 0
  570 23:03:20.042459  <6>[    0.136487] Setting up static identity map for 0x80300000 - 0x803000ac
  571 23:03:20.048957  <6>[    0.146289] rcu: Hierarchical SRCU implementation.
  572 23:03:20.056984  <6>[    0.151579] rcu: 	Max phase no-delay instances is 1000.
  573 23:03:20.066166  <6>[    0.163222] EFI services will not be available.
  574 23:03:20.072147  <6>[    0.168512] smp: Bringing up secondary CPUs ...
  575 23:03:20.077794  <6>[    0.173566] smp: Brought up 1 node, 1 CPU
  576 23:03:20.083522  <6>[    0.177963] SMP: Total of 1 processors activated (996.14 BogoMIPS).
  577 23:03:20.089437  <6>[    0.184734] CPU: All CPU(s) started in SVC mode.
  578 23:03:20.108953  <6>[    0.189935] Memory: 404440K/522240K available (17408K kernel code, 2538K rwdata, 6696K rodata, 2048K init, 432K bss, 50608K reserved, 65536K cma-reserved, 0K highmem)
  579 23:03:20.109358  <6>[    0.206250] devtmpfs: initialized
  580 23:03:20.132807  <6>[    0.223987] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
  581 23:03:20.141200  <6>[    0.232604] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
  582 23:03:20.150392  <6>[    0.243064] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
  583 23:03:20.161129  <6>[    0.255432] pinctrl core: initialized pinctrl subsystem
  584 23:03:20.170978  <6>[    0.266459] DMI not present or invalid.
  585 23:03:20.177891  <6>[    0.272361] NET: Registered PF_NETLINK/PF_ROUTE protocol family
  586 23:03:20.188765  <6>[    0.281353] DMA: preallocated 256 KiB pool for atomic coherent allocations
  587 23:03:20.203362  <6>[    0.293072] thermal_sys: Registered thermal governor 'step_wise'
  588 23:03:20.204110  <6>[    0.293269] cpuidle: using governor menu
  589 23:03:20.231769  <6>[    0.328879] No ATAGs?
  590 23:03:20.236977  <6>[    0.331615] hw-breakpoint: debug architecture 0x4 unsupported.
  591 23:03:20.247645  <6>[    0.343896] Serial: AMBA PL011 UART driver
  592 23:03:20.285306  <6>[    0.382445] iommu: Default domain type: Translated
  593 23:03:20.294416  <6>[    0.387681] iommu: DMA domain TLB invalidation policy: strict mode
  594 23:03:20.314138  <5>[    0.410879] SCSI subsystem initialized
  595 23:03:20.328432  <6>[    0.420040] usbcore: registered new interface driver usbfs
  596 23:03:20.335521  <6>[    0.426004] usbcore: registered new interface driver hub
  597 23:03:20.336030  <6>[    0.431845] usbcore: registered new device driver usb
  598 23:03:20.342747  <6>[    0.438411] pps_core: LinuxPPS API ver. 1 registered
  599 23:03:20.354286  <6>[    0.443847] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
  600 23:03:20.360635  <6>[    0.453555] PTP clock support registered
  601 23:03:20.361088  <6>[    0.458009] EDAC MC: Ver: 3.0.0
  602 23:03:20.417060  <6>[    0.511351] scmi_core: SCMI protocol bus registered
  603 23:03:20.422657  <6>[    0.519620] vgaarb: loaded
  604 23:03:20.435143  <6>[    0.532422] clocksource: Switched to clocksource dmtimer
  605 23:03:20.462791  <6>[    0.559665] NET: Registered PF_INET protocol family
  606 23:03:20.475430  <6>[    0.565392] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
  607 23:03:20.481266  <6>[    0.574413] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
  608 23:03:20.492673  <6>[    0.583347] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
  609 23:03:20.498491  <6>[    0.591593] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
  610 23:03:20.510030  <6>[    0.599879] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
  611 23:03:20.515960  <6>[    0.607596] TCP: Hash tables configured (established 4096 bind 4096)
  612 23:03:20.521694  <6>[    0.614519] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
  613 23:03:20.527603  <6>[    0.621531] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
  614 23:03:20.534203  <6>[    0.629146] NET: Registered PF_UNIX/PF_LOCAL protocol family
  615 23:03:20.629377  <6>[    0.721056] RPC: Registered named UNIX socket transport module.
  616 23:03:20.629870  <6>[    0.727501] RPC: Registered udp transport module.
  617 23:03:20.635228  <6>[    0.732634] RPC: Registered tcp transport module.
  618 23:03:20.643666  <6>[    0.737740] RPC: Registered tcp-with-tls transport module.
  619 23:03:20.649480  <6>[    0.743663] RPC: Registered tcp NFSv4.1 backchannel transport module.
  620 23:03:20.656793  <6>[    0.750571] PCI: CLS 0 bytes, default 64
  621 23:03:20.658700  <5>[    0.756471] Initialise system trusted keyrings
  622 23:03:20.682626  <6>[    0.777764] Trying to unpack rootfs image as initramfs...
  623 23:03:20.742228  <6>[    0.833292] workingset: timestamp_bits=30 max_order=17 bucket_order=0
  624 23:03:20.746167  <6>[    0.840825] squashfs: version 4.0 (2009/01/31) Phillip Lougher
  625 23:03:20.796148  <5>[    0.893250] NFS: Registering the id_resolver key type
  626 23:03:20.801927  <5>[    0.898852] Key type id_resolver registered
  627 23:03:20.807663  <5>[    0.903563] Key type id_legacy registered
  628 23:03:20.813419  <6>[    0.908013] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
  629 23:03:20.823032  <6>[    0.915214] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
  630 23:03:20.896102  <5>[    0.993339] Key type asymmetric registered
  631 23:03:20.901974  <5>[    0.997865] Asymmetric key parser 'x509' registered
  632 23:03:20.913485  <6>[    1.003413] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
  633 23:03:20.913941  <6>[    1.011306] io scheduler mq-deadline registered
  634 23:03:20.919311  <6>[    1.016301] io scheduler kyber registered
  635 23:03:20.924945  <6>[    1.020759] io scheduler bfq registered
  636 23:03:21.031658  <6>[    1.125397] ledtrig-cpu: registered to indicate activity on CPUs
  637 23:03:21.340834  <6>[    1.434466] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
  638 23:03:21.370971  <6>[    1.467923] msm_serial: driver initialized
  639 23:03:21.376892  <6>[    1.472945] SuperH (H)SCI(F) driver initialized
  640 23:03:21.382830  <6>[    1.478072] STMicroelectronics ASC driver initialized
  641 23:03:21.388070  <6>[    1.483749] STM32 USART driver initialized
  642 23:03:21.520640  <6>[    1.617381] brd: module loaded
  643 23:03:21.561243  <6>[    1.657905] loop: module loaded
  644 23:03:21.594009  <6>[    1.690390] CAN device driver interface
  645 23:03:21.600752  <6>[    1.695704] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
  646 23:03:21.606474  <6>[    1.702847] e1000e: Intel(R) PRO/1000 Network Driver
  647 23:03:21.612334  <6>[    1.708240] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
  648 23:03:21.618065  <6>[    1.714705] igb: Intel(R) Gigabit Ethernet Network Driver
  649 23:03:21.626375  <6>[    1.720528] igb: Copyright (c) 2007-2014 Intel Corporation.
  650 23:03:21.638272  <6>[    1.729851] pegasus: Pegasus/Pegasus II USB Ethernet driver
  651 23:03:21.644114  <6>[    1.736027] usbcore: registered new interface driver pegasus
  652 23:03:21.649847  <6>[    1.742157] usbcore: registered new interface driver asix
  653 23:03:21.655634  <6>[    1.748050] usbcore: registered new interface driver ax88179_178a
  654 23:03:21.661404  <6>[    1.754653] usbcore: registered new interface driver cdc_ether
  655 23:03:21.667228  <6>[    1.760951] usbcore: registered new interface driver smsc75xx
  656 23:03:21.672997  <6>[    1.767185] usbcore: registered new interface driver smsc95xx
  657 23:03:21.678753  <6>[    1.773432] usbcore: registered new interface driver net1080
  658 23:03:21.684576  <6>[    1.779553] usbcore: registered new interface driver cdc_subset
  659 23:03:21.690432  <6>[    1.785987] usbcore: registered new interface driver zaurus
  660 23:03:21.697961  <6>[    1.792035] usbcore: registered new interface driver cdc_ncm
  661 23:03:21.707869  <6>[    1.801606] usbcore: registered new interface driver usb-storage
  662 23:03:22.013647  <6>[    2.109101] i2c_dev: i2c /dev entries driver
  663 23:03:22.060065  <5>[    2.149322] cpuidle: enable-method property 'ti,am3352' found operations
  664 23:03:22.065946  <6>[    2.159056] sdhci: Secure Digital Host Controller Interface driver
  665 23:03:22.073549  <6>[    2.165842] sdhci: Copyright(c) Pierre Ossman
  666 23:03:22.080808  <6>[    2.172368] Synopsys Designware Multimedia Card Interface Driver
  667 23:03:22.086299  <6>[    2.180424] sdhci-pltfm: SDHCI platform and OF driver helper
  668 23:03:22.216181  <6>[    2.306152] usbcore: registered new interface driver usbhid
  669 23:03:22.216672  <6>[    2.312193] usbhid: USB HID core driver
  670 23:03:22.269392  <6>[    2.364094] NET: Registered PF_INET6 protocol family
  671 23:03:22.303179  <6>[    2.400511] Segment Routing with IPv6
  672 23:03:22.309001  <6>[    2.404762] In-situ OAM (IOAM) with IPv6
  673 23:03:22.315726  <6>[    2.409177] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
  674 23:03:22.321461  <6>[    2.416518] NET: Registered PF_PACKET protocol family
  675 23:03:22.327376  <6>[    2.422013] can: controller area network core
  676 23:03:22.333198  <6>[    2.426920] NET: Registered PF_CAN protocol family
  677 23:03:22.333654  <6>[    2.432125] can: raw protocol
  678 23:03:22.339062  <6>[    2.435477] can: broadcast manager protocol
  679 23:03:22.345490  <6>[    2.440058] can: netlink gateway - max_hops=1
  680 23:03:22.351548  <5>[    2.445610] Key type dns_resolver registered
  681 23:03:22.357917  <6>[    2.450606] ThumbEE CPU extension supported.
  682 23:03:22.358500  <5>[    2.455418] Registering SWP/SWPB emulation handler
  683 23:03:22.367676  <3>[    2.461082] omap_voltage_late_init: Voltage driver support not added
  684 23:03:22.577259  <5>[    2.673144] Loading compiled-in X.509 certificates
  685 23:03:22.718122  <6>[    2.802678] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
  686 23:03:22.725403  <6>[    2.819301] pinctrl-single 44e10800.pinmux: 142 pins, size 568
  687 23:03:22.751408  <3>[    2.843758] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
  688 23:03:22.956575  <3>[    3.047962] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
  689 23:03:23.157356  <6>[    3.253069] OMAP GPIO hardware version 0.1
  690 23:03:23.178537  <6>[    3.272195] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
  691 23:03:23.250738  <4>[    3.344206] at24 2-0054: supply vcc not found, using dummy regulator
  692 23:03:23.286445  <4>[    3.377469] at24 2-0055: supply vcc not found, using dummy regulator
  693 23:03:23.332880  <4>[    3.426287] at24 2-0056: supply vcc not found, using dummy regulator
  694 23:03:23.372986  <4>[    3.466461] at24 2-0057: supply vcc not found, using dummy regulator
  695 23:03:23.411652  <6>[    3.505947] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
  696 23:03:23.469675  <3>[    3.559893] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
  697 23:03:23.494713  <6>[    3.581184] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  698 23:03:23.517134  <4>[    3.607697] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  699 23:03:23.524927  <4>[    3.616934] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  700 23:03:23.623909  <6>[    3.720924] Freeing initrd memory: 14984K
  701 23:03:23.632173  <6>[    3.725714] omap_rng 48310000.rng: Random Number Generator ver. 20
  702 23:03:23.656446  <5>[    3.752745] random: crng init done
  703 23:03:23.700340  <6>[    3.792416] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
  704 23:03:23.753689  <6>[    3.844893] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
  705 23:03:23.759531  <6>[    3.855212] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
  706 23:03:23.771246  <6>[    3.862554] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
  707 23:03:23.777126  <6>[    3.870035] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
  708 23:03:23.788655  <6>[    3.878185] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
  709 23:03:23.796172  <6>[    3.889830] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
  710 23:03:23.809282  <5>[    3.898955] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
  711 23:03:23.837689  <3>[    3.929392] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
  712 23:03:23.843484  <6>[    3.937988] edma 49000000.dma: TI EDMA DMA engine driver
  713 23:03:23.918131  <3>[    4.007613] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
  714 23:03:23.931509  <6>[    4.022170] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
  715 23:03:23.944657  <3>[    4.039472] l3-aon-clkctrl:0000:0: failed to disable
  716 23:03:23.999678  <6>[    4.091224] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
  717 23:03:24.005359  <6>[    4.100756] printk: legacy console [ttyS0] enabled
  718 23:03:24.008084  <6>[    4.100756] printk: legacy console [ttyS0] enabled
  719 23:03:24.013709  <6>[    4.111089] printk: legacy bootconsole [omap8250] disabled
  720 23:03:24.022502  <6>[    4.111089] printk: legacy bootconsole [omap8250] disabled
  721 23:03:24.052685  <4>[    4.143236] tps65217-pmic: Failed to locate of_node [id: -1]
  722 23:03:24.056228  <4>[    4.150663] tps65217-bl: Failed to locate of_node [id: -1]
  723 23:03:24.073124  <6>[    4.170816] tps65217 0-0024: TPS65217 ID 0xe version 1.2
  724 23:03:24.093834  <6>[    4.177848] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
  725 23:03:24.105385  <6>[    4.191567] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
  726 23:03:24.108254  <6>[    4.203483] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
  727 23:03:24.131806  <6>[    4.223608] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
  728 23:03:24.137577  <6>[    4.232761] sdhci-omap 48060000.mmc: Got CD GPIO
  729 23:03:24.145557  <4>[    4.237905] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
  730 23:03:24.160577  <4>[    4.251731] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
  731 23:03:24.166957  <4>[    4.260433] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
  732 23:03:24.176935  <4>[    4.269132] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
  733 23:03:24.301418  <6>[    4.394353] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
  734 23:03:24.348201  <6>[    4.438885] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
  735 23:03:24.354845  <6>[    4.448237] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
  736 23:03:24.363957  <6>[    4.457283] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
  737 23:03:24.414368  <6>[    4.502079] mmc0: new high speed SDHC card at address 1234
  738 23:03:24.414985  <6>[    4.509858] mmcblk0: mmc0:1234 SA32G 29.1 GiB
  739 23:03:24.422068  <6>[    4.519081]  mmcblk0: p1
  740 23:03:24.444473  <6>[    4.533873] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
  741 23:03:24.466229  <6>[    4.554571] mmc1: new high speed MMC card at address 0001
  742 23:03:24.466817  <6>[    4.561774] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
  743 23:03:24.474374  <6>[    4.570080] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
  744 23:03:24.482081  <6>[    4.577186] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
  745 23:03:24.489814  <6>[    4.584385] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
  746 23:03:26.581839  <6>[    6.673471] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
  747 23:03:32.384982  <5>[    6.702437] Sending DHCP requests ..., OK
  748 23:03:32.396250  <6>[   12.487039] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.30
  749 23:03:32.396806  <6>[   12.495213] IP-Config: Complete:
  750 23:03:32.407274  <6>[   12.498754]      device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.30, mask=255.255.255.0, gw=192.168.6.1
  751 23:03:32.413643  <6>[   12.509282]      host=192.168.6.30, domain=, nis-domain=(none)
  752 23:03:32.425549  <6>[   12.515495]      bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
  753 23:03:32.426007  <6>[   12.515533]      nameserver0=10.255.253.1
  754 23:03:32.431648  <6>[   12.528186] clk: Disabling unused clocks
  755 23:03:32.437712  <6>[   12.532921] PM: genpd: Disabling unused power domains
  756 23:03:32.456035  <6>[   12.550420] Freeing unused kernel image (initmem) memory: 2048K
  757 23:03:32.463593  <6>[   12.560336] Run /init as init process
  758 23:03:32.489748  Loading, please wait...
  759 23:03:32.567257  Starting systemd-udevd version 252.22-1~deb12u1
  760 23:03:35.608320  <4>[   15.699157] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  761 23:03:35.752534  <4>[   15.843507] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
  762 23:03:35.909449  <6>[   16.007748] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
  763 23:03:35.920289  <6>[   16.013566] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
  764 23:03:36.146292  <6>[   16.243052] hub 1-0:1.0: USB hub found
  765 23:03:36.185559  <6>[   16.282197] hub 1-0:1.0: 1 port detected
  766 23:03:36.322174  <6>[   16.417673] tda998x 0-0070: found TDA19988
  767 23:03:39.189443  Begin: Loading essential drivers ... done.
  768 23:03:39.194915  Begin: Running /scripts/init-premount ... done.
  769 23:03:39.200612  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
  770 23:03:39.211205  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
  771 23:03:39.220513  Device /sys/class/net/eth0 found
  772 23:03:39.220825  done.
  773 23:03:39.280619  Begin: Waiting up to 180 secs for any network device to become available ... done.
  774 23:03:39.347678  IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
  775 23:03:39.397762  IP-Config: eth0 guessed broadcast address 192.168.6.255
  776 23:03:39.403297  IP-Config: eth0 complete (dhcp from 192.168.6.1):
  777 23:03:39.408892   address: 192.168.6.30     broadcast: 192.168.6.255    netmask: 255.255.255.0   
  778 23:03:39.420060   gateway: 192.168.6.1      dns0     : 10.255.253.1     dns1   : 0.0.0.0         
  779 23:03:39.420423   rootserver: 192.168.6.1 rootpath: 
  780 23:03:39.423547   filename  : 
  781 23:03:39.521202  done.
  782 23:03:39.535591  Begin: Running /scripts/nfs-bottom ... done.
  783 23:03:39.608072  Begin: Running /scripts/init-bottom ... done.
  784 23:03:41.136874  <30>[   21.230482] systemd[1]: System time before build time, advancing clock.
  785 23:03:41.329889  <30>[   21.397913] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
  786 23:03:41.340195  <30>[   21.435232] systemd[1]: Detected architecture arm.
  787 23:03:41.353842  
  788 23:03:41.354385  Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
  789 23:03:41.354859  
  790 23:03:41.376732  <30>[   21.472322] systemd[1]: Hostname set to <debian-bookworm-armhf>.
  791 23:03:43.556966  <30>[   23.650604] systemd[1]: Queued start job for default target graphical.target.
  792 23:03:43.574339  <30>[   23.665851] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
  793 23:03:43.581923  [[0;32m  OK  [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
  794 23:03:43.603564  <30>[   23.695270] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
  795 23:03:43.611786  [[0;32m  OK  [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
  796 23:03:43.634225  <30>[   23.725848] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
  797 23:03:43.642420  [[0;32m  OK  [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
  798 23:03:43.662316  <30>[   23.754469] systemd[1]: Created slice user.slice - User and Session Slice.
  799 23:03:43.668986  [[0;32m  OK  [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
  800 23:03:43.697503  <30>[   23.783886] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
  801 23:03:43.703568  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
  802 23:03:43.721402  <30>[   23.813583] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
  803 23:03:43.732429  [[0;32m  OK  [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
  804 23:03:43.762333  <30>[   23.843548] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
  805 23:03:43.768761  <30>[   23.864054] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
  806 23:03:43.777266           Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
  807 23:03:43.800475  <30>[   23.892916] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
  808 23:03:43.808701  [[0;32m  OK  [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
  809 23:03:43.831238  <30>[   23.923348] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
  810 23:03:43.839688  [[0;32m  OK  [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
  811 23:03:43.861021  <30>[   23.953402] systemd[1]: Reached target paths.target - Path Units.
  812 23:03:43.866110  [[0;32m  OK  [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
  813 23:03:43.893606  <30>[   23.984080] systemd[1]: Reached target remote-fs.target - Remote File Systems.
  814 23:03:43.900027  [[0;32m  OK  [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
  815 23:03:43.920480  <30>[   24.012968] systemd[1]: Reached target slices.target - Slice Units.
  816 23:03:43.925909  [[0;32m  OK  [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
  817 23:03:43.950742  <30>[   24.043165] systemd[1]: Reached target swap.target - Swaps.
  818 23:03:43.954782  [[0;32m  OK  [0m] Reached target [0;1;39mswap.target[0m - Swaps.
  819 23:03:43.981189  <30>[   24.073271] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
  820 23:03:43.989110  [[0;32m  OK  [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
  821 23:03:44.012119  <30>[   24.104050] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
  822 23:03:44.020329  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
  823 23:03:44.111361  <30>[   24.198644] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
  824 23:03:44.124278  <30>[   24.216262] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
  825 23:03:44.132668  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
  826 23:03:44.162824  <30>[   24.254216] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
  827 23:03:44.170110  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
  828 23:03:44.194461  <30>[   24.286272] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
  829 23:03:44.202633  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
  830 23:03:44.232332  <30>[   24.323584] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
  831 23:03:44.237907  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
  832 23:03:44.262116  <30>[   24.354106] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
  833 23:03:44.270611  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
  834 23:03:44.298235  <30>[   24.384273] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
  835 23:03:44.314848  <30>[   24.400958] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
  836 23:03:44.360887  <30>[   24.453917] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
  837 23:03:44.384746           Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
  838 23:03:44.442710  <30>[   24.535665] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
  839 23:03:44.461753           Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
  840 23:03:44.534252  <30>[   24.626219] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
  841 23:03:44.558769           Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
  842 23:03:44.611739  <30>[   24.704150] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
  843 23:03:44.631239           Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
  844 23:03:44.662248  <30>[   24.755024] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
  845 23:03:44.690736           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  846 23:03:44.730363  <30>[   24.823748] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
  847 23:03:44.742015           Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
  848 23:03:44.779747  <30>[   24.871791] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
  849 23:03:44.809703           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  850 23:03:44.860436  <30>[   24.953666] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
  851 23:03:44.878861           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  852 23:03:44.941168  <30>[   25.034438] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
  853 23:03:44.960135           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  854 23:03:44.986766  <28>[   25.074917] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
  855 23:03:44.999236  <28>[   25.091781] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
  856 23:03:45.040583  <30>[   25.134408] systemd[1]: Starting systemd-journald.service - Journal Service...
  857 23:03:45.058801           Starting [0;1;39msystemd-journald.service[0m - Journal Service...
  858 23:03:45.130689  <30>[   25.223775] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
  859 23:03:45.149638           Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
  860 23:03:45.187357  <30>[   25.280625] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
  861 23:03:45.232544           Starting [0;1;39msystemd-network-g… units from Kernel command line...
  862 23:03:45.294671  <30>[   25.386405] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
  863 23:03:45.350816           Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
  864 23:03:45.425824  <30>[   25.518378] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
  865 23:03:45.485907           Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
  866 23:03:45.570675  <30>[   25.663117] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
  867 23:03:45.578911  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
  868 23:03:45.612367  <30>[   25.705639] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
  869 23:03:45.650606  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
  870 23:03:45.675352  <30>[   25.767570] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
  871 23:03:45.714064  [[0;32m  OK  [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
  872 23:03:45.854510  <30>[   25.948115] systemd[1]: modprobe@configfs.service: Deactivated successfully.
  873 23:03:45.891481  <30>[   25.984165] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
  874 23:03:45.920573  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
  875 23:03:45.941315  <30>[   26.035284] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
  876 23:03:45.980802  <30>[   26.073919] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
  877 23:03:46.009890  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  878 23:03:46.031800  <30>[   26.124274] systemd[1]: Started systemd-journald.service - Journal Service.
  879 23:03:46.038546  [[0;32m  OK  [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
  880 23:03:46.062041  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
  881 23:03:46.086551  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  882 23:03:46.125399  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  883 23:03:46.165085  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  884 23:03:46.200589  [[0;32m  OK  [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
  885 23:03:46.224114  [[0;32m  OK  [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
  886 23:03:46.260492  [[0;32m  OK  [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
  887 23:03:46.290278  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
  888 23:03:46.350632           Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
  889 23:03:46.390536           Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
  890 23:03:46.452738           Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
  891 23:03:46.511282           Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
  892 23:03:46.563524           Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
  893 23:03:46.721529  [[0;32m  OK  [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
  894 23:03:46.869945  <46>[   26.963204] systemd-journald[163]: Received client request to flush runtime journal.
  895 23:03:46.924243  [[0;32m  OK  [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
  896 23:03:46.978524  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
  897 23:03:47.810152  [[0;32m  OK  [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
  898 23:03:47.875845           Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
  899 23:03:48.618835  [[0;32m  OK  [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
  900 23:03:48.720751  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
  901 23:03:48.742856  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
  902 23:03:48.760330  [[0;32m  OK  [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
  903 23:03:48.842228           Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
  904 23:03:48.879416           Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
  905 23:03:49.862949  [[0;32m  OK  [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
  906 23:03:49.930840           Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
  907 23:03:50.270798  [[0;32m  OK  [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
  908 23:03:50.394301           Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
  909 23:03:50.497860           Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
  910 23:03:52.422873  [[0m[0;31m*     [0m] (1 of 5) Job systemd-update-utmp.service/start running (8s / no limit)
  911 23:03:52.586726  M
[K[[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
  912 23:03:52.838863  [K<5>[   32.930424] cfg80211: Loading compiled-in X.509 certificates for regulatory database
  913 23:03:52.847197  [[0;32m  OK  [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
  914 23:03:53.952481  [[0;32m  OK  [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
  915 23:03:54.323144  <5>[   34.418719] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
  916 23:03:54.394427  <5>[   34.488590] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
  917 23:03:54.418278  <4>[   34.511544] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
  918 23:03:54.424233  <6>[   34.520734] cfg80211: failed to load regulatory.db
  919 23:03:55.511662  <46>[   35.596133] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
  920 23:03:55.532930  [[0;32m  OK  [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
  921 23:03:55.548104  <46>[   35.634704] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
  922 23:03:55.562200  [[0;32m  OK  [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
  923 23:04:04.516211  [[0;32m  OK  [0m] Reached target [0;1;39mnetwork.target[0m - Network.
  924 23:04:04.544784  [[0;32m  OK  [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
  925 23:04:04.572273  [[0;32m  OK  [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
  926 23:04:04.592217  [[0;32m  OK  [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
  927 23:04:04.650263           Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
  928 23:04:04.700991           Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
  929 23:04:04.753397           Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
  930 23:04:04.842018           Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
  931 23:04:04.900567  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
  932 23:04:04.925340  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
  933 23:04:04.965816  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
  934 23:04:04.994400  [[0;32m  OK  [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
  935 23:04:05.037231  [[0;32m  OK  [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
  936 23:04:05.070950  [[0;32m  OK  [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
  937 23:04:05.104218  [[0;32m  OK  [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
  938 23:04:05.132672  [[0;32m  OK  [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
  939 23:04:05.157450  [[0;32m  OK  [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
  940 23:04:05.188067  [[0;32m  OK  [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
  941 23:04:05.211674  [[0;32m  OK  [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
  942 23:04:05.230574  [[0;32m  OK  [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
  943 23:04:05.257438  [[0;32m  OK  [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
  944 23:04:05.278941  [[0;32m  OK  [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
  945 23:04:05.303010  [[0;32m  OK  [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
  946 23:04:05.380860           Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
  947 23:04:05.440133           Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
  948 23:04:05.536735           Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
  949 23:04:05.611892           Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
  950 23:04:05.661835           Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
  951 23:04:05.696430  [[0;32m  OK  [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
  952 23:04:05.725276  [[0;32m  OK  [0m] Reached target [0;1;39msound.target[0m - Sound Card.
  953 23:04:05.909896  [[0;32m  OK  [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
  954 23:04:05.969896  [[0;32m  OK  [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
  955 23:04:06.039783  [[0;32m  OK  [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
  956 23:04:06.059347  [[0;32m  OK  [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
  957 23:04:06.147661  [[0;32m  OK  [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
  958 23:04:06.375119  [[0;32m  OK  [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
  959 23:04:06.726243  [[0;32m  OK  [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
  960 23:04:06.773034  [[0;32m  OK  [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
  961 23:04:06.804332  [[0;32m  OK  [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
  962 23:04:06.894492           Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
  963 23:04:07.065865  [[0;32m  OK  [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
  964 23:04:07.201446  
  965 23:04:07.205171  Debian GNU/Linux 12 debiworm-armhf login: root (automatic login)
  966 23:04:07.205714  
  967 23:04:07.556175  Linux debian-bookworm-armhf 6.12.0-rc2 #1 SMP Thu Oct 10 22:15:17 UTC 2024 armv7l
  968 23:04:07.556803  
  969 23:04:07.561826  The programs included with the Debian GNU/Linux system are free software;
  970 23:04:07.565205  the exact distribution terms for each program are described in the
  971 23:04:07.570805  individual files in /usr/share/doc/*/copyright.
  972 23:04:07.571369  
  973 23:04:07.576358  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
  974 23:04:07.581092  permitted by applicable law.
  975 23:04:12.291916  Unable to match end of the kernel message
  977 23:04:12.292905  Setting prompt string to ['/ #']
  978 23:04:12.293234  end: 2.4.4.1 login-action (duration 00:00:53) [common]
  980 23:04:12.293975  end: 2.4.4 auto-login-action (duration 00:00:54) [common]
  981 23:04:12.294273  start: 2.4.5 expect-shell-connection (timeout 00:03:07) [common]
  982 23:04:12.294523  Setting prompt string to ['/ #']
  983 23:04:12.294767  Forcing a shell prompt, looking for ['/ #']
  985 23:04:12.345496  / # 
  986 23:04:12.346293  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
  987 23:04:12.346841  Waiting using forced prompt support (timeout 00:02:30)
  988 23:04:12.350174  
  989 23:04:12.357970  end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
  990 23:04:12.358648  start: 2.4.6 export-device-env (timeout 00:03:07) [common]
  991 23:04:12.359165  Sending with 10 millisecond of delay
  993 23:04:17.351109  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1'
  994 23:04:17.362129  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/837393/extract-nfsrootfs-yzcvs8b1'
  995 23:04:17.364076  Sending with 10 millisecond of delay
  997 23:04:19.465563  / # export NFS_SERVER_IP='192.168.6.2'
  998 23:04:19.476384  export NFS_SERVER_IP='192.168.6.2'
  999 23:04:19.477899  end: 2.4.6 export-device-env (duration 00:00:07) [common]
 1000 23:04:19.478384  end: 2.4 uboot-commands (duration 00:02:00) [common]
 1001 23:04:19.478739  end: 2 uboot-action (duration 00:02:00) [common]
 1002 23:04:19.479085  start: 3 lava-test-retry (timeout 00:06:49) [common]
 1003 23:04:19.479447  start: 3.1 lava-test-shell (timeout 00:06:49) [common]
 1004 23:04:19.479761  Using namespace: common
 1006 23:04:19.580698  / # #
 1007 23:04:19.581589  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
 1008 23:04:19.585257  #
 1009 23:04:19.593272  Using /lava-837393
 1011 23:04:19.694727  / # export SHELL=/bin/bash
 1012 23:04:19.699824  export SHELL=/bin/bash
 1014 23:04:19.807897  / # . /lava-837393/environment
 1015 23:04:19.813654  . /lava-837393/environment
 1017 23:04:19.928184  / # /lava-837393/bin/lava-test-runner /lava-837393/0
 1018 23:04:19.929001  Test shell timeout: 10s (minimum of the action and connection timeout)
 1019 23:04:19.933829  /lava-837393/bin/lava-test-runner /lava-837393/0
 1020 23:04:20.403665  + export TESTRUN_ID=0_timesync-off
 1021 23:04:20.411736  + TESTRUN_ID=0_timesync-off
 1022 23:04:20.412226  + cd /lava-837393/0/tests/0_timesync-off
 1023 23:04:20.412561  ++ cat uuid
 1024 23:04:20.427271  + UUID=837393_1.6.2.4.1
 1025 23:04:20.427749  + set +x
 1026 23:04:20.437237  <LAVA_SIGNAL_STARTRUN 0_timesync-off 837393_1.6.2.4.1>
 1027 23:04:20.437628  + systemctl stop systemd-timesyncd
 1028 23:04:20.438379  Received signal: <STARTRUN> 0_timesync-off 837393_1.6.2.4.1
 1029 23:04:20.438753  Starting test lava.0_timesync-off (837393_1.6.2.4.1)
 1030 23:04:20.439169  Skipping test definition patterns.
 1031 23:04:20.733803  + set +x
 1032 23:04:20.734328  <LAVA_SIGNAL_ENDRUN 0_timesync-off 837393_1.6.2.4.1>
 1033 23:04:20.734907  Received signal: <ENDRUN> 0_timesync-off 837393_1.6.2.4.1
 1034 23:04:20.735304  Ending use of test pattern.
 1035 23:04:20.735625  Ending test lava.0_timesync-off (837393_1.6.2.4.1), duration 0.30
 1037 23:04:20.906994  + export TESTRUN_ID=1_kselftest-dt
 1038 23:04:20.915035  + TESTRUN_ID=1_kselftest-dt
 1039 23:04:20.915415  + cd /lava-837393/0/tests/1_kselftest-dt
 1040 23:04:20.915724  ++ cat uuid
 1041 23:04:20.931687  + UUID=837393_1.6.2.4.5
 1042 23:04:20.932167  + set +x
 1043 23:04:20.937155  <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 837393_1.6.2.4.5>
 1044 23:04:20.937568  + cd ./automated/linux/kselftest/
 1045 23:04:20.938144  Received signal: <STARTRUN> 1_kselftest-dt 837393_1.6.2.4.5
 1046 23:04:20.938487  Starting test lava.1_kselftest-dt (837393_1.6.2.4.5)
 1047 23:04:20.938855  Skipping test definition patterns.
 1048 23:04:20.965781  + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/mainline/master/v6.12-rc2-205-g1d227fcc72223/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g mainline -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
 1049 23:04:21.081552  INFO: install_deps skipped
 1050 23:04:21.677573  --2024-10-10 23:04:21--  http://storage.kernelci.org/mainline/master/v6.12-rc2-205-g1d227fcc72223/arm/multi_v7_defconfig/clang-16/kselftest.tar.xz
 1051 23:04:21.713952  Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
 1052 23:04:21.862753  Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
 1053 23:04:22.010031  HTTP request sent, awaiting response... 200 OK
 1054 23:04:22.010459  Length: 2723236 (2.6M) [application/octet-stream]
 1055 23:04:22.015721  Saving to: 'kselftest_armhf.tar.gz'
 1056 23:04:22.016079  
 1057 23:04:23.947169  
kselftest_armhf.tar   0%[                    ]       0  --.-KB/s               
kselftest_armhf.tar   1%[                    ]  49.92K   171KB/s               
kselftest_armhf.tar   7%[>                   ] 194.76K   331KB/s               
kselftest_armhf.tar  23%[===>                ] 611.85K   776KB/s               
kselftest_armhf.tar  24%[===>                ] 651.79K   637KB/s               
kselftest_armhf.tar  43%[=======>            ]   1.12M   894KB/s               
kselftest_armhf.tar  63%[===========>        ]   1.66M  1.11MB/s               
kselftest_armhf.tar  78%[==============>     ]   2.05M  1.21MB/s               
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kselftest_armhf.tar 100%[===================>]   2.60M  1.35MB/s    in 1.9s    
 1058 23:04:23.947713  
 1059 23:04:24.290709  2024-10-10 23:04:23 (1.35 MB/s) - 'kselftest_armhf.tar.gz' saved [2723236/2723236]
 1060 23:04:24.291196  
 1061 23:04:35.584765  skiplist:
 1062 23:04:35.585268  ========================================
 1063 23:04:35.590487  ========================================
 1064 23:04:35.690977  dt:test_unprobed_devices.sh
 1065 23:04:35.723108  ============== Tests to run ===============
 1066 23:04:35.732281  dt:test_unprobed_devices.sh
 1067 23:04:35.736260  ===========End Tests to run ===============
 1068 23:04:35.745450  shardfile-dt pass
 1069 23:04:35.983954  <12>[   76.083165] kselftest: Running tests in dt
 1070 23:04:36.012695  TAP version 13
 1071 23:04:36.036887  1..1
 1072 23:04:36.091363  # timeout set to 45
 1073 23:04:36.091807  # selftests: dt: test_unprobed_devices.sh
 1074 23:04:37.002950  # TAP version 13
 1075 23:05:02.625592  # 1..257
 1076 23:05:02.798571  # ok 1 / # SKIP
 1077 23:05:02.820805  # ok 2 /clk_mcasp0
 1078 23:05:02.898694  # ok 3 /clk_mcasp0_fixed # SKIP
 1079 23:05:02.969922  # ok 4 /cpus/cpu@0 # SKIP
 1080 23:05:03.047720  # ok 5 /cpus/idle-states/mpu_gate # SKIP
 1081 23:05:03.068939  # ok 6 /fixedregulator0
 1082 23:05:03.085837  # ok 7 /leds
 1083 23:05:03.108457  # ok 8 /ocp
 1084 23:05:03.131853  # ok 9 /ocp/interconnect@44c00000
 1085 23:05:03.160361  # ok 10 /ocp/interconnect@44c00000/segment@0
 1086 23:05:03.179580  # ok 11 /ocp/interconnect@44c00000/segment@100000
 1087 23:05:03.209052  # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
 1088 23:05:03.283472  # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
 1089 23:05:03.301768  # ok 14 /ocp/interconnect@44c00000/segment@200000
 1090 23:05:03.325307  # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
 1091 23:05:03.434060  # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
 1092 23:05:03.512708  # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
 1093 23:05:03.585711  # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
 1094 23:05:03.658409  # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
 1095 23:05:03.732510  # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
 1096 23:05:03.806934  # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
 1097 23:05:03.881303  # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
 1098 23:05:03.955279  # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
 1099 23:05:04.029554  # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
 1100 23:05:04.102829  # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
 1101 23:05:04.176780  # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
 1102 23:05:04.255836  # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
 1103 23:05:04.330200  # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
 1104 23:05:04.400844  # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
 1105 23:05:04.473752  # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
 1106 23:05:04.549292  # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
 1107 23:05:04.621993  # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
 1108 23:05:04.696976  # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
 1109 23:05:04.770685  # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
 1110 23:05:04.845123  # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
 1111 23:05:04.918650  # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
 1112 23:05:04.992622  # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
 1113 23:05:05.071513  # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
 1114 23:05:05.145162  # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
 1115 23:05:05.216296  # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
 1116 23:05:05.290204  # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
 1117 23:05:05.364963  # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
 1118 23:05:05.440440  # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
 1119 23:05:05.514021  # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
 1120 23:05:05.589388  # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
 1121 23:05:05.663874  # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
 1122 23:05:05.739396  # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
 1123 23:05:05.812976  # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
 1124 23:05:05.888895  # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
 1125 23:05:05.963187  # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
 1126 23:05:06.037878  # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
 1127 23:05:06.112979  # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
 1128 23:05:06.187976  # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
 1129 23:05:06.262940  # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
 1130 23:05:06.336831  # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
 1131 23:05:06.410681  # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
 1132 23:05:06.485472  # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
 1133 23:05:06.560169  # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
 1134 23:05:06.636168  # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
 1135 23:05:06.711275  # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
 1136 23:05:06.788894  # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
 1137 23:05:06.862851  # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
 1138 23:05:06.937750  # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
 1139 23:05:07.012619  # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
 1140 23:05:07.088774  # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
 1141 23:05:07.165535  # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
 1142 23:05:07.237020  # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
 1143 23:05:07.314097  # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
 1144 23:05:07.386207  # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
 1145 23:05:07.458899  # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
 1146 23:05:07.533463  # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
 1147 23:05:07.610657  # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
 1148 23:05:07.685250  # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
 1149 23:05:07.760501  # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
 1150 23:05:07.834030  # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
 1151 23:05:07.908989  # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
 1152 23:05:07.983097  # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
 1153 23:05:08.059029  # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
 1154 23:05:08.129879  # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
 1155 23:05:08.204718  # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
 1156 23:05:08.282992  # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
 1157 23:05:08.356351  # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
 1158 23:05:08.431411  # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
 1159 23:05:08.501140  # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
 1160 23:05:08.574690  # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
 1161 23:05:08.650096  # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
 1162 23:05:08.724473  # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
 1163 23:05:08.799210  # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
 1164 23:05:08.875589  # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
 1165 23:05:08.955828  # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
 1166 23:05:09.023798  # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
 1167 23:05:09.104278  # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
 1168 23:05:09.176993  # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
 1169 23:05:09.249096  # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
 1170 23:05:09.271476  # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
 1171 23:05:09.295073  # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
 1172 23:05:09.319529  # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
 1173 23:05:09.343481  # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
 1174 23:05:09.368276  # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
 1175 23:05:09.392652  # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
 1176 23:05:09.417721  # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
 1177 23:05:09.443176  # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
 1178 23:05:09.549205  # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
 1179 23:05:09.574364  # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
 1180 23:05:09.602601  # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
 1181 23:05:09.623235  # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
 1182 23:05:09.732738  # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
 1183 23:05:09.813889  # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
 1184 23:05:09.887336  # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
 1185 23:05:09.958661  # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
 1186 23:05:10.033585  # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
 1187 23:05:10.113571  # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
 1188 23:05:10.187437  # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
 1189 23:05:10.263343  # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
 1190 23:05:10.337125  # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
 1191 23:05:10.409838  # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
 1192 23:05:10.484715  # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
 1193 23:05:10.563572  # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
 1194 23:05:10.632242  # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
 1195 23:05:10.712644  # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
 1196 23:05:10.785246  # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
 1197 23:05:10.860254  # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
 1198 23:05:10.882182  # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
 1199 23:05:10.957282  # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
 1200 23:05:11.027756  # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
 1201 23:05:11.104671  # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
 1202 23:05:11.129423  # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
 1203 23:05:11.204041  # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
 1204 23:05:11.223710  # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
 1205 23:05:11.301833  # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
 1206 23:05:11.323011  # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
 1207 23:05:11.350002  # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
 1208 23:05:11.372637  # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
 1209 23:05:11.399788  # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
 1210 23:05:11.417152  # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
 1211 23:05:11.442611  # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
 1212 23:05:11.469420  # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
 1213 23:05:11.545339  # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
 1214 23:05:11.567548  # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
 1215 23:05:11.591244  # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
 1216 23:05:11.664297  # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
 1217 23:05:11.738580  # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
 1218 23:05:11.762855  # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
 1219 23:05:11.863656  # not ok 144 /ocp/interconnect@47c00000
 1220 23:05:11.937112  # not ok 145 /ocp/interconnect@47c00000/segment@0
 1221 23:05:11.958768  # ok 146 /ocp/interconnect@48000000
 1222 23:05:11.987926  # ok 147 /ocp/interconnect@48000000/segment@0
 1223 23:05:12.012915  # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
 1224 23:05:12.033377  # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
 1225 23:05:12.057067  # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
 1226 23:05:12.080768  # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
 1227 23:05:12.104788  # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
 1228 23:05:12.129358  # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
 1229 23:05:12.158018  # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
 1230 23:05:12.226857  # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
 1231 23:05:12.301585  # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
 1232 23:05:12.328686  # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
 1233 23:05:12.353384  # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
 1234 23:05:12.372747  # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
 1235 23:05:12.397435  # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
 1236 23:05:12.420258  # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
 1237 23:05:12.445493  # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
 1238 23:05:12.468243  # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
 1239 23:05:12.492754  # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
 1240 23:05:12.515900  # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
 1241 23:05:12.543244  # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
 1242 23:05:12.568362  # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
 1243 23:05:12.593240  # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
 1244 23:05:12.619766  # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
 1245 23:05:12.637518  # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
 1246 23:05:12.661973  # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
 1247 23:05:12.691509  # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
 1248 23:05:12.712732  # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
 1249 23:05:12.735795  # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
 1250 23:05:12.756507  # ok 175 /ocp/interconnect@48000000/segment@100000
 1251 23:05:12.781913  # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
 1252 23:05:12.806122  # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
 1253 23:05:12.882887  # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
 1254 23:05:12.959298  # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
 1255 23:05:13.031358  # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
 1256 23:05:13.112884  # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
 1257 23:05:13.181100  # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
 1258 23:05:13.258071  # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
 1259 23:05:13.330944  # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
 1260 23:05:13.407159  # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
 1261 23:05:13.426491  # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
 1262 23:05:13.451219  # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
 1263 23:05:13.475366  # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
 1264 23:05:13.498758  # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
 1265 23:05:13.525107  # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
 1266 23:05:13.547161  # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
 1267 23:05:13.572848  # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
 1268 23:05:13.597056  # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
 1269 23:05:13.622897  # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
 1270 23:05:13.644919  # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
 1271 23:05:13.668695  # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
 1272 23:05:13.699054  # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
 1273 23:05:13.715474  # ok 198 /ocp/interconnect@48000000/segment@200000
 1274 23:05:13.740440  # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
 1275 23:05:13.816034  # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
 1276 23:05:13.836406  # ok 201 /ocp/interconnect@48000000/segment@300000
 1277 23:05:13.860642  # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
 1278 23:05:13.890641  # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
 1279 23:05:13.913472  # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
 1280 23:05:13.934905  # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
 1281 23:05:13.958454  # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
 1282 23:05:13.982190  # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
 1283 23:05:14.061172  # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
 1284 23:05:14.080063  # ok 209 /ocp/interconnect@4a000000
 1285 23:05:14.104594  # ok 210 /ocp/interconnect@4a000000/segment@0
 1286 23:05:14.131064  # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
 1287 23:05:14.153436  # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
 1288 23:05:14.181979  # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
 1289 23:05:14.202531  # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
 1290 23:05:14.275691  # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
 1291 23:05:14.389076  # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
 1292 23:05:14.458432  # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
 1293 23:05:14.572368  # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
 1294 23:05:14.640589  # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
 1295 23:05:14.719277  # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
 1296 23:05:14.817292  # not ok 221 /ocp/interconnect@4b140000
 1297 23:05:14.895398  # not ok 222 /ocp/interconnect@4b140000/segment@0
 1298 23:05:14.969554  # ok 223 /ocp/interrupt-controller@48200000 # SKIP
 1299 23:05:14.989951  # ok 224 /ocp/target-module@40300000
 1300 23:05:15.016502  # ok 225 /ocp/target-module@40300000/sram@0
 1301 23:05:15.092491  # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
 1302 23:05:15.164721  # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
 1303 23:05:15.182039  # ok 228 /ocp/target-module@47400000
 1304 23:05:15.207826  # ok 229 /ocp/target-module@47400000/dma-controller@2000
 1305 23:05:15.230367  # ok 230 /ocp/target-module@47400000/usb-phy@1300
 1306 23:05:15.258419  # ok 231 /ocp/target-module@47400000/usb-phy@1b00
 1307 23:05:15.280773  # ok 232 /ocp/target-module@47400000/usb@1400
 1308 23:05:15.300077  # ok 233 /ocp/target-module@47400000/usb@1800
 1309 23:05:15.322814  # ok 234 /ocp/target-module@47810000
 1310 23:05:15.345578  # ok 235 /ocp/target-module@49000000
 1311 23:05:15.369209  # ok 236 /ocp/target-module@49000000/dma@0
 1312 23:05:15.392200  # ok 237 /ocp/target-module@49800000
 1313 23:05:15.419642  # ok 238 /ocp/target-module@49800000/dma@0
 1314 23:05:15.439151  # ok 239 /ocp/target-module@49900000
 1315 23:05:15.466349  # ok 240 /ocp/target-module@49900000/dma@0
 1316 23:05:15.488993  # ok 241 /ocp/target-module@49a00000
 1317 23:05:15.507973  # ok 242 /ocp/target-module@49a00000/dma@0
 1318 23:05:15.530493  # ok 243 /ocp/target-module@4c000000
 1319 23:05:15.608250  # not ok 244 /ocp/target-module@4c000000/emif@0
 1320 23:05:15.629970  # ok 245 /ocp/target-module@50000000
 1321 23:05:15.656934  # ok 246 /ocp/target-module@53100000
 1322 23:05:15.725095  # not ok 247 /ocp/target-module@53100000/sham@0
 1323 23:05:15.746751  # ok 248 /ocp/target-module@53500000
 1324 23:05:15.821497  # not ok 249 /ocp/target-module@53500000/aes@0
 1325 23:05:15.847690  # ok 250 /ocp/target-module@56000000
 1326 23:05:15.957046  # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
 1327 23:05:16.027554  # ok 252 /opp-table # SKIP
 1328 23:05:16.096146  # ok 253 /soc # SKIP
 1329 23:05:16.122559  # ok 254 /sound
 1330 23:05:16.141640  # ok 255 /target-module@4b000000
 1331 23:05:16.167619  # ok 256 /target-module@4b000000/target-module@140000
 1332 23:05:16.189298  # ok 257 /target-module@4b000000/target-module@140000/pmu@0
 1333 23:05:16.197608  # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
 1334 23:05:16.206315  not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
 1335 23:05:18.577549  dt_test_unprobed_devices_sh_ skip
 1336 23:05:18.583246  dt_test_unprobed_devices_sh_clk_mcasp0 pass
 1337 23:05:18.588680  dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
 1338 23:05:18.589169  dt_test_unprobed_devices_sh_cpus_cpu_0 skip
 1339 23:05:18.594224  dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
 1340 23:05:18.599840  dt_test_unprobed_devices_sh_fixedregulator0 pass
 1341 23:05:18.605431  dt_test_unprobed_devices_sh_leds pass
 1342 23:05:18.605881  dt_test_unprobed_devices_sh_ocp pass
 1343 23:05:18.611488  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
 1344 23:05:18.616658  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
 1345 23:05:18.622206  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
 1346 23:05:18.633482  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
 1347 23:05:18.639105  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
 1348 23:05:18.644661  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
 1349 23:05:18.655945  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
 1350 23:05:18.661494  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
 1351 23:05:18.672633  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
 1352 23:05:18.683847  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
 1353 23:05:18.695110  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
 1354 23:05:18.700714  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
 1355 23:05:18.711873  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
 1356 23:05:18.723087  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
 1357 23:05:18.734413  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
 1358 23:05:18.745573  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
 1359 23:05:18.751199  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
 1360 23:05:18.762452  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
 1361 23:05:18.773516  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
 1362 23:05:18.784713  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
 1363 23:05:18.795914  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
 1364 23:05:18.801571  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
 1365 23:05:18.812712  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
 1366 23:05:18.823944  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
 1367 23:05:18.835097  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
 1368 23:05:18.840746  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
 1369 23:05:18.851894  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
 1370 23:05:18.863076  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
 1371 23:05:18.874249  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
 1372 23:05:18.885564  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
 1373 23:05:18.891159  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
 1374 23:05:18.902246  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
 1375 23:05:18.913438  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
 1376 23:05:18.924621  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
 1377 23:05:18.935844  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
 1378 23:05:18.947122  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
 1379 23:05:18.958201  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
 1380 23:05:18.969424  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
 1381 23:05:18.980714  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
 1382 23:05:18.991850  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
 1383 23:05:19.003098  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
 1384 23:05:19.014312  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
 1385 23:05:19.025584  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
 1386 23:05:19.036807  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
 1387 23:05:19.048076  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
 1388 23:05:19.059230  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
 1389 23:05:19.070449  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
 1390 23:05:19.081620  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
 1391 23:05:19.092808  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
 1392 23:05:19.103975  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
 1393 23:05:19.115225  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
 1394 23:05:19.126322  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
 1395 23:05:19.137573  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
 1396 23:05:19.148768  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
 1397 23:05:19.159957  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
 1398 23:05:19.171161  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
 1399 23:05:19.176800  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
 1400 23:05:19.187904  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
 1401 23:05:19.199148  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
 1402 23:05:19.210298  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
 1403 23:05:19.223092  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
 1404 23:05:19.234276  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
 1405 23:05:19.245472  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
 1406 23:05:19.256664  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
 1407 23:05:19.267869  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
 1408 23:05:19.279044  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
 1409 23:05:19.290242  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
 1410 23:05:19.301457  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
 1411 23:05:19.312646  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
 1412 23:05:19.323809  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
 1413 23:05:19.329507  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
 1414 23:05:19.340568  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
 1415 23:05:19.351776  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
 1416 23:05:19.362966  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
 1417 23:05:19.374132  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
 1418 23:05:19.385374  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
 1419 23:05:19.396614  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
 1420 23:05:19.407744  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
 1421 23:05:19.413327  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
 1422 23:05:19.424551  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
 1423 23:05:19.435741  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
 1424 23:05:19.446879  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
 1425 23:05:19.458073  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
 1426 23:05:19.469253  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
 1427 23:05:19.480440  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
 1428 23:05:19.491652  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
 1429 23:05:19.502884  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
 1430 23:05:19.514043  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
 1431 23:05:19.525246  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
 1432 23:05:19.530822  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
 1433 23:05:19.542027  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
 1434 23:05:19.547594  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
 1435 23:05:19.558839  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
 1436 23:05:19.569987  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
 1437 23:05:19.575607  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
 1438 23:05:19.586798  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
 1439 23:05:19.598011  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
 1440 23:05:19.609223  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
 1441 23:05:19.614832  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
 1442 23:05:19.626070  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
 1443 23:05:19.642766  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
 1444 23:05:19.653977  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
 1445 23:05:19.665138  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
 1446 23:05:19.676329  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
 1447 23:05:19.687610  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
 1448 23:05:19.698753  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
 1449 23:05:19.709925  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
 1450 23:05:19.721148  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
 1451 23:05:19.737907  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
 1452 23:05:19.749096  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
 1453 23:05:19.760294  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
 1454 23:05:19.771483  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
 1455 23:05:19.788315  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
 1456 23:05:19.799543  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
 1457 23:05:19.810683  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
 1458 23:05:19.821869  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
 1459 23:05:19.827466  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
 1460 23:05:19.838723  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
 1461 23:05:19.844255  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
 1462 23:05:19.855476  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
 1463 23:05:19.861124  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
 1464 23:05:19.872246  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
 1465 23:05:19.877864  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
 1466 23:05:19.889046  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
 1467 23:05:19.894705  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
 1468 23:05:19.905911  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
 1469 23:05:19.911403  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
 1470 23:05:19.922782  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
 1471 23:05:19.933882  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
 1472 23:05:19.945151  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
 1473 23:05:19.956299  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
 1474 23:05:19.961833  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
 1475 23:05:19.973084  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
 1476 23:05:19.984213  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
 1477 23:05:19.995457  dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
 1478 23:05:19.996056  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
 1479 23:05:20.006608  dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
 1480 23:05:20.007600  dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
 1481 23:05:20.017747  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
 1482 23:05:20.023439  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
 1483 23:05:20.029029  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
 1484 23:05:20.040103  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
 1485 23:05:20.045657  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
 1486 23:05:20.056866  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
 1487 23:05:20.062535  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
 1488 23:05:20.073800  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
 1489 23:05:20.079333  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
 1490 23:05:20.084912  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
 1491 23:05:20.096158  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
 1492 23:05:20.101732  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
 1493 23:05:20.112933  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
 1494 23:05:20.118521  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
 1495 23:05:20.129841  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
 1496 23:05:20.135359  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
 1497 23:05:20.146431  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
 1498 23:05:20.152091  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
 1499 23:05:20.163252  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
 1500 23:05:20.168925  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
 1501 23:05:20.180040  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
 1502 23:05:20.185815  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
 1503 23:05:20.197025  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
 1504 23:05:20.202559  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
 1505 23:05:20.208086  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
 1506 23:05:20.219295  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
 1507 23:05:20.224951  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
 1508 23:05:20.236131  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
 1509 23:05:20.241645  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
 1510 23:05:20.252898  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
 1511 23:05:20.258427  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
 1512 23:05:20.269679  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
 1513 23:05:20.280879  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
 1514 23:05:20.292170  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
 1515 23:05:20.303172  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
 1516 23:05:20.314556  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
 1517 23:05:20.326107  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
 1518 23:05:20.336877  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
 1519 23:05:20.348174  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
 1520 23:05:20.353645  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
 1521 23:05:20.364836  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
 1522 23:05:20.370749  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
 1523 23:05:20.381578  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
 1524 23:05:20.387764  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
 1525 23:05:20.398508  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
 1526 23:05:20.404153  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
 1527 23:05:20.415287  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
 1528 23:05:20.420866  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
 1529 23:05:20.432106  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
 1530 23:05:20.437716  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
 1531 23:05:20.448778  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
 1532 23:05:20.454241  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
 1533 23:05:20.459885  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
 1534 23:05:20.471059  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
 1535 23:05:20.476773  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
 1536 23:05:20.482325  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
 1537 23:05:20.493391  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
 1538 23:05:20.504567  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
 1539 23:05:20.510255  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
 1540 23:05:20.515830  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
 1541 23:05:20.527019  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
 1542 23:05:20.538201  dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
 1543 23:05:20.538705  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
 1544 23:05:20.549426  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
 1545 23:05:20.555006  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
 1546 23:05:20.566479  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
 1547 23:05:20.571850  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
 1548 23:05:20.583042  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
 1549 23:05:20.588670  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
 1550 23:05:20.599788  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
 1551 23:05:20.610982  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
 1552 23:05:20.622167  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
 1553 23:05:20.627836  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
 1554 23:05:20.639063  dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
 1555 23:05:20.644719  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
 1556 23:05:20.650289  dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
 1557 23:05:20.655960  dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
 1558 23:05:20.661508  dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
 1559 23:05:20.667231  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
 1560 23:05:20.672786  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
 1561 23:05:20.683937  dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
 1562 23:05:20.689553  dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
 1563 23:05:20.695228  dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
 1564 23:05:20.700762  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
 1565 23:05:20.706362  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
 1566 23:05:20.711961  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
 1567 23:05:20.723210  dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
 1568 23:05:20.723638  dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
 1569 23:05:20.728888  dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
 1570 23:05:20.734370  dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
 1571 23:05:20.740066  dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
 1572 23:05:20.745577  dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
 1573 23:05:20.751235  dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
 1574 23:05:20.756807  dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
 1575 23:05:20.762453  dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
 1576 23:05:20.768102  dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
 1577 23:05:20.773669  dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
 1578 23:05:20.779280  dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
 1579 23:05:20.784842  dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
 1580 23:05:20.790471  dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
 1581 23:05:20.796153  dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
 1582 23:05:20.801701  dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
 1583 23:05:20.807292  dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
 1584 23:05:20.812792  dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
 1585 23:05:20.818480  dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
 1586 23:05:20.824089  dt_test_unprobed_devices_sh_opp-table skip
 1587 23:05:20.829643  dt_test_unprobed_devices_sh_soc skip
 1588 23:05:20.830077  dt_test_unprobed_devices_sh_sound pass
 1589 23:05:20.835290  dt_test_unprobed_devices_sh_target-module_4b000000 pass
 1590 23:05:20.840883  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
 1591 23:05:20.852112  dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
 1592 23:05:20.852543  dt_test_unprobed_devices_sh fail
 1593 23:05:20.857772  + ../../utils/send-to-lava.sh ./output/result.txt
 1594 23:05:20.863266  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
 1595 23:05:20.864156  Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
 1597 23:05:20.870973  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
 1598 23:05:20.871647  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
 1600 23:05:20.960280  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
 1601 23:05:20.960994  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
 1603 23:05:21.055589  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
 1604 23:05:21.056379  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
 1606 23:05:21.150460  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
 1607 23:05:21.151224  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
 1609 23:05:21.246385  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
 1610 23:05:21.247192  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
 1612 23:05:21.339849  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
 1613 23:05:21.340678  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
 1615 23:05:21.428147  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
 1616 23:05:21.428953  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
 1618 23:05:21.516223  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
 1619 23:05:21.516977  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
 1621 23:05:21.608120  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
 1622 23:05:21.608999  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
 1624 23:05:21.702618  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
 1625 23:05:21.703607  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
 1627 23:05:21.798908  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
 1628 23:05:21.799742  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
 1630 23:05:21.889080  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
 1631 23:05:21.889913  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
 1633 23:05:21.983935  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
 1634 23:05:21.984794  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
 1636 23:05:22.070664  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
 1637 23:05:22.071491  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
 1639 23:05:22.169223  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
 1640 23:05:22.170050  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
 1642 23:05:22.270221  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
 1643 23:05:22.271037  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
 1645 23:05:22.371201  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
 1646 23:05:22.372057  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
 1648 23:05:22.467577  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
 1649 23:05:22.468403  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
 1651 23:05:22.563685  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
 1652 23:05:22.564568  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
 1654 23:05:22.658282  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
 1655 23:05:22.659090  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
 1657 23:05:22.747106  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
 1658 23:05:22.747900  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
 1660 23:05:22.843165  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
 1661 23:05:22.843974  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
 1663 23:05:22.933557  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
 1664 23:05:22.934356  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
 1666 23:05:23.028252  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
 1667 23:05:23.029081  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
 1669 23:05:23.118349  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
 1670 23:05:23.119183  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
 1672 23:05:23.213346  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
 1673 23:05:23.214180  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
 1675 23:05:23.304300  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
 1676 23:05:23.305102  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
 1678 23:05:23.399334  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
 1679 23:05:23.400208  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
 1681 23:05:23.489995  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
 1682 23:05:23.490997  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
 1684 23:05:23.584185  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
 1685 23:05:23.585062  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
 1687 23:05:23.674990  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
 1688 23:05:23.675963  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
 1690 23:05:23.769576  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
 1691 23:05:23.770575  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
 1693 23:05:23.859846  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
 1694 23:05:23.860855  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
 1696 23:05:23.948792  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
 1697 23:05:23.949944  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
 1699 23:05:24.043335  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
 1700 23:05:24.044334  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
 1702 23:05:24.132317  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
 1703 23:05:24.133291  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
 1705 23:05:24.228090  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
 1706 23:05:24.228963  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
 1708 23:05:24.316673  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
 1709 23:05:24.317624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
 1711 23:05:24.412195  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
 1712 23:05:24.413177  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
 1714 23:05:24.507445  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
 1715 23:05:24.508392  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
 1717 23:05:24.604808  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
 1718 23:05:24.605811  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
 1720 23:05:24.699925  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
 1721 23:05:24.700803  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
 1723 23:05:24.789427  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
 1724 23:05:24.790378  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
 1726 23:05:24.879807  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
 1727 23:05:24.880724  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
 1729 23:05:24.975115  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
 1730 23:05:24.976093  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
 1732 23:05:25.071565  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
 1733 23:05:25.072447  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
 1735 23:05:25.166128  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
 1736 23:05:25.167003  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
 1738 23:05:25.261439  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
 1739 23:05:25.262316  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
 1741 23:05:25.358184  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
 1742 23:05:25.359048  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
 1744 23:05:25.454207  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
 1745 23:05:25.455071  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
 1747 23:05:25.549108  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
 1748 23:05:25.549962  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
 1750 23:05:25.638278  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
 1751 23:05:25.639108  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
 1753 23:05:25.736502  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
 1754 23:05:25.737649  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
 1756 23:05:25.840385  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
 1757 23:05:25.841376  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
 1759 23:05:25.947219  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
 1760 23:05:25.948183  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
 1762 23:05:26.047856  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
 1763 23:05:26.048793  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
 1765 23:05:26.147125  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
 1766 23:05:26.148013  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
 1768 23:05:26.240831  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
 1769 23:05:26.241734  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
 1771 23:05:26.334978  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
 1772 23:05:26.335853  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
 1774 23:05:26.508540  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
 1775 23:05:26.509371  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
 1777 23:05:26.614484  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
 1778 23:05:26.615331  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
 1780 23:05:26.703588  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
 1781 23:05:26.704471  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
 1783 23:05:26.800870  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
 1784 23:05:26.801740  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
 1786 23:05:26.896788  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
 1787 23:05:26.897625  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
 1789 23:05:26.992013  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
 1790 23:05:26.992701  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
 1792 23:05:27.088404  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
 1793 23:05:27.089074  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
 1795 23:05:27.179036  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
 1796 23:05:27.180015  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
 1798 23:05:27.267433  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
 1799 23:05:27.268417  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
 1801 23:05:27.364850  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
 1802 23:05:27.365831  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
 1804 23:05:27.462332  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
 1805 23:05:27.463296  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
 1807 23:05:27.562532  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
 1808 23:05:27.563519  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
 1810 23:05:27.655297  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
 1811 23:05:27.656290  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
 1813 23:05:27.751678  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
 1814 23:05:27.752697  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
 1816 23:05:27.852670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
 1817 23:05:27.853647  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
 1819 23:05:27.941337  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
 1820 23:05:27.942050  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
 1822 23:05:28.038301  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
 1823 23:05:28.038997  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
 1825 23:05:28.135068  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
 1826 23:05:28.135999  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
 1828 23:05:28.230050  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
 1829 23:05:28.230924  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
 1831 23:05:28.320899  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
 1832 23:05:28.321886  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
 1834 23:05:28.414908  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
 1835 23:05:28.415793  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
 1837 23:05:28.505511  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
 1838 23:05:28.506367  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
 1840 23:05:28.600964  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
 1841 23:05:28.601935  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
 1843 23:05:28.690512  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
 1844 23:05:28.691372  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
 1846 23:05:28.784483  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
 1847 23:05:28.785350  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
 1849 23:05:28.873750  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
 1850 23:05:28.874615  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
 1852 23:05:28.968486  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
 1853 23:05:28.969319  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
 1855 23:05:29.064541  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
 1856 23:05:29.065392  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
 1858 23:05:29.158886  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
 1859 23:05:29.159717  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
 1861 23:05:29.250470  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
 1862 23:05:29.251405  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
 1864 23:05:29.339216  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
 1865 23:05:29.340082  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
 1867 23:05:29.433087  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
 1868 23:05:29.433922  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
 1870 23:05:29.532424  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
 1871 23:05:29.533244  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
 1873 23:05:29.628074  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
 1874 23:05:29.628974  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
 1876 23:05:29.725092  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
 1877 23:05:29.726000  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
 1879 23:05:29.816836  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
 1880 23:05:29.817738  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
 1882 23:05:29.906581  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
 1883 23:05:29.907473  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
 1885 23:05:29.995647  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
 1886 23:05:29.996589  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
 1888 23:05:30.093212  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
 1889 23:05:30.094124  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
 1891 23:05:30.187306  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
 1892 23:05:30.188234  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
 1894 23:05:30.282522  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
 1895 23:05:30.283426  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
 1897 23:05:30.377508  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
 1898 23:05:30.378415  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
 1900 23:05:30.465688  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
 1901 23:05:30.466583  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
 1903 23:05:30.555444  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
 1904 23:05:30.556349  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
 1906 23:05:30.650763  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
 1907 23:05:30.651683  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
 1909 23:05:30.745305  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
 1910 23:05:30.746526  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
 1912 23:05:30.834685  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
 1913 23:05:30.835606  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
 1915 23:05:30.924543  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
 1916 23:05:30.925475  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
 1918 23:05:31.022097  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
 1919 23:05:31.023025  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
 1921 23:05:31.118462  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
 1922 23:05:31.119369  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
 1924 23:05:31.213519  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
 1925 23:05:31.214414  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
 1927 23:05:31.308801  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
 1928 23:05:31.309668  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
 1930 23:05:31.397886  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
 1931 23:05:31.398767  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
 1933 23:05:31.493227  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
 1934 23:05:31.494093  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
 1936 23:05:31.582110  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
 1937 23:05:31.582956  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
 1939 23:05:31.673416  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
 1940 23:05:31.674238  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
 1942 23:05:31.769137  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
 1943 23:05:31.769940  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
 1945 23:05:31.859742  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
 1946 23:05:31.860583  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
 1948 23:05:31.956380  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
 1949 23:05:31.957173  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
 1951 23:05:32.052828  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
 1952 23:05:32.053614  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
 1954 23:05:32.146948  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
 1956 23:05:32.149201  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
 1957 23:05:32.244062  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
 1959 23:05:32.246247  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
 1960 23:05:32.334472  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
 1962 23:05:32.336944  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
 1963 23:05:32.429621  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
 1964 23:05:32.430477  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
 1966 23:05:32.524304  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
 1967 23:05:32.525413  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
 1969 23:05:32.611000  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
 1970 23:05:32.612187  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
 1972 23:05:32.701639  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
 1973 23:05:32.702660  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
 1975 23:05:32.796314  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
 1976 23:05:32.797312  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
 1978 23:05:32.890185  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
 1979 23:05:32.891181  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
 1981 23:05:32.979707  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
 1982 23:05:32.980744  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
 1984 23:05:33.075030  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
 1985 23:05:33.076061  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
 1987 23:05:33.171714  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
 1988 23:05:33.172668  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
 1990 23:05:33.266849  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
 1991 23:05:33.267760  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
 1993 23:05:33.361310  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
 1994 23:05:33.362170  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
 1996 23:05:33.452318  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
 1997 23:05:33.453162  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
 1999 23:05:33.550565  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
 2000 23:05:33.551395  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
 2002 23:05:33.647865  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
 2003 23:05:33.648520  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
 2005 23:05:33.748927  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
 2006 23:05:33.749781  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
 2008 23:05:33.844623  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
 2009 23:05:33.845631  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
 2011 23:05:33.936929  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
 2012 23:05:33.937785  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
 2014 23:05:34.031968  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
 2015 23:05:34.033019  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
 2017 23:05:34.130065  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
 2018 23:05:34.131337  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
 2020 23:05:34.229541  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
 2021 23:05:34.230414  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
 2023 23:05:34.322355  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
 2024 23:05:34.323376  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
 2026 23:05:34.418233  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
 2027 23:05:34.419084  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
 2029 23:05:34.516067  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
 2030 23:05:34.517375  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
 2032 23:05:34.610820  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
 2033 23:05:34.611806  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
 2035 23:05:34.707660  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
 2036 23:05:34.709054  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
 2038 23:05:34.809396  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
 2039 23:05:34.810724  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
 2041 23:05:34.902056  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
 2042 23:05:34.903104  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
 2044 23:05:34.991812  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
 2045 23:05:34.992949  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
 2047 23:05:35.087066  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
 2048 23:05:35.088116  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
 2050 23:05:35.183560  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
 2051 23:05:35.184468  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
 2053 23:05:35.279332  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
 2054 23:05:35.280112  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
 2056 23:05:35.372904  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
 2057 23:05:35.373926  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
 2059 23:05:35.472117  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
 2060 23:05:35.472996  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
 2062 23:05:35.569171  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
 2063 23:05:35.570038  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
 2065 23:05:35.663848  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
 2066 23:05:35.664830  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
 2068 23:05:35.757479  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
 2069 23:05:35.758328  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
 2071 23:05:35.849403  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
 2072 23:05:35.850261  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
 2074 23:05:35.940426  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
 2075 23:05:35.941255  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
 2077 23:05:36.029286  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
 2078 23:05:36.030109  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
 2080 23:05:36.120818  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
 2081 23:05:36.121624  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
 2083 23:05:36.214911  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
 2084 23:05:36.215746  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
 2086 23:05:36.311771  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
 2087 23:05:36.312613  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
 2089 23:05:36.400129  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
 2090 23:05:36.400973  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
 2092 23:05:36.495487  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
 2093 23:05:36.496386  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
 2095 23:05:36.591340  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
 2096 23:05:36.592457  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
 2098 23:05:36.687328  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
 2099 23:05:36.688241  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
 2101 23:05:36.782424  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
 2102 23:05:36.783084  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
 2104 23:05:36.871364  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
 2105 23:05:36.872192  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
 2107 23:05:36.960044  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
 2108 23:05:36.960876  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
 2110 23:05:37.054799  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
 2111 23:05:37.055631  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
 2113 23:05:37.143167  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
 2114 23:05:37.144068  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
 2116 23:05:37.239423  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
 2117 23:05:37.240205  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
 2119 23:05:37.332720  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
 2120 23:05:37.333496  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
 2122 23:05:37.428277  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
 2123 23:05:37.429063  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
 2125 23:05:37.519255  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
 2126 23:05:37.520075  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
 2128 23:05:37.614619  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
 2129 23:05:37.615399  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
 2131 23:05:37.706329  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
 2132 23:05:37.707374  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
 2134 23:05:37.799387  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
 2135 23:05:37.800424  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
 2137 23:05:37.897619  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
 2138 23:05:37.898514  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
 2140 23:05:37.993087  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
 2141 23:05:37.994076  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
 2143 23:05:38.089849  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
 2144 23:05:38.090898  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
 2146 23:05:38.183665  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
 2147 23:05:38.184615  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
 2149 23:05:38.281188  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
 2150 23:05:38.282084  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
 2152 23:05:38.372750  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
 2153 23:05:38.373773  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
 2155 23:05:38.468035  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
 2156 23:05:38.469024  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
 2158 23:05:38.561805  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
 2159 23:05:38.563198  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
 2161 23:05:38.652162  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
 2162 23:05:38.653128  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
 2164 23:05:38.746415  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
 2165 23:05:38.747362  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
 2167 23:05:38.837180  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
 2168 23:05:38.838124  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
 2170 23:05:38.925436  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
 2171 23:05:38.926343  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
 2173 23:05:39.021169  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
 2174 23:05:39.022148  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
 2176 23:05:39.114559  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
 2177 23:05:39.115485  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
 2179 23:05:39.204318  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
 2180 23:05:39.205323  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
 2182 23:05:39.294337  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
 2183 23:05:39.295326  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
 2185 23:05:39.390972  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
 2186 23:05:39.391891  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
 2188 23:05:39.478674  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
 2189 23:05:39.480073  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
 2191 23:05:39.574221  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
 2192 23:05:39.575649  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
 2194 23:05:39.665168  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
 2195 23:05:39.666577  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
 2197 23:05:39.757443  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
 2198 23:05:39.758442  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
 2200 23:05:39.853233  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
 2201 23:05:39.854121  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
 2203 23:05:39.943582  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
 2204 23:05:39.945175  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
 2206 23:05:40.040359  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
 2207 23:05:40.041330  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
 2209 23:05:40.134989  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
 2210 23:05:40.135857  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
 2212 23:05:40.231660  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
 2213 23:05:40.232685  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
 2215 23:05:40.320348  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
 2216 23:05:40.321239  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
 2218 23:05:40.415759  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
 2219 23:05:40.416688  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
 2221 23:05:40.501187  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
 2222 23:05:40.502071  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
 2224 23:05:40.592923  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
 2225 23:05:40.593760  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
 2227 23:05:40.690366  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
 2228 23:05:40.691167  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
 2230 23:05:40.786654  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
 2231 23:05:40.787475  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
 2233 23:05:40.883571  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
 2234 23:05:40.884425  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
 2236 23:05:40.977280  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
 2237 23:05:40.978076  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
 2239 23:05:41.067240  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
 2240 23:05:41.068083  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
 2242 23:05:41.162985  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
 2243 23:05:41.163803  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
 2245 23:05:41.253495  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
 2246 23:05:41.254287  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
 2248 23:05:41.346546  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
 2249 23:05:41.347374  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
 2251 23:05:41.441380  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
 2252 23:05:41.442263  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
 2254 23:05:41.530688  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
 2255 23:05:41.531567  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
 2257 23:05:41.621664  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
 2258 23:05:41.622447  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
 2260 23:05:41.717596  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
 2261 23:05:41.718246  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
 2263 23:05:41.806199  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
 2264 23:05:41.806932  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
 2266 23:05:41.898153  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
 2267 23:05:41.898882  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
 2269 23:05:41.988065  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
 2270 23:05:41.989095  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
 2272 23:05:42.080430  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
 2273 23:05:42.081422  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
 2275 23:05:42.171600  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
 2277 23:05:42.173689  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
 2278 23:05:42.261738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
 2279 23:05:42.262959  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
 2281 23:05:42.352976  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
 2282 23:05:42.353802  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
 2284 23:05:42.447660  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
 2285 23:05:42.448505  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
 2287 23:05:42.541486  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
 2288 23:05:42.542299  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
 2290 23:05:42.631243  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
 2291 23:05:42.632091  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
 2293 23:05:42.718617  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
 2294 23:05:42.719424  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
 2296 23:05:42.805760  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
 2297 23:05:42.806585  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
 2299 23:05:42.899512  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
 2300 23:05:42.900366  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
 2302 23:05:42.990337  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
 2303 23:05:42.991166  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
 2305 23:05:43.085815  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
 2306 23:05:43.086646  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
 2308 23:05:43.181447  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
 2309 23:05:43.182281  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
 2311 23:05:43.274551  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
 2312 23:05:43.275375  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
 2314 23:05:43.371388  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
 2315 23:05:43.372219  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
 2317 23:05:43.465422  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
 2318 23:05:43.466238  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
 2320 23:05:43.557113  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
 2321 23:05:43.557924  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
 2323 23:05:43.651040  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
 2324 23:05:43.652083  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
 2326 23:05:43.740473  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
 2327 23:05:43.741470  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
 2329 23:05:43.836320  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
 2330 23:05:43.837249  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
 2332 23:05:43.929557  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
 2333 23:05:43.930630  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
 2335 23:05:44.026832  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
 2336 23:05:44.027870  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
 2338 23:05:44.114748  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
 2339 23:05:44.115699  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
 2341 23:05:44.210885  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
 2342 23:05:44.211808  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
 2344 23:05:44.299048  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
 2345 23:05:44.299957  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
 2347 23:05:44.393562  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
 2348 23:05:44.394491  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
 2350 23:05:44.485410  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
 2351 23:05:44.486307  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
 2353 23:05:44.580309  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
 2354 23:05:44.581250  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
 2356 23:05:44.672608  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
 2357 23:05:44.673547  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
 2359 23:05:44.769666  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
 2360 23:05:44.770625  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
 2362 23:05:44.860779  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
 2363 23:05:44.861683  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
 2365 23:05:44.956537  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
 2366 23:05:44.957473  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
 2368 23:05:45.049360  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
 2369 23:05:45.049664  + set +x
 2370 23:05:45.050082  Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
 2372 23:05:45.053656  <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 837393_1.6.2.4.5>
 2373 23:05:45.054192  Received signal: <ENDRUN> 1_kselftest-dt 837393_1.6.2.4.5
 2374 23:05:45.055269  Ending use of test pattern.
 2375 23:05:45.055493  Ending test lava.1_kselftest-dt (837393_1.6.2.4.5), duration 84.12
 2377 23:05:45.060069  <LAVA_TEST_RUNNER EXIT>
 2378 23:05:45.060587  ok: lava_test_shell seems to have completed
 2379 23:05:45.069357  dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass

 2380 23:05:45.071317  end: 3.1 lava-test-shell (duration 00:01:26) [common]
 2381 23:05:45.071610  end: 3 lava-test-retry (duration 00:01:26) [common]
 2382 23:05:45.071906  start: 4 finalize (timeout 00:05:24) [common]
 2383 23:05:45.072224  start: 4.1 power-off (timeout 00:00:30) [common]
 2384 23:05:45.072748  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
 2385 23:05:45.104551  >> OK - accepted request

 2386 23:05:45.106672  Returned 0 in 0 seconds
 2387 23:05:45.207369  end: 4.1 power-off (duration 00:00:00) [common]
 2389 23:05:45.209351  start: 4.2 read-feedback (timeout 00:05:23) [common]
 2390 23:05:45.210154  Listened to connection for namespace 'common' for up to 1s
 2391 23:05:45.210890  Listened to connection for namespace 'common' for up to 1s
 2392 23:05:46.211064  Finalising connection for namespace 'common'
 2393 23:05:46.211561  Disconnecting from shell: Finalise
 2394 23:05:46.211844  / # 
 2395 23:05:46.312504  end: 4.2 read-feedback (duration 00:00:01) [common]
 2396 23:05:46.312943  end: 4 finalize (duration 00:00:01) [common]
 2397 23:05:46.313544  Cleaning after the job
 2398 23:05:46.313937  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/ramdisk
 2399 23:05:46.315543  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/kernel
 2400 23:05:46.317369  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/dtb
 2401 23:05:46.318735  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/nfsrootfs
 2402 23:05:46.356382  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/837393/tftp-deploy-ldrfha3p/modules
 2403 23:05:46.360710  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/837393
 2404 23:05:49.358537  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/837393
 2405 23:05:49.359079  Job finished correctly