Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:09:38.811741 lava-dispatcher, installed at version: 2024.01
2 21:09:38.812577 start: 0 validate
3 21:09:38.813058 Start time: 2024-10-08 21:09:38.813028+00:00 (UTC)
4 21:09:38.813600 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:09:38.814153 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 21:09:38.852635 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:09:38.853224 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:09:38.884060 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:09:38.884883 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:09:39.929240 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:09:39.929774 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 21:09:39.968668 validate duration: 1.16
14 21:09:39.969539 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 21:09:39.969898 start: 1.1 download-retry (timeout 00:10:00) [common]
16 21:09:39.970205 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 21:09:39.970890 Not decompressing ramdisk as can be used compressed.
18 21:09:39.971508 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 21:09:39.971786 saving as /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/ramdisk/rootfs.cpio.gz
20 21:09:39.972071 total size: 8181887 (7 MB)
21 21:09:40.011427 progress 0 % (0 MB)
22 21:09:40.022126 progress 5 % (0 MB)
23 21:09:40.033005 progress 10 % (0 MB)
24 21:09:40.044283 progress 15 % (1 MB)
25 21:09:40.049877 progress 20 % (1 MB)
26 21:09:40.055770 progress 25 % (1 MB)
27 21:09:40.061215 progress 30 % (2 MB)
28 21:09:40.067076 progress 35 % (2 MB)
29 21:09:40.072704 progress 40 % (3 MB)
30 21:09:40.078678 progress 45 % (3 MB)
31 21:09:40.084250 progress 50 % (3 MB)
32 21:09:40.090102 progress 55 % (4 MB)
33 21:09:40.095530 progress 60 % (4 MB)
34 21:09:40.101340 progress 65 % (5 MB)
35 21:09:40.106755 progress 70 % (5 MB)
36 21:09:40.112548 progress 75 % (5 MB)
37 21:09:40.117927 progress 80 % (6 MB)
38 21:09:40.123708 progress 85 % (6 MB)
39 21:09:40.129112 progress 90 % (7 MB)
40 21:09:40.134867 progress 95 % (7 MB)
41 21:09:40.140128 progress 100 % (7 MB)
42 21:09:40.140824 7 MB downloaded in 0.17 s (46.24 MB/s)
43 21:09:40.141391 end: 1.1.1 http-download (duration 00:00:00) [common]
45 21:09:40.142308 end: 1.1 download-retry (duration 00:00:00) [common]
46 21:09:40.142617 start: 1.2 download-retry (timeout 00:10:00) [common]
47 21:09:40.142902 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 21:09:40.143410 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/kernel/Image
49 21:09:40.143672 saving as /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/kernel/Image
50 21:09:40.144012 total size: 45713920 (43 MB)
51 21:09:40.144284 No compression specified
52 21:09:40.175535 progress 0 % (0 MB)
53 21:09:40.204541 progress 5 % (2 MB)
54 21:09:40.234068 progress 10 % (4 MB)
55 21:09:40.264163 progress 15 % (6 MB)
56 21:09:40.294432 progress 20 % (8 MB)
57 21:09:40.324062 progress 25 % (10 MB)
58 21:09:40.354233 progress 30 % (13 MB)
59 21:09:40.384215 progress 35 % (15 MB)
60 21:09:40.414186 progress 40 % (17 MB)
61 21:09:40.443444 progress 45 % (19 MB)
62 21:09:40.473341 progress 50 % (21 MB)
63 21:09:40.503382 progress 55 % (24 MB)
64 21:09:40.533502 progress 60 % (26 MB)
65 21:09:40.563384 progress 65 % (28 MB)
66 21:09:40.593443 progress 70 % (30 MB)
67 21:09:40.623711 progress 75 % (32 MB)
68 21:09:40.653341 progress 80 % (34 MB)
69 21:09:40.682849 progress 85 % (37 MB)
70 21:09:40.713181 progress 90 % (39 MB)
71 21:09:40.743088 progress 95 % (41 MB)
72 21:09:40.772853 progress 100 % (43 MB)
73 21:09:40.773386 43 MB downloaded in 0.63 s (69.27 MB/s)
74 21:09:40.773889 end: 1.2.1 http-download (duration 00:00:01) [common]
76 21:09:40.774732 end: 1.2 download-retry (duration 00:00:01) [common]
77 21:09:40.775039 start: 1.3 download-retry (timeout 00:09:59) [common]
78 21:09:40.775332 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 21:09:40.775850 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 21:09:40.776179 saving as /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/dtb/meson-g12b-a311d-libretech-cc.dtb
81 21:09:40.776402 total size: 54703 (0 MB)
82 21:09:40.776623 No compression specified
83 21:09:40.812923 progress 59 % (0 MB)
84 21:09:40.813792 progress 100 % (0 MB)
85 21:09:40.814364 0 MB downloaded in 0.04 s (1.37 MB/s)
86 21:09:40.814869 end: 1.3.1 http-download (duration 00:00:00) [common]
88 21:09:40.815708 end: 1.3 download-retry (duration 00:00:00) [common]
89 21:09:40.815999 start: 1.4 download-retry (timeout 00:09:59) [common]
90 21:09:40.816290 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 21:09:40.816779 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/modules.tar.xz
92 21:09:40.817033 saving as /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/modules/modules.tar
93 21:09:40.817248 total size: 11613728 (11 MB)
94 21:09:40.817465 Using unxz to decompress xz
95 21:09:40.850449 progress 0 % (0 MB)
96 21:09:40.913446 progress 5 % (0 MB)
97 21:09:40.994917 progress 10 % (1 MB)
98 21:09:41.086668 progress 15 % (1 MB)
99 21:09:41.181514 progress 20 % (2 MB)
100 21:09:41.266200 progress 25 % (2 MB)
101 21:09:41.349948 progress 30 % (3 MB)
102 21:09:41.434088 progress 35 % (3 MB)
103 21:09:41.511065 progress 40 % (4 MB)
104 21:09:41.590126 progress 45 % (5 MB)
105 21:09:41.673533 progress 50 % (5 MB)
106 21:09:41.753688 progress 55 % (6 MB)
107 21:09:41.841316 progress 60 % (6 MB)
108 21:09:41.917776 progress 65 % (7 MB)
109 21:09:41.999321 progress 70 % (7 MB)
110 21:09:42.074504 progress 75 % (8 MB)
111 21:09:42.153991 progress 80 % (8 MB)
112 21:09:42.244328 progress 85 % (9 MB)
113 21:09:42.334836 progress 90 % (9 MB)
114 21:09:42.424877 progress 95 % (10 MB)
115 21:09:42.511152 progress 100 % (11 MB)
116 21:09:42.524685 11 MB downloaded in 1.71 s (6.49 MB/s)
117 21:09:42.525389 end: 1.4.1 http-download (duration 00:00:02) [common]
119 21:09:42.526254 end: 1.4 download-retry (duration 00:00:02) [common]
120 21:09:42.526530 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 21:09:42.526799 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 21:09:42.527048 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 21:09:42.527305 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 21:09:42.529354 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592
125 21:09:42.530703 makedir: /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin
126 21:09:42.531305 makedir: /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/tests
127 21:09:42.539345 makedir: /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/results
128 21:09:42.540005 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-add-keys
129 21:09:42.546941 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-add-sources
130 21:09:42.557126 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-background-process-start
131 21:09:42.561625 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-background-process-stop
132 21:09:42.567561 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-common-functions
133 21:09:42.569041 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-echo-ipv4
134 21:09:42.569873 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-install-packages
135 21:09:42.570564 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-installed-packages
136 21:09:42.571213 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-os-build
137 21:09:42.572025 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-probe-channel
138 21:09:42.572972 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-probe-ip
139 21:09:42.573662 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-target-ip
140 21:09:42.574319 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-target-mac
141 21:09:42.574964 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-target-storage
142 21:09:42.575627 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-test-case
143 21:09:42.576311 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-test-event
144 21:09:42.576952 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-test-feedback
145 21:09:42.577620 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-test-raise
146 21:09:42.578309 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-test-reference
147 21:09:42.578974 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-test-runner
148 21:09:42.579695 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-test-set
149 21:09:42.580423 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-test-shell
150 21:09:42.581118 Updating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-install-packages (oe)
151 21:09:42.581820 Updating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/bin/lava-installed-packages (oe)
152 21:09:42.582436 Creating /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/environment
153 21:09:42.582983 LAVA metadata
154 21:09:42.583323 - LAVA_JOB_ID=823597
155 21:09:42.583581 - LAVA_DISPATCHER_IP=192.168.6.2
156 21:09:42.584085 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 21:09:42.585418 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 21:09:42.585892 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 21:09:42.586155 skipped lava-vland-overlay
160 21:09:42.586436 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 21:09:42.586738 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 21:09:42.587014 skipped lava-multinode-overlay
163 21:09:42.587376 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 21:09:42.587688 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 21:09:42.588033 Loading test definitions
166 21:09:42.588449 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 21:09:42.588741 Using /lava-823597 at stage 0
168 21:09:42.590428 uuid=823597_1.5.2.4.1 testdef=None
169 21:09:42.590866 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 21:09:42.591202 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 21:09:42.593616 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 21:09:42.594603 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 21:09:42.602047 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 21:09:42.603134 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 21:09:42.606636 runner path: /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/0/tests/0_dmesg test_uuid 823597_1.5.2.4.1
178 21:09:42.607409 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 21:09:42.608372 Creating lava-test-runner.conf files
181 21:09:42.608631 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/823597/lava-overlay-10rb8592/lava-823597/0 for stage 0
182 21:09:42.609108 - 0_dmesg
183 21:09:42.609586 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 21:09:42.609957 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 21:09:42.641031 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 21:09:42.641540 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 21:09:42.641878 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 21:09:42.642184 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 21:09:42.642486 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 21:09:43.622260 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 21:09:43.622719 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 21:09:43.622966 extracting modules file /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823597/extract-overlay-ramdisk-vqw0i3sh/ramdisk
193 21:09:44.956927 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 21:09:44.957442 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 21:09:44.957705 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823597/compress-overlay-5n9rzhdr/overlay-1.5.2.5.tar.gz to ramdisk
196 21:09:44.957915 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823597/compress-overlay-5n9rzhdr/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/823597/extract-overlay-ramdisk-vqw0i3sh/ramdisk
197 21:09:44.987878 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 21:09:44.988344 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 21:09:44.988614 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 21:09:44.988842 Converting downloaded kernel to a uImage
201 21:09:44.989143 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/kernel/Image /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/kernel/uImage
202 21:09:45.465511 output: Image Name:
203 21:09:45.466023 output: Created: Tue Oct 8 21:09:44 2024
204 21:09:45.466284 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 21:09:45.466522 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 21:09:45.466768 output: Load Address: 01080000
207 21:09:45.467011 output: Entry Point: 01080000
208 21:09:45.467250 output:
209 21:09:45.467647 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 21:09:45.467974 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 21:09:45.468349 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 21:09:45.468654 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 21:09:45.468968 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 21:09:45.469270 Building ramdisk /var/lib/lava/dispatcher/tmp/823597/extract-overlay-ramdisk-vqw0i3sh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/823597/extract-overlay-ramdisk-vqw0i3sh/ramdisk
215 21:09:48.103950 >> 181557 blocks
216 21:09:56.540930 Adding RAMdisk u-boot header.
217 21:09:56.541363 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/823597/extract-overlay-ramdisk-vqw0i3sh/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/823597/extract-overlay-ramdisk-vqw0i3sh/ramdisk.cpio.gz.uboot
218 21:09:56.811151 output: Image Name:
219 21:09:56.811559 output: Created: Tue Oct 8 21:09:56 2024
220 21:09:56.811768 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 21:09:56.811971 output: Data Size: 26051053 Bytes = 25440.48 KiB = 24.84 MiB
222 21:09:56.812457 output: Load Address: 00000000
223 21:09:56.812852 output: Entry Point: 00000000
224 21:09:56.813254 output:
225 21:09:56.814289 rename /var/lib/lava/dispatcher/tmp/823597/extract-overlay-ramdisk-vqw0i3sh/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/ramdisk/ramdisk.cpio.gz.uboot
226 21:09:56.814999 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 21:09:56.815529 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 21:09:56.816076 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 21:09:56.816533 No LXC device requested
230 21:09:56.817029 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 21:09:56.817530 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 21:09:56.818011 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 21:09:56.818414 Checking files for TFTP limit of 4294967296 bytes.
234 21:09:56.821122 end: 1 tftp-deploy (duration 00:00:17) [common]
235 21:09:56.821731 start: 2 uboot-action (timeout 00:05:00) [common]
236 21:09:56.822252 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 21:09:56.822746 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 21:09:56.823238 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 21:09:56.823764 Using kernel file from prepare-kernel: 823597/tftp-deploy-sxzrn4ne/kernel/uImage
240 21:09:56.824419 substitutions:
241 21:09:56.824831 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 21:09:56.825229 - {DTB_ADDR}: 0x01070000
243 21:09:56.825620 - {DTB}: 823597/tftp-deploy-sxzrn4ne/dtb/meson-g12b-a311d-libretech-cc.dtb
244 21:09:56.826014 - {INITRD}: 823597/tftp-deploy-sxzrn4ne/ramdisk/ramdisk.cpio.gz.uboot
245 21:09:56.826404 - {KERNEL_ADDR}: 0x01080000
246 21:09:56.826793 - {KERNEL}: 823597/tftp-deploy-sxzrn4ne/kernel/uImage
247 21:09:56.827180 - {LAVA_MAC}: None
248 21:09:56.827604 - {PRESEED_CONFIG}: None
249 21:09:56.828015 - {PRESEED_LOCAL}: None
250 21:09:56.828411 - {RAMDISK_ADDR}: 0x08000000
251 21:09:56.828795 - {RAMDISK}: 823597/tftp-deploy-sxzrn4ne/ramdisk/ramdisk.cpio.gz.uboot
252 21:09:56.829188 - {ROOT_PART}: None
253 21:09:56.829573 - {ROOT}: None
254 21:09:56.829961 - {SERVER_IP}: 192.168.6.2
255 21:09:56.830351 - {TEE_ADDR}: 0x83000000
256 21:09:56.830735 - {TEE}: None
257 21:09:56.831121 Parsed boot commands:
258 21:09:56.831492 - setenv autoload no
259 21:09:56.831873 - setenv initrd_high 0xffffffff
260 21:09:56.832283 - setenv fdt_high 0xffffffff
261 21:09:56.832666 - dhcp
262 21:09:56.833048 - setenv serverip 192.168.6.2
263 21:09:56.833429 - tftpboot 0x01080000 823597/tftp-deploy-sxzrn4ne/kernel/uImage
264 21:09:56.833812 - tftpboot 0x08000000 823597/tftp-deploy-sxzrn4ne/ramdisk/ramdisk.cpio.gz.uboot
265 21:09:56.834198 - tftpboot 0x01070000 823597/tftp-deploy-sxzrn4ne/dtb/meson-g12b-a311d-libretech-cc.dtb
266 21:09:56.834581 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 21:09:56.834970 - bootm 0x01080000 0x08000000 0x01070000
268 21:09:56.835469 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 21:09:56.836966 start: 2.3 connect-device (timeout 00:05:00) [common]
271 21:09:56.837403 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 21:09:56.852367 Setting prompt string to ['lava-test: # ']
273 21:09:56.853866 end: 2.3 connect-device (duration 00:00:00) [common]
274 21:09:56.854461 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 21:09:56.854985 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 21:09:56.855500 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 21:09:56.856707 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 21:09:56.900085 >> OK - accepted request
279 21:09:56.902122 Returned 0 in 0 seconds
280 21:09:57.003017 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 21:09:57.004744 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 21:09:57.005308 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 21:09:57.005809 Setting prompt string to ['Hit any key to stop autoboot']
285 21:09:57.006260 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 21:09:57.007834 Trying 192.168.56.21...
287 21:09:57.008353 Connected to conserv1.
288 21:09:57.008763 Escape character is '^]'.
289 21:09:57.009182
290 21:09:57.009603 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 21:09:57.010022
292 21:10:08.073561 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 21:10:08.073992 bl2_stage_init 0x01
294 21:10:08.074231 bl2_stage_init 0x81
295 21:10:08.079152 hw id: 0x0000 - pwm id 0x01
296 21:10:08.079467 bl2_stage_init 0xc1
297 21:10:08.079684 bl2_stage_init 0x02
298 21:10:08.079904
299 21:10:08.084703 L0:00000000
300 21:10:08.084952 L1:20000703
301 21:10:08.085162 L2:00008067
302 21:10:08.085365 L3:14000000
303 21:10:08.090281 B2:00402000
304 21:10:08.090521 B1:e0f83180
305 21:10:08.090729
306 21:10:08.090933 TE: 58167
307 21:10:08.091137
308 21:10:08.095939 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 21:10:08.096203
310 21:10:08.096412 Board ID = 1
311 21:10:08.101482 Set A53 clk to 24M
312 21:10:08.101724 Set A73 clk to 24M
313 21:10:08.101928 Set clk81 to 24M
314 21:10:08.107108 A53 clk: 1200 MHz
315 21:10:08.107348 A73 clk: 1200 MHz
316 21:10:08.107554 CLK81: 166.6M
317 21:10:08.107755 smccc: 00012abe
318 21:10:08.112688 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 21:10:08.118281 board id: 1
320 21:10:08.124198 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 21:10:08.134847 fw parse done
322 21:10:08.140794 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 21:10:08.183454 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 21:10:08.194331 PIEI prepare done
325 21:10:08.194598 fastboot data load
326 21:10:08.194808 fastboot data verify
327 21:10:08.200028 verify result: 266
328 21:10:08.205559 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 21:10:08.205823 LPDDR4 probe
330 21:10:08.206034 ddr clk to 1584MHz
331 21:10:08.213523 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 21:10:08.250792
333 21:10:08.251092 dmc_version 0001
334 21:10:08.257456 Check phy result
335 21:10:08.263336 INFO : End of CA training
336 21:10:08.263586 INFO : End of initialization
337 21:10:08.268962 INFO : Training has run successfully!
338 21:10:08.269219 Check phy result
339 21:10:08.274546 INFO : End of initialization
340 21:10:08.274804 INFO : End of read enable training
341 21:10:08.280166 INFO : End of fine write leveling
342 21:10:08.285761 INFO : End of Write leveling coarse delay
343 21:10:08.286031 INFO : Training has run successfully!
344 21:10:08.286244 Check phy result
345 21:10:08.291323 INFO : End of initialization
346 21:10:08.291573 INFO : End of read dq deskew training
347 21:10:08.296938 INFO : End of MPR read delay center optimization
348 21:10:08.302654 INFO : End of write delay center optimization
349 21:10:08.308228 INFO : End of read delay center optimization
350 21:10:08.308733 INFO : End of max read latency training
351 21:10:08.313829 INFO : Training has run successfully!
352 21:10:08.314345 1D training succeed
353 21:10:08.323037 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 21:10:08.370600 Check phy result
355 21:10:08.371158 INFO : End of initialization
356 21:10:08.393338 INFO : End of 2D read delay Voltage center optimization
357 21:10:08.413603 INFO : End of 2D read delay Voltage center optimization
358 21:10:08.465597 INFO : End of 2D write delay Voltage center optimization
359 21:10:08.514978 INFO : End of 2D write delay Voltage center optimization
360 21:10:08.520421 INFO : Training has run successfully!
361 21:10:08.520960
362 21:10:08.521406 channel==0
363 21:10:08.525988 RxClkDly_Margin_A0==88 ps 9
364 21:10:08.526489 TxDqDly_Margin_A0==98 ps 10
365 21:10:08.531668 RxClkDly_Margin_A1==88 ps 9
366 21:10:08.532154 TxDqDly_Margin_A1==98 ps 10
367 21:10:08.532561 TrainedVREFDQ_A0==74
368 21:10:08.537269 TrainedVREFDQ_A1==74
369 21:10:08.537804 VrefDac_Margin_A0==25
370 21:10:08.538255 DeviceVref_Margin_A0==40
371 21:10:08.542787 VrefDac_Margin_A1==25
372 21:10:08.543278 DeviceVref_Margin_A1==40
373 21:10:08.543675
374 21:10:08.544181
375 21:10:08.548518 channel==1
376 21:10:08.548995 RxClkDly_Margin_A0==98 ps 10
377 21:10:08.549396 TxDqDly_Margin_A0==98 ps 10
378 21:10:08.554047 RxClkDly_Margin_A1==98 ps 10
379 21:10:08.554486 TxDqDly_Margin_A1==98 ps 10
380 21:10:08.559659 TrainedVREFDQ_A0==77
381 21:10:08.560221 TrainedVREFDQ_A1==77
382 21:10:08.560659 VrefDac_Margin_A0==23
383 21:10:08.565335 DeviceVref_Margin_A0==37
384 21:10:08.565823 VrefDac_Margin_A1==24
385 21:10:08.570880 DeviceVref_Margin_A1==37
386 21:10:08.571360
387 21:10:08.571853 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 21:10:08.576438
389 21:10:08.604445 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 21:10:08.605060 2D training succeed
391 21:10:08.610037 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 21:10:08.615623 auto size-- 65535DDR cs0 size: 2048MB
393 21:10:08.616200 DDR cs1 size: 2048MB
394 21:10:08.621274 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 21:10:08.621784 cs0 DataBus test pass
396 21:10:08.626839 cs1 DataBus test pass
397 21:10:08.627345 cs0 AddrBus test pass
398 21:10:08.627739 cs1 AddrBus test pass
399 21:10:08.628182
400 21:10:08.632466 100bdlr_step_size ps== 420
401 21:10:08.632941 result report
402 21:10:08.638089 boot times 0Enable ddr reg access
403 21:10:08.643555 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 21:10:08.657041 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 21:10:09.230834 0.0;M3 CHK:0;cm4_sp_mode 0
406 21:10:09.231489 MVN_1=0x00000000
407 21:10:09.236330 MVN_2=0x00000000
408 21:10:09.242031 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 21:10:09.242603 OPS=0x10
410 21:10:09.243019 ring efuse init
411 21:10:09.243460 chipver efuse init
412 21:10:09.247600 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 21:10:09.253325 [0.018961 Inits done]
414 21:10:09.253845 secure task start!
415 21:10:09.254259 high task start!
416 21:10:09.257793 low task start!
417 21:10:09.258228 run into bl31
418 21:10:09.264351 NOTICE: BL31: v1.3(release):4fc40b1
419 21:10:09.272176 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 21:10:09.272645 NOTICE: BL31: G12A normal boot!
421 21:10:09.298551 NOTICE: BL31: BL33 decompress pass
422 21:10:09.303253 ERROR: Error initializing runtime service opteed_fast
423 21:10:10.536160
424 21:10:10.536791
425 21:10:10.544542 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 21:10:10.545001
427 21:10:10.545404 Model: Libre Computer AML-A311D-CC Alta
428 21:10:10.753039 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 21:10:10.777374 DRAM: 2 GiB (effective 3.8 GiB)
430 21:10:10.919462 Core: 408 devices, 31 uclasses, devicetree: separate
431 21:10:10.925152 WDT: Not starting watchdog@f0d0
432 21:10:10.957570 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 21:10:10.969847 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 21:10:10.974941 ** Bad device specification mmc 0 **
435 21:10:10.985254 Card did not respond to voltage select! : -110
436 21:10:10.992926 ** Bad device specification mmc 0 **
437 21:10:10.993582 Couldn't find partition mmc 0
438 21:10:11.001156 Card did not respond to voltage select! : -110
439 21:10:11.006681 ** Bad device specification mmc 0 **
440 21:10:11.006909 Couldn't find partition mmc 0
441 21:10:11.011718 Error: could not access storage.
442 21:10:12.273848 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 21:10:12.274460 bl2_stage_init 0x01
444 21:10:12.274885 bl2_stage_init 0x81
445 21:10:12.279442 hw id: 0x0000 - pwm id 0x01
446 21:10:12.279892 bl2_stage_init 0xc1
447 21:10:12.280360 bl2_stage_init 0x02
448 21:10:12.280764
449 21:10:12.285033 L0:00000000
450 21:10:12.285493 L1:20000703
451 21:10:12.285897 L2:00008067
452 21:10:12.286291 L3:14000000
453 21:10:12.287905 B2:00402000
454 21:10:12.288363 B1:e0f83180
455 21:10:12.288770
456 21:10:12.289170 TE: 58167
457 21:10:12.289568
458 21:10:12.299126 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 21:10:12.299582
460 21:10:12.300017 Board ID = 1
461 21:10:12.300423 Set A53 clk to 24M
462 21:10:12.300816 Set A73 clk to 24M
463 21:10:12.304706 Set clk81 to 24M
464 21:10:12.305140 A53 clk: 1200 MHz
465 21:10:12.305543 A73 clk: 1200 MHz
466 21:10:12.310283 CLK81: 166.6M
467 21:10:12.310712 smccc: 00012abe
468 21:10:12.316002 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 21:10:12.316461 board id: 1
470 21:10:12.324690 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 21:10:12.335327 fw parse done
472 21:10:12.341294 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 21:10:12.383879 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 21:10:12.394793 PIEI prepare done
475 21:10:12.395283 fastboot data load
476 21:10:12.395694 fastboot data verify
477 21:10:12.400455 verify result: 266
478 21:10:12.405994 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 21:10:12.406448 LPDDR4 probe
480 21:10:12.406857 ddr clk to 1584MHz
481 21:10:12.414027 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 21:10:12.451284
483 21:10:12.451782 dmc_version 0001
484 21:10:12.457835 Check phy result
485 21:10:12.463754 INFO : End of CA training
486 21:10:12.464224 INFO : End of initialization
487 21:10:12.469369 INFO : Training has run successfully!
488 21:10:12.469806 Check phy result
489 21:10:12.474908 INFO : End of initialization
490 21:10:12.475337 INFO : End of read enable training
491 21:10:12.478221 INFO : End of fine write leveling
492 21:10:12.483844 INFO : End of Write leveling coarse delay
493 21:10:12.489390 INFO : Training has run successfully!
494 21:10:12.489829 Check phy result
495 21:10:12.490228 INFO : End of initialization
496 21:10:12.494959 INFO : End of read dq deskew training
497 21:10:12.498406 INFO : End of MPR read delay center optimization
498 21:10:12.504030 INFO : End of write delay center optimization
499 21:10:12.509600 INFO : End of read delay center optimization
500 21:10:12.510028 INFO : End of max read latency training
501 21:10:12.515167 INFO : Training has run successfully!
502 21:10:12.515616 1D training succeed
503 21:10:12.523369 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 21:10:12.570930 Check phy result
505 21:10:12.571409 INFO : End of initialization
506 21:10:12.594933 INFO : End of 2D read delay Voltage center optimization
507 21:10:12.613858 INFO : End of 2D read delay Voltage center optimization
508 21:10:12.666070 INFO : End of 2D write delay Voltage center optimization
509 21:10:12.715307 INFO : End of 2D write delay Voltage center optimization
510 21:10:12.720898 INFO : Training has run successfully!
511 21:10:12.721353
512 21:10:12.721764 channel==0
513 21:10:12.726431 RxClkDly_Margin_A0==88 ps 9
514 21:10:12.726865 TxDqDly_Margin_A0==98 ps 10
515 21:10:12.732080 RxClkDly_Margin_A1==88 ps 9
516 21:10:12.732524 TxDqDly_Margin_A1==98 ps 10
517 21:10:12.732932 TrainedVREFDQ_A0==74
518 21:10:12.737627 TrainedVREFDQ_A1==74
519 21:10:12.738082 VrefDac_Margin_A0==25
520 21:10:12.738485 DeviceVref_Margin_A0==40
521 21:10:12.743157 VrefDac_Margin_A1==25
522 21:10:12.743590 DeviceVref_Margin_A1==40
523 21:10:12.744023
524 21:10:12.744428
525 21:10:12.748939 channel==1
526 21:10:12.749385 RxClkDly_Margin_A0==98 ps 10
527 21:10:12.749788 TxDqDly_Margin_A0==88 ps 9
528 21:10:12.754444 RxClkDly_Margin_A1==88 ps 9
529 21:10:12.754876 TxDqDly_Margin_A1==88 ps 9
530 21:10:12.760057 TrainedVREFDQ_A0==76
531 21:10:12.760499 TrainedVREFDQ_A1==77
532 21:10:12.760901 VrefDac_Margin_A0==23
533 21:10:12.765623 DeviceVref_Margin_A0==38
534 21:10:12.766060 VrefDac_Margin_A1==24
535 21:10:12.771163 DeviceVref_Margin_A1==37
536 21:10:12.771588
537 21:10:12.772013 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 21:10:12.772412
539 21:10:12.804860 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 21:10:12.805344 2D training succeed
541 21:10:12.810401 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 21:10:12.815976 auto size-- 65535DDR cs0 size: 2048MB
543 21:10:12.816438 DDR cs1 size: 2048MB
544 21:10:12.821621 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 21:10:12.822053 cs0 DataBus test pass
546 21:10:12.827223 cs1 DataBus test pass
547 21:10:12.827646 cs0 AddrBus test pass
548 21:10:12.828076 cs1 AddrBus test pass
549 21:10:12.828480
550 21:10:12.832857 100bdlr_step_size ps== 420
551 21:10:12.833296 result report
552 21:10:12.838392 boot times 0Enable ddr reg access
553 21:10:12.843677 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 21:10:12.857244 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 21:10:13.430909 0.0;M3 CHK:0;cm4_sp_mode 0
556 21:10:13.431523 MVN_1=0x00000000
557 21:10:13.436300 MVN_2=0x00000000
558 21:10:13.442068 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 21:10:13.442580 OPS=0x10
560 21:10:13.443020 ring efuse init
561 21:10:13.443425 chipver efuse init
562 21:10:13.447648 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 21:10:13.453246 [0.018961 Inits done]
564 21:10:13.453682 secure task start!
565 21:10:13.454067 high task start!
566 21:10:13.457812 low task start!
567 21:10:13.458232 run into bl31
568 21:10:13.464478 NOTICE: BL31: v1.3(release):4fc40b1
569 21:10:13.472284 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 21:10:13.472746 NOTICE: BL31: G12A normal boot!
571 21:10:13.497705 NOTICE: BL31: BL33 decompress pass
572 21:10:13.503348 ERROR: Error initializing runtime service opteed_fast
573 21:10:14.736242
574 21:10:14.736640
575 21:10:14.744618 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 21:10:14.744906
577 21:10:14.745112 Model: Libre Computer AML-A311D-CC Alta
578 21:10:14.953158 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 21:10:14.976511 DRAM: 2 GiB (effective 3.8 GiB)
580 21:10:15.119623 Core: 408 devices, 31 uclasses, devicetree: separate
581 21:10:15.125340 WDT: Not starting watchdog@f0d0
582 21:10:15.157659 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 21:10:15.170140 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 21:10:15.175057 ** Bad device specification mmc 0 **
585 21:10:15.185458 Card did not respond to voltage select! : -110
586 21:10:15.193167 ** Bad device specification mmc 0 **
587 21:10:15.193813 Couldn't find partition mmc 0
588 21:10:15.202674 Card did not respond to voltage select! : -110
589 21:10:15.207004 ** Bad device specification mmc 0 **
590 21:10:15.207617 Couldn't find partition mmc 0
591 21:10:15.212108 Error: could not access storage.
592 21:10:15.554493 Net: eth0: ethernet@ff3f0000
593 21:10:15.555172 starting USB...
594 21:10:15.806392 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 21:10:15.807058 Starting the controller
596 21:10:15.813211 USB XHCI 1.10
597 21:10:17.474223 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
598 21:10:17.474923 bl2_stage_init 0x81
599 21:10:17.479793 hw id: 0x0000 - pwm id 0x01
600 21:10:17.480350 bl2_stage_init 0xc1
601 21:10:17.480813 bl2_stage_init 0x02
602 21:10:17.481260
603 21:10:17.485407 L0:00000000
604 21:10:17.485912 L1:20000703
605 21:10:17.486367 L2:00008067
606 21:10:17.486810 L3:14000000
607 21:10:17.487248 B2:00402000
608 21:10:17.490959 B1:e0f83180
609 21:10:17.491456
610 21:10:17.491907 TE: 58150
611 21:10:17.492391
612 21:10:17.496577 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 21:10:17.497077
614 21:10:17.497529 Board ID = 1
615 21:10:17.502158 Set A53 clk to 24M
616 21:10:17.502649 Set A73 clk to 24M
617 21:10:17.503096 Set clk81 to 24M
618 21:10:17.507750 A53 clk: 1200 MHz
619 21:10:17.508273 A73 clk: 1200 MHz
620 21:10:17.508724 CLK81: 166.6M
621 21:10:17.509161 smccc: 00012aab
622 21:10:17.513468 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 21:10:17.518944 board id: 1
624 21:10:17.523790 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 21:10:17.535393 fw parse done
626 21:10:17.540400 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 21:10:17.583024 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 21:10:17.594851 PIEI prepare done
629 21:10:17.595162 fastboot data load
630 21:10:17.595400 fastboot data verify
631 21:10:17.600544 verify result: 266
632 21:10:17.606112 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 21:10:17.606539 LPDDR4 probe
634 21:10:17.606908 ddr clk to 1584MHz
635 21:10:17.613173 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 21:10:17.650452
637 21:10:17.650792 dmc_version 0001
638 21:10:17.657106 Check phy result
639 21:10:17.663916 INFO : End of CA training
640 21:10:17.664263 INFO : End of initialization
641 21:10:17.669590 INFO : Training has run successfully!
642 21:10:17.670046 Check phy result
643 21:10:17.675112 INFO : End of initialization
644 21:10:17.675559 INFO : End of read enable training
645 21:10:17.678503 INFO : End of fine write leveling
646 21:10:17.684042 INFO : End of Write leveling coarse delay
647 21:10:17.689644 INFO : Training has run successfully!
648 21:10:17.689973 Check phy result
649 21:10:17.690211 INFO : End of initialization
650 21:10:17.695269 INFO : End of read dq deskew training
651 21:10:17.698666 INFO : End of MPR read delay center optimization
652 21:10:17.704271 INFO : End of write delay center optimization
653 21:10:17.709854 INFO : End of read delay center optimization
654 21:10:17.710254 INFO : End of max read latency training
655 21:10:17.715556 INFO : Training has run successfully!
656 21:10:17.715909 1D training succeed
657 21:10:17.722660 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 21:10:17.770145 Check phy result
659 21:10:17.770508 INFO : End of initialization
660 21:10:17.792729 INFO : End of 2D read delay Voltage center optimization
661 21:10:17.812871 INFO : End of 2D read delay Voltage center optimization
662 21:10:17.865155 INFO : End of 2D write delay Voltage center optimization
663 21:10:17.915559 INFO : End of 2D write delay Voltage center optimization
664 21:10:17.921296 INFO : Training has run successfully!
665 21:10:17.921820
666 21:10:17.922269 channel==0
667 21:10:17.926904 RxClkDly_Margin_A0==88 ps 9
668 21:10:17.927422 TxDqDly_Margin_A0==108 ps 11
669 21:10:17.932427 RxClkDly_Margin_A1==88 ps 9
670 21:10:17.932936 TxDqDly_Margin_A1==98 ps 10
671 21:10:17.933377 TrainedVREFDQ_A0==74
672 21:10:17.938109 TrainedVREFDQ_A1==74
673 21:10:17.938632 VrefDac_Margin_A0==25
674 21:10:17.943526 DeviceVref_Margin_A0==40
675 21:10:17.944062 VrefDac_Margin_A1==25
676 21:10:17.944487 DeviceVref_Margin_A1==40
677 21:10:17.944887
678 21:10:17.945289
679 21:10:17.949192 channel==1
680 21:10:17.949703 RxClkDly_Margin_A0==98 ps 10
681 21:10:17.950126 TxDqDly_Margin_A0==98 ps 10
682 21:10:17.954809 RxClkDly_Margin_A1==98 ps 10
683 21:10:17.955307 TxDqDly_Margin_A1==98 ps 10
684 21:10:17.960399 TrainedVREFDQ_A0==77
685 21:10:17.960924 TrainedVREFDQ_A1==78
686 21:10:17.961349 VrefDac_Margin_A0==24
687 21:10:17.966022 DeviceVref_Margin_A0==37
688 21:10:17.966514 VrefDac_Margin_A1==23
689 21:10:17.971645 DeviceVref_Margin_A1==36
690 21:10:17.972159
691 21:10:17.977321 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 21:10:17.977814
693 21:10:18.004923 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000061
694 21:10:18.005477 2D training succeed
695 21:10:18.010716 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 21:10:18.016226 auto size-- 65535DDR cs0 size: 2048MB
697 21:10:18.016718 DDR cs1 size: 2048MB
698 21:10:18.021861 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 21:10:18.022482 cs0 DataBus test pass
700 21:10:18.027481 cs1 DataBus test pass
701 21:10:18.028205 cs0 AddrBus test pass
702 21:10:18.028768 cs1 AddrBus test pass
703 21:10:18.029301
704 21:10:18.033022 100bdlr_step_size ps== 420
705 21:10:18.033526 result report
706 21:10:18.038647 boot times 0Enable ddr reg access
707 21:10:18.043204 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 21:10:18.056731 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 21:10:18.631353 0.0;M3 CHK:0;cm4_sp_mode 0
710 21:10:18.632015 MVN_1=0x00000000
711 21:10:18.637065 MVN_2=0x00000000
712 21:10:18.642730 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 21:10:18.643257 OPS=0x10
714 21:10:18.643714 ring efuse init
715 21:10:18.644192 chipver efuse init
716 21:10:18.650901 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 21:10:18.651423 [0.018961 Inits done]
718 21:10:18.651821 secure task start!
719 21:10:18.658392 high task start!
720 21:10:18.658862 low task start!
721 21:10:18.659253 run into bl31
722 21:10:18.665029 NOTICE: BL31: v1.3(release):4fc40b1
723 21:10:18.672861 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 21:10:18.673375 NOTICE: BL31: G12A normal boot!
725 21:10:18.698734 NOTICE: BL31: BL33 decompress pass
726 21:10:18.704450 ERROR: Error initializing runtime service opteed_fast
727 21:10:19.937317
728 21:10:19.937905
729 21:10:19.944888 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 21:10:19.945376
731 21:10:19.945794 Model: Libre Computer AML-A311D-CC Alta
732 21:10:20.153260 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 21:10:20.176709 DRAM: 2 GiB (effective 3.8 GiB)
734 21:10:20.320644 Core: 408 devices, 31 uclasses, devicetree: separate
735 21:10:20.325433 WDT: Not starting watchdog@f0d0
736 21:10:20.358660 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 21:10:20.371150 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 21:10:20.375290 ** Bad device specification mmc 0 **
739 21:10:20.386473 Card did not respond to voltage select! : -110
740 21:10:20.393103 ** Bad device specification mmc 0 **
741 21:10:20.393569 Couldn't find partition mmc 0
742 21:10:20.402417 Card did not respond to voltage select! : -110
743 21:10:20.408023 ** Bad device specification mmc 0 **
744 21:10:20.408494 Couldn't find partition mmc 0
745 21:10:20.412084 Error: could not access storage.
746 21:10:20.755657 Net: eth0: ethernet@ff3f0000
747 21:10:20.756274 starting USB...
748 21:10:21.008311 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 21:10:21.008896 Starting the controller
750 21:10:21.014360 USB XHCI 1.10
751 21:10:23.174442 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
752 21:10:23.175061 bl2_stage_init 0x81
753 21:10:23.179874 hw id: 0x0000 - pwm id 0x01
754 21:10:23.180394 bl2_stage_init 0xc1
755 21:10:23.180815 bl2_stage_init 0x02
756 21:10:23.181225
757 21:10:23.185551 L0:00000000
758 21:10:23.186010 L1:20000703
759 21:10:23.186417 L2:00008067
760 21:10:23.186815 L3:14000000
761 21:10:23.187206 B2:00402000
762 21:10:23.188435 B1:e0f83180
763 21:10:23.188891
764 21:10:23.189298 TE: 58150
765 21:10:23.189697
766 21:10:23.199595 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 21:10:23.200143
768 21:10:23.200575 Board ID = 1
769 21:10:23.200981 Set A53 clk to 24M
770 21:10:23.201382 Set A73 clk to 24M
771 21:10:23.205244 Set clk81 to 24M
772 21:10:23.205720 A53 clk: 1200 MHz
773 21:10:23.206134 A73 clk: 1200 MHz
774 21:10:23.208639 CLK81: 166.6M
775 21:10:23.209096 smccc: 00012aab
776 21:10:23.214153 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 21:10:23.219741 board id: 1
778 21:10:23.224877 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 21:10:23.235599 fw parse done
780 21:10:23.241544 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 21:10:23.284181 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 21:10:23.295228 PIEI prepare done
783 21:10:23.295728 fastboot data load
784 21:10:23.296189 fastboot data verify
785 21:10:23.300699 verify result: 266
786 21:10:23.306439 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 21:10:23.306923 LPDDR4 probe
788 21:10:23.307339 ddr clk to 1584MHz
789 21:10:23.314342 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 21:10:23.351659
791 21:10:23.352226 dmc_version 0001
792 21:10:23.358271 Check phy result
793 21:10:23.364091 INFO : End of CA training
794 21:10:23.364581 INFO : End of initialization
795 21:10:23.369735 INFO : Training has run successfully!
796 21:10:23.370211 Check phy result
797 21:10:23.375322 INFO : End of initialization
798 21:10:23.375799 INFO : End of read enable training
799 21:10:23.380903 INFO : End of fine write leveling
800 21:10:23.386493 INFO : End of Write leveling coarse delay
801 21:10:23.386954 INFO : Training has run successfully!
802 21:10:23.387362 Check phy result
803 21:10:23.392011 INFO : End of initialization
804 21:10:23.392460 INFO : End of read dq deskew training
805 21:10:23.397620 INFO : End of MPR read delay center optimization
806 21:10:23.403173 INFO : End of write delay center optimization
807 21:10:23.408804 INFO : End of read delay center optimization
808 21:10:23.409108 INFO : End of max read latency training
809 21:10:23.414391 INFO : Training has run successfully!
810 21:10:23.414692 1D training succeed
811 21:10:23.423576 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 21:10:23.471145 Check phy result
813 21:10:23.471489 INFO : End of initialization
814 21:10:23.493731 INFO : End of 2D read delay Voltage center optimization
815 21:10:23.512990 INFO : End of 2D read delay Voltage center optimization
816 21:10:23.565877 INFO : End of 2D write delay Voltage center optimization
817 21:10:23.615118 INFO : End of 2D write delay Voltage center optimization
818 21:10:23.620612 INFO : Training has run successfully!
819 21:10:23.621131
820 21:10:23.621560 channel==0
821 21:10:23.626285 RxClkDly_Margin_A0==88 ps 9
822 21:10:23.626808 TxDqDly_Margin_A0==98 ps 10
823 21:10:23.629787 RxClkDly_Margin_A1==88 ps 9
824 21:10:23.630299 TxDqDly_Margin_A1==98 ps 10
825 21:10:23.635068 TrainedVREFDQ_A0==74
826 21:10:23.635613 TrainedVREFDQ_A1==74
827 21:10:23.640620 VrefDac_Margin_A0==25
828 21:10:23.640948 DeviceVref_Margin_A0==40
829 21:10:23.641222 VrefDac_Margin_A1==25
830 21:10:23.646013 DeviceVref_Margin_A1==40
831 21:10:23.646312
832 21:10:23.646527
833 21:10:23.646731 channel==1
834 21:10:23.646931 RxClkDly_Margin_A0==98 ps 10
835 21:10:23.649894 TxDqDly_Margin_A0==88 ps 9
836 21:10:23.655573 RxClkDly_Margin_A1==98 ps 10
837 21:10:23.655867 TxDqDly_Margin_A1==88 ps 9
838 21:10:23.656113 TrainedVREFDQ_A0==76
839 21:10:23.661072 TrainedVREFDQ_A1==77
840 21:10:23.661413 VrefDac_Margin_A0==22
841 21:10:23.666735 DeviceVref_Margin_A0==38
842 21:10:23.667029 VrefDac_Margin_A1==22
843 21:10:23.667240 DeviceVref_Margin_A1==37
844 21:10:23.667442
845 21:10:23.672402 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 21:10:23.672753
847 21:10:23.706006 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
848 21:10:23.706393 2D training succeed
849 21:10:23.711583 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 21:10:23.717096 auto size-- 65535DDR cs0 size: 2048MB
851 21:10:23.717506 DDR cs1 size: 2048MB
852 21:10:23.722686 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 21:10:23.723020 cs0 DataBus test pass
854 21:10:23.723229 cs1 DataBus test pass
855 21:10:23.728295 cs0 AddrBus test pass
856 21:10:23.728633 cs1 AddrBus test pass
857 21:10:23.728861
858 21:10:23.733855 100bdlr_step_size ps== 420
859 21:10:23.734211 result report
860 21:10:23.734426 boot times 0Enable ddr reg access
861 21:10:23.743371 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 21:10:23.755799 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 21:10:24.328826 0.0;M3 CHK:0;cm4_sp_mode 0
864 21:10:24.329246 MVN_1=0x00000000
865 21:10:24.334457 MVN_2=0x00000000
866 21:10:24.340075 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 21:10:24.340369 OPS=0x10
868 21:10:24.340584 ring efuse init
869 21:10:24.340787 chipver efuse init
870 21:10:24.345630 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 21:10:24.351336 [0.018961 Inits done]
872 21:10:24.351787 secure task start!
873 21:10:24.352160 high task start!
874 21:10:24.355798 low task start!
875 21:10:24.356228 run into bl31
876 21:10:24.362567 NOTICE: BL31: v1.3(release):4fc40b1
877 21:10:24.370047 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 21:10:24.370394 NOTICE: BL31: G12A normal boot!
879 21:10:24.395728 NOTICE: BL31: BL33 decompress pass
880 21:10:24.401487 ERROR: Error initializing runtime service opteed_fast
881 21:10:25.634213
882 21:10:25.634666
883 21:10:25.642665 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 21:10:25.643138
885 21:10:25.643388 Model: Libre Computer AML-A311D-CC Alta
886 21:10:25.850169 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 21:10:25.874435 DRAM: 2 GiB (effective 3.8 GiB)
888 21:10:26.017488 Core: 408 devices, 31 uclasses, devicetree: separate
889 21:10:26.023219 WDT: Not starting watchdog@f0d0
890 21:10:26.055594 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 21:10:26.067926 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 21:10:26.072912 ** Bad device specification mmc 0 **
893 21:10:26.083237 Card did not respond to voltage select! : -110
894 21:10:26.090010 ** Bad device specification mmc 0 **
895 21:10:26.090590 Couldn't find partition mmc 0
896 21:10:26.099259 Card did not respond to voltage select! : -110
897 21:10:26.104774 ** Bad device specification mmc 0 **
898 21:10:26.105329 Couldn't find partition mmc 0
899 21:10:26.109828 Error: could not access storage.
900 21:10:26.452379 Net: eth0: ethernet@ff3f0000
901 21:10:26.452787 starting USB...
902 21:10:26.704302 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 21:10:26.704724 Starting the controller
904 21:10:26.710200 USB XHCI 1.10
905 21:10:28.265110 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
906 21:10:28.273431 scanning usb for storage devices... 0 Storage Device(s) found
908 21:10:28.324515 Hit any key to stop autoboot: 1
909 21:10:28.325132 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
910 21:10:28.325473 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
911 21:10:28.325735 Setting prompt string to ['=>']
912 21:10:28.325990 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
913 21:10:28.329931 0
914 21:10:28.330521 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
915 21:10:28.330785 Sending with 10 millisecond of delay
917 21:10:29.465034 => setenv autoload no
918 21:10:29.475621 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
919 21:10:29.478343 setenv autoload no
920 21:10:29.478854 Sending with 10 millisecond of delay
922 21:10:31.275224 => setenv initrd_high 0xffffffff
923 21:10:31.285800 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
924 21:10:31.286653 setenv initrd_high 0xffffffff
925 21:10:31.287561 Sending with 10 millisecond of delay
927 21:10:32.905299 => setenv fdt_high 0xffffffff
928 21:10:32.915860 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
929 21:10:32.916354 setenv fdt_high 0xffffffff
930 21:10:32.916808 Sending with 10 millisecond of delay
932 21:10:33.208167 => dhcp
933 21:10:33.218907 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
934 21:10:33.219741 dhcp
935 21:10:33.220246 Speed: 1000, full duplex
936 21:10:33.220671 BOOTP broadcast 1
937 21:10:33.467049 BOOTP broadcast 2
938 21:10:33.570765 DHCP client bound to address 192.168.6.33 (351 ms)
939 21:10:33.571414 Sending with 10 millisecond of delay
941 21:10:35.249730 => setenv serverip 192.168.6.2
942 21:10:35.260593 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
943 21:10:35.261744 setenv serverip 192.168.6.2
944 21:10:35.262588 Sending with 10 millisecond of delay
946 21:10:38.986139 => tftpboot 0x01080000 823597/tftp-deploy-sxzrn4ne/kernel/uImage
947 21:10:38.996713 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
948 21:10:38.997228 tftpboot 0x01080000 823597/tftp-deploy-sxzrn4ne/kernel/uImage
949 21:10:38.997472 Speed: 1000, full duplex
950 21:10:38.997684 Using ethernet@ff3f0000 device
951 21:10:38.999518 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
952 21:10:39.004925 Filename '823597/tftp-deploy-sxzrn4ne/kernel/uImage'.
953 21:10:39.009145 Load address: 0x1080000
954 21:10:43.376597 Loading: *################################################## 43.6 MiB
955 21:10:43.376998 10 MiB/s
956 21:10:43.377217 done
957 21:10:43.380120 Bytes transferred = 45713984 (2b98a40 hex)
958 21:10:43.380929 Sending with 10 millisecond of delay
960 21:10:48.067559 => tftpboot 0x08000000 823597/tftp-deploy-sxzrn4ne/ramdisk/ramdisk.cpio.gz.uboot
961 21:10:48.078409 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
962 21:10:48.079259 tftpboot 0x08000000 823597/tftp-deploy-sxzrn4ne/ramdisk/ramdisk.cpio.gz.uboot
963 21:10:48.079732 Speed: 1000, full duplex
964 21:10:48.080187 Using ethernet@ff3f0000 device
965 21:10:48.080933 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
966 21:10:48.089654 Filename '823597/tftp-deploy-sxzrn4ne/ramdisk/ramdisk.cpio.gz.uboot'.
967 21:10:48.090139 Load address: 0x8000000
968 21:10:50.785483 Loading: *################################################# UDP wrong checksum 00000005 00000cca
969 21:10:55.787385 T UDP wrong checksum 00000005 00000cca
970 21:11:05.789375 T T UDP wrong checksum 00000005 00000cca
971 21:11:22.030187 T T T UDP wrong checksum 000000ff 0000d5ba
972 21:11:22.059721 UDP wrong checksum 000000ff 000067ad
973 21:11:25.793082 T UDP wrong checksum 00000005 00000cca
974 21:11:29.462851 UDP wrong checksum 000000ff 00005cfd
975 21:11:29.472550 UDP wrong checksum 000000ff 0000f0ef
976 21:11:38.940929 T T UDP wrong checksum 000000ff 0000898d
977 21:11:38.970483 UDP wrong checksum 000000ff 00001e80
978 21:11:45.798210 T
979 21:11:45.798587 Retry count exceeded; starting again
981 21:11:45.799438 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
984 21:11:45.801035 end: 2.4 uboot-commands (duration 00:01:49) [common]
986 21:11:45.802379 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
988 21:11:45.803404 end: 2 uboot-action (duration 00:01:49) [common]
990 21:11:45.804961 Cleaning after the job
991 21:11:45.805517 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/ramdisk
992 21:11:45.806728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/kernel
993 21:11:45.834232 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/dtb
994 21:11:45.835498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823597/tftp-deploy-sxzrn4ne/modules
995 21:11:45.841834 start: 4.1 power-off (timeout 00:00:30) [common]
996 21:11:45.842848 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
997 21:11:45.875666 >> OK - accepted request
998 21:11:45.877430 Returned 0 in 0 seconds
999 21:11:45.978534 end: 4.1 power-off (duration 00:00:00) [common]
1001 21:11:45.980251 start: 4.2 read-feedback (timeout 00:10:00) [common]
1002 21:11:45.981367 Listened to connection for namespace 'common' for up to 1s
1003 21:11:46.981848 Finalising connection for namespace 'common'
1004 21:11:46.982548 Disconnecting from shell: Finalise
1005 21:11:46.983048 =>
1006 21:11:47.084027 end: 4.2 read-feedback (duration 00:00:01) [common]
1007 21:11:47.084653 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/823597
1008 21:11:47.357360 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/823597
1009 21:11:47.357939 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.