Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:19:19.506311 lava-dispatcher, installed at version: 2024.01
2 21:19:19.507093 start: 0 validate
3 21:19:19.507580 Start time: 2024-10-08 21:19:19.507549+00:00 (UTC)
4 21:19:19.508144 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:19:19.508692 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 21:19:19.550800 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:19:19.551331 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:19:19.579664 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:19:19.580324 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:19:19.616096 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:19:19.616593 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 21:19:19.643336 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 21:19:19.643872 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 21:19:19.682243 validate duration: 0.17
16 21:19:19.683089 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:19:19.683461 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:19:19.683812 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:19:19.684460 Not decompressing ramdisk as can be used compressed.
20 21:19:19.684917 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 21:19:19.685189 saving as /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/ramdisk/initrd.cpio.gz
22 21:19:19.685454 total size: 5628169 (5 MB)
23 21:19:19.719210 progress 0 % (0 MB)
24 21:19:19.724021 progress 5 % (0 MB)
25 21:19:19.728099 progress 10 % (0 MB)
26 21:19:19.731708 progress 15 % (0 MB)
27 21:19:19.735718 progress 20 % (1 MB)
28 21:19:19.739304 progress 25 % (1 MB)
29 21:19:19.743326 progress 30 % (1 MB)
30 21:19:19.747421 progress 35 % (1 MB)
31 21:19:19.750935 progress 40 % (2 MB)
32 21:19:19.754871 progress 45 % (2 MB)
33 21:19:19.758415 progress 50 % (2 MB)
34 21:19:19.762460 progress 55 % (2 MB)
35 21:19:19.766423 progress 60 % (3 MB)
36 21:19:19.769892 progress 65 % (3 MB)
37 21:19:19.773735 progress 70 % (3 MB)
38 21:19:19.777431 progress 75 % (4 MB)
39 21:19:19.781256 progress 80 % (4 MB)
40 21:19:19.784543 progress 85 % (4 MB)
41 21:19:19.788155 progress 90 % (4 MB)
42 21:19:19.791648 progress 95 % (5 MB)
43 21:19:19.794877 progress 100 % (5 MB)
44 21:19:19.795511 5 MB downloaded in 0.11 s (48.78 MB/s)
45 21:19:19.796075 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:19:19.797066 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:19:19.797373 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:19:19.797641 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:19:19.798112 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/kernel/Image
51 21:19:19.798351 saving as /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/kernel/Image
52 21:19:19.798562 total size: 45713920 (43 MB)
53 21:19:19.798771 No compression specified
54 21:19:19.838692 progress 0 % (0 MB)
55 21:19:19.865875 progress 5 % (2 MB)
56 21:19:19.892465 progress 10 % (4 MB)
57 21:19:19.920062 progress 15 % (6 MB)
58 21:19:19.947079 progress 20 % (8 MB)
59 21:19:19.973639 progress 25 % (10 MB)
60 21:19:20.000782 progress 30 % (13 MB)
61 21:19:20.027586 progress 35 % (15 MB)
62 21:19:20.054438 progress 40 % (17 MB)
63 21:19:20.081064 progress 45 % (19 MB)
64 21:19:20.107377 progress 50 % (21 MB)
65 21:19:20.134255 progress 55 % (24 MB)
66 21:19:20.161135 progress 60 % (26 MB)
67 21:19:20.187799 progress 65 % (28 MB)
68 21:19:20.214722 progress 70 % (30 MB)
69 21:19:20.242482 progress 75 % (32 MB)
70 21:19:20.270169 progress 80 % (34 MB)
71 21:19:20.301934 progress 85 % (37 MB)
72 21:19:20.334731 progress 90 % (39 MB)
73 21:19:20.367163 progress 95 % (41 MB)
74 21:19:20.398488 progress 100 % (43 MB)
75 21:19:20.399177 43 MB downloaded in 0.60 s (72.59 MB/s)
76 21:19:20.399763 end: 1.2.1 http-download (duration 00:00:01) [common]
78 21:19:20.400797 end: 1.2 download-retry (duration 00:00:01) [common]
79 21:19:20.401136 start: 1.3 download-retry (timeout 00:09:59) [common]
80 21:19:20.401461 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 21:19:20.402030 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 21:19:20.402372 saving as /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/dtb/meson-g12b-a311d-libretech-cc.dtb
83 21:19:20.402622 total size: 54703 (0 MB)
84 21:19:20.402876 No compression specified
85 21:19:20.437156 progress 59 % (0 MB)
86 21:19:20.438075 progress 100 % (0 MB)
87 21:19:20.438700 0 MB downloaded in 0.04 s (1.45 MB/s)
88 21:19:20.439275 end: 1.3.1 http-download (duration 00:00:00) [common]
90 21:19:20.440343 end: 1.3 download-retry (duration 00:00:00) [common]
91 21:19:20.440671 start: 1.4 download-retry (timeout 00:09:59) [common]
92 21:19:20.440991 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 21:19:20.441503 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 21:19:20.441794 saving as /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/nfsrootfs/full.rootfs.tar
95 21:19:20.442033 total size: 120894716 (115 MB)
96 21:19:20.442272 Using unxz to decompress xz
97 21:19:20.479647 progress 0 % (0 MB)
98 21:19:21.345251 progress 5 % (5 MB)
99 21:19:22.190502 progress 10 % (11 MB)
100 21:19:22.985486 progress 15 % (17 MB)
101 21:19:23.724518 progress 20 % (23 MB)
102 21:19:24.318844 progress 25 % (28 MB)
103 21:19:25.144393 progress 30 % (34 MB)
104 21:19:25.938122 progress 35 % (40 MB)
105 21:19:26.319607 progress 40 % (46 MB)
106 21:19:26.690184 progress 45 % (51 MB)
107 21:19:27.537450 progress 50 % (57 MB)
108 21:19:28.427093 progress 55 % (63 MB)
109 21:19:29.210123 progress 60 % (69 MB)
110 21:19:29.971008 progress 65 % (74 MB)
111 21:19:30.836629 progress 70 % (80 MB)
112 21:19:31.701233 progress 75 % (86 MB)
113 21:19:32.503586 progress 80 % (92 MB)
114 21:19:33.267625 progress 85 % (98 MB)
115 21:19:34.124479 progress 90 % (103 MB)
116 21:19:34.909379 progress 95 % (109 MB)
117 21:19:35.745480 progress 100 % (115 MB)
118 21:19:35.758689 115 MB downloaded in 15.32 s (7.53 MB/s)
119 21:19:35.759631 end: 1.4.1 http-download (duration 00:00:15) [common]
121 21:19:35.761804 end: 1.4 download-retry (duration 00:00:15) [common]
122 21:19:35.762485 start: 1.5 download-retry (timeout 00:09:44) [common]
123 21:19:35.763160 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 21:19:35.764264 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/modules.tar.xz
125 21:19:35.764882 saving as /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/modules/modules.tar
126 21:19:35.765423 total size: 11613728 (11 MB)
127 21:19:35.765967 Using unxz to decompress xz
128 21:19:35.812292 progress 0 % (0 MB)
129 21:19:35.875125 progress 5 % (0 MB)
130 21:19:35.954754 progress 10 % (1 MB)
131 21:19:36.044212 progress 15 % (1 MB)
132 21:19:36.136471 progress 20 % (2 MB)
133 21:19:36.219551 progress 25 % (2 MB)
134 21:19:36.297618 progress 30 % (3 MB)
135 21:19:36.380410 progress 35 % (3 MB)
136 21:19:36.456155 progress 40 % (4 MB)
137 21:19:36.533624 progress 45 % (5 MB)
138 21:19:36.615731 progress 50 % (5 MB)
139 21:19:36.694365 progress 55 % (6 MB)
140 21:19:36.779403 progress 60 % (6 MB)
141 21:19:36.854948 progress 65 % (7 MB)
142 21:19:36.935310 progress 70 % (7 MB)
143 21:19:37.008612 progress 75 % (8 MB)
144 21:19:37.085169 progress 80 % (8 MB)
145 21:19:37.169055 progress 85 % (9 MB)
146 21:19:37.247720 progress 90 % (9 MB)
147 21:19:37.329374 progress 95 % (10 MB)
148 21:19:37.408850 progress 100 % (11 MB)
149 21:19:37.421844 11 MB downloaded in 1.66 s (6.69 MB/s)
150 21:19:37.422419 end: 1.5.1 http-download (duration 00:00:02) [common]
152 21:19:37.423237 end: 1.5 download-retry (duration 00:00:02) [common]
153 21:19:37.423503 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 21:19:37.423767 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 21:19:54.901274 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/823615/extract-nfsrootfs-2brvgi69
156 21:19:54.901871 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 21:19:54.902153 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 21:19:54.902757 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk
159 21:19:54.903192 makedir: /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin
160 21:19:54.903574 makedir: /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/tests
161 21:19:54.903891 makedir: /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/results
162 21:19:54.904246 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-add-keys
163 21:19:54.904782 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-add-sources
164 21:19:54.905331 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-background-process-start
165 21:19:54.905895 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-background-process-stop
166 21:19:54.906472 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-common-functions
167 21:19:54.906978 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-echo-ipv4
168 21:19:54.907450 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-install-packages
169 21:19:54.907941 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-installed-packages
170 21:19:54.908462 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-os-build
171 21:19:54.908936 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-probe-channel
172 21:19:54.909467 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-probe-ip
173 21:19:54.909951 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-target-ip
174 21:19:54.910421 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-target-mac
175 21:19:54.910893 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-target-storage
176 21:19:54.911369 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-test-case
177 21:19:54.911839 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-test-event
178 21:19:54.912348 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-test-feedback
179 21:19:54.912816 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-test-raise
180 21:19:54.913312 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-test-reference
181 21:19:54.913854 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-test-runner
182 21:19:54.914349 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-test-set
183 21:19:54.914815 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-test-shell
184 21:19:54.915364 Updating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-add-keys (debian)
185 21:19:54.915914 Updating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-add-sources (debian)
186 21:19:54.916505 Updating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-install-packages (debian)
187 21:19:54.917020 Updating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-installed-packages (debian)
188 21:19:54.917505 Updating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/bin/lava-os-build (debian)
189 21:19:54.917954 Creating /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/environment
190 21:19:54.918323 LAVA metadata
191 21:19:54.918579 - LAVA_JOB_ID=823615
192 21:19:54.918792 - LAVA_DISPATCHER_IP=192.168.6.2
193 21:19:54.919151 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 21:19:54.920109 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 21:19:54.920419 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 21:19:54.920624 skipped lava-vland-overlay
197 21:19:54.920862 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 21:19:54.921111 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 21:19:54.921324 skipped lava-multinode-overlay
200 21:19:54.921561 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 21:19:54.921808 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 21:19:54.922052 Loading test definitions
203 21:19:54.922352 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 21:19:54.922593 Using /lava-823615 at stage 0
205 21:19:54.923671 uuid=823615_1.6.2.4.1 testdef=None
206 21:19:54.923967 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 21:19:54.924253 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 21:19:54.925791 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 21:19:54.926576 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 21:19:54.928485 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 21:19:54.929307 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 21:19:54.931100 runner path: /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/0/tests/0_timesync-off test_uuid 823615_1.6.2.4.1
215 21:19:54.931654 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 21:19:54.932487 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 21:19:54.932710 Using /lava-823615 at stage 0
219 21:19:54.933062 Fetching tests from https://github.com/kernelci/test-definitions.git
220 21:19:54.933349 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/0/tests/1_kselftest-alsa'
221 21:19:58.317378 Running '/usr/bin/git checkout kernelci.org
222 21:19:58.606437 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 21:19:58.607877 uuid=823615_1.6.2.4.5 testdef=None
224 21:19:58.608259 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 21:19:58.609035 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 21:19:58.611882 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 21:19:58.612740 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 21:19:58.616494 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 21:19:58.617382 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 21:19:58.621012 runner path: /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/0/tests/1_kselftest-alsa test_uuid 823615_1.6.2.4.5
234 21:19:58.621306 BOARD='meson-g12b-a311d-libretech-cc'
235 21:19:58.621523 BRANCH='mainline'
236 21:19:58.621727 SKIPFILE='/dev/null'
237 21:19:58.621931 SKIP_INSTALL='True'
238 21:19:58.622133 TESTPROG_URL='http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 21:19:58.622338 TST_CASENAME=''
240 21:19:58.622537 TST_CMDFILES='alsa'
241 21:19:58.623114 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 21:19:58.623916 Creating lava-test-runner.conf files
244 21:19:58.624151 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/823615/lava-overlay-rdldfsfk/lava-823615/0 for stage 0
245 21:19:58.624525 - 0_timesync-off
246 21:19:58.624778 - 1_kselftest-alsa
247 21:19:58.625130 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 21:19:58.625427 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 21:20:21.993038 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 21:20:21.993491 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 21:20:21.993791 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 21:20:21.994103 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 21:20:21.994396 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 21:20:22.639231 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 21:20:22.639732 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 21:20:22.640117 extracting modules file /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823615/extract-nfsrootfs-2brvgi69
257 21:20:24.022222 extracting modules file /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823615/extract-overlay-ramdisk-no_279dw/ramdisk
258 21:20:25.422333 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 21:20:25.422813 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 21:20:25.423092 [common] Applying overlay to NFS
261 21:20:25.423306 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823615/compress-overlay-75zeh6e2/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/823615/extract-nfsrootfs-2brvgi69
262 21:20:28.172832 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 21:20:28.173308 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 21:20:28.173586 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 21:20:28.173820 Converting downloaded kernel to a uImage
266 21:20:28.174127 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/kernel/Image /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/kernel/uImage
267 21:20:28.653957 output: Image Name:
268 21:20:28.654372 output: Created: Tue Oct 8 21:20:28 2024
269 21:20:28.654582 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 21:20:28.654783 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 21:20:28.654982 output: Load Address: 01080000
272 21:20:28.655179 output: Entry Point: 01080000
273 21:20:28.655373 output:
274 21:20:28.655706 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 21:20:28.655977 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 21:20:28.656750 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 21:20:28.657031 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 21:20:28.657293 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 21:20:28.657555 Building ramdisk /var/lib/lava/dispatcher/tmp/823615/extract-overlay-ramdisk-no_279dw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/823615/extract-overlay-ramdisk-no_279dw/ramdisk
280 21:20:30.842179 >> 166774 blocks
281 21:20:38.952974 Adding RAMdisk u-boot header.
282 21:20:38.953626 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/823615/extract-overlay-ramdisk-no_279dw/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/823615/extract-overlay-ramdisk-no_279dw/ramdisk.cpio.gz.uboot
283 21:20:39.190570 output: Image Name:
284 21:20:39.191000 output: Created: Tue Oct 8 21:20:38 2024
285 21:20:39.191213 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 21:20:39.191418 output: Data Size: 23422567 Bytes = 22873.60 KiB = 22.34 MiB
287 21:20:39.191623 output: Load Address: 00000000
288 21:20:39.191824 output: Entry Point: 00000000
289 21:20:39.192143 output:
290 21:20:39.193187 rename /var/lib/lava/dispatcher/tmp/823615/extract-overlay-ramdisk-no_279dw/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/ramdisk/ramdisk.cpio.gz.uboot
291 21:20:39.193927 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 21:20:39.194478 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 21:20:39.195003 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 21:20:39.195452 No LXC device requested
295 21:20:39.195945 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 21:20:39.196488 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 21:20:39.196983 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 21:20:39.197390 Checking files for TFTP limit of 4294967296 bytes.
299 21:20:39.200042 end: 1 tftp-deploy (duration 00:01:20) [common]
300 21:20:39.200612 start: 2 uboot-action (timeout 00:05:00) [common]
301 21:20:39.201126 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 21:20:39.201618 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 21:20:39.202115 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 21:20:39.202633 Using kernel file from prepare-kernel: 823615/tftp-deploy-z5m0yg35/kernel/uImage
305 21:20:39.203249 substitutions:
306 21:20:39.203652 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 21:20:39.204082 - {DTB_ADDR}: 0x01070000
308 21:20:39.204483 - {DTB}: 823615/tftp-deploy-z5m0yg35/dtb/meson-g12b-a311d-libretech-cc.dtb
309 21:20:39.204882 - {INITRD}: 823615/tftp-deploy-z5m0yg35/ramdisk/ramdisk.cpio.gz.uboot
310 21:20:39.205275 - {KERNEL_ADDR}: 0x01080000
311 21:20:39.205665 - {KERNEL}: 823615/tftp-deploy-z5m0yg35/kernel/uImage
312 21:20:39.206055 - {LAVA_MAC}: None
313 21:20:39.206481 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/823615/extract-nfsrootfs-2brvgi69
314 21:20:39.206875 - {NFS_SERVER_IP}: 192.168.6.2
315 21:20:39.207263 - {PRESEED_CONFIG}: None
316 21:20:39.207647 - {PRESEED_LOCAL}: None
317 21:20:39.208096 - {RAMDISK_ADDR}: 0x08000000
318 21:20:39.208491 - {RAMDISK}: 823615/tftp-deploy-z5m0yg35/ramdisk/ramdisk.cpio.gz.uboot
319 21:20:39.208877 - {ROOT_PART}: None
320 21:20:39.209261 - {ROOT}: None
321 21:20:39.209641 - {SERVER_IP}: 192.168.6.2
322 21:20:39.210020 - {TEE_ADDR}: 0x83000000
323 21:20:39.210401 - {TEE}: None
324 21:20:39.210779 Parsed boot commands:
325 21:20:39.211150 - setenv autoload no
326 21:20:39.211528 - setenv initrd_high 0xffffffff
327 21:20:39.211907 - setenv fdt_high 0xffffffff
328 21:20:39.212315 - dhcp
329 21:20:39.212696 - setenv serverip 192.168.6.2
330 21:20:39.213079 - tftpboot 0x01080000 823615/tftp-deploy-z5m0yg35/kernel/uImage
331 21:20:39.213463 - tftpboot 0x08000000 823615/tftp-deploy-z5m0yg35/ramdisk/ramdisk.cpio.gz.uboot
332 21:20:39.213844 - tftpboot 0x01070000 823615/tftp-deploy-z5m0yg35/dtb/meson-g12b-a311d-libretech-cc.dtb
333 21:20:39.214222 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/823615/extract-nfsrootfs-2brvgi69,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 21:20:39.214616 - bootm 0x01080000 0x08000000 0x01070000
335 21:20:39.215101 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 21:20:39.216588 start: 2.3 connect-device (timeout 00:05:00) [common]
338 21:20:39.217004 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 21:20:39.232019 Setting prompt string to ['lava-test: # ']
340 21:20:39.233538 end: 2.3 connect-device (duration 00:00:00) [common]
341 21:20:39.234141 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 21:20:39.234714 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 21:20:39.235231 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 21:20:39.236396 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 21:20:39.273516 >> OK - accepted request
346 21:20:39.275741 Returned 0 in 0 seconds
347 21:20:39.376906 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 21:20:39.378557 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 21:20:39.379107 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 21:20:39.379603 Setting prompt string to ['Hit any key to stop autoboot']
352 21:20:39.380087 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 21:20:39.381657 Trying 192.168.56.21...
354 21:20:39.382130 Connected to conserv1.
355 21:20:39.382538 Escape character is '^]'.
356 21:20:39.382946
357 21:20:39.383357 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 21:20:39.383778
359 21:20:51.110144 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 21:20:51.110538 bl2_stage_init 0x01
361 21:20:51.110770 bl2_stage_init 0x81
362 21:20:51.115691 hw id: 0x0000 - pwm id 0x01
363 21:20:51.115954 bl2_stage_init 0xc1
364 21:20:51.116336 bl2_stage_init 0x02
365 21:20:51.116729
366 21:20:51.121392 L0:00000000
367 21:20:51.121847 L1:20000703
368 21:20:51.122253 L2:00008067
369 21:20:51.122660 L3:14000000
370 21:20:51.124267 B2:00402000
371 21:20:51.124702 B1:e0f83180
372 21:20:51.125111
373 21:20:51.125499 TE: 58167
374 21:20:51.125887
375 21:20:51.135459 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 21:20:51.135890
377 21:20:51.136312 Board ID = 1
378 21:20:51.136699 Set A53 clk to 24M
379 21:20:51.137078 Set A73 clk to 24M
380 21:20:51.141077 Set clk81 to 24M
381 21:20:51.141493 A53 clk: 1200 MHz
382 21:20:51.141878 A73 clk: 1200 MHz
383 21:20:51.146703 CLK81: 166.6M
384 21:20:51.147114 smccc: 00012abe
385 21:20:51.152222 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 21:20:51.152636 board id: 1
387 21:20:51.160874 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 21:20:51.171323 fw parse done
389 21:20:51.177290 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 21:20:51.219962 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 21:20:51.230805 PIEI prepare done
392 21:20:51.231213 fastboot data load
393 21:20:51.231599 fastboot data verify
394 21:20:51.236484 verify result: 266
395 21:20:51.242063 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 21:20:51.242477 LPDDR4 probe
397 21:20:51.242859 ddr clk to 1584MHz
398 21:20:51.250075 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 21:20:51.287329
400 21:20:51.287785 dmc_version 0001
401 21:20:51.294048 Check phy result
402 21:20:51.299886 INFO : End of CA training
403 21:20:51.300334 INFO : End of initialization
404 21:20:51.305511 INFO : Training has run successfully!
405 21:20:51.305944 Check phy result
406 21:20:51.311128 INFO : End of initialization
407 21:20:51.311544 INFO : End of read enable training
408 21:20:51.316701 INFO : End of fine write leveling
409 21:20:51.322340 INFO : End of Write leveling coarse delay
410 21:20:51.322761 INFO : Training has run successfully!
411 21:20:51.323160 Check phy result
412 21:20:51.327878 INFO : End of initialization
413 21:20:51.328336 INFO : End of read dq deskew training
414 21:20:51.333516 INFO : End of MPR read delay center optimization
415 21:20:51.339104 INFO : End of write delay center optimization
416 21:20:51.344723 INFO : End of read delay center optimization
417 21:20:51.345146 INFO : End of max read latency training
418 21:20:51.350294 INFO : Training has run successfully!
419 21:20:51.350720 1D training succeed
420 21:20:51.359546 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 21:20:51.407347 Check phy result
422 21:20:51.407788 INFO : End of initialization
423 21:20:51.428843 INFO : End of 2D read delay Voltage center optimization
424 21:20:51.448945 INFO : End of 2D read delay Voltage center optimization
425 21:20:51.501072 INFO : End of 2D write delay Voltage center optimization
426 21:20:51.550437 INFO : End of 2D write delay Voltage center optimization
427 21:20:51.555960 INFO : Training has run successfully!
428 21:20:51.556426
429 21:20:51.556832 channel==0
430 21:20:51.561645 RxClkDly_Margin_A0==88 ps 9
431 21:20:51.562064 TxDqDly_Margin_A0==108 ps 11
432 21:20:51.565009 RxClkDly_Margin_A1==88 ps 9
433 21:20:51.565428 TxDqDly_Margin_A1==98 ps 10
434 21:20:51.570573 TrainedVREFDQ_A0==74
435 21:20:51.570992 TrainedVREFDQ_A1==75
436 21:20:51.576189 VrefDac_Margin_A0==25
437 21:20:51.576607 DeviceVref_Margin_A0==40
438 21:20:51.577009 VrefDac_Margin_A1==25
439 21:20:51.581775 DeviceVref_Margin_A1==39
440 21:20:51.582200
441 21:20:51.582602
442 21:20:51.583001 channel==1
443 21:20:51.583396 RxClkDly_Margin_A0==88 ps 9
444 21:20:51.587400 TxDqDly_Margin_A0==88 ps 9
445 21:20:51.587825 RxClkDly_Margin_A1==98 ps 10
446 21:20:51.592973 TxDqDly_Margin_A1==88 ps 9
447 21:20:51.593395 TrainedVREFDQ_A0==76
448 21:20:51.593798 TrainedVREFDQ_A1==77
449 21:20:51.598566 VrefDac_Margin_A0==22
450 21:20:51.598985 DeviceVref_Margin_A0==38
451 21:20:51.604173 VrefDac_Margin_A1==22
452 21:20:51.604598 DeviceVref_Margin_A1==37
453 21:20:51.604997
454 21:20:51.609737 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 21:20:51.610160
456 21:20:51.637741 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000018 dram_vref_reg_value 0x 00000060
457 21:20:51.643313 2D training succeed
458 21:20:51.649060 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 21:20:51.649693 auto size-- 65535DDR cs0 size: 2048MB
460 21:20:51.654613 DDR cs1 size: 2048MB
461 21:20:51.655206 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 21:20:51.660357 cs0 DataBus test pass
463 21:20:51.660929 cs1 DataBus test pass
464 21:20:51.661361 cs0 AddrBus test pass
465 21:20:51.665876 cs1 AddrBus test pass
466 21:20:51.666470
467 21:20:51.666938 100bdlr_step_size ps== 420
468 21:20:51.667410 result report
469 21:20:51.671478 boot times 0Enable ddr reg access
470 21:20:51.679201 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 21:20:51.692862 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 21:20:52.266350 0.0;M3 CHK:0;cm4_sp_mode 0
473 21:20:52.266967 MVN_1=0x00000000
474 21:20:52.271824 MVN_2=0x00000000
475 21:20:52.277484 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 21:20:52.277965 OPS=0x10
477 21:20:52.278386 ring efuse init
478 21:20:52.278795 chipver efuse init
479 21:20:52.283174 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 21:20:52.288788 [0.018960 Inits done]
481 21:20:52.289249 secure task start!
482 21:20:52.289665 high task start!
483 21:20:52.293402 low task start!
484 21:20:52.293867 run into bl31
485 21:20:52.300076 NOTICE: BL31: v1.3(release):4fc40b1
486 21:20:52.307859 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 21:20:52.308363 NOTICE: BL31: G12A normal boot!
488 21:20:52.333051 NOTICE: BL31: BL33 decompress pass
489 21:20:52.338775 ERROR: Error initializing runtime service opteed_fast
490 21:20:53.571725
491 21:20:53.572391
492 21:20:53.580145 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 21:20:53.580649
494 21:20:53.581111 Model: Libre Computer AML-A311D-CC Alta
495 21:20:53.788617 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 21:20:53.811966 DRAM: 2 GiB (effective 3.8 GiB)
497 21:20:53.954831 Core: 408 devices, 31 uclasses, devicetree: separate
498 21:20:53.960578 WDT: Not starting watchdog@f0d0
499 21:20:53.992868 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 21:20:54.005355 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 21:20:54.010348 ** Bad device specification mmc 0 **
502 21:20:54.020665 Card did not respond to voltage select! : -110
503 21:20:54.028336 ** Bad device specification mmc 0 **
504 21:20:54.028819 Couldn't find partition mmc 0
505 21:20:54.037193 Card did not respond to voltage select! : -110
506 21:20:54.042257 ** Bad device specification mmc 0 **
507 21:20:54.042815 Couldn't find partition mmc 0
508 21:20:54.047363 Error: could not access storage.
509 21:20:55.310641 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 21:20:55.311281 bl2_stage_init 0x01
511 21:20:55.311765 bl2_stage_init 0x81
512 21:20:55.316267 hw id: 0x0000 - pwm id 0x01
513 21:20:55.316768 bl2_stage_init 0xc1
514 21:20:55.317228 bl2_stage_init 0x02
515 21:20:55.317679
516 21:20:55.321871 L0:00000000
517 21:20:55.322355 L1:20000703
518 21:20:55.322807 L2:00008067
519 21:20:55.323255 L3:14000000
520 21:20:55.324799 B2:00402000
521 21:20:55.325282 B1:e0f83180
522 21:20:55.325735
523 21:20:55.326179 TE: 58124
524 21:20:55.326627
525 21:20:55.335962 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 21:20:55.336476
527 21:20:55.336929 Board ID = 1
528 21:20:55.337374 Set A53 clk to 24M
529 21:20:55.337819 Set A73 clk to 24M
530 21:20:55.341553 Set clk81 to 24M
531 21:20:55.342031 A53 clk: 1200 MHz
532 21:20:55.342478 A73 clk: 1200 MHz
533 21:20:55.345105 CLK81: 166.6M
534 21:20:55.345583 smccc: 00012a92
535 21:20:55.350662 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 21:20:55.356167 board id: 1
537 21:20:55.361222 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 21:20:55.371867 fw parse done
539 21:20:55.377835 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 21:20:55.420488 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 21:20:55.431449 PIEI prepare done
542 21:20:55.431947 fastboot data load
543 21:20:55.432445 fastboot data verify
544 21:20:55.437018 verify result: 266
545 21:20:55.442640 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 21:20:55.443115 LPDDR4 probe
547 21:20:55.443560 ddr clk to 1584MHz
548 21:20:55.450609 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 21:20:55.487885
550 21:20:55.488398 dmc_version 0001
551 21:20:55.494570 Check phy result
552 21:20:55.500468 INFO : End of CA training
553 21:20:55.500941 INFO : End of initialization
554 21:20:55.506082 INFO : Training has run successfully!
555 21:20:55.506556 Check phy result
556 21:20:55.511680 INFO : End of initialization
557 21:20:55.512180 INFO : End of read enable training
558 21:20:55.517244 INFO : End of fine write leveling
559 21:20:55.522899 INFO : End of Write leveling coarse delay
560 21:20:55.523377 INFO : Training has run successfully!
561 21:20:55.523824 Check phy result
562 21:20:55.528502 INFO : End of initialization
563 21:20:55.528977 INFO : End of read dq deskew training
564 21:20:55.534089 INFO : End of MPR read delay center optimization
565 21:20:55.539671 INFO : End of write delay center optimization
566 21:20:55.545240 INFO : End of read delay center optimization
567 21:20:55.545716 INFO : End of max read latency training
568 21:20:55.550849 INFO : Training has run successfully!
569 21:20:55.551323 1D training succeed
570 21:20:55.560088 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 21:20:55.607583 Check phy result
572 21:20:55.608109 INFO : End of initialization
573 21:20:55.629370 INFO : End of 2D read delay Voltage center optimization
574 21:20:55.649633 INFO : End of 2D read delay Voltage center optimization
575 21:20:55.701745 INFO : End of 2D write delay Voltage center optimization
576 21:20:55.751113 INFO : End of 2D write delay Voltage center optimization
577 21:20:55.756556 INFO : Training has run successfully!
578 21:20:55.757093
579 21:20:55.757581 channel==0
580 21:20:55.762288 RxClkDly_Margin_A0==88 ps 9
581 21:20:55.762803 TxDqDly_Margin_A0==98 ps 10
582 21:20:55.765565 RxClkDly_Margin_A1==88 ps 9
583 21:20:55.766074 TxDqDly_Margin_A1==98 ps 10
584 21:20:55.771103 TrainedVREFDQ_A0==74
585 21:20:55.771589 TrainedVREFDQ_A1==74
586 21:20:55.772079 VrefDac_Margin_A0==25
587 21:20:55.776809 DeviceVref_Margin_A0==40
588 21:20:55.777293 VrefDac_Margin_A1==25
589 21:20:55.782361 DeviceVref_Margin_A1==40
590 21:20:55.782837
591 21:20:55.783287
592 21:20:55.783732 channel==1
593 21:20:55.784209 RxClkDly_Margin_A0==98 ps 10
594 21:20:55.788071 TxDqDly_Margin_A0==98 ps 10
595 21:20:55.788549 RxClkDly_Margin_A1==98 ps 10
596 21:20:55.793621 TxDqDly_Margin_A1==88 ps 9
597 21:20:55.794098 TrainedVREFDQ_A0==77
598 21:20:55.794545 TrainedVREFDQ_A1==77
599 21:20:55.799142 VrefDac_Margin_A0==22
600 21:20:55.799614 DeviceVref_Margin_A0==37
601 21:20:55.804759 VrefDac_Margin_A1==22
602 21:20:55.805229 DeviceVref_Margin_A1==37
603 21:20:55.805671
604 21:20:55.810332 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 21:20:55.810812
606 21:20:55.838305 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 21:20:55.843939 2D training succeed
608 21:20:55.849540 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 21:20:55.850033 auto size-- 65535DDR cs0 size: 2048MB
610 21:20:55.855100 DDR cs1 size: 2048MB
611 21:20:55.855576 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 21:20:55.860714 cs0 DataBus test pass
613 21:20:55.861215 cs1 DataBus test pass
614 21:20:55.861665 cs0 AddrBus test pass
615 21:20:55.866308 cs1 AddrBus test pass
616 21:20:55.866782
617 21:20:55.867228 100bdlr_step_size ps== 420
618 21:20:55.867682 result report
619 21:20:55.871891 boot times 0Enable ddr reg access
620 21:20:55.879588 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 21:20:55.893084 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 21:20:56.466657 0.0;M3 CHK:0;cm4_sp_mode 0
623 21:20:56.468153 MVN_1=0x00000000
624 21:20:56.472373 MVN_2=0x00000000
625 21:20:56.477996 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 21:20:56.478506 OPS=0x10
627 21:20:56.478942 ring efuse init
628 21:20:56.479362 chipver efuse init
629 21:20:56.483566 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 21:20:56.489231 [0.018960 Inits done]
631 21:20:56.489711 secure task start!
632 21:20:56.490086 high task start!
633 21:20:56.493832 low task start!
634 21:20:56.494137 run into bl31
635 21:20:56.500584 NOTICE: BL31: v1.3(release):4fc40b1
636 21:20:56.508318 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 21:20:56.508848 NOTICE: BL31: G12A normal boot!
638 21:20:56.533578 NOTICE: BL31: BL33 decompress pass
639 21:20:56.539198 ERROR: Error initializing runtime service opteed_fast
640 21:20:57.772185
641 21:20:57.772806
642 21:20:57.780497 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 21:20:57.780954
644 21:20:57.781371 Model: Libre Computer AML-A311D-CC Alta
645 21:20:57.989018 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 21:20:58.012262 DRAM: 2 GiB (effective 3.8 GiB)
647 21:20:58.155341 Core: 408 devices, 31 uclasses, devicetree: separate
648 21:20:58.161195 WDT: Not starting watchdog@f0d0
649 21:20:58.193470 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 21:20:58.205953 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 21:20:58.210891 ** Bad device specification mmc 0 **
652 21:20:58.221200 Card did not respond to voltage select! : -110
653 21:20:58.228874 ** Bad device specification mmc 0 **
654 21:20:58.229317 Couldn't find partition mmc 0
655 21:20:58.237225 Card did not respond to voltage select! : -110
656 21:20:58.242828 ** Bad device specification mmc 0 **
657 21:20:58.243278 Couldn't find partition mmc 0
658 21:20:58.247849 Error: could not access storage.
659 21:20:58.590246 Net: eth0: ethernet@ff3f0000
660 21:20:58.590852 starting USB...
661 21:20:58.842088 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 21:20:58.842672 Starting the controller
663 21:20:58.849039 USB XHCI 1.10
664 21:21:00.559246 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 21:21:00.559712 bl2_stage_init 0x01
666 21:21:00.559954 bl2_stage_init 0x81
667 21:21:00.564827 hw id: 0x0000 - pwm id 0x01
668 21:21:00.565125 bl2_stage_init 0xc1
669 21:21:00.565356 bl2_stage_init 0x02
670 21:21:00.565579
671 21:21:00.570375 L0:00000000
672 21:21:00.570729 L1:20000703
673 21:21:00.570966 L2:00008067
674 21:21:00.571188 L3:14000000
675 21:21:00.576095 B2:00402000
676 21:21:00.576378 B1:e0f83180
677 21:21:00.576608
678 21:21:00.576835 TE: 58167
679 21:21:00.577062
680 21:21:00.581577 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 21:21:00.581870
682 21:21:00.582112 Board ID = 1
683 21:21:00.587188 Set A53 clk to 24M
684 21:21:00.587478 Set A73 clk to 24M
685 21:21:00.587706 Set clk81 to 24M
686 21:21:00.592835 A53 clk: 1200 MHz
687 21:21:00.593118 A73 clk: 1200 MHz
688 21:21:00.593342 CLK81: 166.6M
689 21:21:00.593572 smccc: 00012abe
690 21:21:00.598351 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 21:21:00.604103 board id: 1
692 21:21:00.609909 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 21:21:00.620516 fw parse done
694 21:21:00.626437 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 21:21:00.669170 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 21:21:00.680078 PIEI prepare done
697 21:21:00.680393 fastboot data load
698 21:21:00.680624 fastboot data verify
699 21:21:00.685647 verify result: 266
700 21:21:00.691360 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 21:21:00.691862 LPDDR4 probe
702 21:21:00.692308 ddr clk to 1584MHz
703 21:21:00.699411 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 21:21:00.736565
705 21:21:00.737133 dmc_version 0001
706 21:21:00.743313 Check phy result
707 21:21:00.749199 INFO : End of CA training
708 21:21:00.749685 INFO : End of initialization
709 21:21:00.754685 INFO : Training has run successfully!
710 21:21:00.755174 Check phy result
711 21:21:00.760403 INFO : End of initialization
712 21:21:00.760935 INFO : End of read enable training
713 21:21:00.766057 INFO : End of fine write leveling
714 21:21:00.771584 INFO : End of Write leveling coarse delay
715 21:21:00.772069 INFO : Training has run successfully!
716 21:21:00.772476 Check phy result
717 21:21:00.777213 INFO : End of initialization
718 21:21:00.777663 INFO : End of read dq deskew training
719 21:21:00.782657 INFO : End of MPR read delay center optimization
720 21:21:00.788302 INFO : End of write delay center optimization
721 21:21:00.793986 INFO : End of read delay center optimization
722 21:21:00.794423 INFO : End of max read latency training
723 21:21:00.799437 INFO : Training has run successfully!
724 21:21:00.799886 1D training succeed
725 21:21:00.808667 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 21:21:00.856301 Check phy result
727 21:21:00.856776 INFO : End of initialization
728 21:21:00.877946 INFO : End of 2D read delay Voltage center optimization
729 21:21:00.898085 INFO : End of 2D read delay Voltage center optimization
730 21:21:00.950119 INFO : End of 2D write delay Voltage center optimization
731 21:21:00.999481 INFO : End of 2D write delay Voltage center optimization
732 21:21:01.004903 INFO : Training has run successfully!
733 21:21:01.005358
734 21:21:01.005759 channel==0
735 21:21:01.010364 RxClkDly_Margin_A0==88 ps 9
736 21:21:01.010808 TxDqDly_Margin_A0==98 ps 10
737 21:21:01.016217 RxClkDly_Margin_A1==88 ps 9
738 21:21:01.016669 TxDqDly_Margin_A1==88 ps 9
739 21:21:01.017067 TrainedVREFDQ_A0==74
740 21:21:01.021579 TrainedVREFDQ_A1==74
741 21:21:01.022029 VrefDac_Margin_A0==25
742 21:21:01.022422 DeviceVref_Margin_A0==40
743 21:21:01.027234 VrefDac_Margin_A1==24
744 21:21:01.027688 DeviceVref_Margin_A1==40
745 21:21:01.028123
746 21:21:01.028521
747 21:21:01.028909 channel==1
748 21:21:01.032917 RxClkDly_Margin_A0==98 ps 10
749 21:21:01.033404 TxDqDly_Margin_A0==98 ps 10
750 21:21:01.038434 RxClkDly_Margin_A1==88 ps 9
751 21:21:01.038885 TxDqDly_Margin_A1==88 ps 9
752 21:21:01.043930 TrainedVREFDQ_A0==77
753 21:21:01.044405 TrainedVREFDQ_A1==77
754 21:21:01.044800 VrefDac_Margin_A0==22
755 21:21:01.049595 DeviceVref_Margin_A0==37
756 21:21:01.050036 VrefDac_Margin_A1==24
757 21:21:01.055331 DeviceVref_Margin_A1==37
758 21:21:01.055785
759 21:21:01.056220 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 21:21:01.056614
761 21:21:01.088678 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
762 21:21:01.089220 2D training succeed
763 21:21:01.094475 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 21:21:01.100301 auto size-- 65535DDR cs0 size: 2048MB
765 21:21:01.100789 DDR cs1 size: 2048MB
766 21:21:01.105680 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 21:21:01.106177 cs0 DataBus test pass
768 21:21:01.111547 cs1 DataBus test pass
769 21:21:01.112075 cs0 AddrBus test pass
770 21:21:01.112515 cs1 AddrBus test pass
771 21:21:01.112915
772 21:21:01.116737 100bdlr_step_size ps== 420
773 21:21:01.117227 result report
774 21:21:01.122261 boot times 0Enable ddr reg access
775 21:21:01.127641 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 21:21:01.141165 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 21:21:01.713044 0.0;M3 CHK:0;cm4_sp_mode 0
778 21:21:01.713706 MVN_1=0x00000000
779 21:21:01.718537 MVN_2=0x00000000
780 21:21:01.724328 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 21:21:01.724856 OPS=0x10
782 21:21:01.725263 ring efuse init
783 21:21:01.725656 chipver efuse init
784 21:21:01.729828 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 21:21:01.735444 [0.018960 Inits done]
786 21:21:01.735960 secure task start!
787 21:21:01.736449 high task start!
788 21:21:01.740154 low task start!
789 21:21:01.740695 run into bl31
790 21:21:01.746713 NOTICE: BL31: v1.3(release):4fc40b1
791 21:21:01.754860 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 21:21:01.755344 NOTICE: BL31: G12A normal boot!
793 21:21:01.779918 NOTICE: BL31: BL33 decompress pass
794 21:21:01.785612 ERROR: Error initializing runtime service opteed_fast
795 21:21:03.018519
796 21:21:03.019004
797 21:21:03.026826 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 21:21:03.027331
799 21:21:03.027749 Model: Libre Computer AML-A311D-CC Alta
800 21:21:03.235318 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 21:21:03.258670 DRAM: 2 GiB (effective 3.8 GiB)
802 21:21:03.401697 Core: 408 devices, 31 uclasses, devicetree: separate
803 21:21:03.407600 WDT: Not starting watchdog@f0d0
804 21:21:03.439767 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 21:21:03.452271 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 21:21:03.457200 ** Bad device specification mmc 0 **
807 21:21:03.467558 Card did not respond to voltage select! : -110
808 21:21:03.475201 ** Bad device specification mmc 0 **
809 21:21:03.475495 Couldn't find partition mmc 0
810 21:21:03.483526 Card did not respond to voltage select! : -110
811 21:21:03.489024 ** Bad device specification mmc 0 **
812 21:21:03.489295 Couldn't find partition mmc 0
813 21:21:03.494128 Error: could not access storage.
814 21:21:03.837702 Net: eth0: ethernet@ff3f0000
815 21:21:03.838132 starting USB...
816 21:21:04.089495 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 21:21:04.089931 Starting the controller
818 21:21:04.096467 USB XHCI 1.10
819 21:21:06.259508 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 21:21:06.260183 bl2_stage_init 0x01
821 21:21:06.260620 bl2_stage_init 0x81
822 21:21:06.265107 hw id: 0x0000 - pwm id 0x01
823 21:21:06.265587 bl2_stage_init 0xc1
824 21:21:06.266004 bl2_stage_init 0x02
825 21:21:06.266414
826 21:21:06.270799 L0:00000000
827 21:21:06.271269 L1:20000703
828 21:21:06.271681 L2:00008067
829 21:21:06.272115 L3:14000000
830 21:21:06.276460 B2:00402000
831 21:21:06.276984 B1:e0f83180
832 21:21:06.277410
833 21:21:06.277814 TE: 58167
834 21:21:06.278218
835 21:21:06.281929 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 21:21:06.282398
837 21:21:06.282811 Board ID = 1
838 21:21:06.287566 Set A53 clk to 24M
839 21:21:06.288057 Set A73 clk to 24M
840 21:21:06.288465 Set clk81 to 24M
841 21:21:06.293098 A53 clk: 1200 MHz
842 21:21:06.293556 A73 clk: 1200 MHz
843 21:21:06.293965 CLK81: 166.6M
844 21:21:06.294366 smccc: 00012abd
845 21:21:06.298784 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 21:21:06.304345 board id: 1
847 21:21:06.310281 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 21:21:06.320857 fw parse done
849 21:21:06.326930 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 21:21:06.369371 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 21:21:06.380305 PIEI prepare done
852 21:21:06.380804 fastboot data load
853 21:21:06.381221 fastboot data verify
854 21:21:06.385901 verify result: 266
855 21:21:06.391489 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 21:21:06.391976 LPDDR4 probe
857 21:21:06.392432 ddr clk to 1584MHz
858 21:21:06.399403 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 21:21:06.436705
860 21:21:06.437212 dmc_version 0001
861 21:21:06.443396 Check phy result
862 21:21:06.449235 INFO : End of CA training
863 21:21:06.449698 INFO : End of initialization
864 21:21:06.454840 INFO : Training has run successfully!
865 21:21:06.455300 Check phy result
866 21:21:06.460431 INFO : End of initialization
867 21:21:06.460892 INFO : End of read enable training
868 21:21:06.466040 INFO : End of fine write leveling
869 21:21:06.471673 INFO : End of Write leveling coarse delay
870 21:21:06.472163 INFO : Training has run successfully!
871 21:21:06.472579 Check phy result
872 21:21:06.477243 INFO : End of initialization
873 21:21:06.477742 INFO : End of read dq deskew training
874 21:21:06.482905 INFO : End of MPR read delay center optimization
875 21:21:06.488470 INFO : End of write delay center optimization
876 21:21:06.494034 INFO : End of read delay center optimization
877 21:21:06.494497 INFO : End of max read latency training
878 21:21:06.499686 INFO : Training has run successfully!
879 21:21:06.500186 1D training succeed
880 21:21:06.508879 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 21:21:06.556524 Check phy result
882 21:21:06.557081 INFO : End of initialization
883 21:21:06.578208 INFO : End of 2D read delay Voltage center optimization
884 21:21:06.598225 INFO : End of 2D read delay Voltage center optimization
885 21:21:06.650248 INFO : End of 2D write delay Voltage center optimization
886 21:21:06.699415 INFO : End of 2D write delay Voltage center optimization
887 21:21:06.704974 INFO : Training has run successfully!
888 21:21:06.705444
889 21:21:06.705859 channel==0
890 21:21:06.711890 RxClkDly_Margin_A0==88 ps 9
891 21:21:06.712390 TxDqDly_Margin_A0==98 ps 10
892 21:21:06.714935 RxClkDly_Margin_A1==88 ps 9
893 21:21:06.715387 TxDqDly_Margin_A1==98 ps 10
894 21:21:06.720657 TrainedVREFDQ_A0==74
895 21:21:06.721136 TrainedVREFDQ_A1==74
896 21:21:06.721548 VrefDac_Margin_A0==25
897 21:21:06.727182 DeviceVref_Margin_A0==40
898 21:21:06.727747 VrefDac_Margin_A1==25
899 21:21:06.728195 DeviceVref_Margin_A1==40
900 21:21:06.731643
901 21:21:06.732122
902 21:21:06.732521 channel==1
903 21:21:06.732908 RxClkDly_Margin_A0==98 ps 10
904 21:21:06.737295 TxDqDly_Margin_A0==88 ps 9
905 21:21:06.737748 RxClkDly_Margin_A1==98 ps 10
906 21:21:06.742896 TxDqDly_Margin_A1==88 ps 9
907 21:21:06.743383 TrainedVREFDQ_A0==76
908 21:21:06.743775 TrainedVREFDQ_A1==77
909 21:21:06.748513 VrefDac_Margin_A0==22
910 21:21:06.748963 DeviceVref_Margin_A0==38
911 21:21:06.749349 VrefDac_Margin_A1==24
912 21:21:06.754128 DeviceVref_Margin_A1==37
913 21:21:06.754580
914 21:21:06.759702 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 21:21:06.760189
916 21:21:06.787705 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 21:21:06.788348 2D training succeed
918 21:21:06.798733 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 21:21:06.799207 auto size-- 65535DDR cs0 size: 2048MB
920 21:21:06.799734 DDR cs1 size: 2048MB
921 21:21:06.804378 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 21:21:06.804922 cs0 DataBus test pass
923 21:21:06.810038 cs1 DataBus test pass
924 21:21:06.810577 cs0 AddrBus test pass
925 21:21:06.815588 cs1 AddrBus test pass
926 21:21:06.816173
927 21:21:06.816582 100bdlr_step_size ps== 420
928 21:21:06.816981 result report
929 21:21:06.821175 boot times 0Enable ddr reg access
930 21:21:06.827687 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 21:21:06.841193 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 21:21:07.413341 0.0;M3 CHK:0;cm4_sp_mode 0
933 21:21:07.413968 MVN_1=0x00000000
934 21:21:07.418762 MVN_2=0x00000000
935 21:21:07.424522 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 21:21:07.424991 OPS=0x10
937 21:21:07.425409 ring efuse init
938 21:21:07.425813 chipver efuse init
939 21:21:07.430124 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 21:21:07.435718 [0.018961 Inits done]
941 21:21:07.436228 secure task start!
942 21:21:07.436645 high task start!
943 21:21:07.440287 low task start!
944 21:21:07.440745 run into bl31
945 21:21:07.446919 NOTICE: BL31: v1.3(release):4fc40b1
946 21:21:07.454718 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 21:21:07.455193 NOTICE: BL31: G12A normal boot!
948 21:21:07.480183 NOTICE: BL31: BL33 decompress pass
949 21:21:07.485796 ERROR: Error initializing runtime service opteed_fast
950 21:21:08.718781
951 21:21:08.719414
952 21:21:08.727056 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 21:21:08.727530
954 21:21:08.727967 Model: Libre Computer AML-A311D-CC Alta
955 21:21:08.935606 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 21:21:08.958816 DRAM: 2 GiB (effective 3.8 GiB)
957 21:21:09.101893 Core: 408 devices, 31 uclasses, devicetree: separate
958 21:21:09.107731 WDT: Not starting watchdog@f0d0
959 21:21:09.139972 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 21:21:09.152391 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 21:21:09.157507 ** Bad device specification mmc 0 **
962 21:21:09.167731 Card did not respond to voltage select! : -110
963 21:21:09.175424 ** Bad device specification mmc 0 **
964 21:21:09.175890 Couldn't find partition mmc 0
965 21:21:09.183693 Card did not respond to voltage select! : -110
966 21:21:09.189343 ** Bad device specification mmc 0 **
967 21:21:09.189809 Couldn't find partition mmc 0
968 21:21:09.194468 Error: could not access storage.
969 21:21:09.537864 Net: eth0: ethernet@ff3f0000
970 21:21:09.538483 starting USB...
971 21:21:09.789762 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 21:21:09.790187 Starting the controller
973 21:21:09.796720 USB XHCI 1.10
974 21:21:11.660009 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 21:21:11.660626 bl2_stage_init 0x01
976 21:21:11.661053 bl2_stage_init 0x81
977 21:21:11.665733 hw id: 0x0000 - pwm id 0x01
978 21:21:11.666202 bl2_stage_init 0xc1
979 21:21:11.666615 bl2_stage_init 0x02
980 21:21:11.667019
981 21:21:11.671194 L0:00000000
982 21:21:11.671650 L1:20000703
983 21:21:11.672096 L2:00008067
984 21:21:11.672503 L3:14000000
985 21:21:11.676792 B2:00402000
986 21:21:11.677248 B1:e0f83180
987 21:21:11.677655
988 21:21:11.678058 TE: 58124
989 21:21:11.678456
990 21:21:11.682423 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 21:21:11.682882
992 21:21:11.683291 Board ID = 1
993 21:21:11.687947 Set A53 clk to 24M
994 21:21:11.688425 Set A73 clk to 24M
995 21:21:11.688826 Set clk81 to 24M
996 21:21:11.693711 A53 clk: 1200 MHz
997 21:21:11.694163 A73 clk: 1200 MHz
998 21:21:11.694570 CLK81: 166.6M
999 21:21:11.694965 smccc: 00012a92
1000 21:21:11.699171 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 21:21:11.704779 board id: 1
1002 21:21:11.710753 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 21:21:11.721856 fw parse done
1004 21:21:11.727331 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 21:21:11.769893 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 21:21:11.780788 PIEI prepare done
1007 21:21:11.781237 fastboot data load
1008 21:21:11.781631 fastboot data verify
1009 21:21:11.786454 verify result: 266
1010 21:21:11.791976 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 21:21:11.792460 LPDDR4 probe
1012 21:21:11.792851 ddr clk to 1584MHz
1013 21:21:11.800172 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 21:21:11.837490
1015 21:21:11.837968 dmc_version 0001
1016 21:21:11.844202 Check phy result
1017 21:21:11.849880 INFO : End of CA training
1018 21:21:11.850325 INFO : End of initialization
1019 21:21:11.855620 INFO : Training has run successfully!
1020 21:21:11.856123 Check phy result
1021 21:21:11.861201 INFO : End of initialization
1022 21:21:11.861659 INFO : End of read enable training
1023 21:21:11.864466 INFO : End of fine write leveling
1024 21:21:11.870016 INFO : End of Write leveling coarse delay
1025 21:21:11.875664 INFO : Training has run successfully!
1026 21:21:11.876141 Check phy result
1027 21:21:11.876554 INFO : End of initialization
1028 21:21:11.881191 INFO : End of read dq deskew training
1029 21:21:11.886855 INFO : End of MPR read delay center optimization
1030 21:21:11.887307 INFO : End of write delay center optimization
1031 21:21:11.892353 INFO : End of read delay center optimization
1032 21:21:11.897936 INFO : End of max read latency training
1033 21:21:11.898396 INFO : Training has run successfully!
1034 21:21:11.903539 1D training succeed
1035 21:21:11.909468 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 21:21:11.957036 Check phy result
1037 21:21:11.957508 INFO : End of initialization
1038 21:21:11.978645 INFO : End of 2D read delay Voltage center optimization
1039 21:21:11.998747 INFO : End of 2D read delay Voltage center optimization
1040 21:21:12.050796 INFO : End of 2D write delay Voltage center optimization
1041 21:21:12.099900 INFO : End of 2D write delay Voltage center optimization
1042 21:21:12.105446 INFO : Training has run successfully!
1043 21:21:12.105918
1044 21:21:12.106333 channel==0
1045 21:21:12.111017 RxClkDly_Margin_A0==88 ps 9
1046 21:21:12.111471 TxDqDly_Margin_A0==98 ps 10
1047 21:21:12.114373 RxClkDly_Margin_A1==88 ps 9
1048 21:21:12.114830 TxDqDly_Margin_A1==98 ps 10
1049 21:21:12.120074 TrainedVREFDQ_A0==74
1050 21:21:12.120531 TrainedVREFDQ_A1==74
1051 21:21:12.120942 VrefDac_Margin_A0==25
1052 21:21:12.125679 DeviceVref_Margin_A0==40
1053 21:21:12.126134 VrefDac_Margin_A1==25
1054 21:21:12.131224 DeviceVref_Margin_A1==40
1055 21:21:12.131674
1056 21:21:12.132113
1057 21:21:12.132521 channel==1
1058 21:21:12.132918 RxClkDly_Margin_A0==98 ps 10
1059 21:21:12.134681 TxDqDly_Margin_A0==88 ps 9
1060 21:21:12.140183 RxClkDly_Margin_A1==98 ps 10
1061 21:21:12.140634 TxDqDly_Margin_A1==108 ps 11
1062 21:21:12.145721 TrainedVREFDQ_A0==77
1063 21:21:12.146172 TrainedVREFDQ_A1==78
1064 21:21:12.146578 VrefDac_Margin_A0==22
1065 21:21:12.151319 DeviceVref_Margin_A0==37
1066 21:21:12.151767 VrefDac_Margin_A1==24
1067 21:21:12.152206 DeviceVref_Margin_A1==36
1068 21:21:12.152602
1069 21:21:12.156984 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 21:21:12.157440
1071 21:21:12.190467 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 21:21:12.190956 2D training succeed
1073 21:21:12.196080 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 21:21:12.201615 auto size-- 65535DDR cs0 size: 2048MB
1075 21:21:12.202125 DDR cs1 size: 2048MB
1076 21:21:12.207290 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 21:21:12.208057 cs0 DataBus test pass
1078 21:21:12.208525 cs1 DataBus test pass
1079 21:21:12.212872 cs0 AddrBus test pass
1080 21:21:12.213341 cs1 AddrBus test pass
1081 21:21:12.213760
1082 21:21:12.218415 100bdlr_step_size ps== 420
1083 21:21:12.218889 result report
1084 21:21:12.219302 boot times 0Enable ddr reg access
1085 21:21:12.228447 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 21:21:12.241896 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 21:21:12.813963 0.0;M3 CHK:0;cm4_sp_mode 0
1088 21:21:12.814578 MVN_1=0x00000000
1089 21:21:12.819392 MVN_2=0x00000000
1090 21:21:12.825151 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 21:21:12.825606 OPS=0x10
1092 21:21:12.826021 ring efuse init
1093 21:21:12.826427 chipver efuse init
1094 21:21:12.830795 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 21:21:12.836349 [0.018961 Inits done]
1096 21:21:12.836804 secure task start!
1097 21:21:12.837213 high task start!
1098 21:21:12.840923 low task start!
1099 21:21:12.841375 run into bl31
1100 21:21:12.847570 NOTICE: BL31: v1.3(release):4fc40b1
1101 21:21:12.855366 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 21:21:12.855829 NOTICE: BL31: G12A normal boot!
1103 21:21:12.880874 NOTICE: BL31: BL33 decompress pass
1104 21:21:12.886419 ERROR: Error initializing runtime service opteed_fast
1105 21:21:14.119290
1106 21:21:14.119908
1107 21:21:14.127718 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 21:21:14.128219
1109 21:21:14.128642 Model: Libre Computer AML-A311D-CC Alta
1110 21:21:14.336141 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 21:21:14.359524 DRAM: 2 GiB (effective 3.8 GiB)
1112 21:21:14.502581 Core: 408 devices, 31 uclasses, devicetree: separate
1113 21:21:14.508398 WDT: Not starting watchdog@f0d0
1114 21:21:14.540673 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 21:21:14.553083 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 21:21:14.558104 ** Bad device specification mmc 0 **
1117 21:21:14.568408 Card did not respond to voltage select! : -110
1118 21:21:14.576109 ** Bad device specification mmc 0 **
1119 21:21:14.576592 Couldn't find partition mmc 0
1120 21:21:14.584439 Card did not respond to voltage select! : -110
1121 21:21:14.590040 ** Bad device specification mmc 0 **
1122 21:21:14.590501 Couldn't find partition mmc 0
1123 21:21:14.595090 Error: could not access storage.
1124 21:21:14.937455 Net: eth0: ethernet@ff3f0000
1125 21:21:14.938048 starting USB...
1126 21:21:15.191756 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 21:21:15.192361 Starting the controller
1128 21:21:15.196138 USB XHCI 1.10
1129 21:21:16.750441 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 21:21:16.758672 scanning usb for storage devices... 0 Storage Device(s) found
1132 21:21:16.809757 Hit any key to stop autoboot: 1
1133 21:21:16.810498 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 21:21:16.810869 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 21:21:16.811123 Setting prompt string to ['=>']
1136 21:21:16.811382 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 21:21:16.816170 0
1138 21:21:16.816751 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 21:21:16.817017 Sending with 10 millisecond of delay
1141 21:21:17.951382 => setenv autoload no
1142 21:21:17.962071 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 21:21:17.965214 setenv autoload no
1144 21:21:17.965966 Sending with 10 millisecond of delay
1146 21:21:19.763099 => setenv initrd_high 0xffffffff
1147 21:21:19.773842 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 21:21:19.774706 setenv initrd_high 0xffffffff
1149 21:21:19.775429 Sending with 10 millisecond of delay
1151 21:21:21.392834 => setenv fdt_high 0xffffffff
1152 21:21:21.403650 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 21:21:21.404597 setenv fdt_high 0xffffffff
1154 21:21:21.405365 Sending with 10 millisecond of delay
1156 21:21:21.697236 => dhcp
1157 21:21:21.707975 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1158 21:21:21.708881 dhcp
1159 21:21:21.709353 Speed: 1000, full duplex
1160 21:21:21.709807 BOOTP broadcast 1
1161 21:21:21.955931 BOOTP broadcast 2
1162 21:21:21.967864 DHCP client bound to address 192.168.6.33 (259 ms)
1163 21:21:21.968706 Sending with 10 millisecond of delay
1165 21:21:23.645160 => setenv serverip 192.168.6.2
1166 21:21:23.656009 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1167 21:21:23.656922 setenv serverip 192.168.6.2
1168 21:21:23.657684 Sending with 10 millisecond of delay
1170 21:21:27.380479 => tftpboot 0x01080000 823615/tftp-deploy-z5m0yg35/kernel/uImage
1171 21:21:27.391344 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1172 21:21:27.392364 tftpboot 0x01080000 823615/tftp-deploy-z5m0yg35/kernel/uImage
1173 21:21:27.392844 Speed: 1000, full duplex
1174 21:21:27.393282 Using ethernet@ff3f0000 device
1175 21:21:27.394234 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1176 21:21:27.399600 Filename '823615/tftp-deploy-z5m0yg35/kernel/uImage'.
1177 21:21:27.403481 Load address: 0x1080000
1178 21:21:32.217927 Loading: *######################################### UDP wrong checksum 000000ff 0000a74a
1179 21:21:32.248222 UDP wrong checksum 000000ff 0000443d
1180 21:21:41.046086 T T ######### 43.6 MiB
1181 21:21:41.046489 3.2 MiB/s
1182 21:21:41.046723 done
1183 21:21:41.050487 Bytes transferred = 45713984 (2b98a40 hex)
1184 21:21:41.051062 Sending with 10 millisecond of delay
1186 21:21:45.742707 => tftpboot 0x08000000 823615/tftp-deploy-z5m0yg35/ramdisk/ramdisk.cpio.gz.uboot
1187 21:21:45.753308 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:53)
1188 21:21:45.753833 tftpboot 0x08000000 823615/tftp-deploy-z5m0yg35/ramdisk/ramdisk.cpio.gz.uboot
1189 21:21:45.754074 Speed: 1000, full duplex
1190 21:21:45.754288 Using ethernet@ff3f0000 device
1191 21:21:45.756349 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1192 21:21:45.764879 Filename '823615/tftp-deploy-z5m0yg35/ramdisk/ramdisk.cpio.gz.uboot'.
1193 21:21:45.765179 Load address: 0x8000000
1194 21:21:47.754263 Loading: *################################################# UDP wrong checksum 00000005 0000f745
1195 21:21:52.754466 T UDP wrong checksum 00000005 0000f745
1196 21:22:02.756114 T T UDP wrong checksum 00000005 0000f745
1197 21:22:22.760150 T T T T UDP wrong checksum 00000005 0000f745
1198 21:22:37.383498 T T UDP wrong checksum 000000ff 00008682
1199 21:22:37.392636 UDP wrong checksum 000000ff 00001075
1200 21:22:40.872507 T UDP wrong checksum 000000ff 00004ecb
1201 21:22:40.902271 UDP wrong checksum 000000ff 0000e4bd
1202 21:22:42.765414
1203 21:22:42.765959 Retry count exceeded; starting again
1205 21:22:42.767034 end: 2.4.3 bootloader-commands (duration 00:01:26) [common]
1208 21:22:42.768245 end: 2.4 uboot-commands (duration 00:02:04) [common]
1210 21:22:42.769255 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1212 21:22:42.770108 end: 2 uboot-action (duration 00:02:04) [common]
1214 21:22:42.771269 Cleaning after the job
1215 21:22:42.771727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/ramdisk
1216 21:22:42.773035 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/kernel
1217 21:22:42.784403 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/dtb
1218 21:22:42.785565 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/nfsrootfs
1219 21:22:42.816101 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823615/tftp-deploy-z5m0yg35/modules
1220 21:22:42.825197 start: 4.1 power-off (timeout 00:00:30) [common]
1221 21:22:42.826057 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1222 21:22:42.860921 >> OK - accepted request
1223 21:22:42.862953 Returned 0 in 0 seconds
1224 21:22:42.963952 end: 4.1 power-off (duration 00:00:00) [common]
1226 21:22:42.965398 start: 4.2 read-feedback (timeout 00:10:00) [common]
1227 21:22:42.966305 Listened to connection for namespace 'common' for up to 1s
1228 21:22:43.966690 Finalising connection for namespace 'common'
1229 21:22:43.967461 Disconnecting from shell: Finalise
1230 21:22:43.968064 =>
1231 21:22:44.069097 end: 4.2 read-feedback (duration 00:00:01) [common]
1232 21:22:44.069760 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/823615
1233 21:22:48.041457 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/823615
1234 21:22:48.042109 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.