Boot log: meson-g12b-a311d-libretech-cc

    1 21:41:19.978354  lava-dispatcher, installed at version: 2024.01
    2 21:41:19.979120  start: 0 validate
    3 21:41:19.979585  Start time: 2024-10-08 21:41:19.979555+00:00 (UTC)
    4 21:41:19.980135  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    5 21:41:19.980664  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
    6 21:41:20.021033  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    7 21:41:20.021594  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
    8 21:41:20.053276  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
    9 21:41:20.053907  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
   10 21:41:20.087610  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   11 21:41:20.088138  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 21:41:20.120454  Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
   13 21:41:20.120943  Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
   14 21:41:20.153304  validate duration: 0.17
   16 21:41:20.154171  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 21:41:20.154517  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 21:41:20.154856  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 21:41:20.155434  Not decompressing ramdisk as can be used compressed.
   20 21:41:20.155881  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
   21 21:41:20.156196  saving as /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/ramdisk/initrd.cpio.gz
   22 21:41:20.156479  total size: 5628140 (5 MB)
   23 21:41:20.193888  progress   0 % (0 MB)
   24 21:41:20.201531  progress   5 % (0 MB)
   25 21:41:20.209103  progress  10 % (0 MB)
   26 21:41:20.216248  progress  15 % (0 MB)
   27 21:41:20.220454  progress  20 % (1 MB)
   28 21:41:20.224174  progress  25 % (1 MB)
   29 21:41:20.228171  progress  30 % (1 MB)
   30 21:41:20.232276  progress  35 % (1 MB)
   31 21:41:20.235900  progress  40 % (2 MB)
   32 21:41:20.239926  progress  45 % (2 MB)
   33 21:41:20.243561  progress  50 % (2 MB)
   34 21:41:20.247668  progress  55 % (2 MB)
   35 21:41:20.253985  progress  60 % (3 MB)
   36 21:41:20.257626  progress  65 % (3 MB)
   37 21:41:20.261655  progress  70 % (3 MB)
   38 21:41:20.265240  progress  75 % (4 MB)
   39 21:41:20.269251  progress  80 % (4 MB)
   40 21:41:20.272866  progress  85 % (4 MB)
   41 21:41:20.276917  progress  90 % (4 MB)
   42 21:41:20.280729  progress  95 % (5 MB)
   43 21:41:20.284056  progress 100 % (5 MB)
   44 21:41:20.284740  5 MB downloaded in 0.13 s (41.85 MB/s)
   45 21:41:20.285306  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 21:41:20.286201  end: 1.1 download-retry (duration 00:00:00) [common]
   48 21:41:20.286502  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 21:41:20.286778  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 21:41:20.287254  downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/kernel/Image
   51 21:41:20.287511  saving as /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/kernel/Image
   52 21:41:20.287723  total size: 45713920 (43 MB)
   53 21:41:20.287932  No compression specified
   54 21:41:20.324559  progress   0 % (0 MB)
   55 21:41:20.353014  progress   5 % (2 MB)
   56 21:41:20.381601  progress  10 % (4 MB)
   57 21:41:20.412433  progress  15 % (6 MB)
   58 21:41:20.440781  progress  20 % (8 MB)
   59 21:41:20.468910  progress  25 % (10 MB)
   60 21:41:20.497198  progress  30 % (13 MB)
   61 21:41:20.525720  progress  35 % (15 MB)
   62 21:41:20.554086  progress  40 % (17 MB)
   63 21:41:20.582107  progress  45 % (19 MB)
   64 21:41:20.610591  progress  50 % (21 MB)
   65 21:41:20.639040  progress  55 % (24 MB)
   66 21:41:20.667583  progress  60 % (26 MB)
   67 21:41:20.695656  progress  65 % (28 MB)
   68 21:41:20.724388  progress  70 % (30 MB)
   69 21:41:20.753024  progress  75 % (32 MB)
   70 21:41:20.781451  progress  80 % (34 MB)
   71 21:41:20.809682  progress  85 % (37 MB)
   72 21:41:20.838443  progress  90 % (39 MB)
   73 21:41:20.867312  progress  95 % (41 MB)
   74 21:41:20.895415  progress 100 % (43 MB)
   75 21:41:20.895973  43 MB downloaded in 0.61 s (71.68 MB/s)
   76 21:41:20.896506  end: 1.2.1 http-download (duration 00:00:01) [common]
   78 21:41:20.897343  end: 1.2 download-retry (duration 00:00:01) [common]
   79 21:41:20.897631  start: 1.3 download-retry (timeout 00:09:59) [common]
   80 21:41:20.897904  start: 1.3.1 http-download (timeout 00:09:59) [common]
   81 21:41:20.898387  downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
   82 21:41:20.898680  saving as /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/dtb/meson-g12b-a311d-libretech-cc.dtb
   83 21:41:20.898893  total size: 54703 (0 MB)
   84 21:41:20.899103  No compression specified
   85 21:41:20.942112  progress  59 % (0 MB)
   86 21:41:20.943007  progress 100 % (0 MB)
   87 21:41:20.943573  0 MB downloaded in 0.04 s (1.17 MB/s)
   88 21:41:20.944107  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 21:41:20.944955  end: 1.3 download-retry (duration 00:00:00) [common]
   91 21:41:20.945229  start: 1.4 download-retry (timeout 00:09:59) [common]
   92 21:41:20.945500  start: 1.4.1 http-download (timeout 00:09:59) [common]
   93 21:41:20.945966  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
   94 21:41:20.946229  saving as /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/nfsrootfs/full.rootfs.tar
   95 21:41:20.946440  total size: 474398908 (452 MB)
   96 21:41:20.946651  Using unxz to decompress xz
   97 21:41:20.986109  progress   0 % (0 MB)
   98 21:41:22.078746  progress   5 % (22 MB)
   99 21:41:23.519574  progress  10 % (45 MB)
  100 21:41:23.953474  progress  15 % (67 MB)
  101 21:41:24.759765  progress  20 % (90 MB)
  102 21:41:25.294988  progress  25 % (113 MB)
  103 21:41:25.652479  progress  30 % (135 MB)
  104 21:41:26.254643  progress  35 % (158 MB)
  105 21:41:27.193995  progress  40 % (181 MB)
  106 21:41:28.038105  progress  45 % (203 MB)
  107 21:41:28.752763  progress  50 % (226 MB)
  108 21:41:29.373204  progress  55 % (248 MB)
  109 21:41:30.574961  progress  60 % (271 MB)
  110 21:41:32.071182  progress  65 % (294 MB)
  111 21:41:33.780100  progress  70 % (316 MB)
  112 21:41:36.956011  progress  75 % (339 MB)
  113 21:41:39.373742  progress  80 % (361 MB)
  114 21:41:42.233576  progress  85 % (384 MB)
  115 21:41:45.370848  progress  90 % (407 MB)
  116 21:41:48.681590  progress  95 % (429 MB)
  117 21:41:51.816433  progress 100 % (452 MB)
  118 21:41:51.829239  452 MB downloaded in 30.88 s (14.65 MB/s)
  119 21:41:51.829789  end: 1.4.1 http-download (duration 00:00:31) [common]
  121 21:41:51.830616  end: 1.4 download-retry (duration 00:00:31) [common]
  122 21:41:51.830881  start: 1.5 download-retry (timeout 00:09:28) [common]
  123 21:41:51.831145  start: 1.5.1 http-download (timeout 00:09:28) [common]
  124 21:41:51.831798  downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/modules.tar.xz
  125 21:41:51.832206  saving as /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/modules/modules.tar
  126 21:41:51.832677  total size: 11613728 (11 MB)
  127 21:41:51.833138  Using unxz to decompress xz
  128 21:41:51.883202  progress   0 % (0 MB)
  129 21:41:51.944933  progress   5 % (0 MB)
  130 21:41:52.023218  progress  10 % (1 MB)
  131 21:41:52.110739  progress  15 % (1 MB)
  132 21:41:52.204281  progress  20 % (2 MB)
  133 21:41:52.288176  progress  25 % (2 MB)
  134 21:41:52.365862  progress  30 % (3 MB)
  135 21:41:52.449916  progress  35 % (3 MB)
  136 21:41:52.525261  progress  40 % (4 MB)
  137 21:41:52.602478  progress  45 % (5 MB)
  138 21:41:52.684237  progress  50 % (5 MB)
  139 21:41:52.762154  progress  55 % (6 MB)
  140 21:41:52.847879  progress  60 % (6 MB)
  141 21:41:52.922842  progress  65 % (7 MB)
  142 21:41:53.002931  progress  70 % (7 MB)
  143 21:41:53.075855  progress  75 % (8 MB)
  144 21:41:53.152060  progress  80 % (8 MB)
  145 21:41:53.236000  progress  85 % (9 MB)
  146 21:41:53.314927  progress  90 % (9 MB)
  147 21:41:53.399555  progress  95 % (10 MB)
  148 21:41:53.479012  progress 100 % (11 MB)
  149 21:41:53.491211  11 MB downloaded in 1.66 s (6.68 MB/s)
  150 21:41:53.491797  end: 1.5.1 http-download (duration 00:00:02) [common]
  152 21:41:53.493322  end: 1.5 download-retry (duration 00:00:02) [common]
  153 21:41:53.493846  start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
  154 21:41:53.494366  start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
  155 21:42:08.780965  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/823657/extract-nfsrootfs-99zzesod
  156 21:42:08.781558  end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
  157 21:42:08.781846  start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
  158 21:42:08.782568  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j
  159 21:42:08.783019  makedir: /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin
  160 21:42:08.783350  makedir: /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/tests
  161 21:42:08.783668  makedir: /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/results
  162 21:42:08.784036  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-add-keys
  163 21:42:08.784585  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-add-sources
  164 21:42:08.785093  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-background-process-start
  165 21:42:08.785590  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-background-process-stop
  166 21:42:08.786100  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-common-functions
  167 21:42:08.786587  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-echo-ipv4
  168 21:42:08.787063  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-install-packages
  169 21:42:08.787566  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-installed-packages
  170 21:42:08.788138  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-os-build
  171 21:42:08.788655  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-probe-channel
  172 21:42:08.789172  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-probe-ip
  173 21:42:08.789690  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-target-ip
  174 21:42:08.790174  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-target-mac
  175 21:42:08.790657  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-target-storage
  176 21:42:08.791147  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-test-case
  177 21:42:08.791633  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-test-event
  178 21:42:08.792140  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-test-feedback
  179 21:42:08.792637  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-test-raise
  180 21:42:08.793142  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-test-reference
  181 21:42:08.793651  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-test-runner
  182 21:42:08.794138  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-test-set
  183 21:42:08.794621  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-test-shell
  184 21:42:08.795130  Updating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-install-packages (oe)
  185 21:42:08.795709  Updating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/bin/lava-installed-packages (oe)
  186 21:42:08.796209  Creating /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/environment
  187 21:42:08.796599  LAVA metadata
  188 21:42:08.796862  - LAVA_JOB_ID=823657
  189 21:42:08.797078  - LAVA_DISPATCHER_IP=192.168.6.2
  190 21:42:08.797440  start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
  191 21:42:08.798450  end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
  192 21:42:08.798790  start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
  193 21:42:08.799004  skipped lava-vland-overlay
  194 21:42:08.799250  end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
  195 21:42:08.799508  start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
  196 21:42:08.799735  skipped lava-multinode-overlay
  197 21:42:08.800012  end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
  198 21:42:08.800281  start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
  199 21:42:08.800550  Loading test definitions
  200 21:42:08.800836  start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
  201 21:42:08.801060  Using /lava-823657 at stage 0
  202 21:42:08.802325  uuid=823657_1.6.2.4.1 testdef=None
  203 21:42:08.802684  end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
  204 21:42:08.802957  start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
  205 21:42:08.804885  end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
  207 21:42:08.805728  start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
  208 21:42:08.808072  end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
  210 21:42:08.808967  start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
  211 21:42:08.811201  runner path: /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 823657_1.6.2.4.1
  212 21:42:08.811916  end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
  214 21:42:08.812740  Creating lava-test-runner.conf files
  215 21:42:08.812947  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/823657/lava-overlay-h9w6qz_j/lava-823657/0 for stage 0
  216 21:42:08.813316  - 0_v4l2-decoder-conformance-h264
  217 21:42:08.813691  end: 1.6.2.4 test-definition (duration 00:00:00) [common]
  218 21:42:08.813980  start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
  219 21:42:08.836243  end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
  220 21:42:08.836701  start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
  221 21:42:08.836968  end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
  222 21:42:08.837243  end: 1.6.2 lava-overlay (duration 00:00:00) [common]
  223 21:42:08.837514  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
  224 21:42:09.450564  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  225 21:42:09.451022  start: 1.6.4 extract-modules (timeout 00:09:11) [common]
  226 21:42:09.451275  extracting modules file /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823657/extract-nfsrootfs-99zzesod
  227 21:42:10.817629  extracting modules file /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823657/extract-overlay-ramdisk-tw3qpevo/ramdisk
  228 21:42:12.239351  end: 1.6.4 extract-modules (duration 00:00:03) [common]
  229 21:42:12.239830  start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
  230 21:42:12.240133  [common] Applying overlay to NFS
  231 21:42:12.240349  [common] Applying overlay /var/lib/lava/dispatcher/tmp/823657/compress-overlay-1f7rjo58/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/823657/extract-nfsrootfs-99zzesod
  232 21:42:12.269851  end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
  233 21:42:12.270230  start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
  234 21:42:12.270502  start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
  235 21:42:12.270728  Converting downloaded kernel to a uImage
  236 21:42:12.271039  mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/kernel/Image /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/kernel/uImage
  237 21:42:12.747370  output: Image Name:   
  238 21:42:12.747798  output: Created:      Tue Oct  8 21:42:12 2024
  239 21:42:12.748047  output: Image Type:   AArch64 Linux Kernel Image (uncompressed)
  240 21:42:12.748258  output: Data Size:    45713920 Bytes = 44642.50 KiB = 43.60 MiB
  241 21:42:12.748462  output: Load Address: 01080000
  242 21:42:12.748665  output: Entry Point:  01080000
  243 21:42:12.748863  output: 
  244 21:42:12.749205  end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
  245 21:42:12.749473  end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
  246 21:42:12.749742  start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
  247 21:42:12.749997  end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
  248 21:42:12.750257  start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
  249 21:42:12.750513  Building ramdisk /var/lib/lava/dispatcher/tmp/823657/extract-overlay-ramdisk-tw3qpevo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/823657/extract-overlay-ramdisk-tw3qpevo/ramdisk
  250 21:42:15.244897  >> 166774 blocks

  251 21:42:22.927645  Adding RAMdisk u-boot header.
  252 21:42:22.928355  mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/823657/extract-overlay-ramdisk-tw3qpevo/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/823657/extract-overlay-ramdisk-tw3qpevo/ramdisk.cpio.gz.uboot
  253 21:42:23.174031  output: Image Name:   
  254 21:42:23.174658  output: Created:      Tue Oct  8 21:42:22 2024
  255 21:42:23.175095  output: Image Type:   AArch64 Linux RAMDisk Image (uncompressed)
  256 21:42:23.175510  output: Data Size:    23423611 Bytes = 22874.62 KiB = 22.34 MiB
  257 21:42:23.175918  output: Load Address: 00000000
  258 21:42:23.176371  output: Entry Point:  00000000
  259 21:42:23.176778  output: 
  260 21:42:23.177752  rename /var/lib/lava/dispatcher/tmp/823657/extract-overlay-ramdisk-tw3qpevo/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/ramdisk/ramdisk.cpio.gz.uboot
  261 21:42:23.178470  end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
  262 21:42:23.179027  end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
  263 21:42:23.179603  start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
  264 21:42:23.180110  No LXC device requested
  265 21:42:23.180635  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  266 21:42:23.181161  start: 1.8 deploy-device-env (timeout 00:08:57) [common]
  267 21:42:23.181672  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  268 21:42:23.182095  Checking files for TFTP limit of 4294967296 bytes.
  269 21:42:23.184789  end: 1 tftp-deploy (duration 00:01:03) [common]
  270 21:42:23.185362  start: 2 uboot-action (timeout 00:05:00) [common]
  271 21:42:23.185897  start: 2.1 uboot-from-media (timeout 00:05:00) [common]
  272 21:42:23.186401  end: 2.1 uboot-from-media (duration 00:00:00) [common]
  273 21:42:23.186916  start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
  274 21:42:23.187447  Using kernel file from prepare-kernel: 823657/tftp-deploy-tf2x0oe7/kernel/uImage
  275 21:42:23.188106  substitutions:
  276 21:42:23.188528  - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
  277 21:42:23.188937  - {DTB_ADDR}: 0x01070000
  278 21:42:23.189346  - {DTB}: 823657/tftp-deploy-tf2x0oe7/dtb/meson-g12b-a311d-libretech-cc.dtb
  279 21:42:23.189752  - {INITRD}: 823657/tftp-deploy-tf2x0oe7/ramdisk/ramdisk.cpio.gz.uboot
  280 21:42:23.190157  - {KERNEL_ADDR}: 0x01080000
  281 21:42:23.190556  - {KERNEL}: 823657/tftp-deploy-tf2x0oe7/kernel/uImage
  282 21:42:23.190956  - {LAVA_MAC}: None
  283 21:42:23.191392  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/823657/extract-nfsrootfs-99zzesod
  284 21:42:23.191799  - {NFS_SERVER_IP}: 192.168.6.2
  285 21:42:23.192222  - {PRESEED_CONFIG}: None
  286 21:42:23.192624  - {PRESEED_LOCAL}: None
  287 21:42:23.193022  - {RAMDISK_ADDR}: 0x08000000
  288 21:42:23.193413  - {RAMDISK}: 823657/tftp-deploy-tf2x0oe7/ramdisk/ramdisk.cpio.gz.uboot
  289 21:42:23.193808  - {ROOT_PART}: None
  290 21:42:23.194201  - {ROOT}: None
  291 21:42:23.194590  - {SERVER_IP}: 192.168.6.2
  292 21:42:23.194979  - {TEE_ADDR}: 0x83000000
  293 21:42:23.195372  - {TEE}: None
  294 21:42:23.195763  Parsed boot commands:
  295 21:42:23.196176  - setenv autoload no
  296 21:42:23.196576  - setenv initrd_high 0xffffffff
  297 21:42:23.196964  - setenv fdt_high 0xffffffff
  298 21:42:23.197351  - dhcp
  299 21:42:23.197742  - setenv serverip 192.168.6.2
  300 21:42:23.198132  - tftpboot 0x01080000 823657/tftp-deploy-tf2x0oe7/kernel/uImage
  301 21:42:23.198520  - tftpboot 0x08000000 823657/tftp-deploy-tf2x0oe7/ramdisk/ramdisk.cpio.gz.uboot
  302 21:42:23.198907  - tftpboot 0x01070000 823657/tftp-deploy-tf2x0oe7/dtb/meson-g12b-a311d-libretech-cc.dtb
  303 21:42:23.199302  - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/823657/extract-nfsrootfs-99zzesod,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
  304 21:42:23.199709  - bootm 0x01080000 0x08000000 0x01070000
  305 21:42:23.200241  end: 2.2 bootloader-overlay (duration 00:00:00) [common]
  307 21:42:23.201743  start: 2.3 connect-device (timeout 00:05:00) [common]
  308 21:42:23.202165  [common] connect-device Connecting to device using 'telnet conserv1 3007'
  309 21:42:23.216622  Setting prompt string to ['lava-test: # ']
  310 21:42:23.218089  end: 2.3 connect-device (duration 00:00:00) [common]
  311 21:42:23.218698  start: 2.4 uboot-commands (timeout 00:05:00) [common]
  312 21:42:23.219457  start: 2.4.1 reset-device (timeout 00:05:00) [common]
  313 21:42:23.220065  start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
  314 21:42:23.220795  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
  315 21:42:23.268236  >> OK - accepted request

  316 21:42:23.270373  Returned 0 in 0 seconds
  317 21:42:23.371458  end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
  319 21:42:23.373092  end: 2.4.1 reset-device (duration 00:00:00) [common]
  320 21:42:23.373674  start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
  321 21:42:23.374206  Setting prompt string to ['Hit any key to stop autoboot']
  322 21:42:23.374671  bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
  323 21:42:23.376258  Trying 192.168.56.21...
  324 21:42:23.376743  Connected to conserv1.
  325 21:42:23.377181  Escape character is '^]'.
  326 21:42:23.377605  
  327 21:42:23.378028  ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
  328 21:42:23.378445  
  329 21:42:34.838675  G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  330 21:42:34.839300  bl2_stage_init 0x01
  331 21:42:34.839728  bl2_stage_init 0x81
  332 21:42:34.844195  hw id: 0x0000 - pwm id 0x01
  333 21:42:34.844716  bl2_stage_init 0xc1
  334 21:42:34.845133  bl2_stage_init 0x02
  335 21:42:34.845531  
  336 21:42:34.849750  L0:00000000
  337 21:42:34.850223  L1:20000703
  338 21:42:34.850621  L2:00008067
  339 21:42:34.851019  L3:14000000
  340 21:42:34.852744  B2:00402000
  341 21:42:34.853231  B1:e0f83180
  342 21:42:34.853626  
  343 21:42:34.854020  TE: 58159
  344 21:42:34.854413  
  345 21:42:34.863914  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  346 21:42:34.864410  
  347 21:42:34.864810  Board ID = 1
  348 21:42:34.865198  Set A53 clk to 24M
  349 21:42:34.865583  Set A73 clk to 24M
  350 21:42:34.869500  Set clk81 to 24M
  351 21:42:34.869956  A53 clk: 1200 MHz
  352 21:42:34.870346  A73 clk: 1200 MHz
  353 21:42:34.872928  CLK81: 166.6M
  354 21:42:34.873386  smccc: 00012ab5
  355 21:42:34.878441  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  356 21:42:34.884079  board id: 1
  357 21:42:34.889174  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  358 21:42:34.899770  fw parse done
  359 21:42:34.905751  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  360 21:42:34.948403  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  361 21:42:34.959385  PIEI prepare done
  362 21:42:34.959866  fastboot data load
  363 21:42:34.960314  fastboot data verify
  364 21:42:34.964957  verify result: 266
  365 21:42:34.970614  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  366 21:42:34.971080  LPDDR4 probe
  367 21:42:34.971481  ddr clk to 1584MHz
  368 21:42:34.978562  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  369 21:42:35.015833  
  370 21:42:35.016337  dmc_version 0001
  371 21:42:35.022621  Check phy result
  372 21:42:35.028396  INFO : End of CA training
  373 21:42:35.028865  INFO : End of initialization
  374 21:42:35.034013  INFO : Training has run successfully!
  375 21:42:35.034481  Check phy result
  376 21:42:35.039612  INFO : End of initialization
  377 21:42:35.040106  INFO : End of read enable training
  378 21:42:35.042875  INFO : End of fine write leveling
  379 21:42:35.048414  INFO : End of Write leveling coarse delay
  380 21:42:35.054121  INFO : Training has run successfully!
  381 21:42:35.054642  Check phy result
  382 21:42:35.055061  INFO : End of initialization
  383 21:42:35.059700  INFO : End of read dq deskew training
  384 21:42:35.063108  INFO : End of MPR read delay center optimization
  385 21:42:35.068622  INFO : End of write delay center optimization
  386 21:42:35.074256  INFO : End of read delay center optimization
  387 21:42:35.074724  INFO : End of max read latency training
  388 21:42:35.079891  INFO : Training has run successfully!
  389 21:42:35.080415  1D training succeed
  390 21:42:35.088002  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  391 21:42:35.135561  Check phy result
  392 21:42:35.136071  INFO : End of initialization
  393 21:42:35.157234  INFO : End of 2D read delay Voltage center optimization
  394 21:42:35.176672  INFO : End of 2D read delay Voltage center optimization
  395 21:42:35.228696  INFO : End of 2D write delay Voltage center optimization
  396 21:42:35.278048  INFO : End of 2D write delay Voltage center optimization
  397 21:42:35.283615  INFO : Training has run successfully!
  398 21:42:35.284146  
  399 21:42:35.284591  channel==0
  400 21:42:35.289212  RxClkDly_Margin_A0==88 ps 9
  401 21:42:35.289720  TxDqDly_Margin_A0==98 ps 10
  402 21:42:35.292633  RxClkDly_Margin_A1==88 ps 9
  403 21:42:35.293117  TxDqDly_Margin_A1==98 ps 10
  404 21:42:35.298141  TrainedVREFDQ_A0==74
  405 21:42:35.298635  TrainedVREFDQ_A1==74
  406 21:42:35.299056  VrefDac_Margin_A0==25
  407 21:42:35.303819  DeviceVref_Margin_A0==40
  408 21:42:35.304414  VrefDac_Margin_A1==25
  409 21:42:35.309383  DeviceVref_Margin_A1==40
  410 21:42:35.309898  
  411 21:42:35.310329  
  412 21:42:35.310741  channel==1
  413 21:42:35.311144  RxClkDly_Margin_A0==88 ps 9
  414 21:42:35.314942  TxDqDly_Margin_A0==98 ps 10
  415 21:42:35.315436  RxClkDly_Margin_A1==88 ps 9
  416 21:42:35.320613  TxDqDly_Margin_A1==88 ps 9
  417 21:42:35.321103  TrainedVREFDQ_A0==77
  418 21:42:35.321523  TrainedVREFDQ_A1==77
  419 21:42:35.326143  VrefDac_Margin_A0==23
  420 21:42:35.326632  DeviceVref_Margin_A0==37
  421 21:42:35.331770  VrefDac_Margin_A1==24
  422 21:42:35.332305  DeviceVref_Margin_A1==37
  423 21:42:35.332726  
  424 21:42:35.337320   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  425 21:42:35.337805  
  426 21:42:35.365322  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
  427 21:42:35.370950  2D training succeed
  428 21:42:35.376612  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  429 21:42:35.377104  auto size-- 65535DDR cs0 size: 2048MB
  430 21:42:35.382117  DDR cs1 size: 2048MB
  431 21:42:35.382606  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  432 21:42:35.387741  cs0 DataBus test pass
  433 21:42:35.388269  cs1 DataBus test pass
  434 21:42:35.388690  cs0 AddrBus test pass
  435 21:42:35.393331  cs1 AddrBus test pass
  436 21:42:35.393813  
  437 21:42:35.394239  100bdlr_step_size ps== 420
  438 21:42:35.394658  result report
  439 21:42:35.398926  boot times 0Enable ddr reg access
  440 21:42:35.406462  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  441 21:42:35.419901  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  442 21:42:35.994918  0.0;M3 CHK:0;cm4_sp_mode 0
  443 21:42:35.995557  MVN_1=0x00000000
  444 21:42:35.998940  MVN_2=0x00000000
  445 21:42:36.004692  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  446 21:42:36.005207  OPS=0x10
  447 21:42:36.005674  ring efuse init
  448 21:42:36.006126  chipver efuse init
  449 21:42:36.010312  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  450 21:42:36.015904  [0.018961 Inits done]
  451 21:42:36.016428  secure task start!
  452 21:42:36.016889  high task start!
  453 21:42:36.020484  low task start!
  454 21:42:36.020983  run into bl31
  455 21:42:36.027136  NOTICE:  BL31: v1.3(release):4fc40b1
  456 21:42:36.034937  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  457 21:42:36.035511  NOTICE:  BL31: G12A normal boot!
  458 21:42:36.060392  NOTICE:  BL31: BL33 decompress pass
  459 21:42:36.066033  ERROR:   Error initializing runtime service opteed_fast
  460 21:42:37.298926  
  461 21:42:37.299336  
  462 21:42:37.307343  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  463 21:42:37.307892  
  464 21:42:37.308257  Model: Libre Computer AML-A311D-CC Alta
  465 21:42:37.515655  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  466 21:42:37.539085  DRAM:  2 GiB (effective 3.8 GiB)
  467 21:42:37.682057  Core:  408 devices, 31 uclasses, devicetree: separate
  468 21:42:37.687947  WDT:   Not starting watchdog@f0d0
  469 21:42:37.720209  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  470 21:42:37.732784  Loading Environment from FAT... Card did not respond to voltage select! : -110
  471 21:42:37.737639  ** Bad device specification mmc 0 **
  472 21:42:37.748013  Card did not respond to voltage select! : -110
  473 21:42:37.755631  ** Bad device specification mmc 0 **
  474 21:42:37.756177  Couldn't find partition mmc 0
  475 21:42:37.763957  Card did not respond to voltage select! : -110
  476 21:42:37.769518  ** Bad device specification mmc 0 **
  477 21:42:37.770029  Couldn't find partition mmc 0
  478 21:42:37.774565  Error: could not access storage.
  479 21:42:39.039070  G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  480 21:42:39.039692  bl2_stage_init 0x01
  481 21:42:39.040242  bl2_stage_init 0x81
  482 21:42:39.044533  hw id: 0x0000 - pwm id 0x01
  483 21:42:39.045047  bl2_stage_init 0xc1
  484 21:42:39.045504  bl2_stage_init 0x02
  485 21:42:39.045957  
  486 21:42:39.050180  L0:00000000
  487 21:42:39.050742  L1:20000703
  488 21:42:39.051210  L2:00008067
  489 21:42:39.051664  L3:14000000
  490 21:42:39.053038  B2:00402000
  491 21:42:39.053566  B1:e0f83180
  492 21:42:39.054025  
  493 21:42:39.054473  TE: 58124
  494 21:42:39.054919  
  495 21:42:39.064254  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  496 21:42:39.064834  
  497 21:42:39.065345  Board ID = 1
  498 21:42:39.065800  Set A53 clk to 24M
  499 21:42:39.066244  Set A73 clk to 24M
  500 21:42:39.069802  Set clk81 to 24M
  501 21:42:39.070325  A53 clk: 1200 MHz
  502 21:42:39.070774  A73 clk: 1200 MHz
  503 21:42:39.075497  CLK81: 166.6M
  504 21:42:39.076024  smccc: 00012a92
  505 21:42:39.081053  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  506 21:42:39.081581  board id: 1
  507 21:42:39.089614  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  508 21:42:39.100287  fw parse done
  509 21:42:39.106249  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  510 21:42:39.148890  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  511 21:42:39.159756  PIEI prepare done
  512 21:42:39.160317  fastboot data load
  513 21:42:39.160784  fastboot data verify
  514 21:42:39.165369  verify result: 266
  515 21:42:39.171038  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  516 21:42:39.171527  LPDDR4 probe
  517 21:42:39.171970  ddr clk to 1584MHz
  518 21:42:39.179060  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  519 21:42:39.216222  
  520 21:42:39.216706  dmc_version 0001
  521 21:42:39.222887  Check phy result
  522 21:42:39.228760  INFO : End of CA training
  523 21:42:39.229280  INFO : End of initialization
  524 21:42:39.234357  INFO : Training has run successfully!
  525 21:42:39.234840  Check phy result
  526 21:42:39.240082  INFO : End of initialization
  527 21:42:39.240640  INFO : End of read enable training
  528 21:42:39.245563  INFO : End of fine write leveling
  529 21:42:39.251131  INFO : End of Write leveling coarse delay
  530 21:42:39.251627  INFO : Training has run successfully!
  531 21:42:39.252095  Check phy result
  532 21:42:39.256715  INFO : End of initialization
  533 21:42:39.257196  INFO : End of read dq deskew training
  534 21:42:39.262309  INFO : End of MPR read delay center optimization
  535 21:42:39.268068  INFO : End of write delay center optimization
  536 21:42:39.273622  INFO : End of read delay center optimization
  537 21:42:39.274137  INFO : End of max read latency training
  538 21:42:39.279156  INFO : Training has run successfully!
  539 21:42:39.279669  1D training succeed
  540 21:42:39.288340  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  541 21:42:39.336041  Check phy result
  542 21:42:39.336562  INFO : End of initialization
  543 21:42:39.357526  INFO : End of 2D read delay Voltage center optimization
  544 21:42:39.377787  INFO : End of 2D read delay Voltage center optimization
  545 21:42:39.429668  INFO : End of 2D write delay Voltage center optimization
  546 21:42:39.478866  INFO : End of 2D write delay Voltage center optimization
  547 21:42:39.484358  INFO : Training has run successfully!
  548 21:42:39.484831  
  549 21:42:39.485269  channel==0
  550 21:42:39.489960  RxClkDly_Margin_A0==88 ps 9
  551 21:42:39.490430  TxDqDly_Margin_A0==98 ps 10
  552 21:42:39.495556  RxClkDly_Margin_A1==88 ps 9
  553 21:42:39.496065  TxDqDly_Margin_A1==98 ps 10
  554 21:42:39.496514  TrainedVREFDQ_A0==74
  555 21:42:39.501155  TrainedVREFDQ_A1==74
  556 21:42:39.501640  VrefDac_Margin_A0==25
  557 21:42:39.502074  DeviceVref_Margin_A0==40
  558 21:42:39.506745  VrefDac_Margin_A1==25
  559 21:42:39.507209  DeviceVref_Margin_A1==40
  560 21:42:39.507643  
  561 21:42:39.508106  
  562 21:42:39.512323  channel==1
  563 21:42:39.512807  RxClkDly_Margin_A0==98 ps 10
  564 21:42:39.513245  TxDqDly_Margin_A0==88 ps 9
  565 21:42:39.517949  RxClkDly_Margin_A1==98 ps 10
  566 21:42:39.518418  TxDqDly_Margin_A1==88 ps 9
  567 21:42:39.523528  TrainedVREFDQ_A0==77
  568 21:42:39.524013  TrainedVREFDQ_A1==77
  569 21:42:39.524458  VrefDac_Margin_A0==22
  570 21:42:39.529134  DeviceVref_Margin_A0==37
  571 21:42:39.529594  VrefDac_Margin_A1==22
  572 21:42:39.534748  DeviceVref_Margin_A1==37
  573 21:42:39.535225  
  574 21:42:39.535662   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  575 21:42:39.536127  
  576 21:42:39.568354  soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
  577 21:42:39.568868  2D training succeed
  578 21:42:39.574024  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  579 21:42:39.579555  auto size-- 65535DDR cs0 size: 2048MB
  580 21:42:39.580057  DDR cs1 size: 2048MB
  581 21:42:39.585155  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  582 21:42:39.585628  cs0 DataBus test pass
  583 21:42:39.590758  cs1 DataBus test pass
  584 21:42:39.591226  cs0 AddrBus test pass
  585 21:42:39.591661  cs1 AddrBus test pass
  586 21:42:39.592120  
  587 21:42:39.596347  100bdlr_step_size ps== 420
  588 21:42:39.596831  result report
  589 21:42:39.601973  boot times 0Enable ddr reg access
  590 21:42:39.607282  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  591 21:42:39.620740  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  592 21:42:40.193047  0.0;M3 CHK:0;cm4_sp_mode 0
  593 21:42:40.193677  MVN_1=0x00000000
  594 21:42:40.198457  MVN_2=0x00000000
  595 21:42:40.204274  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  596 21:42:40.204836  OPS=0x10
  597 21:42:40.205319  ring efuse init
  598 21:42:40.205802  chipver efuse init
  599 21:42:40.209746  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  600 21:42:40.215379  [0.018961 Inits done]
  601 21:42:40.215864  secure task start!
  602 21:42:40.216367  high task start!
  603 21:42:40.220265  low task start!
  604 21:42:40.220746  run into bl31
  605 21:42:40.226643  NOTICE:  BL31: v1.3(release):4fc40b1
  606 21:42:40.234385  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  607 21:42:40.234864  NOTICE:  BL31: G12A normal boot!
  608 21:42:40.259762  NOTICE:  BL31: BL33 decompress pass
  609 21:42:40.265544  ERROR:   Error initializing runtime service opteed_fast
  610 21:42:41.498508  
  611 21:42:41.499140  
  612 21:42:41.506864  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  613 21:42:41.507374  
  614 21:42:41.507855  Model: Libre Computer AML-A311D-CC Alta
  615 21:42:41.715328  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  616 21:42:41.738688  DRAM:  2 GiB (effective 3.8 GiB)
  617 21:42:41.881675  Core:  408 devices, 31 uclasses, devicetree: separate
  618 21:42:41.887501  WDT:   Not starting watchdog@f0d0
  619 21:42:41.919695  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  620 21:42:41.932089  Loading Environment from FAT... Card did not respond to voltage select! : -110
  621 21:42:41.937195  ** Bad device specification mmc 0 **
  622 21:42:41.947525  Card did not respond to voltage select! : -110
  623 21:42:41.955150  ** Bad device specification mmc 0 **
  624 21:42:41.955666  Couldn't find partition mmc 0
  625 21:42:41.963526  Card did not respond to voltage select! : -110
  626 21:42:41.968942  ** Bad device specification mmc 0 **
  627 21:42:41.969452  Couldn't find partition mmc 0
  628 21:42:41.973972  Error: could not access storage.
  629 21:42:42.316538  Net:   eth0: ethernet@ff3f0000
  630 21:42:42.317099  starting USB...
  631 21:42:42.568329  Bus usb@ff500000: Register 3000140 NbrPorts 3
  632 21:42:42.568911  Starting the controller
  633 21:42:42.575278  USB XHCI 1.10
  634 21:42:44.287686  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  635 21:42:44.288360  bl2_stage_init 0x01
  636 21:42:44.288799  bl2_stage_init 0x81
  637 21:42:44.293224  hw id: 0x0000 - pwm id 0x01
  638 21:42:44.293703  bl2_stage_init 0xc1
  639 21:42:44.294126  bl2_stage_init 0x02
  640 21:42:44.294537  
  641 21:42:44.298874  L0:00000000
  642 21:42:44.299343  L1:20000703
  643 21:42:44.299759  L2:00008067
  644 21:42:44.300203  L3:14000000
  645 21:42:44.301854  B2:00402000
  646 21:42:44.302313  B1:e0f83180
  647 21:42:44.302731  
  648 21:42:44.303139  TE: 58159
  649 21:42:44.303543  
  650 21:42:44.312850  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  651 21:42:44.313339  
  652 21:42:44.313763  Board ID = 1
  653 21:42:44.314170  Set A53 clk to 24M
  654 21:42:44.314576  Set A73 clk to 24M
  655 21:42:44.318578  Set clk81 to 24M
  656 21:42:44.319049  A53 clk: 1200 MHz
  657 21:42:44.319462  A73 clk: 1200 MHz
  658 21:42:44.322140  CLK81: 166.6M
  659 21:42:44.322603  smccc: 00012ab5
  660 21:42:44.327609  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  661 21:42:44.333282  board id: 1
  662 21:42:44.338502  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  663 21:42:44.348869  fw parse done
  664 21:42:44.354845  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  665 21:42:44.397435  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  666 21:42:44.408438  PIEI prepare done
  667 21:42:44.408902  fastboot data load
  668 21:42:44.409320  fastboot data verify
  669 21:42:44.414046  verify result: 266
  670 21:42:44.419627  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  671 21:42:44.420126  LPDDR4 probe
  672 21:42:44.420551  ddr clk to 1584MHz
  673 21:42:44.427624  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  674 21:42:44.464942  
  675 21:42:44.465408  dmc_version 0001
  676 21:42:44.471550  Check phy result
  677 21:42:44.477415  INFO : End of CA training
  678 21:42:44.477881  INFO : End of initialization
  679 21:42:44.483025  INFO : Training has run successfully!
  680 21:42:44.483491  Check phy result
  681 21:42:44.488625  INFO : End of initialization
  682 21:42:44.489088  INFO : End of read enable training
  683 21:42:44.494242  INFO : End of fine write leveling
  684 21:42:44.499875  INFO : End of Write leveling coarse delay
  685 21:42:44.500368  INFO : Training has run successfully!
  686 21:42:44.500784  Check phy result
  687 21:42:44.505418  INFO : End of initialization
  688 21:42:44.505878  INFO : End of read dq deskew training
  689 21:42:44.511021  INFO : End of MPR read delay center optimization
  690 21:42:44.516630  INFO : End of write delay center optimization
  691 21:42:44.522216  INFO : End of read delay center optimization
  692 21:42:44.522672  INFO : End of max read latency training
  693 21:42:44.527884  INFO : Training has run successfully!
  694 21:42:44.528385  1D training succeed
  695 21:42:44.536985  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  696 21:42:44.584566  Check phy result
  697 21:42:44.585031  INFO : End of initialization
  698 21:42:44.606141  INFO : End of 2D read delay Voltage center optimization
  699 21:42:44.626244  INFO : End of 2D read delay Voltage center optimization
  700 21:42:44.678182  INFO : End of 2D write delay Voltage center optimization
  701 21:42:44.727374  INFO : End of 2D write delay Voltage center optimization
  702 21:42:44.733014  INFO : Training has run successfully!
  703 21:42:44.733500  
  704 21:42:44.733919  channel==0
  705 21:42:44.738592  RxClkDly_Margin_A0==88 ps 9
  706 21:42:44.739094  TxDqDly_Margin_A0==98 ps 10
  707 21:42:44.741928  RxClkDly_Margin_A1==88 ps 9
  708 21:42:44.742396  TxDqDly_Margin_A1==88 ps 9
  709 21:42:44.747510  TrainedVREFDQ_A0==74
  710 21:42:44.748028  TrainedVREFDQ_A1==74
  711 21:42:44.748457  VrefDac_Margin_A0==25
  712 21:42:44.753130  DeviceVref_Margin_A0==40
  713 21:42:44.753779  VrefDac_Margin_A1==25
  714 21:42:44.758711  DeviceVref_Margin_A1==40
  715 21:42:44.759195  
  716 21:42:44.759609  
  717 21:42:44.760042  channel==1
  718 21:42:44.760448  RxClkDly_Margin_A0==98 ps 10
  719 21:42:44.764322  TxDqDly_Margin_A0==98 ps 10
  720 21:42:44.764808  RxClkDly_Margin_A1==88 ps 9
  721 21:42:44.769936  TxDqDly_Margin_A1==98 ps 10
  722 21:42:44.770433  TrainedVREFDQ_A0==77
  723 21:42:44.770851  TrainedVREFDQ_A1==77
  724 21:42:44.778400  VrefDac_Margin_A0==22
  725 21:42:44.778893  DeviceVref_Margin_A0==37
  726 21:42:44.781114  VrefDac_Margin_A1==24
  727 21:42:44.781578  DeviceVref_Margin_A1==37
  728 21:42:44.781984  
  729 21:42:44.786719   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  730 21:42:44.787192  
  731 21:42:44.814655  soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
  732 21:42:44.820279  2D training succeed
  733 21:42:44.825915  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  734 21:42:44.826377  auto size-- 65535DDR cs0 size: 2048MB
  735 21:42:44.831496  DDR cs1 size: 2048MB
  736 21:42:44.831956  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  737 21:42:44.837086  cs0 DataBus test pass
  738 21:42:44.837549  cs1 DataBus test pass
  739 21:42:44.837961  cs0 AddrBus test pass
  740 21:42:44.842705  cs1 AddrBus test pass
  741 21:42:44.843170  
  742 21:42:44.843586  100bdlr_step_size ps== 420
  743 21:42:44.844029  result report
  744 21:42:44.848303  boot times 0Enable ddr reg access
  745 21:42:44.856030  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  746 21:42:44.869321  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  747 21:42:45.441331  0.0;M3 CHK:0;cm4_sp_mode 0
  748 21:42:45.441888  MVN_1=0x00000000
  749 21:42:45.446958  MVN_2=0x00000000
  750 21:42:45.452623  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  751 21:42:45.453121  OPS=0x10
  752 21:42:45.453514  ring efuse init
  753 21:42:45.453899  chipver efuse init
  754 21:42:45.458169  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  755 21:42:45.463757  [0.018961 Inits done]
  756 21:42:45.464277  secure task start!
  757 21:42:45.464676  high task start!
  758 21:42:45.468358  low task start!
  759 21:42:45.468801  run into bl31
  760 21:42:45.475040  NOTICE:  BL31: v1.3(release):4fc40b1
  761 21:42:45.482841  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  762 21:42:45.483292  NOTICE:  BL31: G12A normal boot!
  763 21:42:45.508196  NOTICE:  BL31: BL33 decompress pass
  764 21:42:45.513992  ERROR:   Error initializing runtime service opteed_fast
  765 21:42:46.746807  
  766 21:42:46.747244  
  767 21:42:46.755164  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  768 21:42:46.755575  
  769 21:42:46.755903  Model: Libre Computer AML-A311D-CC Alta
  770 21:42:46.963628  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  771 21:42:46.986966  DRAM:  2 GiB (effective 3.8 GiB)
  772 21:42:47.130016  Core:  408 devices, 31 uclasses, devicetree: separate
  773 21:42:47.135791  WDT:   Not starting watchdog@f0d0
  774 21:42:47.168051  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  775 21:42:47.180478  Loading Environment from FAT... Card did not respond to voltage select! : -110
  776 21:42:47.185456  ** Bad device specification mmc 0 **
  777 21:42:47.195876  Card did not respond to voltage select! : -110
  778 21:42:47.203485  ** Bad device specification mmc 0 **
  779 21:42:47.203790  Couldn't find partition mmc 0
  780 21:42:47.211825  Card did not respond to voltage select! : -110
  781 21:42:47.217380  ** Bad device specification mmc 0 **
  782 21:42:47.217678  Couldn't find partition mmc 0
  783 21:42:47.222408  Error: could not access storage.
  784 21:42:47.565988  Net:   eth0: ethernet@ff3f0000
  785 21:42:47.566419  starting USB...
  786 21:42:47.817777  Bus usb@ff500000: Register 3000140 NbrPorts 3
  787 21:42:47.818369  Starting the controller
  788 21:42:47.824698  USB XHCI 1.10
  789 21:42:49.988142  scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  790 21:42:49.988766  bl2_stage_init 0x01
  791 21:42:49.989194  bl2_stage_init 0x81
  792 21:42:49.993761  hw id: 0x0000 - pwm id 0x01
  793 21:42:49.994233  bl2_stage_init 0xc1
  794 21:42:49.994644  bl2_stage_init 0x02
  795 21:42:49.995046  
  796 21:42:49.999368  L0:00000000
  797 21:42:49.999839  L1:20000703
  798 21:42:50.000300  L2:00008067
  799 21:42:50.000708  L3:14000000
  800 21:42:50.004765  B2:00402000
  801 21:42:50.005242  B1:e0f83180
  802 21:42:50.005669  
  803 21:42:50.006086  TE: 58124
  804 21:42:50.006494  
  805 21:42:50.010488  BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
  806 21:42:50.010958  
  807 21:42:50.011374  Board ID = 1
  808 21:42:50.016036  Set A53 clk to 24M
  809 21:42:50.016502  Set A73 clk to 24M
  810 21:42:50.016912  Set clk81 to 24M
  811 21:42:50.021580  A53 clk: 1200 MHz
  812 21:42:50.022038  A73 clk: 1200 MHz
  813 21:42:50.022447  CLK81: 166.6M
  814 21:42:50.022848  smccc: 00012a91
  815 21:42:50.027203  DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
  816 21:42:50.032812  board id: 1
  817 21:42:50.038666  Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  818 21:42:50.049308  fw parse done
  819 21:42:50.055297  Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  820 21:42:50.097928  Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
  821 21:42:50.108736  PIEI prepare done
  822 21:42:50.109194  fastboot data load
  823 21:42:50.109603  fastboot data verify
  824 21:42:50.114331  verify result: 266
  825 21:42:50.119948  Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
  826 21:42:50.120439  LPDDR4 probe
  827 21:42:50.120848  ddr clk to 1584MHz
  828 21:42:50.127942  Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
  829 21:42:50.165172  
  830 21:42:50.165633  dmc_version 0001
  831 21:42:50.171872  Check phy result
  832 21:42:50.177730  INFO : End of CA training
  833 21:42:50.178185  INFO : End of initialization
  834 21:42:50.183312  INFO : Training has run successfully!
  835 21:42:50.183763  Check phy result
  836 21:42:50.188920  INFO : End of initialization
  837 21:42:50.189377  INFO : End of read enable training
  838 21:42:50.194545  INFO : End of fine write leveling
  839 21:42:50.200140  INFO : End of Write leveling coarse delay
  840 21:42:50.200604  INFO : Training has run successfully!
  841 21:42:50.201012  Check phy result
  842 21:42:50.205699  INFO : End of initialization
  843 21:42:50.206148  INFO : End of read dq deskew training
  844 21:42:50.211319  INFO : End of MPR read delay center optimization
  845 21:42:50.216949  INFO : End of write delay center optimization
  846 21:42:50.222574  INFO : End of read delay center optimization
  847 21:42:50.223029  INFO : End of max read latency training
  848 21:42:50.228144  INFO : Training has run successfully!
  849 21:42:50.228598  1D training succeed
  850 21:42:50.237313  Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
  851 21:42:50.284921  Check phy result
  852 21:42:50.285397  INFO : End of initialization
  853 21:42:50.307486  INFO : End of 2D read delay Voltage center optimization
  854 21:42:50.327714  INFO : End of 2D read delay Voltage center optimization
  855 21:42:50.379719  INFO : End of 2D write delay Voltage center optimization
  856 21:42:50.429095  INFO : End of 2D write delay Voltage center optimization
  857 21:42:50.434702  INFO : Training has run successfully!
  858 21:42:50.435157  
  859 21:42:50.435571  channel==0
  860 21:42:50.440349  RxClkDly_Margin_A0==88 ps 9
  861 21:42:50.440806  TxDqDly_Margin_A0==98 ps 10
  862 21:42:50.443766  RxClkDly_Margin_A1==88 ps 9
  863 21:42:50.444252  TxDqDly_Margin_A1==88 ps 9
  864 21:42:50.449350  TrainedVREFDQ_A0==74
  865 21:42:50.449838  TrainedVREFDQ_A1==74
  866 21:42:50.450253  VrefDac_Margin_A0==25
  867 21:42:50.454895  DeviceVref_Margin_A0==40
  868 21:42:50.455349  VrefDac_Margin_A1==25
  869 21:42:50.460566  DeviceVref_Margin_A1==40
  870 21:42:50.461004  
  871 21:42:50.461394  
  872 21:42:50.461775  channel==1
  873 21:42:50.462155  RxClkDly_Margin_A0==98 ps 10
  874 21:42:50.466063  TxDqDly_Margin_A0==88 ps 9
  875 21:42:50.466509  RxClkDly_Margin_A1==88 ps 9
  876 21:42:50.471725  TxDqDly_Margin_A1==108 ps 11
  877 21:42:50.472198  TrainedVREFDQ_A0==77
  878 21:42:50.472591  TrainedVREFDQ_A1==78
  879 21:42:50.477339  VrefDac_Margin_A0==22
  880 21:42:50.477776  DeviceVref_Margin_A0==37
  881 21:42:50.482913  VrefDac_Margin_A1==24
  882 21:42:50.483349  DeviceVref_Margin_A1==36
  883 21:42:50.483735  
  884 21:42:50.488508   dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
  885 21:42:50.488950  
  886 21:42:50.516412  soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
  887 21:42:50.522141  2D training succeed
  888 21:42:50.527608  aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
  889 21:42:50.528081  auto size-- 65535DDR cs0 size: 2048MB
  890 21:42:50.533185  DDR cs1 size: 2048MB
  891 21:42:50.533620  DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  892 21:42:50.538795  cs0 DataBus test pass
  893 21:42:50.539230  cs1 DataBus test pass
  894 21:42:50.539618  cs0 AddrBus test pass
  895 21:42:50.544373  cs1 AddrBus test pass
  896 21:42:50.544835  
  897 21:42:50.545236  100bdlr_step_size ps== 420
  898 21:42:50.545640  result report
  899 21:42:50.549974  boot times 0Enable ddr reg access
  900 21:42:50.557532  Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  901 21:42:50.571007  Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
  902 21:42:51.144784  0.0;M3 CHK:0;cm4_sp_mode 0
  903 21:42:51.145375  MVN_1=0x00000000
  904 21:42:51.150251  MVN_2=0x00000000
  905 21:42:51.156031  [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
  906 21:42:51.156491  OPS=0x10
  907 21:42:51.156902  ring efuse init
  908 21:42:51.157301  chipver efuse init
  909 21:42:51.161640  29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50 
  910 21:42:51.167190  [0.018961 Inits done]
  911 21:42:51.167635  secure task start!
  912 21:42:51.168070  high task start!
  913 21:42:51.171759  low task start!
  914 21:42:51.172231  run into bl31
  915 21:42:51.178457  NOTICE:  BL31: v1.3(release):4fc40b1
  916 21:42:51.186246  NOTICE:  BL31: Built : 15:58:17, May 22 2019
  917 21:42:51.186706  NOTICE:  BL31: G12A normal boot!
  918 21:42:51.212187  NOTICE:  BL31: BL33 decompress pass
  919 21:42:51.217856  ERROR:   Error initializing runtime service opteed_fast
  920 21:42:52.450820  
  921 21:42:52.451375  
  922 21:42:52.459193  U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
  923 21:42:52.459656  
  924 21:42:52.460097  Model: Libre Computer AML-A311D-CC Alta
  925 21:42:52.667574  SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
  926 21:42:52.690863  DRAM:  2 GiB (effective 3.8 GiB)
  927 21:42:52.833969  Core:  408 devices, 31 uclasses, devicetree: separate
  928 21:42:52.839857  WDT:   Not starting watchdog@f0d0
  929 21:42:52.872102  MMC:   mmc@ffe05000: 1, mmc@ffe07000: 0
  930 21:42:52.884535  Loading Environment from FAT... Card did not respond to voltage select! : -110
  931 21:42:52.889550  ** Bad device specification mmc 0 **
  932 21:42:52.899903  Card did not respond to voltage select! : -110
  933 21:42:52.907538  ** Bad device specification mmc 0 **
  934 21:42:52.908018  Couldn't find partition mmc 0
  935 21:42:52.915922  Card did not respond to voltage select! : -110
  936 21:42:52.921399  ** Bad device specification mmc 0 **
  937 21:42:52.921858  Couldn't find partition mmc 0
  938 21:42:52.926462  Error: could not access storage.
  939 21:42:53.269978  Net:   eth0: ethernet@ff3f0000
  940 21:42:53.270493  starting USB...
  941 21:42:53.521756  Bus usb@ff500000: Register 3000140 NbrPorts 3
  942 21:42:53.522249  Starting the controller
  943 21:42:53.528750  USB XHCI 1.10
  944 21:42:55.082676  scanning bus usb@ff500000 for devices... 3 USB Device(s) found
  945 21:42:55.091013         scanning usb for storage devices... 0 Storage Device(s) found
  947 21:42:55.142535  Hit any key to stop autoboot:  1 
  948 21:42:55.143614  end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
  949 21:42:55.144253  start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
  950 21:42:55.144735  Setting prompt string to ['=>']
  951 21:42:55.145222  bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
  952 21:42:55.158466   0 
  953 21:42:55.159337  Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
  954 21:42:55.159828  Sending with 10 millisecond of delay
  956 21:42:56.294919  => setenv autoload no
  957 21:42:56.305751  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
  958 21:42:56.311138  setenv autoload no
  959 21:42:56.311914  Sending with 10 millisecond of delay
  961 21:42:58.109328  => setenv initrd_high 0xffffffff
  962 21:42:58.120112  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
  963 21:42:58.120986  setenv initrd_high 0xffffffff
  964 21:42:58.121746  Sending with 10 millisecond of delay
  966 21:42:59.738935  => setenv fdt_high 0xffffffff
  967 21:42:59.749754  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
  968 21:42:59.750606  setenv fdt_high 0xffffffff
  969 21:42:59.751359  Sending with 10 millisecond of delay
  971 21:43:00.043377  => dhcp
  972 21:43:00.054212  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
  973 21:43:00.055074  dhcp
  974 21:43:00.055578  Speed: 1000, full duplex
  975 21:43:00.056079  BOOTP broadcast 1
  976 21:43:00.302329  BOOTP broadcast 2
  977 21:43:00.419048   UDP wrong checksum 000000ff 00008fb0
  978 21:43:00.803362  BOOTP broadcast 3
  979 21:43:00.814778  DHCP client bound to address 192.168.6.33 (760 ms)
  980 21:43:00.815607  Sending with 10 millisecond of delay
  982 21:43:02.492614  => setenv serverip 192.168.6.2
  983 21:43:02.503508  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
  984 21:43:02.504600  setenv serverip 192.168.6.2
  985 21:43:02.505368  Sending with 10 millisecond of delay
  987 21:43:06.228836  => tftpboot 0x01080000 823657/tftp-deploy-tf2x0oe7/kernel/uImage
  988 21:43:06.239621  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
  989 21:43:06.240448  tftpboot 0x01080000 823657/tftp-deploy-tf2x0oe7/kernel/uImage
  990 21:43:06.240889  Speed: 1000, full duplex
  991 21:43:06.241302  Using ethernet@ff3f0000 device
  992 21:43:06.242342  TFTP from server 192.168.6.2; our IP address is 192.168.6.33
  993 21:43:06.247943  Filename '823657/tftp-deploy-tf2x0oe7/kernel/uImage'.
  994 21:43:06.251917  Load address: 0x1080000
  995 21:43:11.160564  Loading: *##################################################  43.6 MiB
  996 21:43:11.161192  	 8.9 MiB/s
  997 21:43:11.161626  done
  998 21:43:11.164443  Bytes transferred = 45713984 (2b98a40 hex)
  999 21:43:11.165238  Sending with 10 millisecond of delay
 1001 21:43:15.852568  => tftpboot 0x08000000 823657/tftp-deploy-tf2x0oe7/ramdisk/ramdisk.cpio.gz.uboot
 1002 21:43:15.863352  bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:07)
 1003 21:43:15.864197  tftpboot 0x08000000 823657/tftp-deploy-tf2x0oe7/ramdisk/ramdisk.cpio.gz.uboot
 1004 21:43:15.864646  Speed: 1000, full duplex
 1005 21:43:15.865058  Using ethernet@ff3f0000 device
 1006 21:43:15.867167  TFTP from server 192.168.6.2; our IP address is 192.168.6.33
 1007 21:43:15.874927  Filename '823657/tftp-deploy-tf2x0oe7/ramdisk/ramdisk.cpio.gz.uboot'.
 1008 21:43:15.875421  Load address: 0x8000000
 1009 21:43:17.916217  Loading: *################################################# UDP wrong checksum 00000005 00000d80
 1010 21:43:22.915838  T  UDP wrong checksum 00000005 00000d80
 1011 21:43:32.917805  T T  UDP wrong checksum 00000005 00000d80
 1012 21:43:52.921883  T T T T  UDP wrong checksum 00000005 00000d80
 1013 21:44:12.926794  T T T 
 1014 21:44:12.927186  Retry count exceeded; starting again
 1016 21:44:12.928181  end: 2.4.3 bootloader-commands (duration 00:01:18) [common]
 1019 21:44:12.930089  end: 2.4 uboot-commands (duration 00:01:50) [common]
 1021 21:44:12.931475  uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
 1023 21:44:12.932517  end: 2 uboot-action (duration 00:01:50) [common]
 1025 21:44:12.934024  Cleaning after the job
 1026 21:44:12.934568  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/ramdisk
 1027 21:44:12.935829  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/kernel
 1028 21:44:12.979350  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/dtb
 1029 21:44:12.980218  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/nfsrootfs
 1030 21:44:13.207383  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823657/tftp-deploy-tf2x0oe7/modules
 1031 21:44:13.227035  start: 4.1 power-off (timeout 00:00:30) [common]
 1032 21:44:13.227757  Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
 1033 21:44:13.262109  >> OK - accepted request

 1034 21:44:13.264214  Returned 0 in 0 seconds
 1035 21:44:13.365209  end: 4.1 power-off (duration 00:00:00) [common]
 1037 21:44:13.366710  start: 4.2 read-feedback (timeout 00:10:00) [common]
 1038 21:44:13.367741  Listened to connection for namespace 'common' for up to 1s
 1039 21:44:14.368583  Finalising connection for namespace 'common'
 1040 21:44:14.369230  Disconnecting from shell: Finalise
 1041 21:44:14.369626  => 
 1042 21:44:14.470467  end: 4.2 read-feedback (duration 00:00:01) [common]
 1043 21:44:14.471022  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/823657
 1044 21:44:17.169779  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/823657
 1045 21:44:17.170406  InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.