Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:15:38.961662 lava-dispatcher, installed at version: 2024.01
2 21:15:38.962434 start: 0 validate
3 21:15:38.962919 Start time: 2024-10-08 21:15:38.962889+00:00 (UTC)
4 21:15:38.963458 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:15:38.964031 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 21:15:39.002940 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:15:39.003517 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:15:39.034496 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:15:39.035151 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:15:39.066982 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:15:39.067490 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 21:15:39.100403 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 21:15:39.100942 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 21:15:39.140347 validate duration: 0.18
16 21:15:39.141213 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:15:39.141544 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:15:39.141864 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:15:39.142462 Not decompressing ramdisk as can be used compressed.
20 21:15:39.142933 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 21:15:39.143221 saving as /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/ramdisk/initrd.cpio.gz
22 21:15:39.143498 total size: 5628140 (5 MB)
23 21:15:39.175604 progress 0 % (0 MB)
24 21:15:39.180691 progress 5 % (0 MB)
25 21:15:39.185730 progress 10 % (0 MB)
26 21:15:39.190358 progress 15 % (0 MB)
27 21:15:39.195545 progress 20 % (1 MB)
28 21:15:39.202411 progress 25 % (1 MB)
29 21:15:39.207514 progress 30 % (1 MB)
30 21:15:39.212610 progress 35 % (1 MB)
31 21:15:39.217143 progress 40 % (2 MB)
32 21:15:39.222286 progress 45 % (2 MB)
33 21:15:39.226796 progress 50 % (2 MB)
34 21:15:39.231825 progress 55 % (2 MB)
35 21:15:39.236842 progress 60 % (3 MB)
36 21:15:39.241406 progress 65 % (3 MB)
37 21:15:39.246543 progress 70 % (3 MB)
38 21:15:39.251044 progress 75 % (4 MB)
39 21:15:39.255939 progress 80 % (4 MB)
40 21:15:39.260608 progress 85 % (4 MB)
41 21:15:39.265624 progress 90 % (4 MB)
42 21:15:39.270519 progress 95 % (5 MB)
43 21:15:39.274513 progress 100 % (5 MB)
44 21:15:39.275368 5 MB downloaded in 0.13 s (40.71 MB/s)
45 21:15:39.276120 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:15:39.277325 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:15:39.277735 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:15:39.278093 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:15:39.278691 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/kernel/Image
51 21:15:39.279023 saving as /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/kernel/Image
52 21:15:39.279291 total size: 45713920 (43 MB)
53 21:15:39.279565 No compression specified
54 21:15:39.320158 progress 0 % (0 MB)
55 21:15:39.353428 progress 5 % (2 MB)
56 21:15:39.386408 progress 10 % (4 MB)
57 21:15:39.420318 progress 15 % (6 MB)
58 21:15:39.453969 progress 20 % (8 MB)
59 21:15:39.486913 progress 25 % (10 MB)
60 21:15:39.520118 progress 30 % (13 MB)
61 21:15:39.553801 progress 35 % (15 MB)
62 21:15:39.587275 progress 40 % (17 MB)
63 21:15:39.619959 progress 45 % (19 MB)
64 21:15:39.652678 progress 50 % (21 MB)
65 21:15:39.685886 progress 55 % (24 MB)
66 21:15:39.719471 progress 60 % (26 MB)
67 21:15:39.752378 progress 65 % (28 MB)
68 21:15:39.786006 progress 70 % (30 MB)
69 21:15:39.819420 progress 75 % (32 MB)
70 21:15:39.852987 progress 80 % (34 MB)
71 21:15:39.885582 progress 85 % (37 MB)
72 21:15:39.919173 progress 90 % (39 MB)
73 21:15:39.952676 progress 95 % (41 MB)
74 21:15:39.986072 progress 100 % (43 MB)
75 21:15:39.986738 43 MB downloaded in 0.71 s (61.63 MB/s)
76 21:15:39.987346 end: 1.2.1 http-download (duration 00:00:01) [common]
78 21:15:39.988427 end: 1.2 download-retry (duration 00:00:01) [common]
79 21:15:39.988804 start: 1.3 download-retry (timeout 00:09:59) [common]
80 21:15:39.989160 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 21:15:39.989744 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 21:15:39.990091 saving as /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/dtb/meson-g12b-a311d-libretech-cc.dtb
83 21:15:39.990364 total size: 54703 (0 MB)
84 21:15:39.990629 No compression specified
85 21:15:40.027975 progress 59 % (0 MB)
86 21:15:40.029111 progress 100 % (0 MB)
87 21:15:40.029883 0 MB downloaded in 0.04 s (1.32 MB/s)
88 21:15:40.030791 end: 1.3.1 http-download (duration 00:00:00) [common]
90 21:15:40.031888 end: 1.3 download-retry (duration 00:00:00) [common]
91 21:15:40.032300 start: 1.4 download-retry (timeout 00:09:59) [common]
92 21:15:40.032689 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 21:15:40.033387 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 21:15:40.033731 saving as /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/nfsrootfs/full.rootfs.tar
95 21:15:40.034178 total size: 474398908 (452 MB)
96 21:15:40.034530 Using unxz to decompress xz
97 21:15:40.071074 progress 0 % (0 MB)
98 21:15:41.184370 progress 5 % (22 MB)
99 21:15:42.652957 progress 10 % (45 MB)
100 21:15:43.109472 progress 15 % (67 MB)
101 21:15:43.874054 progress 20 % (90 MB)
102 21:15:44.389058 progress 25 % (113 MB)
103 21:15:44.732150 progress 30 % (135 MB)
104 21:15:45.326839 progress 35 % (158 MB)
105 21:15:46.228539 progress 40 % (181 MB)
106 21:15:46.993360 progress 45 % (203 MB)
107 21:15:47.579712 progress 50 % (226 MB)
108 21:15:48.212302 progress 55 % (248 MB)
109 21:15:49.392485 progress 60 % (271 MB)
110 21:15:50.874855 progress 65 % (294 MB)
111 21:15:52.481609 progress 70 % (316 MB)
112 21:15:55.618351 progress 75 % (339 MB)
113 21:15:58.075479 progress 80 % (361 MB)
114 21:16:00.989132 progress 85 % (384 MB)
115 21:16:04.204819 progress 90 % (407 MB)
116 21:16:07.445014 progress 95 % (429 MB)
117 21:16:10.618328 progress 100 % (452 MB)
118 21:16:10.631222 452 MB downloaded in 30.60 s (14.79 MB/s)
119 21:16:10.631841 end: 1.4.1 http-download (duration 00:00:31) [common]
121 21:16:10.632796 end: 1.4 download-retry (duration 00:00:31) [common]
122 21:16:10.633087 start: 1.5 download-retry (timeout 00:09:29) [common]
123 21:16:10.633365 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 21:16:10.634031 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/modules.tar.xz
125 21:16:10.634315 saving as /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/modules/modules.tar
126 21:16:10.634534 total size: 11613728 (11 MB)
127 21:16:10.634757 Using unxz to decompress xz
128 21:16:10.677567 progress 0 % (0 MB)
129 21:16:10.739386 progress 5 % (0 MB)
130 21:16:10.818859 progress 10 % (1 MB)
131 21:16:10.906678 progress 15 % (1 MB)
132 21:16:10.999705 progress 20 % (2 MB)
133 21:16:11.082765 progress 25 % (2 MB)
134 21:16:11.160632 progress 30 % (3 MB)
135 21:16:11.244617 progress 35 % (3 MB)
136 21:16:11.320669 progress 40 % (4 MB)
137 21:16:11.398833 progress 45 % (5 MB)
138 21:16:11.480889 progress 50 % (5 MB)
139 21:16:11.558807 progress 55 % (6 MB)
140 21:16:11.643055 progress 60 % (6 MB)
141 21:16:11.718127 progress 65 % (7 MB)
142 21:16:11.798280 progress 70 % (7 MB)
143 21:16:11.871850 progress 75 % (8 MB)
144 21:16:11.948761 progress 80 % (8 MB)
145 21:16:12.033557 progress 85 % (9 MB)
146 21:16:12.112632 progress 90 % (9 MB)
147 21:16:12.193861 progress 95 % (10 MB)
148 21:16:12.274073 progress 100 % (11 MB)
149 21:16:12.286226 11 MB downloaded in 1.65 s (6.71 MB/s)
150 21:16:12.286822 end: 1.5.1 http-download (duration 00:00:02) [common]
152 21:16:12.287686 end: 1.5 download-retry (duration 00:00:02) [common]
153 21:16:12.287961 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 21:16:12.288617 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 21:16:28.118816 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/823595/extract-nfsrootfs-345spu24
156 21:16:28.119432 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 21:16:28.119784 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 21:16:28.120539 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62
159 21:16:28.121215 makedir: /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin
160 21:16:28.122126 makedir: /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/tests
161 21:16:28.122615 makedir: /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/results
162 21:16:28.123003 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-add-keys
163 21:16:28.123700 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-add-sources
164 21:16:28.124311 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-background-process-start
165 21:16:28.124906 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-background-process-stop
166 21:16:28.125562 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-common-functions
167 21:16:28.126135 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-echo-ipv4
168 21:16:28.126968 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-install-packages
169 21:16:28.127616 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-installed-packages
170 21:16:28.128293 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-os-build
171 21:16:28.128968 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-probe-channel
172 21:16:28.129534 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-probe-ip
173 21:16:28.130082 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-target-ip
174 21:16:28.130774 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-target-mac
175 21:16:28.131333 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-target-storage
176 21:16:28.131881 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-test-case
177 21:16:28.132486 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-test-event
178 21:16:28.133035 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-test-feedback
179 21:16:28.133597 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-test-raise
180 21:16:28.134215 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-test-reference
181 21:16:28.134768 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-test-runner
182 21:16:28.135306 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-test-set
183 21:16:28.135832 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-test-shell
184 21:16:28.136593 Updating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-install-packages (oe)
185 21:16:28.137252 Updating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/bin/lava-installed-packages (oe)
186 21:16:28.137769 Creating /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/environment
187 21:16:28.138334 LAVA metadata
188 21:16:28.138644 - LAVA_JOB_ID=823595
189 21:16:28.138890 - LAVA_DISPATCHER_IP=192.168.6.2
190 21:16:28.139374 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 21:16:28.140552 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 21:16:28.140930 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 21:16:28.141147 skipped lava-vland-overlay
194 21:16:28.141403 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 21:16:28.141667 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 21:16:28.141895 skipped lava-multinode-overlay
197 21:16:28.142143 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 21:16:28.142402 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 21:16:28.142668 Loading test definitions
200 21:16:28.142961 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 21:16:28.143186 Using /lava-823595 at stage 0
202 21:16:28.144666 uuid=823595_1.6.2.4.1 testdef=None
203 21:16:28.145023 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 21:16:28.145293 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 21:16:28.149435 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 21:16:28.150262 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 21:16:28.153064 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 21:16:28.153969 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 21:16:28.156631 runner path: /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 823595_1.6.2.4.1
212 21:16:28.157280 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 21:16:28.158096 Creating lava-test-runner.conf files
215 21:16:28.158330 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/823595/lava-overlay-l33g9j62/lava-823595/0 for stage 0
216 21:16:28.158713 - 0_v4l2-decoder-conformance-h265
217 21:16:28.159083 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 21:16:28.159382 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 21:16:28.188729 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 21:16:28.189187 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 21:16:28.189762 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 21:16:28.190050 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 21:16:28.190316 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 21:16:29.088309 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 21:16:29.088781 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 21:16:29.089030 extracting modules file /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823595/extract-nfsrootfs-345spu24
227 21:16:30.496680 extracting modules file /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823595/extract-overlay-ramdisk-f23c48ic/ramdisk
228 21:16:31.918499 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 21:16:31.918979 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 21:16:31.919274 [common] Applying overlay to NFS
231 21:16:31.919498 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823595/compress-overlay-gdz3u9ul/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/823595/extract-nfsrootfs-345spu24
232 21:16:31.949438 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 21:16:31.949836 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 21:16:31.950128 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 21:16:31.950367 Converting downloaded kernel to a uImage
236 21:16:31.950681 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/kernel/Image /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/kernel/uImage
237 21:16:32.467026 output: Image Name:
238 21:16:32.467431 output: Created: Tue Oct 8 21:16:31 2024
239 21:16:32.467661 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 21:16:32.467877 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 21:16:32.468122 output: Load Address: 01080000
242 21:16:32.468333 output: Entry Point: 01080000
243 21:16:32.468536 output:
244 21:16:32.468914 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 21:16:32.469212 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 21:16:32.469494 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 21:16:32.469758 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 21:16:32.470026 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 21:16:32.470289 Building ramdisk /var/lib/lava/dispatcher/tmp/823595/extract-overlay-ramdisk-f23c48ic/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/823595/extract-overlay-ramdisk-f23c48ic/ramdisk
250 21:16:34.750004 >> 166774 blocks
251 21:16:42.476066 Adding RAMdisk u-boot header.
252 21:16:42.476797 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/823595/extract-overlay-ramdisk-f23c48ic/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/823595/extract-overlay-ramdisk-f23c48ic/ramdisk.cpio.gz.uboot
253 21:16:42.724978 output: Image Name:
254 21:16:42.725428 output: Created: Tue Oct 8 21:16:42 2024
255 21:16:42.725670 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 21:16:42.725909 output: Data Size: 23422541 Bytes = 22873.58 KiB = 22.34 MiB
257 21:16:42.726137 output: Load Address: 00000000
258 21:16:42.726353 output: Entry Point: 00000000
259 21:16:42.726561 output:
260 21:16:42.727287 rename /var/lib/lava/dispatcher/tmp/823595/extract-overlay-ramdisk-f23c48ic/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/ramdisk/ramdisk.cpio.gz.uboot
261 21:16:42.727754 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 21:16:42.728103 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 21:16:42.728402 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 21:16:42.728677 No LXC device requested
265 21:16:42.728990 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 21:16:42.729297 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 21:16:42.729591 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 21:16:42.729816 Checking files for TFTP limit of 4294967296 bytes.
269 21:16:42.731317 end: 1 tftp-deploy (duration 00:01:04) [common]
270 21:16:42.731648 start: 2 uboot-action (timeout 00:05:00) [common]
271 21:16:42.731933 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 21:16:42.732466 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 21:16:42.733041 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 21:16:42.733633 Using kernel file from prepare-kernel: 823595/tftp-deploy-fe4pngen/kernel/uImage
275 21:16:42.734340 substitutions:
276 21:16:42.734801 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 21:16:42.735253 - {DTB_ADDR}: 0x01070000
278 21:16:42.735702 - {DTB}: 823595/tftp-deploy-fe4pngen/dtb/meson-g12b-a311d-libretech-cc.dtb
279 21:16:42.736209 - {INITRD}: 823595/tftp-deploy-fe4pngen/ramdisk/ramdisk.cpio.gz.uboot
280 21:16:42.736665 - {KERNEL_ADDR}: 0x01080000
281 21:16:42.737105 - {KERNEL}: 823595/tftp-deploy-fe4pngen/kernel/uImage
282 21:16:42.737545 - {LAVA_MAC}: None
283 21:16:42.738031 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/823595/extract-nfsrootfs-345spu24
284 21:16:42.738482 - {NFS_SERVER_IP}: 192.168.6.2
285 21:16:42.738922 - {PRESEED_CONFIG}: None
286 21:16:42.739358 - {PRESEED_LOCAL}: None
287 21:16:42.739794 - {RAMDISK_ADDR}: 0x08000000
288 21:16:42.740380 - {RAMDISK}: 823595/tftp-deploy-fe4pngen/ramdisk/ramdisk.cpio.gz.uboot
289 21:16:42.741098 - {ROOT_PART}: None
290 21:16:42.741569 - {ROOT}: None
291 21:16:42.741782 - {SERVER_IP}: 192.168.6.2
292 21:16:42.741988 - {TEE_ADDR}: 0x83000000
293 21:16:42.742190 - {TEE}: None
294 21:16:42.742393 Parsed boot commands:
295 21:16:42.742598 - setenv autoload no
296 21:16:42.742808 - setenv initrd_high 0xffffffff
297 21:16:42.743008 - setenv fdt_high 0xffffffff
298 21:16:42.743206 - dhcp
299 21:16:42.743611 - setenv serverip 192.168.6.2
300 21:16:42.743851 - tftpboot 0x01080000 823595/tftp-deploy-fe4pngen/kernel/uImage
301 21:16:42.744080 - tftpboot 0x08000000 823595/tftp-deploy-fe4pngen/ramdisk/ramdisk.cpio.gz.uboot
302 21:16:42.744288 - tftpboot 0x01070000 823595/tftp-deploy-fe4pngen/dtb/meson-g12b-a311d-libretech-cc.dtb
303 21:16:42.744490 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/823595/extract-nfsrootfs-345spu24,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 21:16:42.744700 - bootm 0x01080000 0x08000000 0x01070000
305 21:16:42.744992 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 21:16:42.745788 start: 2.3 connect-device (timeout 00:05:00) [common]
308 21:16:42.746016 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 21:16:42.757907 Setting prompt string to ['lava-test: # ']
310 21:16:42.759511 end: 2.3 connect-device (duration 00:00:00) [common]
311 21:16:42.760229 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 21:16:42.760871 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 21:16:42.761482 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 21:16:42.762624 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 21:16:42.800439 >> OK - accepted request
316 21:16:42.802801 Returned 0 in 0 seconds
317 21:16:42.903792 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 21:16:42.904886 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 21:16:42.905210 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 21:16:42.905509 Setting prompt string to ['Hit any key to stop autoboot']
322 21:16:42.905746 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 21:16:42.906702 Trying 192.168.56.21...
324 21:16:42.907006 Connected to conserv1.
325 21:16:42.907264 Escape character is '^]'.
326 21:16:42.907516
327 21:16:42.907819 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 21:16:42.908092
329 21:16:54.206980 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 21:16:54.207642 bl2_stage_init 0x01
331 21:16:54.208140 bl2_stage_init 0x81
332 21:16:54.212458 hw id: 0x0000 - pwm id 0x01
333 21:16:54.212949 bl2_stage_init 0xc1
334 21:16:54.213403 bl2_stage_init 0x02
335 21:16:54.213841
336 21:16:54.218154 L0:00000000
337 21:16:54.218634 L1:20000703
338 21:16:54.219071 L2:00008067
339 21:16:54.219510 L3:14000000
340 21:16:54.223635 B2:00402000
341 21:16:54.224143 B1:e0f83180
342 21:16:54.224580
343 21:16:54.225013 TE: 58124
344 21:16:54.225450
345 21:16:54.229224 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 21:16:54.229710
347 21:16:54.230151 Board ID = 1
348 21:16:54.234883 Set A53 clk to 24M
349 21:16:54.235347 Set A73 clk to 24M
350 21:16:54.235780 Set clk81 to 24M
351 21:16:54.240414 A53 clk: 1200 MHz
352 21:16:54.240903 A73 clk: 1200 MHz
353 21:16:54.241334 CLK81: 166.6M
354 21:16:54.241757 smccc: 00012a92
355 21:16:54.246141 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 21:16:54.251599 board id: 1
357 21:16:54.257481 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 21:16:54.268173 fw parse done
359 21:16:54.274205 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 21:16:54.316743 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 21:16:54.327625 PIEI prepare done
362 21:16:54.328122 fastboot data load
363 21:16:54.328564 fastboot data verify
364 21:16:54.333292 verify result: 266
365 21:16:54.338975 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 21:16:54.339439 LPDDR4 probe
367 21:16:54.339876 ddr clk to 1584MHz
368 21:16:54.346923 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 21:16:54.384185
370 21:16:54.384691 dmc_version 0001
371 21:16:54.390781 Check phy result
372 21:16:54.396679 INFO : End of CA training
373 21:16:54.397140 INFO : End of initialization
374 21:16:54.402276 INFO : Training has run successfully!
375 21:16:54.402739 Check phy result
376 21:16:54.408012 INFO : End of initialization
377 21:16:54.408480 INFO : End of read enable training
378 21:16:54.413473 INFO : End of fine write leveling
379 21:16:54.419209 INFO : End of Write leveling coarse delay
380 21:16:54.419664 INFO : Training has run successfully!
381 21:16:54.420132 Check phy result
382 21:16:54.424702 INFO : End of initialization
383 21:16:54.425158 INFO : End of read dq deskew training
384 21:16:54.430249 INFO : End of MPR read delay center optimization
385 21:16:54.435859 INFO : End of write delay center optimization
386 21:16:54.441462 INFO : End of read delay center optimization
387 21:16:54.441917 INFO : End of max read latency training
388 21:16:54.447227 INFO : Training has run successfully!
389 21:16:54.447685 1D training succeed
390 21:16:54.456257 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 21:16:54.503861 Check phy result
392 21:16:54.504375 INFO : End of initialization
393 21:16:54.525520 INFO : End of 2D read delay Voltage center optimization
394 21:16:54.545643 INFO : End of 2D read delay Voltage center optimization
395 21:16:54.597624 INFO : End of 2D write delay Voltage center optimization
396 21:16:54.646863 INFO : End of 2D write delay Voltage center optimization
397 21:16:54.652268 INFO : Training has run successfully!
398 21:16:54.652769
399 21:16:54.653238 channel==0
400 21:16:54.657870 RxClkDly_Margin_A0==88 ps 9
401 21:16:54.658381 TxDqDly_Margin_A0==98 ps 10
402 21:16:54.661290 RxClkDly_Margin_A1==88 ps 9
403 21:16:54.661808 TxDqDly_Margin_A1==98 ps 10
404 21:16:54.666817 TrainedVREFDQ_A0==74
405 21:16:54.667323 TrainedVREFDQ_A1==74
406 21:16:54.667785 VrefDac_Margin_A0==25
407 21:16:54.672412 DeviceVref_Margin_A0==40
408 21:16:54.672902 VrefDac_Margin_A1==25
409 21:16:54.678033 DeviceVref_Margin_A1==40
410 21:16:54.678536
411 21:16:54.679000
412 21:16:54.679473 channel==1
413 21:16:54.680090 RxClkDly_Margin_A0==98 ps 10
414 21:16:54.683585 TxDqDly_Margin_A0==88 ps 9
415 21:16:54.684103 RxClkDly_Margin_A1==98 ps 10
416 21:16:54.689243 TxDqDly_Margin_A1==88 ps 9
417 21:16:54.689727 TrainedVREFDQ_A0==76
418 21:16:54.690179 TrainedVREFDQ_A1==77
419 21:16:54.694837 VrefDac_Margin_A0==22
420 21:16:54.695342 DeviceVref_Margin_A0==38
421 21:16:54.700428 VrefDac_Margin_A1==24
422 21:16:54.700943 DeviceVref_Margin_A1==37
423 21:16:54.701394
424 21:16:54.706076 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 21:16:54.706606
426 21:16:54.734002 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 21:16:54.739645 2D training succeed
428 21:16:54.745254 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 21:16:54.745733 auto size-- 65535DDR cs0 size: 2048MB
430 21:16:54.750819 DDR cs1 size: 2048MB
431 21:16:54.751293 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 21:16:54.756365 cs0 DataBus test pass
433 21:16:54.756847 cs1 DataBus test pass
434 21:16:54.757298 cs0 AddrBus test pass
435 21:16:54.761959 cs1 AddrBus test pass
436 21:16:54.762429
437 21:16:54.762878 100bdlr_step_size ps== 420
438 21:16:54.763330 result report
439 21:16:54.767627 boot times 0Enable ddr reg access
440 21:16:54.775310 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 21:16:54.788661 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 21:16:55.360709 0.0;M3 CHK:0;cm4_sp_mode 0
443 21:16:55.361114 MVN_1=0x00000000
444 21:16:55.366395 MVN_2=0x00000000
445 21:16:55.372076 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 21:16:55.372360 OPS=0x10
447 21:16:55.372573 ring efuse init
448 21:16:55.372775 chipver efuse init
449 21:16:55.377598 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 21:16:55.383325 [0.018961 Inits done]
451 21:16:55.383726 secure task start!
452 21:16:55.384077 high task start!
453 21:16:55.387749 low task start!
454 21:16:55.388160 run into bl31
455 21:16:55.394449 NOTICE: BL31: v1.3(release):4fc40b1
456 21:16:55.402208 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 21:16:55.402505 NOTICE: BL31: G12A normal boot!
458 21:16:55.427594 NOTICE: BL31: BL33 decompress pass
459 21:16:55.433387 ERROR: Error initializing runtime service opteed_fast
460 21:16:56.666271
461 21:16:56.666699
462 21:16:56.673758 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 21:16:56.674243
464 21:16:56.674562 Model: Libre Computer AML-A311D-CC Alta
465 21:16:56.883095 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 21:16:56.906416 DRAM: 2 GiB (effective 3.8 GiB)
467 21:16:57.049424 Core: 408 devices, 31 uclasses, devicetree: separate
468 21:16:57.055255 WDT: Not starting watchdog@f0d0
469 21:16:57.087574 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 21:16:57.100032 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 21:16:57.104979 ** Bad device specification mmc 0 **
472 21:16:57.115358 Card did not respond to voltage select! : -110
473 21:16:57.121978 ** Bad device specification mmc 0 **
474 21:16:57.122256 Couldn't find partition mmc 0
475 21:16:57.131291 Card did not respond to voltage select! : -110
476 21:16:57.136822 ** Bad device specification mmc 0 **
477 21:16:57.137102 Couldn't find partition mmc 0
478 21:16:57.141877 Error: could not access storage.
479 21:16:58.407526 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 21:16:58.408135 bl2_stage_init 0x01
481 21:16:58.408628 bl2_stage_init 0x81
482 21:16:58.412858 hw id: 0x0000 - pwm id 0x01
483 21:16:58.413258 bl2_stage_init 0xc1
484 21:16:58.413605 bl2_stage_init 0x02
485 21:16:58.413938
486 21:16:58.418529 L0:00000000
487 21:16:58.418935 L1:20000703
488 21:16:58.419253 L2:00008067
489 21:16:58.419596 L3:14000000
490 21:16:58.421347 B2:00402000
491 21:16:58.421718 B1:e0f83180
492 21:16:58.422062
493 21:16:58.422392 TE: 58124
494 21:16:58.422699
495 21:16:58.432560 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 21:16:58.432980
497 21:16:58.433295 Board ID = 1
498 21:16:58.433642 Set A53 clk to 24M
499 21:16:58.433979 Set A73 clk to 24M
500 21:16:58.438130 Set clk81 to 24M
501 21:16:58.438512 A53 clk: 1200 MHz
502 21:16:58.438852 A73 clk: 1200 MHz
503 21:16:58.441580 CLK81: 166.6M
504 21:16:58.441949 smccc: 00012a91
505 21:16:58.447157 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 21:16:58.452873 board id: 1
507 21:16:58.458038 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 21:16:58.468522 fw parse done
509 21:16:58.474425 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 21:16:58.517096 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 21:16:58.528059 PIEI prepare done
512 21:16:58.528460 fastboot data load
513 21:16:58.528812 fastboot data verify
514 21:16:58.533582 verify result: 266
515 21:16:58.539146 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 21:16:58.539528 LPDDR4 probe
517 21:16:58.539871 ddr clk to 1584MHz
518 21:16:58.547139 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 21:16:58.584570
520 21:16:58.585089 dmc_version 0001
521 21:16:58.591158 Check phy result
522 21:16:58.597084 INFO : End of CA training
523 21:16:58.597401 INFO : End of initialization
524 21:16:58.602641 INFO : Training has run successfully!
525 21:16:58.602915 Check phy result
526 21:16:58.608205 INFO : End of initialization
527 21:16:58.608476 INFO : End of read enable training
528 21:16:58.611527 INFO : End of fine write leveling
529 21:16:58.617125 INFO : End of Write leveling coarse delay
530 21:16:58.622786 INFO : Training has run successfully!
531 21:16:58.623203 Check phy result
532 21:16:58.623517 INFO : End of initialization
533 21:16:58.628239 INFO : End of read dq deskew training
534 21:16:58.633892 INFO : End of MPR read delay center optimization
535 21:16:58.634263 INFO : End of write delay center optimization
536 21:16:58.639522 INFO : End of read delay center optimization
537 21:16:58.645113 INFO : End of max read latency training
538 21:16:58.645518 INFO : Training has run successfully!
539 21:16:58.650779 1D training succeed
540 21:16:58.656629 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 21:16:58.704172 Check phy result
542 21:16:58.704601 INFO : End of initialization
543 21:16:58.725950 INFO : End of 2D read delay Voltage center optimization
544 21:16:58.745870 INFO : End of 2D read delay Voltage center optimization
545 21:16:58.797061 INFO : End of 2D write delay Voltage center optimization
546 21:16:58.847331 INFO : End of 2D write delay Voltage center optimization
547 21:16:58.852812 INFO : Training has run successfully!
548 21:16:58.853229
549 21:16:58.853546 channel==0
550 21:16:58.858495 RxClkDly_Margin_A0==88 ps 9
551 21:16:58.858875 TxDqDly_Margin_A0==98 ps 10
552 21:16:58.861700 RxClkDly_Margin_A1==88 ps 9
553 21:16:58.861979 TxDqDly_Margin_A1==98 ps 10
554 21:16:58.867200 TrainedVREFDQ_A0==74
555 21:16:58.867586 TrainedVREFDQ_A1==74
556 21:16:58.872770 VrefDac_Margin_A0==25
557 21:16:58.873048 DeviceVref_Margin_A0==40
558 21:16:58.873292 VrefDac_Margin_A1==25
559 21:16:58.878570 DeviceVref_Margin_A1==40
560 21:16:58.878961
561 21:16:58.879301
562 21:16:58.879636 channel==1
563 21:16:58.879965 RxClkDly_Margin_A0==98 ps 10
564 21:16:58.884106 TxDqDly_Margin_A0==88 ps 9
565 21:16:58.885020 RxClkDly_Margin_A1==88 ps 9
566 21:16:58.889725 TxDqDly_Margin_A1==88 ps 9
567 21:16:58.890594 TrainedVREFDQ_A0==76
568 21:16:58.891390 TrainedVREFDQ_A1==77
569 21:16:58.895181 VrefDac_Margin_A0==22
570 21:16:58.896066 DeviceVref_Margin_A0==38
571 21:16:58.900751 VrefDac_Margin_A1==24
572 21:16:58.901674 DeviceVref_Margin_A1==37
573 21:16:58.902506
574 21:16:58.906311 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 21:16:58.907261
576 21:16:58.934223 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 21:16:58.939833 2D training succeed
578 21:16:58.945381 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 21:16:58.946246 auto size-- 65535DDR cs0 size: 2048MB
580 21:16:58.951067 DDR cs1 size: 2048MB
581 21:16:58.951893 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 21:16:58.956575 cs0 DataBus test pass
583 21:16:58.957393 cs1 DataBus test pass
584 21:16:58.958177 cs0 AddrBus test pass
585 21:16:58.962234 cs1 AddrBus test pass
586 21:16:58.963054
587 21:16:58.963850 100bdlr_step_size ps== 420
588 21:16:58.964695 result report
589 21:16:58.967799 boot times 0Enable ddr reg access
590 21:16:58.974509 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 21:16:58.988140 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 21:16:59.561078 0.0;M3 CHK:0;cm4_sp_mode 0
593 21:16:59.561660 MVN_1=0x00000000
594 21:16:59.566364 MVN_2=0x00000000
595 21:16:59.572130 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 21:16:59.572507 OPS=0x10
597 21:16:59.572851 ring efuse init
598 21:16:59.573189 chipver efuse init
599 21:16:59.577877 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 21:16:59.583413 [0.018961 Inits done]
601 21:16:59.583803 secure task start!
602 21:16:59.584194 high task start!
603 21:16:59.587920 low task start!
604 21:16:59.588302 run into bl31
605 21:16:59.594597 NOTICE: BL31: v1.3(release):4fc40b1
606 21:16:59.602361 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 21:16:59.602633 NOTICE: BL31: G12A normal boot!
608 21:16:59.627854 NOTICE: BL31: BL33 decompress pass
609 21:16:59.633510 ERROR: Error initializing runtime service opteed_fast
610 21:17:00.866404
611 21:17:00.866832
612 21:17:00.874771 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 21:17:00.875045
614 21:17:00.875282 Model: Libre Computer AML-A311D-CC Alta
615 21:17:01.083366 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 21:17:01.106672 DRAM: 2 GiB (effective 3.8 GiB)
617 21:17:01.249655 Core: 408 devices, 31 uclasses, devicetree: separate
618 21:17:01.254528 WDT: Not starting watchdog@f0d0
619 21:17:01.287780 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 21:17:01.300172 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 21:17:01.304231 ** Bad device specification mmc 0 **
622 21:17:01.315456 Card did not respond to voltage select! : -110
623 21:17:01.322235 ** Bad device specification mmc 0 **
624 21:17:01.322677 Couldn't find partition mmc 0
625 21:17:01.331449 Card did not respond to voltage select! : -110
626 21:17:01.337058 ** Bad device specification mmc 0 **
627 21:17:01.337437 Couldn't find partition mmc 0
628 21:17:01.342127 Error: could not access storage.
629 21:17:01.685597 Net: eth0: ethernet@ff3f0000
630 21:17:01.686006 starting USB...
631 21:17:01.937637 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 21:17:01.938019 Starting the controller
633 21:17:01.944459 USB XHCI 1.10
634 21:17:03.658289 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 21:17:03.658684 bl2_stage_init 0x01
636 21:17:03.658908 bl2_stage_init 0x81
637 21:17:03.663863 hw id: 0x0000 - pwm id 0x01
638 21:17:03.664157 bl2_stage_init 0xc1
639 21:17:03.664380 bl2_stage_init 0x02
640 21:17:03.664592
641 21:17:03.669447 L0:00000000
642 21:17:03.669710 L1:20000703
643 21:17:03.669925 L2:00008067
644 21:17:03.670136 L3:14000000
645 21:17:03.672371 B2:00402000
646 21:17:03.672633 B1:e0f83180
647 21:17:03.672848
648 21:17:03.673061 TE: 58124
649 21:17:03.673267
650 21:17:03.683430 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 21:17:03.683714
652 21:17:03.683932 Board ID = 1
653 21:17:03.684174 Set A53 clk to 24M
654 21:17:03.684388 Set A73 clk to 24M
655 21:17:03.689036 Set clk81 to 24M
656 21:17:03.689309 A53 clk: 1200 MHz
657 21:17:03.689524 A73 clk: 1200 MHz
658 21:17:03.692467 CLK81: 166.6M
659 21:17:03.692736 smccc: 00012a91
660 21:17:03.698091 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 21:17:03.703674 board id: 1
662 21:17:03.708937 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 21:17:03.719643 fw parse done
664 21:17:03.724665 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 21:17:03.768206 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 21:17:03.779125 PIEI prepare done
667 21:17:03.779432 fastboot data load
668 21:17:03.779653 fastboot data verify
669 21:17:03.784691 verify result: 266
670 21:17:03.790290 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 21:17:03.790584 LPDDR4 probe
672 21:17:03.790803 ddr clk to 1584MHz
673 21:17:03.798294 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 21:17:03.835616
675 21:17:03.835951 dmc_version 0001
676 21:17:03.842232 Check phy result
677 21:17:03.848118 INFO : End of CA training
678 21:17:03.848401 INFO : End of initialization
679 21:17:03.853681 INFO : Training has run successfully!
680 21:17:03.853966 Check phy result
681 21:17:03.859288 INFO : End of initialization
682 21:17:03.859571 INFO : End of read enable training
683 21:17:03.864876 INFO : End of fine write leveling
684 21:17:03.870497 INFO : End of Write leveling coarse delay
685 21:17:03.870781 INFO : Training has run successfully!
686 21:17:03.871000 Check phy result
687 21:17:03.876135 INFO : End of initialization
688 21:17:03.876423 INFO : End of read dq deskew training
689 21:17:03.881702 INFO : End of MPR read delay center optimization
690 21:17:03.887340 INFO : End of write delay center optimization
691 21:17:03.892926 INFO : End of read delay center optimization
692 21:17:03.893222 INFO : End of max read latency training
693 21:17:03.898749 INFO : Training has run successfully!
694 21:17:03.899037 1D training succeed
695 21:17:03.907854 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 21:17:03.955467 Check phy result
697 21:17:03.956056 INFO : End of initialization
698 21:17:03.976997 INFO : End of 2D read delay Voltage center optimization
699 21:17:03.997166 INFO : End of 2D read delay Voltage center optimization
700 21:17:04.049033 INFO : End of 2D write delay Voltage center optimization
701 21:17:04.098283 INFO : End of 2D write delay Voltage center optimization
702 21:17:04.103772 INFO : Training has run successfully!
703 21:17:04.104316
704 21:17:04.104770 channel==0
705 21:17:04.109646 RxClkDly_Margin_A0==88 ps 9
706 21:17:04.110163 TxDqDly_Margin_A0==98 ps 10
707 21:17:04.112719 RxClkDly_Margin_A1==88 ps 9
708 21:17:04.113212 TxDqDly_Margin_A1==98 ps 10
709 21:17:04.118273 TrainedVREFDQ_A0==74
710 21:17:04.118767 TrainedVREFDQ_A1==74
711 21:17:04.123823 VrefDac_Margin_A0==25
712 21:17:04.124346 DeviceVref_Margin_A0==40
713 21:17:04.124792 VrefDac_Margin_A1==25
714 21:17:04.129496 DeviceVref_Margin_A1==40
715 21:17:04.129991
716 21:17:04.130434
717 21:17:04.130870 channel==1
718 21:17:04.131305 RxClkDly_Margin_A0==88 ps 9
719 21:17:04.132953 TxDqDly_Margin_A0==98 ps 10
720 21:17:04.138454 RxClkDly_Margin_A1==88 ps 9
721 21:17:04.138944 TxDqDly_Margin_A1==88 ps 9
722 21:17:04.139390 TrainedVREFDQ_A0==77
723 21:17:04.144143 TrainedVREFDQ_A1==77
724 21:17:04.144632 VrefDac_Margin_A0==22
725 21:17:04.149755 DeviceVref_Margin_A0==37
726 21:17:04.150240 VrefDac_Margin_A1==24
727 21:17:04.150678 DeviceVref_Margin_A1==37
728 21:17:04.151110
729 21:17:04.158710 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 21:17:04.159204
731 21:17:04.184559 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 21:17:04.190126 2D training succeed
733 21:17:04.195741 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 21:17:04.201427 auto size-- 65535DDR cs0 size: 2048MB
735 21:17:04.201922 DDR cs1 size: 2048MB
736 21:17:04.202364 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 21:17:04.206753 cs0 DataBus test pass
738 21:17:04.207234 cs1 DataBus test pass
739 21:17:04.212335 cs0 AddrBus test pass
740 21:17:04.212822 cs1 AddrBus test pass
741 21:17:04.213260
742 21:17:04.213696 100bdlr_step_size ps== 420
743 21:17:04.217929 result report
744 21:17:04.218408 boot times 0Enable ddr reg access
745 21:17:04.226702 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 21:17:04.240058 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 21:17:04.812127 0.0;M3 CHK:0;cm4_sp_mode 0
748 21:17:04.812758 MVN_1=0x00000000
749 21:17:04.817607 MVN_2=0x00000000
750 21:17:04.823308 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 21:17:04.823837 OPS=0x10
752 21:17:04.824316 ring efuse init
753 21:17:04.824747 chipver efuse init
754 21:17:04.828898 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 21:17:04.834522 [0.018961 Inits done]
756 21:17:04.835070 secure task start!
757 21:17:04.835498 high task start!
758 21:17:04.838186 low task start!
759 21:17:04.838715 run into bl31
760 21:17:04.845788 NOTICE: BL31: v1.3(release):4fc40b1
761 21:17:04.853601 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 21:17:04.854159 NOTICE: BL31: G12A normal boot!
763 21:17:04.878909 NOTICE: BL31: BL33 decompress pass
764 21:17:04.884695 ERROR: Error initializing runtime service opteed_fast
765 21:17:06.117455
766 21:17:06.118076
767 21:17:06.125901 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 21:17:06.126402
769 21:17:06.126828 Model: Libre Computer AML-A311D-CC Alta
770 21:17:06.334272 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 21:17:06.357699 DRAM: 2 GiB (effective 3.8 GiB)
772 21:17:06.500671 Core: 408 devices, 31 uclasses, devicetree: separate
773 21:17:06.506476 WDT: Not starting watchdog@f0d0
774 21:17:06.538907 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 21:17:06.551203 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 21:17:06.556198 ** Bad device specification mmc 0 **
777 21:17:06.566606 Card did not respond to voltage select! : -110
778 21:17:06.574169 ** Bad device specification mmc 0 **
779 21:17:06.574655 Couldn't find partition mmc 0
780 21:17:06.582494 Card did not respond to voltage select! : -110
781 21:17:06.588038 ** Bad device specification mmc 0 **
782 21:17:06.588557 Couldn't find partition mmc 0
783 21:17:06.593134 Error: could not access storage.
784 21:17:06.934694 Net: eth0: ethernet@ff3f0000
785 21:17:06.935300 starting USB...
786 21:17:07.187464 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 21:17:07.187951 Starting the controller
788 21:17:07.194315 USB XHCI 1.10
789 21:17:09.357655 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
790 21:17:09.358081 bl2_stage_init 0x81
791 21:17:09.363299 hw id: 0x0000 - pwm id 0x01
792 21:17:09.363615 bl2_stage_init 0xc1
793 21:17:09.363844 bl2_stage_init 0x02
794 21:17:09.364110
795 21:17:09.368707 L0:00000000
796 21:17:09.368999 L1:20000703
797 21:17:09.369227 L2:00008067
798 21:17:09.369456 L3:14000000
799 21:17:09.369681 B2:00402000
800 21:17:09.371620 B1:e0f83180
801 21:17:09.371896
802 21:17:09.372151 TE: 58150
803 21:17:09.372387
804 21:17:09.383073 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 21:17:09.383382
806 21:17:09.383615 Board ID = 1
807 21:17:09.383836 Set A53 clk to 24M
808 21:17:09.384080 Set A73 clk to 24M
809 21:17:09.388464 Set clk81 to 24M
810 21:17:09.388751 A53 clk: 1200 MHz
811 21:17:09.388980 A73 clk: 1200 MHz
812 21:17:09.391863 CLK81: 166.6M
813 21:17:09.392157 smccc: 00012aac
814 21:17:09.397396 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 21:17:09.403060 board id: 1
816 21:17:09.408216 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 21:17:09.418705 fw parse done
818 21:17:09.424678 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 21:17:09.467326 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 21:17:09.478326 PIEI prepare done
821 21:17:09.478654 fastboot data load
822 21:17:09.478878 fastboot data verify
823 21:17:09.483917 verify result: 266
824 21:17:09.489519 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 21:17:09.489853 LPDDR4 probe
826 21:17:09.490100 ddr clk to 1584MHz
827 21:17:09.497451 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 21:17:09.533786
829 21:17:09.534176 dmc_version 0001
830 21:17:09.540549 Check phy result
831 21:17:09.547355 INFO : End of CA training
832 21:17:09.547700 INFO : End of initialization
833 21:17:09.552883 INFO : Training has run successfully!
834 21:17:09.553235 Check phy result
835 21:17:09.558494 INFO : End of initialization
836 21:17:09.558836 INFO : End of read enable training
837 21:17:09.564137 INFO : End of fine write leveling
838 21:17:09.569708 INFO : End of Write leveling coarse delay
839 21:17:09.570058 INFO : Training has run successfully!
840 21:17:09.570310 Check phy result
841 21:17:09.575321 INFO : End of initialization
842 21:17:09.575663 INFO : End of read dq deskew training
843 21:17:09.580878 INFO : End of MPR read delay center optimization
844 21:17:09.586483 INFO : End of write delay center optimization
845 21:17:09.592128 INFO : End of read delay center optimization
846 21:17:09.592475 INFO : End of max read latency training
847 21:17:09.597690 INFO : Training has run successfully!
848 21:17:09.598026 1D training succeed
849 21:17:09.605962 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 21:17:09.654500 Check phy result
851 21:17:09.654898 INFO : End of initialization
852 21:17:09.676252 INFO : End of 2D read delay Voltage center optimization
853 21:17:09.696444 INFO : End of 2D read delay Voltage center optimization
854 21:17:09.748502 INFO : End of 2D write delay Voltage center optimization
855 21:17:09.797907 INFO : End of 2D write delay Voltage center optimization
856 21:17:09.803435 INFO : Training has run successfully!
857 21:17:09.803785
858 21:17:09.804070 channel==0
859 21:17:09.809132 RxClkDly_Margin_A0==88 ps 9
860 21:17:09.809484 TxDqDly_Margin_A0==98 ps 10
861 21:17:09.812366 RxClkDly_Margin_A1==88 ps 9
862 21:17:09.812728 TxDqDly_Margin_A1==98 ps 10
863 21:17:09.817989 TrainedVREFDQ_A0==74
864 21:17:09.818334 TrainedVREFDQ_A1==74
865 21:17:09.818578 VrefDac_Margin_A0==25
866 21:17:09.823570 DeviceVref_Margin_A0==40
867 21:17:09.823896 VrefDac_Margin_A1==25
868 21:17:09.829152 DeviceVref_Margin_A1==40
869 21:17:09.829495
870 21:17:09.829726
871 21:17:09.829944 channel==1
872 21:17:09.830157 RxClkDly_Margin_A0==98 ps 10
873 21:17:09.834686 TxDqDly_Margin_A0==98 ps 10
874 21:17:09.835014 RxClkDly_Margin_A1==88 ps 9
875 21:17:09.840225 TxDqDly_Margin_A1==88 ps 9
876 21:17:09.840551 TrainedVREFDQ_A0==77
877 21:17:09.840778 TrainedVREFDQ_A1==77
878 21:17:09.845854 VrefDac_Margin_A0==22
879 21:17:09.846179 DeviceVref_Margin_A0==37
880 21:17:09.851420 VrefDac_Margin_A1==24
881 21:17:09.851752 DeviceVref_Margin_A1==37
882 21:17:09.852001
883 21:17:09.857030 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 21:17:09.857356
885 21:17:09.885017 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
886 21:17:09.890626 2D training succeed
887 21:17:09.896216 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 21:17:09.896541 auto size-- 65535DDR cs0 size: 2048MB
889 21:17:09.901841 DDR cs1 size: 2048MB
890 21:17:09.902159 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 21:17:09.907418 cs0 DataBus test pass
892 21:17:09.907739 cs1 DataBus test pass
893 21:17:09.907968 cs0 AddrBus test pass
894 21:17:09.913040 cs1 AddrBus test pass
895 21:17:09.913506
896 21:17:09.913908 100bdlr_step_size ps== 420
897 21:17:09.914308 result report
898 21:17:09.918665 boot times 0Enable ddr reg access
899 21:17:09.926325 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 21:17:09.939738 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 21:17:10.512887 0.0;M3 CHK:0;cm4_sp_mode 0
902 21:17:10.513519 MVN_1=0x00000000
903 21:17:10.518418 MVN_2=0x00000000
904 21:17:10.524019 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 21:17:10.524505 OPS=0x10
906 21:17:10.524929 ring efuse init
907 21:17:10.525336 chipver efuse init
908 21:17:10.529675 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 21:17:10.535400 [0.018961 Inits done]
910 21:17:10.535875 secure task start!
911 21:17:10.536333 high task start!
912 21:17:10.539846 low task start!
913 21:17:10.540323 run into bl31
914 21:17:10.546481 NOTICE: BL31: v1.3(release):4fc40b1
915 21:17:10.554281 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 21:17:10.554758 NOTICE: BL31: G12A normal boot!
917 21:17:10.579573 NOTICE: BL31: BL33 decompress pass
918 21:17:10.585224 ERROR: Error initializing runtime service opteed_fast
919 21:17:11.818213
920 21:17:11.818625
921 21:17:11.826736 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 21:17:11.827334
923 21:17:11.827819 Model: Libre Computer AML-A311D-CC Alta
924 21:17:12.035066 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 21:17:12.058560 DRAM: 2 GiB (effective 3.8 GiB)
926 21:17:12.201749 Core: 408 devices, 31 uclasses, devicetree: separate
927 21:17:12.206514 WDT: Not starting watchdog@f0d0
928 21:17:12.239730 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 21:17:12.252074 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 21:17:12.257038 ** Bad device specification mmc 0 **
931 21:17:12.267420 Card did not respond to voltage select! : -110
932 21:17:12.275081 ** Bad device specification mmc 0 **
933 21:17:12.275670 Couldn't find partition mmc 0
934 21:17:12.283387 Card did not respond to voltage select! : -110
935 21:17:12.288930 ** Bad device specification mmc 0 **
936 21:17:12.289507 Couldn't find partition mmc 0
937 21:17:12.293965 Error: could not access storage.
938 21:17:12.636337 Net: eth0: ethernet@ff3f0000
939 21:17:12.636956 starting USB...
940 21:17:12.888221 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 21:17:12.888838 Starting the controller
942 21:17:12.895209 USB XHCI 1.10
943 21:17:14.757731 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
944 21:17:14.758402 bl2_stage_init 0x81
945 21:17:14.763471 hw id: 0x0000 - pwm id 0x01
946 21:17:14.764055 bl2_stage_init 0xc1
947 21:17:14.764547 bl2_stage_init 0x02
948 21:17:14.765009
949 21:17:14.769225 L0:00000000
950 21:17:14.769773 L1:20000703
951 21:17:14.770241 L2:00008067
952 21:17:14.770693 L3:14000000
953 21:17:14.771141 B2:00402000
954 21:17:14.774734 B1:e0f83180
955 21:17:14.775276
956 21:17:14.775744 TE: 58150
957 21:17:14.776240
958 21:17:14.780249 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 21:17:14.780796
960 21:17:14.781268 Board ID = 1
961 21:17:14.785826 Set A53 clk to 24M
962 21:17:14.786365 Set A73 clk to 24M
963 21:17:14.786830 Set clk81 to 24M
964 21:17:14.791463 A53 clk: 1200 MHz
965 21:17:14.792031 A73 clk: 1200 MHz
966 21:17:14.792505 CLK81: 166.6M
967 21:17:14.792960 smccc: 00012aab
968 21:17:14.796963 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 21:17:14.802697 board id: 1
970 21:17:14.808455 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 21:17:14.818865 fw parse done
972 21:17:14.824927 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 21:17:14.867482 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 21:17:14.878368 PIEI prepare done
975 21:17:14.878897 fastboot data load
976 21:17:14.879340 fastboot data verify
977 21:17:14.884179 verify result: 266
978 21:17:14.889645 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 21:17:14.890167 LPDDR4 probe
980 21:17:14.890603 ddr clk to 1584MHz
981 21:17:14.897642 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 21:17:14.934872
983 21:17:14.935415 dmc_version 0001
984 21:17:14.941588 Check phy result
985 21:17:14.947425 INFO : End of CA training
986 21:17:14.947940 INFO : End of initialization
987 21:17:14.953173 INFO : Training has run successfully!
988 21:17:14.953698 Check phy result
989 21:17:14.958732 INFO : End of initialization
990 21:17:14.959298 INFO : End of read enable training
991 21:17:14.964298 INFO : End of fine write leveling
992 21:17:14.969935 INFO : End of Write leveling coarse delay
993 21:17:14.970472 INFO : Training has run successfully!
994 21:17:14.970936 Check phy result
995 21:17:14.975447 INFO : End of initialization
996 21:17:14.976010 INFO : End of read dq deskew training
997 21:17:14.981197 INFO : End of MPR read delay center optimization
998 21:17:14.986687 INFO : End of write delay center optimization
999 21:17:14.992295 INFO : End of read delay center optimization
1000 21:17:14.992864 INFO : End of max read latency training
1001 21:17:14.997862 INFO : Training has run successfully!
1002 21:17:14.998409 1D training succeed
1003 21:17:15.007014 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 21:17:15.054606 Check phy result
1005 21:17:15.055155 INFO : End of initialization
1006 21:17:15.076585 INFO : End of 2D read delay Voltage center optimization
1007 21:17:15.096720 INFO : End of 2D read delay Voltage center optimization
1008 21:17:15.148938 INFO : End of 2D write delay Voltage center optimization
1009 21:17:15.198195 INFO : End of 2D write delay Voltage center optimization
1010 21:17:15.203863 INFO : Training has run successfully!
1011 21:17:15.204533
1012 21:17:15.205001 channel==0
1013 21:17:15.209229 RxClkDly_Margin_A0==88 ps 9
1014 21:17:15.209766 TxDqDly_Margin_A0==98 ps 10
1015 21:17:15.214771 RxClkDly_Margin_A1==88 ps 9
1016 21:17:15.215271 TxDqDly_Margin_A1==98 ps 10
1017 21:17:15.215698 TrainedVREFDQ_A0==74
1018 21:17:15.220383 TrainedVREFDQ_A1==74
1019 21:17:15.220940 VrefDac_Margin_A0==25
1020 21:17:15.221367 DeviceVref_Margin_A0==40
1021 21:17:15.225939 VrefDac_Margin_A1==25
1022 21:17:15.226420 DeviceVref_Margin_A1==40
1023 21:17:15.226837
1024 21:17:15.227247
1025 21:17:15.232460 channel==1
1026 21:17:15.232944 RxClkDly_Margin_A0==98 ps 10
1027 21:17:15.233361 TxDqDly_Margin_A0==98 ps 10
1028 21:17:15.237167 RxClkDly_Margin_A1==88 ps 9
1029 21:17:15.237657 TxDqDly_Margin_A1==88 ps 9
1030 21:17:15.242751 TrainedVREFDQ_A0==77
1031 21:17:15.243230 TrainedVREFDQ_A1==77
1032 21:17:15.243642 VrefDac_Margin_A0==22
1033 21:17:15.248344 DeviceVref_Margin_A0==37
1034 21:17:15.248831 VrefDac_Margin_A1==24
1035 21:17:15.254037 DeviceVref_Margin_A1==37
1036 21:17:15.254516
1037 21:17:15.254933 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 21:17:15.255344
1039 21:17:15.287601 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1040 21:17:15.288455 2D training succeed
1041 21:17:15.293183 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 21:17:15.298996 auto size-- 65535DDR cs0 size: 2048MB
1043 21:17:15.299533 DDR cs1 size: 2048MB
1044 21:17:15.304517 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 21:17:15.305088 cs0 DataBus test pass
1046 21:17:15.310022 cs1 DataBus test pass
1047 21:17:15.310517 cs0 AddrBus test pass
1048 21:17:15.310933 cs1 AddrBus test pass
1049 21:17:15.311341
1050 21:17:15.315650 100bdlr_step_size ps== 420
1051 21:17:15.316239 result report
1052 21:17:15.321254 boot times 0Enable ddr reg access
1053 21:17:15.327370 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 21:17:15.339954 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 21:17:15.913609 0.0;M3 CHK:0;cm4_sp_mode 0
1056 21:17:15.914256 MVN_1=0x00000000
1057 21:17:15.919108 MVN_2=0x00000000
1058 21:17:15.924750 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 21:17:15.925210 OPS=0x10
1060 21:17:15.925630 ring efuse init
1061 21:17:15.926039 chipver efuse init
1062 21:17:15.930369 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 21:17:15.935961 [0.018961 Inits done]
1064 21:17:15.936444 secure task start!
1065 21:17:15.936853 high task start!
1066 21:17:15.940571 low task start!
1067 21:17:15.941022 run into bl31
1068 21:17:15.947211 NOTICE: BL31: v1.3(release):4fc40b1
1069 21:17:15.955015 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 21:17:15.955470 NOTICE: BL31: G12A normal boot!
1071 21:17:15.980346 NOTICE: BL31: BL33 decompress pass
1072 21:17:15.986173 ERROR: Error initializing runtime service opteed_fast
1073 21:17:17.219017
1074 21:17:17.219623
1075 21:17:17.227401 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 21:17:17.227863
1077 21:17:17.228311 Model: Libre Computer AML-A311D-CC Alta
1078 21:17:17.435766 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 21:17:17.459172 DRAM: 2 GiB (effective 3.8 GiB)
1080 21:17:17.602131 Core: 408 devices, 31 uclasses, devicetree: separate
1081 21:17:17.608027 WDT: Not starting watchdog@f0d0
1082 21:17:17.640391 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 21:17:17.652750 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 21:17:17.657717 ** Bad device specification mmc 0 **
1085 21:17:17.668194 Card did not respond to voltage select! : -110
1086 21:17:17.675719 ** Bad device specification mmc 0 **
1087 21:17:17.676200 Couldn't find partition mmc 0
1088 21:17:17.684098 Card did not respond to voltage select! : -110
1089 21:17:17.689530 ** Bad device specification mmc 0 **
1090 21:17:17.689974 Couldn't find partition mmc 0
1091 21:17:17.694609 Error: could not access storage.
1092 21:17:18.037127 Net: eth0: ethernet@ff3f0000
1093 21:17:18.037699 starting USB...
1094 21:17:18.288871 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 21:17:18.289405 Starting the controller
1096 21:17:18.295852 USB XHCI 1.10
1097 21:17:19.850114 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 21:17:19.858397 scanning usb for storage devices... 0 Storage Device(s) found
1100 21:17:19.909523 Hit any key to stop autoboot: 1
1101 21:17:19.910473 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1102 21:17:19.910846 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1103 21:17:19.911098 Setting prompt string to ['=>']
1104 21:17:19.911349 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1105 21:17:19.925321 0
1106 21:17:19.926324 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 21:17:19.926872 Sending with 10 millisecond of delay
1109 21:17:21.062793 => setenv autoload no
1110 21:17:21.073414 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1111 21:17:21.076105 setenv autoload no
1112 21:17:21.076778 Sending with 10 millisecond of delay
1114 21:17:22.876094 => setenv initrd_high 0xffffffff
1115 21:17:22.886971 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1116 21:17:22.887560 setenv initrd_high 0xffffffff
1117 21:17:22.888107 Sending with 10 millisecond of delay
1119 21:17:24.506038 => setenv fdt_high 0xffffffff
1120 21:17:24.516815 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1121 21:17:24.517379 setenv fdt_high 0xffffffff
1122 21:17:24.517865 Sending with 10 millisecond of delay
1124 21:17:24.809884 => dhcp
1125 21:17:24.820601 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1126 21:17:24.821312 dhcp
1127 21:17:24.821581 Speed: 1000, full duplex
1128 21:17:24.821798 BOOTP broadcast 1
1129 21:17:25.068664 BOOTP broadcast 2
1130 21:17:25.081399 DHCP client bound to address 192.168.6.33 (260 ms)
1131 21:17:25.082022 Sending with 10 millisecond of delay
1133 21:17:26.758771 => setenv serverip 192.168.6.2
1134 21:17:26.769611 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 21:17:26.770539 setenv serverip 192.168.6.2
1136 21:17:26.771285 Sending with 10 millisecond of delay
1138 21:17:30.494959 => tftpboot 0x01080000 823595/tftp-deploy-fe4pngen/kernel/uImage
1139 21:17:30.505787 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1140 21:17:30.506746 tftpboot 0x01080000 823595/tftp-deploy-fe4pngen/kernel/uImage
1141 21:17:30.507226 Speed: 1000, full duplex
1142 21:17:30.507669 Using ethernet@ff3f0000 device
1143 21:17:30.508479 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1144 21:17:30.513958 Filename '823595/tftp-deploy-fe4pngen/kernel/uImage'.
1145 21:17:30.517788 Load address: 0x1080000
1146 21:17:33.145685 Loading: *################################### UDP wrong checksum 000000ff 0000b6b2
1147 21:17:33.165839 UDP wrong checksum 000000ff 00004ba5
1148 21:17:34.687552 ############### 43.6 MiB
1149 21:17:34.687972 10.4 MiB/s
1150 21:17:34.688498 done
1151 21:17:34.692159 Bytes transferred = 45713984 (2b98a40 hex)
1152 21:17:34.693182 Sending with 10 millisecond of delay
1154 21:17:39.384973 => tftpboot 0x08000000 823595/tftp-deploy-fe4pngen/ramdisk/ramdisk.cpio.gz.uboot
1155 21:17:39.395584 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1156 21:17:39.396170 tftpboot 0x08000000 823595/tftp-deploy-fe4pngen/ramdisk/ramdisk.cpio.gz.uboot
1157 21:17:39.396410 Speed: 1000, full duplex
1158 21:17:39.396619 Using ethernet@ff3f0000 device
1159 21:17:39.398993 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 21:17:39.410681 Filename '823595/tftp-deploy-fe4pngen/ramdisk/ramdisk.cpio.gz.uboot'.
1161 21:17:39.411113 Load address: 0x8000000
1162 21:17:41.196356 Loading: *################################################# UDP wrong checksum 00000005 000075d5
1163 21:17:46.195911 T UDP wrong checksum 00000005 000075d5
1164 21:17:54.737378 T UDP wrong checksum 000000ff 00006392
1165 21:17:54.745024 UDP wrong checksum 000000ff 0000f684
1166 21:17:56.198225 T UDP wrong checksum 00000005 000075d5
1167 21:18:16.202199 T T T T UDP wrong checksum 00000005 000075d5
1168 21:18:24.360069 T UDP wrong checksum 000000ff 0000cb52
1169 21:18:24.379887 UDP wrong checksum 000000ff 00006845
1170 21:18:36.207093 T T
1171 21:18:36.207513 Retry count exceeded; starting again
1173 21:18:36.208792 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
1176 21:18:36.210899 end: 2.4 uboot-commands (duration 00:01:53) [common]
1178 21:18:36.212683 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1180 21:18:36.213809 end: 2 uboot-action (duration 00:01:53) [common]
1182 21:18:36.215467 Cleaning after the job
1183 21:18:36.216080 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/ramdisk
1184 21:18:36.217424 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/kernel
1185 21:18:36.248139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/dtb
1186 21:18:36.249666 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/nfsrootfs
1187 21:18:36.303339 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823595/tftp-deploy-fe4pngen/modules
1188 21:18:36.310448 start: 4.1 power-off (timeout 00:00:30) [common]
1189 21:18:36.311126 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1190 21:18:36.348489 >> OK - accepted request
1191 21:18:36.350566 Returned 0 in 0 seconds
1192 21:18:36.451324 end: 4.1 power-off (duration 00:00:00) [common]
1194 21:18:36.452369 start: 4.2 read-feedback (timeout 00:10:00) [common]
1195 21:18:36.453034 Listened to connection for namespace 'common' for up to 1s
1196 21:18:37.454035 Finalising connection for namespace 'common'
1197 21:18:37.454771 Disconnecting from shell: Finalise
1198 21:18:37.455286 =>
1199 21:18:37.556369 end: 4.2 read-feedback (duration 00:00:01) [common]
1200 21:18:37.557125 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/823595
1201 21:18:40.169507 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/823595
1202 21:18:40.170243 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.