Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 21:37:39.826526 lava-dispatcher, installed at version: 2024.01
2 21:37:39.827302 start: 0 validate
3 21:37:39.827774 Start time: 2024-10-08 21:37:39.827744+00:00 (UTC)
4 21:37:39.828324 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 21:37:39.828870 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 21:37:39.872929 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 21:37:39.873464 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 21:37:39.904115 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 21:37:39.904742 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 21:37:39.940461 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 21:37:39.940940 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 21:37:39.971892 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 21:37:39.972514 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fmainline%2Fmaster%2Fv6.12-rc2-50-g5b7c893ed5ed0%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 21:37:40.020155 validate duration: 0.19
16 21:37:40.022035 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 21:37:40.022809 start: 1.1 download-retry (timeout 00:10:00) [common]
18 21:37:40.023550 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 21:37:40.024779 Not decompressing ramdisk as can be used compressed.
20 21:37:40.025739 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 21:37:40.026380 saving as /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/ramdisk/initrd.cpio.gz
22 21:37:40.027017 total size: 5628140 (5 MB)
23 21:37:40.070729 progress 0 % (0 MB)
24 21:37:40.080328 progress 5 % (0 MB)
25 21:37:40.090058 progress 10 % (0 MB)
26 21:37:40.098646 progress 15 % (0 MB)
27 21:37:40.106307 progress 20 % (1 MB)
28 21:37:40.110733 progress 25 % (1 MB)
29 21:37:40.115513 progress 30 % (1 MB)
30 21:37:40.120353 progress 35 % (1 MB)
31 21:37:40.124612 progress 40 % (2 MB)
32 21:37:40.129329 progress 45 % (2 MB)
33 21:37:40.133634 progress 50 % (2 MB)
34 21:37:40.138451 progress 55 % (2 MB)
35 21:37:40.143251 progress 60 % (3 MB)
36 21:37:40.147436 progress 65 % (3 MB)
37 21:37:40.152179 progress 70 % (3 MB)
38 21:37:40.156418 progress 75 % (4 MB)
39 21:37:40.161121 progress 80 % (4 MB)
40 21:37:40.165339 progress 85 % (4 MB)
41 21:37:40.170137 progress 90 % (4 MB)
42 21:37:40.174651 progress 95 % (5 MB)
43 21:37:40.178570 progress 100 % (5 MB)
44 21:37:40.179343 5 MB downloaded in 0.15 s (35.24 MB/s)
45 21:37:40.180040 end: 1.1.1 http-download (duration 00:00:00) [common]
47 21:37:40.181149 end: 1.1 download-retry (duration 00:00:00) [common]
48 21:37:40.181504 start: 1.2 download-retry (timeout 00:10:00) [common]
49 21:37:40.181840 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 21:37:40.182408 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/kernel/Image
51 21:37:40.182708 saving as /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/kernel/Image
52 21:37:40.182964 total size: 45713920 (43 MB)
53 21:37:40.183227 No compression specified
54 21:37:40.222412 progress 0 % (0 MB)
55 21:37:40.256351 progress 5 % (2 MB)
56 21:37:40.290267 progress 10 % (4 MB)
57 21:37:40.322312 progress 15 % (6 MB)
58 21:37:40.350473 progress 20 % (8 MB)
59 21:37:40.378160 progress 25 % (10 MB)
60 21:37:40.406044 progress 30 % (13 MB)
61 21:37:40.434325 progress 35 % (15 MB)
62 21:37:40.462158 progress 40 % (17 MB)
63 21:37:40.489839 progress 45 % (19 MB)
64 21:37:40.517681 progress 50 % (21 MB)
65 21:37:40.546006 progress 55 % (24 MB)
66 21:37:40.573999 progress 60 % (26 MB)
67 21:37:40.601546 progress 65 % (28 MB)
68 21:37:40.629980 progress 70 % (30 MB)
69 21:37:40.657764 progress 75 % (32 MB)
70 21:37:40.685739 progress 80 % (34 MB)
71 21:37:40.713421 progress 85 % (37 MB)
72 21:37:40.741566 progress 90 % (39 MB)
73 21:37:40.769636 progress 95 % (41 MB)
74 21:37:40.797138 progress 100 % (43 MB)
75 21:37:40.797697 43 MB downloaded in 0.61 s (70.92 MB/s)
76 21:37:40.798223 end: 1.2.1 http-download (duration 00:00:01) [common]
78 21:37:40.799090 end: 1.2 download-retry (duration 00:00:01) [common]
79 21:37:40.799402 start: 1.3 download-retry (timeout 00:09:59) [common]
80 21:37:40.799699 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 21:37:40.800222 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 21:37:40.800524 saving as /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/dtb/meson-g12b-a311d-libretech-cc.dtb
83 21:37:40.800753 total size: 54703 (0 MB)
84 21:37:40.800978 No compression specified
85 21:37:40.845328 progress 59 % (0 MB)
86 21:37:40.846207 progress 100 % (0 MB)
87 21:37:40.846793 0 MB downloaded in 0.05 s (1.13 MB/s)
88 21:37:40.847302 end: 1.3.1 http-download (duration 00:00:00) [common]
90 21:37:40.848191 end: 1.3 download-retry (duration 00:00:00) [common]
91 21:37:40.848483 start: 1.4 download-retry (timeout 00:09:59) [common]
92 21:37:40.848768 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 21:37:40.849240 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 21:37:40.849498 saving as /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/nfsrootfs/full.rootfs.tar
95 21:37:40.849718 total size: 474398908 (452 MB)
96 21:37:40.849940 Using unxz to decompress xz
97 21:37:40.885794 progress 0 % (0 MB)
98 21:37:41.973063 progress 5 % (22 MB)
99 21:37:43.425627 progress 10 % (45 MB)
100 21:37:43.861038 progress 15 % (67 MB)
101 21:37:44.627819 progress 20 % (90 MB)
102 21:37:45.154246 progress 25 % (113 MB)
103 21:37:45.512732 progress 30 % (135 MB)
104 21:37:46.121175 progress 35 % (158 MB)
105 21:37:46.995920 progress 40 % (181 MB)
106 21:37:47.778901 progress 45 % (203 MB)
107 21:37:48.391881 progress 50 % (226 MB)
108 21:37:49.043313 progress 55 % (248 MB)
109 21:37:50.228551 progress 60 % (271 MB)
110 21:37:51.624202 progress 65 % (294 MB)
111 21:37:53.194862 progress 70 % (316 MB)
112 21:37:56.269212 progress 75 % (339 MB)
113 21:37:58.685803 progress 80 % (361 MB)
114 21:38:01.540549 progress 85 % (384 MB)
115 21:38:04.668835 progress 90 % (407 MB)
116 21:38:07.847732 progress 95 % (429 MB)
117 21:38:11.002426 progress 100 % (452 MB)
118 21:38:11.015265 452 MB downloaded in 30.17 s (15.00 MB/s)
119 21:38:11.016029 end: 1.4.1 http-download (duration 00:00:30) [common]
121 21:38:11.017702 end: 1.4 download-retry (duration 00:00:30) [common]
122 21:38:11.018235 start: 1.5 download-retry (timeout 00:09:29) [common]
123 21:38:11.018758 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 21:38:11.019690 downloading http://storage.kernelci.org/mainline/master/v6.12-rc2-50-g5b7c893ed5ed0/arm64/defconfig/gcc-12/modules.tar.xz
125 21:38:11.020194 saving as /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/modules/modules.tar
126 21:38:11.020614 total size: 11613728 (11 MB)
127 21:38:11.021035 Using unxz to decompress xz
128 21:38:11.067204 progress 0 % (0 MB)
129 21:38:11.128605 progress 5 % (0 MB)
130 21:38:11.206392 progress 10 % (1 MB)
131 21:38:11.292087 progress 15 % (1 MB)
132 21:38:11.383273 progress 20 % (2 MB)
133 21:38:11.465794 progress 25 % (2 MB)
134 21:38:11.544253 progress 30 % (3 MB)
135 21:38:11.628924 progress 35 % (3 MB)
136 21:38:11.706301 progress 40 % (4 MB)
137 21:38:11.786002 progress 45 % (5 MB)
138 21:38:11.869774 progress 50 % (5 MB)
139 21:38:11.949180 progress 55 % (6 MB)
140 21:38:12.035527 progress 60 % (6 MB)
141 21:38:12.112514 progress 65 % (7 MB)
142 21:38:12.193833 progress 70 % (7 MB)
143 21:38:12.266713 progress 75 % (8 MB)
144 21:38:12.342454 progress 80 % (8 MB)
145 21:38:12.425773 progress 85 % (9 MB)
146 21:38:12.503825 progress 90 % (9 MB)
147 21:38:12.583318 progress 95 % (10 MB)
148 21:38:12.662596 progress 100 % (11 MB)
149 21:38:12.674509 11 MB downloaded in 1.65 s (6.70 MB/s)
150 21:38:12.675242 end: 1.5.1 http-download (duration 00:00:02) [common]
152 21:38:12.676945 end: 1.5 download-retry (duration 00:00:02) [common]
153 21:38:12.677482 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 21:38:12.678010 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 21:38:27.782085 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/823654/extract-nfsrootfs-06im6lha
156 21:38:27.782695 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 21:38:27.782984 start: 1.6.2 lava-overlay (timeout 00:09:12) [common]
158 21:38:27.783767 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi
159 21:38:27.784250 makedir: /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin
160 21:38:27.784581 makedir: /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/tests
161 21:38:27.784892 makedir: /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/results
162 21:38:27.785223 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-add-keys
163 21:38:27.785745 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-add-sources
164 21:38:27.786262 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-background-process-start
165 21:38:27.786809 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-background-process-stop
166 21:38:27.787335 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-common-functions
167 21:38:27.787827 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-echo-ipv4
168 21:38:27.788345 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-install-packages
169 21:38:27.788837 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-installed-packages
170 21:38:27.789304 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-os-build
171 21:38:27.789774 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-probe-channel
172 21:38:27.790329 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-probe-ip
173 21:38:27.790854 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-target-ip
174 21:38:27.791329 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-target-mac
175 21:38:27.791796 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-target-storage
176 21:38:27.792317 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-test-case
177 21:38:27.792795 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-test-event
178 21:38:27.793257 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-test-feedback
179 21:38:27.793720 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-test-raise
180 21:38:27.794198 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-test-reference
181 21:38:27.794710 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-test-runner
182 21:38:27.795188 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-test-set
183 21:38:27.795653 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-test-shell
184 21:38:27.796157 Updating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-install-packages (oe)
185 21:38:27.796698 Updating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/bin/lava-installed-packages (oe)
186 21:38:27.797128 Creating /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/environment
187 21:38:27.797490 LAVA metadata
188 21:38:27.797745 - LAVA_JOB_ID=823654
189 21:38:27.797958 - LAVA_DISPATCHER_IP=192.168.6.2
190 21:38:27.798303 start: 1.6.2.1 ssh-authorize (timeout 00:09:12) [common]
191 21:38:27.799240 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 21:38:27.799546 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:12) [common]
193 21:38:27.799756 skipped lava-vland-overlay
194 21:38:27.800013 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 21:38:27.800273 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:12) [common]
196 21:38:27.800493 skipped lava-multinode-overlay
197 21:38:27.800732 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 21:38:27.800984 start: 1.6.2.4 test-definition (timeout 00:09:12) [common]
199 21:38:27.801232 Loading test definitions
200 21:38:27.801506 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:12) [common]
201 21:38:27.801724 Using /lava-823654 at stage 0
202 21:38:27.802846 uuid=823654_1.6.2.4.1 testdef=None
203 21:38:27.803146 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 21:38:27.803409 start: 1.6.2.4.2 test-overlay (timeout 00:09:12) [common]
205 21:38:27.805143 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 21:38:27.805922 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:12) [common]
208 21:38:27.808064 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 21:38:27.808890 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:12) [common]
211 21:38:27.810927 runner path: /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 823654_1.6.2.4.1
212 21:38:27.811479 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 21:38:27.812252 Creating lava-test-runner.conf files
215 21:38:27.812453 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/823654/lava-overlay-t3rm7dwi/lava-823654/0 for stage 0
216 21:38:27.812777 - 0_v4l2-decoder-conformance-vp9
217 21:38:27.813110 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 21:38:27.813378 start: 1.6.2.5 compress-overlay (timeout 00:09:12) [common]
219 21:38:27.834618 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 21:38:27.834951 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:12) [common]
221 21:38:27.835230 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 21:38:27.835500 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 21:38:27.835760 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:12) [common]
224 21:38:28.450430 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 21:38:28.450896 start: 1.6.4 extract-modules (timeout 00:09:12) [common]
226 21:38:28.451148 extracting modules file /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823654/extract-nfsrootfs-06im6lha
227 21:38:29.808664 extracting modules file /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/823654/extract-overlay-ramdisk-3kec5h2s/ramdisk
228 21:38:31.204342 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 21:38:31.204830 start: 1.6.5 apply-overlay-tftp (timeout 00:09:09) [common]
230 21:38:31.205111 [common] Applying overlay to NFS
231 21:38:31.205328 [common] Applying overlay /var/lib/lava/dispatcher/tmp/823654/compress-overlay-tmr9y1nm/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/823654/extract-nfsrootfs-06im6lha
232 21:38:31.234550 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 21:38:31.234960 start: 1.6.6 prepare-kernel (timeout 00:09:09) [common]
234 21:38:31.235239 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:09) [common]
235 21:38:31.235469 Converting downloaded kernel to a uImage
236 21:38:31.235786 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/kernel/Image /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/kernel/uImage
237 21:38:31.733075 output: Image Name:
238 21:38:31.733496 output: Created: Tue Oct 8 21:38:31 2024
239 21:38:31.733704 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 21:38:31.733908 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 21:38:31.734109 output: Load Address: 01080000
242 21:38:31.734308 output: Entry Point: 01080000
243 21:38:31.734504 output:
244 21:38:31.734838 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 21:38:31.735107 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 21:38:31.735380 start: 1.6.7 configure-preseed-file (timeout 00:09:08) [common]
247 21:38:31.735634 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 21:38:31.735893 start: 1.6.8 compress-ramdisk (timeout 00:09:08) [common]
249 21:38:31.736189 Building ramdisk /var/lib/lava/dispatcher/tmp/823654/extract-overlay-ramdisk-3kec5h2s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/823654/extract-overlay-ramdisk-3kec5h2s/ramdisk
250 21:38:34.189765 >> 166774 blocks
251 21:38:41.955763 Adding RAMdisk u-boot header.
252 21:38:41.956522 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/823654/extract-overlay-ramdisk-3kec5h2s/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/823654/extract-overlay-ramdisk-3kec5h2s/ramdisk.cpio.gz.uboot
253 21:38:42.270442 output: Image Name:
254 21:38:42.271104 output: Created: Tue Oct 8 21:38:41 2024
255 21:38:42.271585 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 21:38:42.272095 output: Data Size: 23424123 Bytes = 22875.12 KiB = 22.34 MiB
257 21:38:42.272558 output: Load Address: 00000000
258 21:38:42.273006 output: Entry Point: 00000000
259 21:38:42.273452 output:
260 21:38:42.274608 rename /var/lib/lava/dispatcher/tmp/823654/extract-overlay-ramdisk-3kec5h2s/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/ramdisk/ramdisk.cpio.gz.uboot
261 21:38:42.275405 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 21:38:42.276058 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 21:38:42.276677 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:58) [common]
264 21:38:42.277201 No LXC device requested
265 21:38:42.277780 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 21:38:42.278366 start: 1.8 deploy-device-env (timeout 00:08:58) [common]
267 21:38:42.278926 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 21:38:42.279392 Checking files for TFTP limit of 4294967296 bytes.
269 21:38:42.282344 end: 1 tftp-deploy (duration 00:01:02) [common]
270 21:38:42.282994 start: 2 uboot-action (timeout 00:05:00) [common]
271 21:38:42.283599 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 21:38:42.284197 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 21:38:42.284775 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 21:38:42.285368 Using kernel file from prepare-kernel: 823654/tftp-deploy-b7lpk3j7/kernel/uImage
275 21:38:42.286074 substitutions:
276 21:38:42.286535 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 21:38:42.286989 - {DTB_ADDR}: 0x01070000
278 21:38:42.287443 - {DTB}: 823654/tftp-deploy-b7lpk3j7/dtb/meson-g12b-a311d-libretech-cc.dtb
279 21:38:42.287888 - {INITRD}: 823654/tftp-deploy-b7lpk3j7/ramdisk/ramdisk.cpio.gz.uboot
280 21:38:42.288366 - {KERNEL_ADDR}: 0x01080000
281 21:38:42.288815 - {KERNEL}: 823654/tftp-deploy-b7lpk3j7/kernel/uImage
282 21:38:42.289261 - {LAVA_MAC}: None
283 21:38:42.289751 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/823654/extract-nfsrootfs-06im6lha
284 21:38:42.290208 - {NFS_SERVER_IP}: 192.168.6.2
285 21:38:42.290648 - {PRESEED_CONFIG}: None
286 21:38:42.291087 - {PRESEED_LOCAL}: None
287 21:38:42.291526 - {RAMDISK_ADDR}: 0x08000000
288 21:38:42.291958 - {RAMDISK}: 823654/tftp-deploy-b7lpk3j7/ramdisk/ramdisk.cpio.gz.uboot
289 21:38:42.292424 - {ROOT_PART}: None
290 21:38:42.292865 - {ROOT}: None
291 21:38:42.293304 - {SERVER_IP}: 192.168.6.2
292 21:38:42.293738 - {TEE_ADDR}: 0x83000000
293 21:38:42.294171 - {TEE}: None
294 21:38:42.294606 Parsed boot commands:
295 21:38:42.295028 - setenv autoload no
296 21:38:42.295461 - setenv initrd_high 0xffffffff
297 21:38:42.295892 - setenv fdt_high 0xffffffff
298 21:38:42.296358 - dhcp
299 21:38:42.296793 - setenv serverip 192.168.6.2
300 21:38:42.297223 - tftpboot 0x01080000 823654/tftp-deploy-b7lpk3j7/kernel/uImage
301 21:38:42.297656 - tftpboot 0x08000000 823654/tftp-deploy-b7lpk3j7/ramdisk/ramdisk.cpio.gz.uboot
302 21:38:42.298088 - tftpboot 0x01070000 823654/tftp-deploy-b7lpk3j7/dtb/meson-g12b-a311d-libretech-cc.dtb
303 21:38:42.298520 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/823654/extract-nfsrootfs-06im6lha,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 21:38:42.298967 - bootm 0x01080000 0x08000000 0x01070000
305 21:38:42.299527 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 21:38:42.301211 start: 2.3 connect-device (timeout 00:05:00) [common]
308 21:38:42.301686 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 21:38:42.317294 Setting prompt string to ['lava-test: # ']
310 21:38:42.318881 end: 2.3 connect-device (duration 00:00:00) [common]
311 21:38:42.319564 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 21:38:42.320219 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 21:38:42.320838 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 21:38:42.322094 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 21:38:42.359759 >> OK - accepted request
316 21:38:42.362074 Returned 0 in 0 seconds
317 21:38:42.463272 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 21:38:42.465125 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 21:38:42.465793 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 21:38:42.466387 Setting prompt string to ['Hit any key to stop autoboot']
322 21:38:42.466911 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 21:38:42.468668 Trying 192.168.56.21...
324 21:38:42.469201 Connected to conserv1.
325 21:38:42.469684 Escape character is '^]'.
326 21:38:42.470157
327 21:38:42.470628 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 21:38:42.471097
329 21:38:53.797457 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 21:38:53.798127 bl2_stage_init 0x01
331 21:38:53.798611 bl2_stage_init 0x81
332 21:38:53.802905 hw id: 0x0000 - pwm id 0x01
333 21:38:53.803447 bl2_stage_init 0xc1
334 21:38:53.803905 bl2_stage_init 0x02
335 21:38:53.804395
336 21:38:53.808358 L0:00000000
337 21:38:53.808843 L1:20000703
338 21:38:53.809277 L2:00008067
339 21:38:53.809714 L3:14000000
340 21:38:53.811338 B2:00402000
341 21:38:53.811816 B1:e0f83180
342 21:38:53.812289
343 21:38:53.812723 TE: 58159
344 21:38:53.813154
345 21:38:53.822545 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 21:38:53.823028
347 21:38:53.823465 Board ID = 1
348 21:38:53.823889 Set A53 clk to 24M
349 21:38:53.824358 Set A73 clk to 24M
350 21:38:53.828189 Set clk81 to 24M
351 21:38:53.828652 A53 clk: 1200 MHz
352 21:38:53.829081 A73 clk: 1200 MHz
353 21:38:53.831798 CLK81: 166.6M
354 21:38:53.832281 smccc: 00012ab5
355 21:38:53.837318 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 21:38:53.842797 board id: 1
357 21:38:53.848071 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 21:38:53.858483 fw parse done
359 21:38:53.864459 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 21:38:53.907040 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 21:38:53.918023 PIEI prepare done
362 21:38:53.918958 fastboot data load
363 21:38:53.919527 fastboot data verify
364 21:38:53.923517 verify result: 266
365 21:38:53.929162 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 21:38:53.929397 LPDDR4 probe
367 21:38:53.929603 ddr clk to 1584MHz
368 21:38:53.937146 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 21:38:53.974357
370 21:38:53.974877 dmc_version 0001
371 21:38:53.981218 Check phy result
372 21:38:53.986969 INFO : End of CA training
373 21:38:53.987456 INFO : End of initialization
374 21:38:53.992560 INFO : Training has run successfully!
375 21:38:53.993041 Check phy result
376 21:38:53.998255 INFO : End of initialization
377 21:38:53.998738 INFO : End of read enable training
378 21:38:54.001428 INFO : End of fine write leveling
379 21:38:54.006981 INFO : End of Write leveling coarse delay
380 21:38:54.012592 INFO : Training has run successfully!
381 21:38:54.013066 Check phy result
382 21:38:54.013512 INFO : End of initialization
383 21:38:54.018259 INFO : End of read dq deskew training
384 21:38:54.023786 INFO : End of MPR read delay center optimization
385 21:38:54.024341 INFO : End of write delay center optimization
386 21:38:54.029382 INFO : End of read delay center optimization
387 21:38:54.034965 INFO : End of max read latency training
388 21:38:54.035436 INFO : Training has run successfully!
389 21:38:54.040588 1D training succeed
390 21:38:54.046555 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 21:38:54.094094 Check phy result
392 21:38:54.094631 INFO : End of initialization
393 21:38:54.115825 INFO : End of 2D read delay Voltage center optimization
394 21:38:54.136080 INFO : End of 2D read delay Voltage center optimization
395 21:38:54.188203 INFO : End of 2D write delay Voltage center optimization
396 21:38:54.237592 INFO : End of 2D write delay Voltage center optimization
397 21:38:54.243150 INFO : Training has run successfully!
398 21:38:54.243651
399 21:38:54.244161 channel==0
400 21:38:54.248748 RxClkDly_Margin_A0==88 ps 9
401 21:38:54.249250 TxDqDly_Margin_A0==98 ps 10
402 21:38:54.252057 RxClkDly_Margin_A1==88 ps 9
403 21:38:54.252539 TxDqDly_Margin_A1==98 ps 10
404 21:38:54.257562 TrainedVREFDQ_A0==74
405 21:38:54.258038 TrainedVREFDQ_A1==74
406 21:38:54.263181 VrefDac_Margin_A0==25
407 21:38:54.263656 DeviceVref_Margin_A0==40
408 21:38:54.264136 VrefDac_Margin_A1==25
409 21:38:54.268754 DeviceVref_Margin_A1==40
410 21:38:54.269229
411 21:38:54.269679
412 21:38:54.270124 channel==1
413 21:38:54.270563 RxClkDly_Margin_A0==98 ps 10
414 21:38:54.274276 TxDqDly_Margin_A0==88 ps 9
415 21:38:54.274752 RxClkDly_Margin_A1==98 ps 10
416 21:38:54.279939 TxDqDly_Margin_A1==88 ps 9
417 21:38:54.280448 TrainedVREFDQ_A0==75
418 21:38:54.280898 TrainedVREFDQ_A1==77
419 21:38:54.285565 VrefDac_Margin_A0==22
420 21:38:54.286043 DeviceVref_Margin_A0==38
421 21:38:54.291115 VrefDac_Margin_A1==22
422 21:38:54.291587 DeviceVref_Margin_A1==37
423 21:38:54.292065
424 21:38:54.296698 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 21:38:54.297178
426 21:38:54.324681 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 21:38:54.330295 2D training succeed
428 21:38:54.335893 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 21:38:54.336407 auto size-- 65535DDR cs0 size: 2048MB
430 21:38:54.341486 DDR cs1 size: 2048MB
431 21:38:54.341961 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 21:38:54.347120 cs0 DataBus test pass
433 21:38:54.347599 cs1 DataBus test pass
434 21:38:54.348095 cs0 AddrBus test pass
435 21:38:54.352682 cs1 AddrBus test pass
436 21:38:54.353156
437 21:38:54.353610 100bdlr_step_size ps== 420
438 21:38:54.354066 result report
439 21:38:54.358289 boot times 0Enable ddr reg access
440 21:38:54.366042 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 21:38:54.379525 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 21:38:54.953308 0.0;M3 CHK:0;cm4_sp_mode 0
443 21:38:54.953967 MVN_1=0x00000000
444 21:38:54.958701 MVN_2=0x00000000
445 21:38:54.964526 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 21:38:54.965011 OPS=0x10
447 21:38:54.965470 ring efuse init
448 21:38:54.965912 chipver efuse init
449 21:38:54.970120 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 21:38:54.975627 [0.018961 Inits done]
451 21:38:54.976137 secure task start!
452 21:38:54.976586 high task start!
453 21:38:54.980427 low task start!
454 21:38:54.980931 run into bl31
455 21:38:54.986948 NOTICE: BL31: v1.3(release):4fc40b1
456 21:38:54.994770 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 21:38:54.995258 NOTICE: BL31: G12A normal boot!
458 21:38:55.020061 NOTICE: BL31: BL33 decompress pass
459 21:38:55.025775 ERROR: Error initializing runtime service opteed_fast
460 21:38:56.258846
461 21:38:56.259266
462 21:38:56.267027 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 21:38:56.267271
464 21:38:56.267486 Model: Libre Computer AML-A311D-CC Alta
465 21:38:56.475575 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 21:38:56.498911 DRAM: 2 GiB (effective 3.8 GiB)
467 21:38:56.641866 Core: 408 devices, 31 uclasses, devicetree: separate
468 21:38:56.647842 WDT: Not starting watchdog@f0d0
469 21:38:56.679923 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 21:38:56.692487 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 21:38:56.697536 ** Bad device specification mmc 0 **
472 21:38:56.707686 Card did not respond to voltage select! : -110
473 21:38:56.715436 ** Bad device specification mmc 0 **
474 21:38:56.715948 Couldn't find partition mmc 0
475 21:38:56.723686 Card did not respond to voltage select! : -110
476 21:38:56.729205 ** Bad device specification mmc 0 **
477 21:38:56.729702 Couldn't find partition mmc 0
478 21:38:56.734337 Error: could not access storage.
479 21:38:57.997748 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 21:38:57.998387 bl2_stage_init 0x01
481 21:38:57.998858 bl2_stage_init 0x81
482 21:38:58.003280 hw id: 0x0000 - pwm id 0x01
483 21:38:58.003778 bl2_stage_init 0xc1
484 21:38:58.004295 bl2_stage_init 0x02
485 21:38:58.004748
486 21:38:58.008878 L0:00000000
487 21:38:58.009353 L1:20000703
488 21:38:58.009801 L2:00008067
489 21:38:58.010244 L3:14000000
490 21:38:58.011801 B2:00402000
491 21:38:58.012293 B1:e0f83180
492 21:38:58.012743
493 21:38:58.013186 TE: 58167
494 21:38:58.013626
495 21:38:58.022924 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 21:38:58.023401
497 21:38:58.023854 Board ID = 1
498 21:38:58.024329 Set A53 clk to 24M
499 21:38:58.024770 Set A73 clk to 24M
500 21:38:58.028416 Set clk81 to 24M
501 21:38:58.028880 A53 clk: 1200 MHz
502 21:38:58.029326 A73 clk: 1200 MHz
503 21:38:58.032083 CLK81: 166.6M
504 21:38:58.032553 smccc: 00012abd
505 21:38:58.037575 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 21:38:58.043231 board id: 1
507 21:38:58.048457 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 21:38:58.058858 fw parse done
509 21:38:58.064844 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 21:38:58.107452 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 21:38:58.118357 PIEI prepare done
512 21:38:58.118863 fastboot data load
513 21:38:58.119320 fastboot data verify
514 21:38:58.123934 verify result: 266
515 21:38:58.129600 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 21:38:58.130074 LPDDR4 probe
517 21:38:58.130521 ddr clk to 1584MHz
518 21:38:58.137518 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 21:38:58.174812
520 21:38:58.175297 dmc_version 0001
521 21:38:58.181449 Check phy result
522 21:38:58.187316 INFO : End of CA training
523 21:38:58.187784 INFO : End of initialization
524 21:38:58.192926 INFO : Training has run successfully!
525 21:38:58.193399 Check phy result
526 21:38:58.198498 INFO : End of initialization
527 21:38:58.198969 INFO : End of read enable training
528 21:38:58.204152 INFO : End of fine write leveling
529 21:38:58.209745 INFO : End of Write leveling coarse delay
530 21:38:58.210230 INFO : Training has run successfully!
531 21:38:58.210677 Check phy result
532 21:38:58.215309 INFO : End of initialization
533 21:38:58.215781 INFO : End of read dq deskew training
534 21:38:58.220920 INFO : End of MPR read delay center optimization
535 21:38:58.226524 INFO : End of write delay center optimization
536 21:38:58.232103 INFO : End of read delay center optimization
537 21:38:58.232572 INFO : End of max read latency training
538 21:38:58.237750 INFO : Training has run successfully!
539 21:38:58.238221 1D training succeed
540 21:38:58.246927 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 21:38:58.294479 Check phy result
542 21:38:58.294998 INFO : End of initialization
543 21:38:58.316199 INFO : End of 2D read delay Voltage center optimization
544 21:38:58.336476 INFO : End of 2D read delay Voltage center optimization
545 21:38:58.388490 INFO : End of 2D write delay Voltage center optimization
546 21:38:58.437823 INFO : End of 2D write delay Voltage center optimization
547 21:38:58.443467 INFO : Training has run successfully!
548 21:38:58.444034
549 21:38:58.444473 channel==0
550 21:38:58.449140 RxClkDly_Margin_A0==88 ps 9
551 21:38:58.449614 TxDqDly_Margin_A0==98 ps 10
552 21:38:58.454758 RxClkDly_Margin_A1==88 ps 9
553 21:38:58.455250 TxDqDly_Margin_A1==98 ps 10
554 21:38:58.455676 TrainedVREFDQ_A0==74
555 21:38:58.460316 TrainedVREFDQ_A1==74
556 21:38:58.460800 VrefDac_Margin_A0==25
557 21:38:58.461217 DeviceVref_Margin_A0==40
558 21:38:58.465908 VrefDac_Margin_A1==25
559 21:38:58.466380 DeviceVref_Margin_A1==40
560 21:38:58.466792
561 21:38:58.467196
562 21:38:58.471512 channel==1
563 21:38:58.472078 RxClkDly_Margin_A0==98 ps 10
564 21:38:58.472790 TxDqDly_Margin_A0==98 ps 10
565 21:38:58.477117 RxClkDly_Margin_A1==98 ps 10
566 21:38:58.477710 TxDqDly_Margin_A1==88 ps 9
567 21:38:58.482629 TrainedVREFDQ_A0==77
568 21:38:58.483225 TrainedVREFDQ_A1==77
569 21:38:58.483757 VrefDac_Margin_A0==22
570 21:38:58.488222 DeviceVref_Margin_A0==37
571 21:38:58.488802 VrefDac_Margin_A1==22
572 21:38:58.493832 DeviceVref_Margin_A1==37
573 21:38:58.494397
574 21:38:58.494943 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 21:38:58.499428
576 21:38:58.527421 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 21:38:58.528128 2D training succeed
578 21:38:58.533046 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 21:38:58.538663 auto size-- 65535DDR cs0 size: 2048MB
580 21:38:58.539265 DDR cs1 size: 2048MB
581 21:38:58.544229 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 21:38:58.544832 cs0 DataBus test pass
583 21:38:58.549848 cs1 DataBus test pass
584 21:38:58.550448 cs0 AddrBus test pass
585 21:38:58.550995 cs1 AddrBus test pass
586 21:38:58.551532
587 21:38:58.555426 100bdlr_step_size ps== 420
588 21:38:58.556072 result report
589 21:38:58.561047 boot times 0Enable ddr reg access
590 21:38:58.566494 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 21:38:58.579968 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 21:38:59.153862 0.0;M3 CHK:0;cm4_sp_mode 0
593 21:38:59.154326 MVN_1=0x00000000
594 21:38:59.159315 MVN_2=0x00000000
595 21:38:59.165046 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 21:38:59.165600 OPS=0x10
597 21:38:59.166001 ring efuse init
598 21:38:59.166391 chipver efuse init
599 21:38:59.170634 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 21:38:59.176225 [0.018961 Inits done]
601 21:38:59.176730 secure task start!
602 21:38:59.177130 high task start!
603 21:38:59.180802 low task start!
604 21:38:59.181284 run into bl31
605 21:38:59.187413 NOTICE: BL31: v1.3(release):4fc40b1
606 21:38:59.195235 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 21:38:59.195734 NOTICE: BL31: G12A normal boot!
608 21:38:59.220526 NOTICE: BL31: BL33 decompress pass
609 21:38:59.226224 ERROR: Error initializing runtime service opteed_fast
610 21:39:00.459154
611 21:39:00.459789
612 21:39:00.467536 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 21:39:00.468088
614 21:39:00.468529 Model: Libre Computer AML-A311D-CC Alta
615 21:39:00.675907 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 21:39:00.699316 DRAM: 2 GiB (effective 3.8 GiB)
617 21:39:00.842291 Core: 408 devices, 31 uclasses, devicetree: separate
618 21:39:00.848273 WDT: Not starting watchdog@f0d0
619 21:39:00.880415 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 21:39:00.892834 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 21:39:00.897857 ** Bad device specification mmc 0 **
622 21:39:00.908193 Card did not respond to voltage select! : -110
623 21:39:00.915847 ** Bad device specification mmc 0 **
624 21:39:00.916393 Couldn't find partition mmc 0
625 21:39:00.924209 Card did not respond to voltage select! : -110
626 21:39:00.929708 ** Bad device specification mmc 0 **
627 21:39:00.930213 Couldn't find partition mmc 0
628 21:39:00.934787 Error: could not access storage.
629 21:39:01.277193 Net: eth0: ethernet@ff3f0000
630 21:39:01.277762 starting USB...
631 21:39:01.529075 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 21:39:01.529693 Starting the controller
633 21:39:01.536084 USB XHCI 1.10
634 21:39:03.246167 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 21:39:03.246801 bl2_stage_init 0x01
636 21:39:03.247239 bl2_stage_init 0x81
637 21:39:03.251759 hw id: 0x0000 - pwm id 0x01
638 21:39:03.252273 bl2_stage_init 0xc1
639 21:39:03.252696 bl2_stage_init 0x02
640 21:39:03.253108
641 21:39:03.257395 L0:00000000
642 21:39:03.257873 L1:20000703
643 21:39:03.258291 L2:00008067
644 21:39:03.258699 L3:14000000
645 21:39:03.262964 B2:00402000
646 21:39:03.263435 B1:e0f83180
647 21:39:03.263848
648 21:39:03.264291 TE: 58124
649 21:39:03.264699
650 21:39:03.268592 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 21:39:03.269071
652 21:39:03.269487 Board ID = 1
653 21:39:03.274250 Set A53 clk to 24M
654 21:39:03.274720 Set A73 clk to 24M
655 21:39:03.275134 Set clk81 to 24M
656 21:39:03.279867 A53 clk: 1200 MHz
657 21:39:03.280362 A73 clk: 1200 MHz
658 21:39:03.280776 CLK81: 166.6M
659 21:39:03.281180 smccc: 00012a91
660 21:39:03.285522 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 21:39:03.290992 board id: 1
662 21:39:03.297058 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 21:39:03.307432 fw parse done
664 21:39:03.313388 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 21:39:03.356007 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 21:39:03.366910 PIEI prepare done
667 21:39:03.367392 fastboot data load
668 21:39:03.367817 fastboot data verify
669 21:39:03.372599 verify result: 266
670 21:39:03.378204 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 21:39:03.378679 LPDDR4 probe
672 21:39:03.379096 ddr clk to 1584MHz
673 21:39:03.386125 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 21:39:03.423410
675 21:39:03.423917 dmc_version 0001
676 21:39:03.430111 Check phy result
677 21:39:03.435966 INFO : End of CA training
678 21:39:03.436461 INFO : End of initialization
679 21:39:03.441638 INFO : Training has run successfully!
680 21:39:03.442138 Check phy result
681 21:39:03.447157 INFO : End of initialization
682 21:39:03.447634 INFO : End of read enable training
683 21:39:03.450592 INFO : End of fine write leveling
684 21:39:03.456079 INFO : End of Write leveling coarse delay
685 21:39:03.461708 INFO : Training has run successfully!
686 21:39:03.462186 Check phy result
687 21:39:03.462597 INFO : End of initialization
688 21:39:03.467322 INFO : End of read dq deskew training
689 21:39:03.472898 INFO : End of MPR read delay center optimization
690 21:39:03.473372 INFO : End of write delay center optimization
691 21:39:03.478562 INFO : End of read delay center optimization
692 21:39:03.484105 INFO : End of max read latency training
693 21:39:03.484582 INFO : Training has run successfully!
694 21:39:03.489701 1D training succeed
695 21:39:03.495646 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 21:39:03.543152 Check phy result
697 21:39:03.543663 INFO : End of initialization
698 21:39:03.564886 INFO : End of 2D read delay Voltage center optimization
699 21:39:03.585116 INFO : End of 2D read delay Voltage center optimization
700 21:39:03.637189 INFO : End of 2D write delay Voltage center optimization
701 21:39:03.686621 INFO : End of 2D write delay Voltage center optimization
702 21:39:03.692139 INFO : Training has run successfully!
703 21:39:03.692650
704 21:39:03.693072 channel==0
705 21:39:03.697736 RxClkDly_Margin_A0==88 ps 9
706 21:39:03.698227 TxDqDly_Margin_A0==98 ps 10
707 21:39:03.703314 RxClkDly_Margin_A1==88 ps 9
708 21:39:03.703787 TxDqDly_Margin_A1==98 ps 10
709 21:39:03.704251 TrainedVREFDQ_A0==74
710 21:39:03.708911 TrainedVREFDQ_A1==74
711 21:39:03.709386 VrefDac_Margin_A0==25
712 21:39:03.709799 DeviceVref_Margin_A0==40
713 21:39:03.714602 VrefDac_Margin_A1==25
714 21:39:03.715070 DeviceVref_Margin_A1==40
715 21:39:03.715482
716 21:39:03.715882
717 21:39:03.720090 channel==1
718 21:39:03.720562 RxClkDly_Margin_A0==98 ps 10
719 21:39:03.720973 TxDqDly_Margin_A0==88 ps 9
720 21:39:03.725710 RxClkDly_Margin_A1==88 ps 9
721 21:39:03.726188 TxDqDly_Margin_A1==98 ps 10
722 21:39:03.731280 TrainedVREFDQ_A0==76
723 21:39:03.731744 TrainedVREFDQ_A1==77
724 21:39:03.732190 VrefDac_Margin_A0==22
725 21:39:03.736875 DeviceVref_Margin_A0==38
726 21:39:03.737342 VrefDac_Margin_A1==24
727 21:39:03.742600 DeviceVref_Margin_A1==37
728 21:39:03.743067
729 21:39:03.743481 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 21:39:03.743882
731 21:39:03.776070 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
732 21:39:03.776620 2D training succeed
733 21:39:03.781741 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 21:39:03.787318 auto size-- 65535DDR cs0 size: 2048MB
735 21:39:03.787802 DDR cs1 size: 2048MB
736 21:39:03.792932 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 21:39:03.793415 cs0 DataBus test pass
738 21:39:03.798606 cs1 DataBus test pass
739 21:39:03.799072 cs0 AddrBus test pass
740 21:39:03.799484 cs1 AddrBus test pass
741 21:39:03.799885
742 21:39:03.804089 100bdlr_step_size ps== 420
743 21:39:03.804568 result report
744 21:39:03.809702 boot times 0Enable ddr reg access
745 21:39:03.815058 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 21:39:03.828486 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 21:39:04.402167 0.0;M3 CHK:0;cm4_sp_mode 0
748 21:39:04.402752 MVN_1=0x00000000
749 21:39:04.407700 MVN_2=0x00000000
750 21:39:04.413484 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 21:39:04.413989 OPS=0x10
752 21:39:04.414384 ring efuse init
753 21:39:04.414767 chipver efuse init
754 21:39:04.419061 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 21:39:04.424834 [0.018961 Inits done]
756 21:39:04.425290 secure task start!
757 21:39:04.425681 high task start!
758 21:39:04.429494 low task start!
759 21:39:04.429941 run into bl31
760 21:39:04.436299 NOTICE: BL31: v1.3(release):4fc40b1
761 21:39:04.444287 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 21:39:04.444772 NOTICE: BL31: G12A normal boot!
763 21:39:04.470442 NOTICE: BL31: BL33 decompress pass
764 21:39:04.476171 ERROR: Error initializing runtime service opteed_fast
765 21:39:05.708144
766 21:39:05.708735
767 21:39:05.716515 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 21:39:05.716991
769 21:39:05.717409 Model: Libre Computer AML-A311D-CC Alta
770 21:39:05.924974 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 21:39:05.948337 DRAM: 2 GiB (effective 3.8 GiB)
772 21:39:06.091274 Core: 408 devices, 31 uclasses, devicetree: separate
773 21:39:06.097176 WDT: Not starting watchdog@f0d0
774 21:39:06.129423 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 21:39:06.141867 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 21:39:06.146894 ** Bad device specification mmc 0 **
777 21:39:06.157207 Card did not respond to voltage select! : -110
778 21:39:06.164900 ** Bad device specification mmc 0 **
779 21:39:06.165357 Couldn't find partition mmc 0
780 21:39:06.173199 Card did not respond to voltage select! : -110
781 21:39:06.178825 ** Bad device specification mmc 0 **
782 21:39:06.179279 Couldn't find partition mmc 0
783 21:39:06.183904 Error: could not access storage.
784 21:39:06.526211 Net: eth0: ethernet@ff3f0000
785 21:39:06.526709 starting USB...
786 21:39:06.778005 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 21:39:06.778478 Starting the controller
788 21:39:06.785062 USB XHCI 1.10
789 21:39:08.946623 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 21:39:08.947209 bl2_stage_init 0x01
791 21:39:08.947635 bl2_stage_init 0x81
792 21:39:08.952242 hw id: 0x0000 - pwm id 0x01
793 21:39:08.952713 bl2_stage_init 0xc1
794 21:39:08.953127 bl2_stage_init 0x02
795 21:39:08.953533
796 21:39:08.957752 L0:00000000
797 21:39:08.958211 L1:20000703
798 21:39:08.958621 L2:00008067
799 21:39:08.959026 L3:14000000
800 21:39:08.963392 B2:00402000
801 21:39:08.963845 B1:e0f83180
802 21:39:08.964282
803 21:39:08.964710 TE: 58159
804 21:39:08.965117
805 21:39:08.968980 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 21:39:08.969446
807 21:39:08.969858 Board ID = 1
808 21:39:08.974506 Set A53 clk to 24M
809 21:39:08.974961 Set A73 clk to 24M
810 21:39:08.975372 Set clk81 to 24M
811 21:39:08.980220 A53 clk: 1200 MHz
812 21:39:08.980680 A73 clk: 1200 MHz
813 21:39:08.981090 CLK81: 166.6M
814 21:39:08.981489 smccc: 00012ab5
815 21:39:08.985771 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 21:39:08.991400 board id: 1
817 21:39:08.997481 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 21:39:09.007749 fw parse done
819 21:39:09.013727 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 21:39:09.056338 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 21:39:09.067275 PIEI prepare done
822 21:39:09.067728 fastboot data load
823 21:39:09.068174 fastboot data verify
824 21:39:09.072948 verify result: 266
825 21:39:09.078531 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 21:39:09.078990 LPDDR4 probe
827 21:39:09.079396 ddr clk to 1584MHz
828 21:39:09.086534 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 21:39:09.123755
830 21:39:09.124239 dmc_version 0001
831 21:39:09.130451 Check phy result
832 21:39:09.136315 INFO : End of CA training
833 21:39:09.136773 INFO : End of initialization
834 21:39:09.141928 INFO : Training has run successfully!
835 21:39:09.142387 Check phy result
836 21:39:09.147518 INFO : End of initialization
837 21:39:09.147975 INFO : End of read enable training
838 21:39:09.153119 INFO : End of fine write leveling
839 21:39:09.158720 INFO : End of Write leveling coarse delay
840 21:39:09.159178 INFO : Training has run successfully!
841 21:39:09.159588 Check phy result
842 21:39:09.164313 INFO : End of initialization
843 21:39:09.164768 INFO : End of read dq deskew training
844 21:39:09.169929 INFO : End of MPR read delay center optimization
845 21:39:09.175514 INFO : End of write delay center optimization
846 21:39:09.181202 INFO : End of read delay center optimization
847 21:39:09.181663 INFO : End of max read latency training
848 21:39:09.186738 INFO : Training has run successfully!
849 21:39:09.187196 1D training succeed
850 21:39:09.195845 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 21:39:09.243464 Check phy result
852 21:39:09.243922 INFO : End of initialization
853 21:39:09.265213 INFO : End of 2D read delay Voltage center optimization
854 21:39:09.285471 INFO : End of 2D read delay Voltage center optimization
855 21:39:09.337461 INFO : End of 2D write delay Voltage center optimization
856 21:39:09.386803 INFO : End of 2D write delay Voltage center optimization
857 21:39:09.392414 INFO : Training has run successfully!
858 21:39:09.392869
859 21:39:09.393281 channel==0
860 21:39:09.398026 RxClkDly_Margin_A0==88 ps 9
861 21:39:09.398493 TxDqDly_Margin_A0==98 ps 10
862 21:39:09.401373 RxClkDly_Margin_A1==88 ps 9
863 21:39:09.401827 TxDqDly_Margin_A1==98 ps 10
864 21:39:09.406928 TrainedVREFDQ_A0==74
865 21:39:09.407384 TrainedVREFDQ_A1==76
866 21:39:09.407807 VrefDac_Margin_A0==25
867 21:39:09.412574 DeviceVref_Margin_A0==40
868 21:39:09.413052 VrefDac_Margin_A1==25
869 21:39:09.418122 DeviceVref_Margin_A1==38
870 21:39:09.418587
871 21:39:09.418978
872 21:39:09.419361 channel==1
873 21:39:09.419740 RxClkDly_Margin_A0==98 ps 10
874 21:39:09.423714 TxDqDly_Margin_A0==88 ps 9
875 21:39:09.424197 RxClkDly_Margin_A1==98 ps 10
876 21:39:09.429349 TxDqDly_Margin_A1==88 ps 9
877 21:39:09.429821 TrainedVREFDQ_A0==77
878 21:39:09.430227 TrainedVREFDQ_A1==77
879 21:39:09.434893 VrefDac_Margin_A0==22
880 21:39:09.435341 DeviceVref_Margin_A0==37
881 21:39:09.440492 VrefDac_Margin_A1==22
882 21:39:09.440933 DeviceVref_Margin_A1==37
883 21:39:09.441320
884 21:39:09.446091 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 21:39:09.446578
886 21:39:09.474087 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 21:39:09.479738 2D training succeed
888 21:39:09.485367 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 21:39:09.485824 auto size-- 65535DDR cs0 size: 2048MB
890 21:39:09.490917 DDR cs1 size: 2048MB
891 21:39:09.491358 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 21:39:09.496513 cs0 DataBus test pass
893 21:39:09.496958 cs1 DataBus test pass
894 21:39:09.497348 cs0 AddrBus test pass
895 21:39:09.502133 cs1 AddrBus test pass
896 21:39:09.502576
897 21:39:09.502965 100bdlr_step_size ps== 420
898 21:39:09.503355 result report
899 21:39:09.507717 boot times 0Enable ddr reg access
900 21:39:09.515439 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 21:39:09.528811 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 21:39:10.102499 0.0;M3 CHK:0;cm4_sp_mode 0
903 21:39:10.103025 MVN_1=0x00000000
904 21:39:10.108041 MVN_2=0x00000000
905 21:39:10.113768 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 21:39:10.114231 OPS=0x10
907 21:39:10.114645 ring efuse init
908 21:39:10.115049 chipver efuse init
909 21:39:10.119371 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 21:39:10.124939 [0.018961 Inits done]
911 21:39:10.125398 secure task start!
912 21:39:10.125808 high task start!
913 21:39:10.129526 low task start!
914 21:39:10.129981 run into bl31
915 21:39:10.136242 NOTICE: BL31: v1.3(release):4fc40b1
916 21:39:10.144006 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 21:39:10.144473 NOTICE: BL31: G12A normal boot!
918 21:39:10.169374 NOTICE: BL31: BL33 decompress pass
919 21:39:10.175027 ERROR: Error initializing runtime service opteed_fast
920 21:39:11.407905
921 21:39:11.408487
922 21:39:11.416337 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 21:39:11.416807
924 21:39:11.417226 Model: Libre Computer AML-A311D-CC Alta
925 21:39:11.624636 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 21:39:11.648041 DRAM: 2 GiB (effective 3.8 GiB)
927 21:39:11.791010 Core: 408 devices, 31 uclasses, devicetree: separate
928 21:39:11.796916 WDT: Not starting watchdog@f0d0
929 21:39:11.829155 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 21:39:11.841600 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 21:39:11.846612 ** Bad device specification mmc 0 **
932 21:39:11.856941 Card did not respond to voltage select! : -110
933 21:39:11.864616 ** Bad device specification mmc 0 **
934 21:39:11.864884 Couldn't find partition mmc 0
935 21:39:11.872933 Card did not respond to voltage select! : -110
936 21:39:11.878498 ** Bad device specification mmc 0 **
937 21:39:11.878761 Couldn't find partition mmc 0
938 21:39:11.883576 Error: could not access storage.
939 21:39:12.226131 Net: eth0: ethernet@ff3f0000
940 21:39:12.226744 starting USB...
941 21:39:12.478002 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 21:39:12.478633 Starting the controller
943 21:39:12.484949 USB XHCI 1.10
944 21:39:14.346458 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 21:39:14.347093 bl2_stage_init 0x01
946 21:39:14.347527 bl2_stage_init 0x81
947 21:39:14.352210 hw id: 0x0000 - pwm id 0x01
948 21:39:14.352777 bl2_stage_init 0xc1
949 21:39:14.353215 bl2_stage_init 0x02
950 21:39:14.353632
951 21:39:14.357767 L0:00000000
952 21:39:14.358277 L1:20000703
953 21:39:14.358701 L2:00008067
954 21:39:14.359108 L3:14000000
955 21:39:14.360599 B2:00402000
956 21:39:14.361088 B1:e0f83180
957 21:39:14.361504
958 21:39:14.361917 TE: 58124
959 21:39:14.362325
960 21:39:14.371650 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 21:39:14.372207
962 21:39:14.372638 Board ID = 1
963 21:39:14.373048 Set A53 clk to 24M
964 21:39:14.373452 Set A73 clk to 24M
965 21:39:14.377353 Set clk81 to 24M
966 21:39:14.377854 A53 clk: 1200 MHz
967 21:39:14.378271 A73 clk: 1200 MHz
968 21:39:14.382959 CLK81: 166.6M
969 21:39:14.383457 smccc: 00012a91
970 21:39:14.388510 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 21:39:14.389018 board id: 1
972 21:39:14.394126 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 21:39:14.407837 fw parse done
974 21:39:14.413691 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 21:39:14.456339 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 21:39:14.467176 PIEI prepare done
977 21:39:14.467678 fastboot data load
978 21:39:14.468113 fastboot data verify
979 21:39:14.472892 verify result: 266
980 21:39:14.478466 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 21:39:14.478955 LPDDR4 probe
982 21:39:14.479343 ddr clk to 1584MHz
983 21:39:14.486418 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 21:39:14.523659
985 21:39:14.524179 dmc_version 0001
986 21:39:14.530349 Check phy result
987 21:39:14.536250 INFO : End of CA training
988 21:39:14.536708 INFO : End of initialization
989 21:39:14.541823 INFO : Training has run successfully!
990 21:39:14.542279 Check phy result
991 21:39:14.547484 INFO : End of initialization
992 21:39:14.548007 INFO : End of read enable training
993 21:39:14.553117 INFO : End of fine write leveling
994 21:39:14.558662 INFO : End of Write leveling coarse delay
995 21:39:14.559162 INFO : Training has run successfully!
996 21:39:14.559577 Check phy result
997 21:39:14.564291 INFO : End of initialization
998 21:39:14.564791 INFO : End of read dq deskew training
999 21:39:14.569865 INFO : End of MPR read delay center optimization
1000 21:39:14.575458 INFO : End of write delay center optimization
1001 21:39:14.581096 INFO : End of read delay center optimization
1002 21:39:14.581564 INFO : End of max read latency training
1003 21:39:14.586657 INFO : Training has run successfully!
1004 21:39:14.587154 1D training succeed
1005 21:39:14.595757 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 21:39:14.643439 Check phy result
1007 21:39:14.643966 INFO : End of initialization
1008 21:39:14.664970 INFO : End of 2D read delay Voltage center optimization
1009 21:39:14.684246 INFO : End of 2D read delay Voltage center optimization
1010 21:39:14.736264 INFO : End of 2D write delay Voltage center optimization
1011 21:39:14.785414 INFO : End of 2D write delay Voltage center optimization
1012 21:39:14.791007 INFO : Training has run successfully!
1013 21:39:14.791494
1014 21:39:14.791931 channel==0
1015 21:39:14.796585 RxClkDly_Margin_A0==88 ps 9
1016 21:39:14.797098 TxDqDly_Margin_A0==98 ps 10
1017 21:39:14.802204 RxClkDly_Margin_A1==88 ps 9
1018 21:39:14.802701 TxDqDly_Margin_A1==88 ps 9
1019 21:39:14.803117 TrainedVREFDQ_A0==74
1020 21:39:14.807780 TrainedVREFDQ_A1==74
1021 21:39:14.808314 VrefDac_Margin_A0==25
1022 21:39:14.808734 DeviceVref_Margin_A0==40
1023 21:39:14.813366 VrefDac_Margin_A1==25
1024 21:39:14.813867 DeviceVref_Margin_A1==40
1025 21:39:14.814281
1026 21:39:14.814690
1027 21:39:14.815091 channel==1
1028 21:39:14.819024 RxClkDly_Margin_A0==88 ps 9
1029 21:39:14.819535 TxDqDly_Margin_A0==88 ps 9
1030 21:39:14.824567 RxClkDly_Margin_A1==88 ps 9
1031 21:39:14.825058 TxDqDly_Margin_A1==88 ps 9
1032 21:39:14.830215 TrainedVREFDQ_A0==77
1033 21:39:14.830749 TrainedVREFDQ_A1==77
1034 21:39:14.831183 VrefDac_Margin_A0==23
1035 21:39:14.835793 DeviceVref_Margin_A0==37
1036 21:39:14.836123 VrefDac_Margin_A1==24
1037 21:39:14.836350 DeviceVref_Margin_A1==37
1038 21:39:14.841355
1039 21:39:14.841883 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 21:39:14.842222
1041 21:39:14.874975 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 21:39:14.875582 2D training succeed
1043 21:39:14.880587 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 21:39:14.886148 auto size-- 65535DDR cs0 size: 2048MB
1045 21:39:14.886638 DDR cs1 size: 2048MB
1046 21:39:14.891758 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 21:39:14.892290 cs0 DataBus test pass
1048 21:39:14.897352 cs1 DataBus test pass
1049 21:39:14.897829 cs0 AddrBus test pass
1050 21:39:14.898242 cs1 AddrBus test pass
1051 21:39:14.898644
1052 21:39:14.903009 100bdlr_step_size ps== 420
1053 21:39:14.903485 result report
1054 21:39:14.908528 boot times 0Enable ddr reg access
1055 21:39:14.913628 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 21:39:14.927006 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 21:39:15.499012 0.0;M3 CHK:0;cm4_sp_mode 0
1058 21:39:15.499611 MVN_1=0x00000000
1059 21:39:15.504551 MVN_2=0x00000000
1060 21:39:15.510299 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 21:39:15.510792 OPS=0x10
1062 21:39:15.511211 ring efuse init
1063 21:39:15.511615 chipver efuse init
1064 21:39:15.515898 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 21:39:15.521480 [0.018961 Inits done]
1066 21:39:15.521951 secure task start!
1067 21:39:15.522361 high task start!
1068 21:39:15.526080 low task start!
1069 21:39:15.526547 run into bl31
1070 21:39:15.532733 NOTICE: BL31: v1.3(release):4fc40b1
1071 21:39:15.540519 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 21:39:15.540989 NOTICE: BL31: G12A normal boot!
1073 21:39:15.565878 NOTICE: BL31: BL33 decompress pass
1074 21:39:15.571552 ERROR: Error initializing runtime service opteed_fast
1075 21:39:16.804389
1076 21:39:16.804996
1077 21:39:16.812838 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 21:39:16.813321
1079 21:39:16.813740 Model: Libre Computer AML-A311D-CC Alta
1080 21:39:17.021225 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 21:39:17.044625 DRAM: 2 GiB (effective 3.8 GiB)
1082 21:39:17.187578 Core: 408 devices, 31 uclasses, devicetree: separate
1083 21:39:17.193517 WDT: Not starting watchdog@f0d0
1084 21:39:17.225724 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 21:39:17.238191 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 21:39:17.243180 ** Bad device specification mmc 0 **
1087 21:39:17.253501 Card did not respond to voltage select! : -110
1088 21:39:17.261169 ** Bad device specification mmc 0 **
1089 21:39:17.261635 Couldn't find partition mmc 0
1090 21:39:17.269503 Card did not respond to voltage select! : -110
1091 21:39:17.275015 ** Bad device specification mmc 0 **
1092 21:39:17.275479 Couldn't find partition mmc 0
1093 21:39:17.280081 Error: could not access storage.
1094 21:39:17.622543 Net: eth0: ethernet@ff3f0000
1095 21:39:17.623135 starting USB...
1096 21:39:17.874389 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 21:39:17.874920 Starting the controller
1098 21:39:17.881335 USB XHCI 1.10
1099 21:39:19.437797 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 21:39:19.446076 scanning usb for storage devices... 0 Storage Device(s) found
1102 21:39:19.497736 Hit any key to stop autoboot: 1
1103 21:39:19.498586 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 21:39:19.499303 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 21:39:19.499772 Setting prompt string to ['=>']
1106 21:39:19.500301 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 21:39:19.513561 0
1108 21:39:19.514437 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 21:39:19.514913 Sending with 10 millisecond of delay
1111 21:39:20.649434 => setenv autoload no
1112 21:39:20.660263 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 21:39:20.665357 setenv autoload no
1114 21:39:20.666121 Sending with 10 millisecond of delay
1116 21:39:22.462919 => setenv initrd_high 0xffffffff
1117 21:39:22.473721 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 21:39:22.474621 setenv initrd_high 0xffffffff
1119 21:39:22.475330 Sending with 10 millisecond of delay
1121 21:39:24.091358 => setenv fdt_high 0xffffffff
1122 21:39:24.102000 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 21:39:24.102740 setenv fdt_high 0xffffffff
1124 21:39:24.103692 Sending with 10 millisecond of delay
1126 21:39:24.396017 => dhcp
1127 21:39:24.406835 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 21:39:24.407798 dhcp
1129 21:39:24.408339 Speed: 1000, full duplex
1130 21:39:24.408810 BOOTP broadcast 1
1131 21:39:24.655192 BOOTP broadcast 2
1132 21:39:24.668750 DHCP client bound to address 192.168.6.33 (263 ms)
1133 21:39:24.669673 Sending with 10 millisecond of delay
1135 21:39:26.346030 => setenv serverip 192.168.6.2
1136 21:39:26.356844 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1137 21:39:26.357790 setenv serverip 192.168.6.2
1138 21:39:26.358569 Sending with 10 millisecond of delay
1140 21:39:30.080948 => tftpboot 0x01080000 823654/tftp-deploy-b7lpk3j7/kernel/uImage
1141 21:39:30.091814 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1142 21:39:30.092814 tftpboot 0x01080000 823654/tftp-deploy-b7lpk3j7/kernel/uImage
1143 21:39:30.093292 Speed: 1000, full duplex
1144 21:39:30.093735 Using ethernet@ff3f0000 device
1145 21:39:30.094500 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1146 21:39:30.100047 Filename '823654/tftp-deploy-b7lpk3j7/kernel/uImage'.
1147 21:39:30.104051 Load address: 0x1080000
1148 21:39:34.135932 Loading: *################################################## 43.6 MiB
1149 21:39:34.136619 10.8 MiB/s
1150 21:39:34.137093 done
1151 21:39:34.140420 Bytes transferred = 45713984 (2b98a40 hex)
1152 21:39:34.141203 Sending with 10 millisecond of delay
1154 21:39:38.828702 => tftpboot 0x08000000 823654/tftp-deploy-b7lpk3j7/ramdisk/ramdisk.cpio.gz.uboot
1155 21:39:38.839378 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
1156 21:39:38.840285 tftpboot 0x08000000 823654/tftp-deploy-b7lpk3j7/ramdisk/ramdisk.cpio.gz.uboot
1157 21:39:38.840519 Speed: 1000, full duplex
1158 21:39:38.840725 Using ethernet@ff3f0000 device
1159 21:39:38.842086 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
1160 21:39:38.853767 Filename '823654/tftp-deploy-b7lpk3j7/ramdisk/ramdisk.cpio.gz.uboot'.
1161 21:39:38.854262 Load address: 0x8000000
1162 21:39:41.258405 Loading: *################################################# UDP wrong checksum 00000005 0000154c
1163 21:39:46.260709 T UDP wrong checksum 00000005 0000154c
1164 21:39:56.262830 T T UDP wrong checksum 00000005 0000154c
1165 21:40:16.266732 T T T T UDP wrong checksum 00000005 0000154c
1166 21:40:36.271625 T T T
1167 21:40:36.272064 Retry count exceeded; starting again
1169 21:40:36.273552 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1172 21:40:36.275184 end: 2.4 uboot-commands (duration 00:01:54) [common]
1174 21:40:36.276027 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1176 21:40:36.276672 end: 2 uboot-action (duration 00:01:54) [common]
1178 21:40:36.277558 Cleaning after the job
1179 21:40:36.277928 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/ramdisk
1180 21:40:36.278727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/kernel
1181 21:40:36.305560 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/dtb
1182 21:40:36.306925 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/nfsrootfs
1183 21:40:36.395885 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/823654/tftp-deploy-b7lpk3j7/modules
1184 21:40:36.414537 start: 4.1 power-off (timeout 00:00:30) [common]
1185 21:40:36.415236 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1186 21:40:36.450372 >> OK - accepted request
1187 21:40:36.452388 Returned 0 in 0 seconds
1188 21:40:36.553324 end: 4.1 power-off (duration 00:00:00) [common]
1190 21:40:36.554657 start: 4.2 read-feedback (timeout 00:10:00) [common]
1191 21:40:36.555531 Listened to connection for namespace 'common' for up to 1s
1192 21:40:37.556279 Finalising connection for namespace 'common'
1193 21:40:37.556887 Disconnecting from shell: Finalise
1194 21:40:37.557240 =>
1195 21:40:37.657962 end: 4.2 read-feedback (duration 00:00:01) [common]
1196 21:40:37.658433 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/823654
1197 21:40:40.399051 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/823654
1198 21:40:40.399615 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.